1 /* Auto-generated file. Avoid direct editing. */ 2 /* Edits will be lost when file regenerated. */ 3 /* See tcb_common.c for auto-generation commands. */ 4 #include <stdio.h> 5 #include "tcb_common.h" 6 7 void t7_display_tcb_aux_0 (_TCBVAR *tvp, int aux) 8 { 9 10 11 12 13 14 15 16 PR("STATE:\n"); 17 PR(" %-12s (%-2u), %s, lock_tid %u, rss_fw %u\n", 18 spr_tcp_state(val("t_state")), 19 val("t_state"), 20 spr_ip_version(val("ip_version")), 21 val("lock_tid"), 22 val("rss_fw") 23 ); 24 PR(" l2t_ix 0x%x, smac sel 0x%x, tos 0x%x\n", 25 val("l2t_ix"), 26 val("smac_sel"), 27 val("tos") 28 ); 29 PR(" maxseg %u, recv_scaleflag %u, recv_tstmp %u, recv_sack %u\n", 30 val("t_maxseg"), val("recv_scale"), 31 val("recv_tstmp"), val("recv_sack")); 32 33 34 PR("TIMERS:\n"); /* **************************************** */ 35 PR(" timer %u, dack_timer %u\n", 36 val("timer"), val("dack_timer")); 37 PR(" mod_schd: tx: %u, rx: %u, reason 0x%1x\n", 38 val("mod_schd_tx"), 39 val("mod_schd_rx"), 40 ((val("mod_schd_reason2")<<2) | (val("mod_schd_reason1")<<1) | 41 val("mod_schd_reason0")) 42 ); 43 44 45 PR(" max_rt %-2u, rxtshift %u, keepalive %u\n", 46 val("max_rt"), val("t_rxtshift"), 47 val("keepalive")); 48 PR(" timestamp_offset 0x%x, timestamp 0x%x\n", 49 val("timestamp_offset"),val("timestamp")); 50 51 52 PR(" t_rtt_ts_recent_age %u t_rttseq_recent %u\n", 53 val("t_rtt_ts_recent_age"), val("t_rtseq_recent")); 54 PR(" t_srtt %u, t_rttvar %u\n", 55 val("t_srtt"),val("t_rttvar")); 56 57 58 59 60 61 62 PR("TRANSMIT BUFFER:\n"); /* *************************** */ 63 PR(" snd_una %u, snd_nxt %u, snd_max %u, tx_max %u\n", 64 val("snd_una"),val("snd_nxt"), 65 val("snd_max"),val("tx_max")); 66 PR(" core_fin %u, tx_hdr_offset %u\n", 67 val("core_fin"), SEQ_SUB(val("tx_max"),val("snd_una")) 68 ); 69 if (val("recv_scale") && !val("active_open")) { 70 PR(" rcv_adv %-5u << %-2u == %u (recv_scaleflag %u rcv_scale %u active open %u)\n", 71 val("rcv_adv"), val("rcv_scale"), 72 val("rcv_adv") << val("rcv_scale"), 73 val("recv_scale"), val("rcv_scale"), val("active_open")); 74 } else { 75 PR(" rcv_adv %-5u (rcv_scale %-2u recv_scaleflag %u active_open %u)\n", 76 val("rcv_adv"), val("rcv_scale"), 77 val("recv_scale"), val("active_open")); 78 } 79 80 PR(" snd_cwnd %-5u snd_ssthresh %u snd_rec %u\n", 81 val("snd_cwnd") , val("snd_ssthresh"), val("snd_rec") 82 ); 83 84 85 86 87 PR(" cctrl: sel %s, ecn %u, ece %u, cwr %u, rfr %u\n", 88 spr_cctrl_sel(val("cctrl_sel0"),val("cctrl_sel1")), 89 val("cctrl_ecn"), val("cctrl_ece"), val("cctrl_cwr"), 90 val("cctrl_rfr")); 91 PR(" t_dupacks %u, dupack_count_odd %u, fast_recovery %u\n", 92 val("t_dupacks"), val("dupack_count_odd"),val("fast_recovery")); 93 PR(" core_more %u, core_urg, %u core_push %u,", 94 val("core_more"),val("core_urg"),val("core_push")); 95 PR(" core_flush %u\n",val("core_flush")); 96 PR(" nagle %u, ssws_disable %u, turbo %u,", 97 val("nagle"), val("ssws_disabled"), val("turbo")); 98 PR(" tx_pdu_out %u\n",val("tx_pdu_out")); 99 PR(" tx_pace_auto %u, tx_pace_fixed %u, tx_queue %u", 100 val("tx_pace_auto"),val("tx_pace_fixed"),val("tx_queue")); 101 102 103 PR(" tx_quiesce %u\n",val("tx_quiesce")); 104 PR(" channel %u, channel_msb %u\n", 105 val("channel"), 106 val("channel_msb") 107 ); 108 109 110 111 112 PR(" tx_hdr_ptr 0x%-6x tx_last_ptr 0x%-6x tx_compact %u\n", 113 val("tx_hdr_ptr"),val("tx_last_ptr"),val("tx_compact")); 114 115 116 117 118 PR("RECEIVE BUFFER:\n"); /* *************************** */ 119 PR(" last_ack_sent %-10u rx_compact %u\n", 120 val("ts_last_ack_sent"),val("rx_compact")); 121 PR(" rcv_nxt %-10u hdr_off %-10u\n", 122 val("rcv_nxt"), val("rx_hdr_offset")); 123 PR(" frag0_idx %-10u length %-10u frag0_ptr 0x%-8x\n", 124 val("rx_frag0_start_idx"), 125 val("rx_frag0_len"), 126 val("rx_ptr")); 127 PR(" frag1_idx %-10u length %-10u ", 128 val("rx_frag1_start_idx_offset"), 129 val("rx_frag1_len")); 130 131 132 133 134 if (val("ulp_type")!=4 && val("ulp_type")!=7) { /* RDMA has FRAG1 idx && len, but no ptr? Should I not display frag1 at all? */ 135 PR("frag1_ptr 0x%-8x\n",val("rx_frag1_ptr")); 136 } else { 137 PR("\n"); 138 } 139 140 141 if (val("ulp_type") != 9 && val("ulp_type")!=8 && val("ulp_type") !=6 && 142 val("ulp_type") != 5 && val("ulp_type") !=4 && val("ulp_type") !=7) { 143 PR(" frag2_idx %-10u length %-10u frag2_ptr 0x%-8x\n", 144 val("rx_frag2_start_idx_offset"), 145 val("rx_frag2_len"), 146 val("rx_frag2_ptr")); 147 PR(" frag3_idx %-10u length %-10u frag3_ptr 0x%-8x\n", 148 val("rx_frag3_start_idx_offset"), 149 val("rx_frag3_len"), 150 val("rx_frag3_ptr")); 151 } 152 153 154 155 156 157 158 PR(" peer_fin %u, rx_pdu_out %u, pdu_len %u\n", 159 val("peer_fin"),val("rx_pdu_out"), val("pdu_len")); 160 161 162 163 164 if (val("recv_scale")) { 165 PR(" rcv_wnd %u >> snd_scale %u == %u, recv_scaleflag = %u\n", 166 val("rcv_wnd"), val("snd_scale"), 167 val("rcv_wnd") >> val("snd_scale"), 168 val("recv_scale")); 169 } else { 170 PR(" rcv_wnd %u. (snd_scale %u, recv_scaleflag = %u)\n", 171 val("rcv_wnd"), val("snd_scale"), 172 val("recv_scale")); 173 } 174 175 176 177 178 PR(" dack_mss %u dack %u, dack_not_acked: %u\n", 179 val("dack_mss"),val("dack"),val("dack_not_acked")); 180 PR(" rcv_coal %u rcv_co_psh %u rcv_co_last_psh %u heart %u\n", 181 val("rcv_coalesce_enable"), 182 val("rcv_coalesce_push"), 183 val("rcv_coalesce_last_psh"), 184 val("rcv_coalesce_heartbeat")); 185 186 PR(" rx_quiesce %u rx_flow_ctrl_dis %u,", 187 val("rx_quiesce"), 188 val("rx_flow_control_disable")); 189 PR(" rx_flow_ctrl_ddp %u\n", 190 val("rx_flow_control_ddp")); 191 192 193 PR("MISCELANEOUS:\n"); /* *************************** */ 194 PR(" pend_ctl: 0x%1x, core_bypass: 0x%x, main_slush: 0x%x\n", 195 ((val("pend_ctl2")<<2) | (val("pend_ctl1")<<1) | 196 val("pend_ctl0")), 197 val("core_bypass"),val("main_slush")); 198 PR(" Migrating %u, ask_mode %u, non_offload %u, rss_info %u\n", 199 val("migrating"), 200 val("ask_mode"), val("non_offload"), val("rss_info")); 201 PR(" ULP: ulp_type %u (%s), ulp_raw %u", 202 val("ulp_type"), spr_ulp_type(val("ulp_type")), 203 val("ulp_raw")); 204 205 206 if (aux==1) { 207 PR(", ulp_ext %u",val("ulp_ext")); 208 } 209 PR("\n"); 210 211 212 213 214 PR(" RDMA: error %u, flm_err %u\n", 215 val("rdma_error"), val("rdma_flm_error")); 216 217 218 } 219 void t7_display_tcb_aux_1 (_TCBVAR *tvp, int aux) 220 { 221 222 223 224 PR(" aux1_slush0: 0x%x aux1_slush1 0x%x\n", 225 val("aux1_slush0"), val("aux1_slush1")); 226 PR(" pdu_hdr_len %u\n",val("pdu_hdr_len")); 227 228 229 230 } 231 void t7_display_tcb_aux_2 (_TCBVAR *tvp, int aux) 232 { 233 234 235 236 237 PR(" qp_id %u, pd_id %u, stag %u\n", 238 val("qp_id"), val("pd_id"),val("stag")); 239 PR(" irs_ulp %u, iss_ulp %u\n", 240 val("irs_ulp"),val("iss_ulp")); 241 PR(" tx_pdu_len %u\n", 242 val("tx_pdu_len")); 243 PR(" cq_idx_sq %u, cq_idx_rq %u\n", 244 val("cq_idx_sq"),val("cq_idx_rq")); 245 PR(" rq_start %u, rq_MSN %u, rq_max_off %u, rq_write_ptr %u\n", 246 val("rq_start"),val("rq_msn"),val("rq_max_offset"), 247 val("rq_write_ptr")); 248 PR(" L_valid %u, rdmap opcode %u\n", 249 val("ord_l_bit_vld"),val("rdmap_opcode")); 250 PR(" tx_flush: %u, tx_oos_rxmt %u, tx_oos_txmt %u\n", 251 val("tx_flush"),val("tx_oos_rxmt"),val("tx_oos_txmt")); 252 253 254 255 256 } 257 void t7_display_tcb_aux_3 (_TCBVAR *tvp, int aux) 258 { 259 260 261 262 263 264 265 PR(" aux3_slush: 0x%x, unused: buf0 0x%x, buf1: 0x%x\n", 266 val("aux3_slush"),val("ddp_buf0_unused"),val("ddp_buf1_unused")); 267 268 269 PR(" ind_full: %u, tls_key_mode: %u\n", 270 val("ddp_indicate_fll"),val("tls_key_mode")); 271 272 273 PR(" DDP: DDPOFF ActBuf IndOut WaitFrag Rx2Tx BufInf\n"); 274 PR(" %u %u %u %u %u %u\n", 275 val("ddp_off"),val("ddp_active_buf"),val("ddp_indicate_out"), 276 val("ddp_wait_frag"),val("ddp_rx2tx"),val("ddp_buf_inf") 277 ); 278 279 280 PR(" Ind PshfEn PushDis Flush NoInvalidate\n"); 281 PR(" Buf0: %u %u %u %u %u\n", 282 val("ddp_buf0_indicate"), 283 val("ddp_pshf_enable_0"), val("ddp_push_disable_0"), 284 val("ddp_buf0_flush"), val("ddp_psh_no_invalidate0") 285 ); 286 PR(" Buf1: %u %u %u %u %u\n", 287 val("ddp_buf1_indicate"), 288 val("ddp_pshf_enable_1"), val("ddp_push_disable_1"), 289 val("ddp_buf1_flush"), val("ddp_psh_no_invalidate1") 290 ); 291 292 293 294 295 296 297 298 299 300 301 PR(" Valid Offset Length Tag\n"); 302 PR(" Buf0: %u 0x%6.6x 0x%6.6x 0x%8.8x", 303 val("ddp_buf0_valid"),val("rx_ddp_buf0_offset"), 304 val("rx_ddp_buf0_len"),val("rx_ddp_buf0_tag") 305 306 307 ); 308 if (0==val("ddp_off") && 1==val("ddp_buf0_valid") && 0==val("ddp_active_buf")) { 309 PR(" (Active)\n"); 310 } else { 311 PR(" (Inactive)\n"); 312 } 313 314 315 PR(" Buf1: %u 0x%6.6x 0x%6.6x 0x%8.8x", 316 val("ddp_buf1_valid"),val("rx_ddp_buf1_offset"), 317 val("rx_ddp_buf1_len"),val("rx_ddp_buf1_tag") 318 319 320 ); 321 322 323 if (0==val("ddp_off") && 1==val("ddp_buf1_valid") && 1==val("ddp_active_buf")) { 324 PR(" (Active)\n"); 325 } else { 326 PR(" (Inactive)\n"); 327 } 328 329 330 331 332 333 334 if (1==val("ddp_off")) { 335 PR(" DDP is off (which also disables indicate)\n"); 336 } else if (1==val("ddp_buf0_valid") && 0==val("ddp_active_buf")) { 337 PR(" Data being DDP'ed to buf 0, "); 338 PR("which has %u - %u = %u bytes of space left\n", 339 val("rx_ddp_buf0_len"),val("rx_ddp_buf0_offset"), 340 val("rx_ddp_buf0_len")-val("rx_ddp_buf0_offset") 341 ); 342 if (1==val("ddp_buf1_valid")) { 343 PR(" And buf1, which is also valid, has %u - %u = %u bytes of space left\n", 344 val("rx_ddp_buf1_len"),val("rx_ddp_buf1_offset"), 345 val("rx_ddp_buf1_len")-val("rx_ddp_buf1_offset") 346 ); 347 } 348 } else if (1==val("ddp_buf1_valid") && 1==val("ddp_active_buf")) { 349 PR(" Data being DDP'ed to buf 1, "); 350 PR("which has %u - %u = %u bytes of space left\n", 351 val("rx_ddp_buf1_len"),val("rx_ddp_buf1_offset"), 352 val("rx_ddp_buf1_len")-val("rx_ddp_buf1_offset") 353 ); 354 if (1==val("ddp_buf0_valid")) { 355 PR(" And buf0, which is also valid, has %u - %u = %u bytes of space left\n", 356 val("rx_ddp_buf0_len"),val("rx_ddp_buf0_offset"), 357 val("rx_ddp_buf0_len")-val("rx_ddp_buf0_offset") 358 ); 359 } 360 } else if (0==val("ddp_buf0_valid") && 1==val("ddp_buf1_valid") && 0==val("ddp_active_buf")) { 361 PR(" !!! Invalid DDP buf 1 valid, but buf 0 active.\n"); 362 } else if (1==val("ddp_buf0_valid") && 0==val("ddp_buf1_valid") && 1==val("ddp_active_buf")) { 363 PR(" !!! Invalid DDP buf 0 valid, but buf 1 active.\n"); 364 } else { 365 PR(" DDP is enabled, but no buffers are active && valid.\n"); 366 367 368 369 370 if (0==val("ddp_indicate_out")) { 371 if (0==val("ddp_buf0_indicate") && 0==val("ddp_buf1_indicate")) { 372 PR(" 0 length Indicate buffers "); 373 if (0==val("rx_hdr_offset")) { 374 PR("will cause new data to be held in PMRX.\n"); 375 } else { 376 PR("is causing %u bytes to be held in PMRX\n", 377 val("rx_hdr_offset")); 378 } 379 } else { 380 PR(" Data being indicated to host\n"); 381 } 382 } else if (1==val("ddp_indicate_out")) { 383 PR(" Indicate is off, which "); 384 if (0==val("rx_hdr_offset")) { 385 PR("will cause new data to be held in PMRX.\n"); 386 } else { 387 PR("is causing %u bytes to be held in PMRX\n", 388 val("rx_hdr_offset")); 389 } 390 } 391 } 392 393 394 395 396 } 397 void t7_display_tcb_aux_4 (_TCBVAR *tvp, int aux) 398 { 399 400 401 402 PR("TLS: offset: 0x%6.6x, len:0x%6.6x, flags: 0x%4.4x\n", 403 val("rx_tls_buf_offset"),val("rx_tls_buf_len"), 404 val("rx_tls_flags")); 405 PR(" seq: 0x%llx \n",val64("rx_tls_seq")); 406 PR(" tag: 0x%8.8x, key:0x%8.8x\n", 407 val("rx_tls_buf_tag"),val("rx_tls_key_tag")); 408 409 410 411 412 } 413