1366f6083SPeter Grehan /*- 24d846d26SWarner Losh * SPDX-License-Identifier: BSD-2-Clause 31de7b4b8SPedro F. Giffuni * 4ba41c3c1SPeter Grehan * Copyright (c) 2013 Chris Torek <torek @ torek net> 5366f6083SPeter Grehan * All rights reserved. 6366f6083SPeter Grehan * 7366f6083SPeter Grehan * Redistribution and use in source and binary forms, with or without 8366f6083SPeter Grehan * modification, are permitted provided that the following conditions 9366f6083SPeter Grehan * are met: 10366f6083SPeter Grehan * 1. Redistributions of source code must retain the above copyright 11366f6083SPeter Grehan * notice, this list of conditions and the following disclaimer. 12366f6083SPeter Grehan * 2. Redistributions in binary form must reproduce the above copyright 13366f6083SPeter Grehan * notice, this list of conditions and the following disclaimer in the 14366f6083SPeter Grehan * documentation and/or other materials provided with the distribution. 15366f6083SPeter Grehan * 16ba41c3c1SPeter Grehan * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17366f6083SPeter Grehan * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18366f6083SPeter Grehan * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19ba41c3c1SPeter Grehan * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20366f6083SPeter Grehan * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21366f6083SPeter Grehan * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22366f6083SPeter Grehan * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23366f6083SPeter Grehan * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24366f6083SPeter Grehan * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25366f6083SPeter Grehan * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26366f6083SPeter Grehan * SUCH DAMAGE. 27366f6083SPeter Grehan */ 28366f6083SPeter Grehan 2954ac6f72SKa Ho Ng #ifndef _BHYVE_VIRTIO_H_ 3054ac6f72SKa Ho Ng #define _BHYVE_VIRTIO_H_ 31366f6083SPeter Grehan 3217e9052cSVincenzo Maffione #include <machine/atomic.h> 3317e9052cSVincenzo Maffione 3454ac6f72SKa Ho Ng #include <dev/virtio/virtio.h> 3554ac6f72SKa Ho Ng #include <dev/virtio/virtio_ring.h> 3654ac6f72SKa Ho Ng #include <dev/virtio/pci/virtio_pci_var.h> 3754ac6f72SKa Ho Ng 38ba41c3c1SPeter Grehan /* 39ba41c3c1SPeter Grehan * These are derived from several virtio specifications. 40ba41c3c1SPeter Grehan * 41ba41c3c1SPeter Grehan * Some useful links: 424258c52eSPeter Grehan * https://github.com/rustyrussell/virtio-spec 43ba41c3c1SPeter Grehan * http://people.redhat.com/pbonzini/virtio-spec.pdf 44ba41c3c1SPeter Grehan */ 45ba41c3c1SPeter Grehan 46ba41c3c1SPeter Grehan /* 47ba41c3c1SPeter Grehan * A virtual device has zero or more "virtual queues" (virtqueue). 48ba41c3c1SPeter Grehan * Each virtqueue uses at least two 4096-byte pages, laid out thus: 49ba41c3c1SPeter Grehan * 50ba41c3c1SPeter Grehan * +-----------------------------------------------+ 51ba41c3c1SPeter Grehan * | "desc": <N> descriptors, 16 bytes each | 52ba41c3c1SPeter Grehan * | ----------------------------------------- | 53ba41c3c1SPeter Grehan * | "avail": 2 uint16; <N> uint16; 1 uint16 | 54ba41c3c1SPeter Grehan * | ----------------------------------------- | 55ba41c3c1SPeter Grehan * | pad to 4k boundary | 56ba41c3c1SPeter Grehan * +-----------------------------------------------+ 57ba41c3c1SPeter Grehan * | "used": 2 x uint16; <N> elems; 1 uint16 | 58ba41c3c1SPeter Grehan * | ----------------------------------------- | 59ba41c3c1SPeter Grehan * | pad to 4k boundary | 60ba41c3c1SPeter Grehan * +-----------------------------------------------+ 61ba41c3c1SPeter Grehan * 62ba41c3c1SPeter Grehan * The number <N> that appears here is always a power of two and is 63ba41c3c1SPeter Grehan * limited to no more than 32768 (as it must fit in a 16-bit field). 64ba41c3c1SPeter Grehan * If <N> is sufficiently large, the above will occupy more than 65ba41c3c1SPeter Grehan * two pages. In any case, all pages must be physically contiguous 66ba41c3c1SPeter Grehan * within the guest's physical address space. 67ba41c3c1SPeter Grehan * 68ba41c3c1SPeter Grehan * The <N> 16-byte "desc" descriptors consist of a 64-bit guest 69ba41c3c1SPeter Grehan * physical address <addr>, a 32-bit length <len>, a 16-bit 70ba41c3c1SPeter Grehan * <flags>, and a 16-bit <next> field (all in guest byte order). 71ba41c3c1SPeter Grehan * 72ba41c3c1SPeter Grehan * There are three flags that may be set : 73ba41c3c1SPeter Grehan * NEXT descriptor is chained, so use its "next" field 74ba41c3c1SPeter Grehan * WRITE descriptor is for host to write into guest RAM 75ba41c3c1SPeter Grehan * (else host is to read from guest RAM) 76ba41c3c1SPeter Grehan * INDIRECT descriptor address field is (guest physical) 77ba41c3c1SPeter Grehan * address of a linear array of descriptors 78ba41c3c1SPeter Grehan * 79ba41c3c1SPeter Grehan * Unless INDIRECT is set, <len> is the number of bytes that may 80ba41c3c1SPeter Grehan * be read/written from guest physical address <addr>. If 81ba41c3c1SPeter Grehan * INDIRECT is set, WRITE is ignored and <len> provides the length 82ba41c3c1SPeter Grehan * of the indirect descriptors (and <len> must be a multiple of 83ba41c3c1SPeter Grehan * 16). Note that NEXT may still be set in the main descriptor 84ba41c3c1SPeter Grehan * pointing to the indirect, and should be set in each indirect 85ba41c3c1SPeter Grehan * descriptor that uses the next descriptor (these should generally 86ba41c3c1SPeter Grehan * be numbered sequentially). However, INDIRECT must not be set 87ba41c3c1SPeter Grehan * in the indirect descriptors. Upon reaching an indirect descriptor 88ba41c3c1SPeter Grehan * without a NEXT bit, control returns to the direct descriptors. 89ba41c3c1SPeter Grehan * 90ba41c3c1SPeter Grehan * Except inside an indirect, each <next> value must be in the 91ba41c3c1SPeter Grehan * range [0 .. N) (i.e., the half-open interval). (Inside an 92ba41c3c1SPeter Grehan * indirect, each <next> must be in the range [0 .. <len>/16).) 93ba41c3c1SPeter Grehan * 94ba41c3c1SPeter Grehan * The "avail" data structures reside in the same pages as the 95ba41c3c1SPeter Grehan * "desc" structures since both together are used by the device to 96ba41c3c1SPeter Grehan * pass information to the hypervisor's virtual driver. These 97ba41c3c1SPeter Grehan * begin with a 16-bit <flags> field and 16-bit index <idx>, then 98ba41c3c1SPeter Grehan * have <N> 16-bit <ring> values, followed by one final 16-bit 99ba41c3c1SPeter Grehan * field <used_event>. The <N> <ring> entries are simply indices 100*ec8a394dSElyes Haouas * into the descriptor ring (and thus must meet the same 101ba41c3c1SPeter Grehan * constraints as each <next> value). However, <idx> is counted 102ba41c3c1SPeter Grehan * up from 0 (initially) and simply wraps around after 65535; it 103ba41c3c1SPeter Grehan * is taken mod <N> to find the next available entry. 104ba41c3c1SPeter Grehan * 105ba41c3c1SPeter Grehan * The "used" ring occupies a separate page or pages, and contains 106ba41c3c1SPeter Grehan * values written from the virtual driver back to the guest OS. 107ba41c3c1SPeter Grehan * This begins with a 16-bit <flags> and 16-bit <idx>, then there 108ba41c3c1SPeter Grehan * are <N> "vring_used" elements, followed by a 16-bit <avail_event>. 109ba41c3c1SPeter Grehan * The <N> "vring_used" elements consist of a 32-bit <id> and a 110ba41c3c1SPeter Grehan * 32-bit <len> (vu_tlen below). The <id> is simply the index of 111ba41c3c1SPeter Grehan * the head of a descriptor chain the guest made available 112ba41c3c1SPeter Grehan * earlier, and the <len> is the number of bytes actually written, 113ba41c3c1SPeter Grehan * e.g., in the case of a network driver that provided a large 114ba41c3c1SPeter Grehan * receive buffer but received only a small amount of data. 115ba41c3c1SPeter Grehan * 116ba41c3c1SPeter Grehan * The two event fields, <used_event> and <avail_event>, in the 117ba41c3c1SPeter Grehan * avail and used rings (respectively -- note the reversal!), are 118ba41c3c1SPeter Grehan * always provided, but are used only if the virtual device 119ba41c3c1SPeter Grehan * negotiates the VIRTIO_RING_F_EVENT_IDX feature during feature 120ba41c3c1SPeter Grehan * negotiation. Similarly, both rings provide a flag -- 121ba41c3c1SPeter Grehan * VRING_AVAIL_F_NO_INTERRUPT and VRING_USED_F_NO_NOTIFY -- in 122ba41c3c1SPeter Grehan * their <flags> field, indicating that the guest does not need an 123ba41c3c1SPeter Grehan * interrupt, or that the hypervisor driver does not need a 124ba41c3c1SPeter Grehan * notify, when descriptors are added to the corresponding ring. 125ba41c3c1SPeter Grehan * (These are provided only for interrupt optimization and need 126ba41c3c1SPeter Grehan * not be implemented.) 127ba41c3c1SPeter Grehan */ 128366f6083SPeter Grehan #define VRING_ALIGN 4096 129366f6083SPeter Grehan 130366f6083SPeter Grehan /* 131ba41c3c1SPeter Grehan * The address of any given virtual queue is determined by a single 132ba41c3c1SPeter Grehan * Page Frame Number register. The guest writes the PFN into the 133ba41c3c1SPeter Grehan * PCI config space. However, a device that has two or more 134ba41c3c1SPeter Grehan * virtqueues can have a different PFN, and size, for each queue. 135ba41c3c1SPeter Grehan * The number of queues is determinable via the PCI config space 136ba41c3c1SPeter Grehan * VTCFG_R_QSEL register. Writes to QSEL select the queue: 0 means 137ba41c3c1SPeter Grehan * queue #0, 1 means queue#1, etc. Once a queue is selected, the 138ba41c3c1SPeter Grehan * remaining PFN and QNUM registers refer to that queue. 139ba41c3c1SPeter Grehan * 140ba41c3c1SPeter Grehan * QNUM is a read-only register containing a nonzero power of two 141ba41c3c1SPeter Grehan * that indicates the (hypervisor's) queue size. Or, if reading it 142ba41c3c1SPeter Grehan * produces zero, the hypervisor does not have a corresponding 143ba41c3c1SPeter Grehan * queue. (The number of possible queues depends on the virtual 144ba41c3c1SPeter Grehan * device. The block device has just one; the network device 145ba41c3c1SPeter Grehan * provides either two -- 0 = receive, 1 = transmit -- or three, 146ba41c3c1SPeter Grehan * with 2 = control.) 147ba41c3c1SPeter Grehan * 148ba41c3c1SPeter Grehan * PFN is a read/write register giving the physical page address of 149ba41c3c1SPeter Grehan * the virtqueue in guest memory (the guest must allocate enough space 150ba41c3c1SPeter Grehan * based on the hypervisor's provided QNUM). 151ba41c3c1SPeter Grehan * 152ba41c3c1SPeter Grehan * QNOTIFY is effectively write-only: when the guest writes a queue 153ba41c3c1SPeter Grehan * number to the register, the hypervisor should scan the specified 154ba41c3c1SPeter Grehan * virtqueue. (Reading QNOTIFY currently always gets 0). 155ba41c3c1SPeter Grehan */ 156ba41c3c1SPeter Grehan 157ba41c3c1SPeter Grehan /* 158366f6083SPeter Grehan * PFN register shift amount 159366f6083SPeter Grehan */ 160366f6083SPeter Grehan #define VRING_PFN 12 161366f6083SPeter Grehan 162366f6083SPeter Grehan /* 163366f6083SPeter Grehan * PCI vendor/device IDs 164366f6083SPeter Grehan */ 165366f6083SPeter Grehan #define VIRTIO_VENDOR 0x1AF4 166366f6083SPeter Grehan #define VIRTIO_DEV_NET 0x1000 167366f6083SPeter Grehan #define VIRTIO_DEV_BLOCK 0x1001 16813ee8ddeSJakub Wojciech Klama #define VIRTIO_DEV_CONSOLE 0x1003 169b4cc5d63SRobert Wing #define VIRTIO_DEV_SCSI 0x1004 17026e6e3e6SPeter Grehan #define VIRTIO_DEV_RANDOM 0x1005 171100353cfSJakub Wojciech Klama #define VIRTIO_DEV_9P 0x1009 172054accacSCorvin Köhne #define VIRTIO_DEV_INPUT 0x1052 173054accacSCorvin Köhne 174054accacSCorvin Köhne /* 175054accacSCorvin Köhne * PCI revision IDs 176054accacSCorvin Köhne */ 177054accacSCorvin Köhne #define VIRTIO_REV_INPUT 1 178054accacSCorvin Köhne 179054accacSCorvin Köhne /* 180054accacSCorvin Köhne * PCI subvendor IDs 181054accacSCorvin Köhne */ 182054accacSCorvin Köhne #define VIRTIO_SUBVEN_INPUT 0x108E 183054accacSCorvin Köhne 184054accacSCorvin Köhne /* 185054accacSCorvin Köhne * PCI subdevice IDs 186054accacSCorvin Köhne */ 187054accacSCorvin Köhne #define VIRTIO_SUBDEV_INPUT 0x1100 188366f6083SPeter Grehan 18991039bb2SNeel Natu /* From section 2.3, "Virtqueue Configuration", of the virtio specification */ 19054ac6f72SKa Ho Ng static inline int 19154ac6f72SKa Ho Ng vring_size_aligned(u_int qsz) 19291039bb2SNeel Natu { 19354ac6f72SKa Ho Ng return (roundup2(vring_size(qsz, VRING_ALIGN), VRING_ALIGN)); 19491039bb2SNeel Natu } 19591039bb2SNeel Natu 196ba41c3c1SPeter Grehan struct pci_devinst; 197ba41c3c1SPeter Grehan struct vqueue_info; 198483d953aSJohn Baldwin struct vm_snapshot_meta; 199ba41c3c1SPeter Grehan 200ba41c3c1SPeter Grehan /* 201ba41c3c1SPeter Grehan * A virtual device, with some number (possibly 0) of virtual 202ba41c3c1SPeter Grehan * queues and some size (possibly 0) of configuration-space 203ba41c3c1SPeter Grehan * registers private to the device. The virtio_softc should come 204ba41c3c1SPeter Grehan * at the front of each "derived class", so that a pointer to the 205ba41c3c1SPeter Grehan * virtio_softc is also a pointer to the more specific, derived- 206ba41c3c1SPeter Grehan * from-virtio driver's softc. 207ba41c3c1SPeter Grehan * 208ba41c3c1SPeter Grehan * Note: inside each hypervisor virtio driver, changes to these 209ba41c3c1SPeter Grehan * data structures must be locked against other threads, if any. 210ba41c3c1SPeter Grehan * Except for PCI config space register read/write, we assume each 211ba41c3c1SPeter Grehan * driver does the required locking, but we need a pointer to the 212ba41c3c1SPeter Grehan * lock (if there is one) for PCI config space read/write ops. 213ba41c3c1SPeter Grehan * 214ba41c3c1SPeter Grehan * When the guest reads or writes the device's config space, the 215ba41c3c1SPeter Grehan * generic layer checks for operations on the special registers 216ba41c3c1SPeter Grehan * described above. If the offset of the register(s) being read 217ba41c3c1SPeter Grehan * or written is past the CFG area (CFG0 or CFG1), the request is 218ba41c3c1SPeter Grehan * passed on to the virtual device, after subtracting off the 219ba41c3c1SPeter Grehan * generic-layer size. (So, drivers can just use the offset as 220ba41c3c1SPeter Grehan * an offset into "struct config", for instance.) 221ba41c3c1SPeter Grehan * 222ba41c3c1SPeter Grehan * (The virtio layer also makes sure that the read or write is to/ 223ba41c3c1SPeter Grehan * from a "good" config offset, hence vc_cfgsize, and on BAR #0. 224ba41c3c1SPeter Grehan * However, the driver must verify the read or write size and offset 225ba41c3c1SPeter Grehan * and that no one is writing a readonly register.) 226ba41c3c1SPeter Grehan * 227ba41c3c1SPeter Grehan * The BROKED flag ("this thing done gone and broked") is for future 228ba41c3c1SPeter Grehan * use. 229ba41c3c1SPeter Grehan */ 230ba41c3c1SPeter Grehan #define VIRTIO_USE_MSIX 0x01 231ba41c3c1SPeter Grehan #define VIRTIO_EVENT_IDX 0x02 /* use the event-index values */ 232ba41c3c1SPeter Grehan #define VIRTIO_BROKED 0x08 /* ??? */ 233ba41c3c1SPeter Grehan 234ba41c3c1SPeter Grehan struct virtio_softc { 235ba41c3c1SPeter Grehan struct virtio_consts *vs_vc; /* constants (see below) */ 236ba41c3c1SPeter Grehan int vs_flags; /* VIRTIO_* flags from above */ 237ba41c3c1SPeter Grehan pthread_mutex_t *vs_mtx; /* POSIX mutex, if any */ 238ba41c3c1SPeter Grehan struct pci_devinst *vs_pi; /* PCI device instance */ 239ba41c3c1SPeter Grehan uint32_t vs_negotiated_caps; /* negotiated capabilities */ 240ba41c3c1SPeter Grehan struct vqueue_info *vs_queues; /* one per vc_nvq */ 241ba41c3c1SPeter Grehan int vs_curq; /* current queue */ 242ba41c3c1SPeter Grehan uint8_t vs_status; /* value from last status write */ 243ba41c3c1SPeter Grehan uint8_t vs_isr; /* ISR flags, if not MSI-X */ 244ba41c3c1SPeter Grehan uint16_t vs_msix_cfg_idx; /* MSI-X vector for config event */ 245ba41c3c1SPeter Grehan }; 246ba41c3c1SPeter Grehan 2473cbf3585SJohn Baldwin #define VS_LOCK(vs) \ 2483cbf3585SJohn Baldwin do { \ 2493cbf3585SJohn Baldwin if (vs->vs_mtx) \ 2503cbf3585SJohn Baldwin pthread_mutex_lock(vs->vs_mtx); \ 2513cbf3585SJohn Baldwin } while (0) 2523cbf3585SJohn Baldwin 2533cbf3585SJohn Baldwin #define VS_UNLOCK(vs) \ 2543cbf3585SJohn Baldwin do { \ 2553cbf3585SJohn Baldwin if (vs->vs_mtx) \ 2563cbf3585SJohn Baldwin pthread_mutex_unlock(vs->vs_mtx); \ 2573cbf3585SJohn Baldwin } while (0) 2583cbf3585SJohn Baldwin 259ba41c3c1SPeter Grehan struct virtio_consts { 260ba41c3c1SPeter Grehan const char *vc_name; /* name of driver (for diagnostics) */ 261ba41c3c1SPeter Grehan int vc_nvq; /* number of virtual queues */ 262ba41c3c1SPeter Grehan size_t vc_cfgsize; /* size of dev-specific config regs */ 263ba41c3c1SPeter Grehan void (*vc_reset)(void *); /* called on virtual device reset */ 264ba41c3c1SPeter Grehan void (*vc_qnotify)(void *, struct vqueue_info *); 265ba41c3c1SPeter Grehan /* called on QNOTIFY if no VQ notify */ 266ba41c3c1SPeter Grehan int (*vc_cfgread)(void *, int, int, uint32_t *); 267ba41c3c1SPeter Grehan /* called to read config regs */ 268ba41c3c1SPeter Grehan int (*vc_cfgwrite)(void *, int, int, uint32_t); 269ba41c3c1SPeter Grehan /* called to write config regs */ 270e18f344bSPeter Grehan void (*vc_apply_features)(void *, uint64_t); 271e18f344bSPeter Grehan /* called to apply negotiated features */ 27218e32ebcSPeter Grehan uint64_t vc_hv_caps; /* hypervisor-provided capabilities */ 273483d953aSJohn Baldwin void (*vc_pause)(void *); /* called to pause device activity */ 274483d953aSJohn Baldwin void (*vc_resume)(void *); /* called to resume device activity */ 275483d953aSJohn Baldwin int (*vc_snapshot)(void *, struct vm_snapshot_meta *); 276483d953aSJohn Baldwin /* called to save / restore device state */ 277ba41c3c1SPeter Grehan }; 278ba41c3c1SPeter Grehan 279ba41c3c1SPeter Grehan /* 280ba41c3c1SPeter Grehan * Data structure allocated (statically) per virtual queue. 281ba41c3c1SPeter Grehan * 282ba41c3c1SPeter Grehan * Drivers may change vq_qsize after a reset. When the guest OS 283ba41c3c1SPeter Grehan * requests a device reset, the hypervisor first calls 284ba41c3c1SPeter Grehan * vs->vs_vc->vc_reset(); then the data structure below is 285ba41c3c1SPeter Grehan * reinitialized (for each virtqueue: vs->vs_vc->vc_nvq). 286ba41c3c1SPeter Grehan * 287ba41c3c1SPeter Grehan * The remaining fields should only be fussed-with by the generic 288ba41c3c1SPeter Grehan * code. 289ba41c3c1SPeter Grehan * 290ba41c3c1SPeter Grehan * Note: the addresses of vq_desc, vq_avail, and vq_used are all 291ba41c3c1SPeter Grehan * computable from each other, but it's a lot simpler if we just 292ba41c3c1SPeter Grehan * keep a pointer to each one. The event indices are similarly 293ba41c3c1SPeter Grehan * (but more easily) computable, and this time we'll compute them: 294ba41c3c1SPeter Grehan * they're just XX_ring[N]. 295ba41c3c1SPeter Grehan */ 296ba41c3c1SPeter Grehan #define VQ_ALLOC 0x01 /* set once we have a pfn */ 297ba41c3c1SPeter Grehan #define VQ_BROKED 0x02 /* ??? */ 298ba41c3c1SPeter Grehan struct vqueue_info { 299ba41c3c1SPeter Grehan uint16_t vq_qsize; /* size of this queue (a power of 2) */ 300ba41c3c1SPeter Grehan void (*vq_notify)(void *, struct vqueue_info *); 301ba41c3c1SPeter Grehan /* called instead of vc_notify, if not NULL */ 302ba41c3c1SPeter Grehan 303ba41c3c1SPeter Grehan struct virtio_softc *vq_vs; /* backpointer to softc */ 304ba41c3c1SPeter Grehan uint16_t vq_num; /* we're the num'th queue in the softc */ 305ba41c3c1SPeter Grehan 306ba41c3c1SPeter Grehan uint16_t vq_flags; /* flags (see above) */ 30754ac6f72SKa Ho Ng uint16_t vq_last_avail; /* a recent value of vq_avail->idx */ 308d55e0373SVincenzo Maffione uint16_t vq_next_used; /* index of the next used slot to be filled */ 30954ac6f72SKa Ho Ng uint16_t vq_save_used; /* saved vq_used->idx; see vq_endchains */ 310ba41c3c1SPeter Grehan uint16_t vq_msix_idx; /* MSI-X index, or VIRTIO_MSI_NO_VECTOR */ 311ba41c3c1SPeter Grehan 312ba41c3c1SPeter Grehan uint32_t vq_pfn; /* PFN of virt queue (not shifted!) */ 313ba41c3c1SPeter Grehan 314593200c2SMark Johnston struct vring_desc *vq_desc; /* descriptor array */ 315593200c2SMark Johnston struct vring_avail *vq_avail; /* the "avail" ring */ 316593200c2SMark Johnston struct vring_used *vq_used; /* the "used" ring */ 317ba41c3c1SPeter Grehan 318ba41c3c1SPeter Grehan }; 319ba41c3c1SPeter Grehan /* as noted above, these are sort of backwards, name-wise */ 320ba41c3c1SPeter Grehan #define VQ_AVAIL_EVENT_IDX(vq) \ 321593200c2SMark Johnston (*(uint16_t *)&(vq)->vq_used->ring[(vq)->vq_qsize]) 322ba41c3c1SPeter Grehan #define VQ_USED_EVENT_IDX(vq) \ 32354ac6f72SKa Ho Ng ((vq)->vq_avail->ring[(vq)->vq_qsize]) 324ba41c3c1SPeter Grehan 325ba41c3c1SPeter Grehan /* 326ba41c3c1SPeter Grehan * Is this ring ready for I/O? 327ba41c3c1SPeter Grehan */ 328ba41c3c1SPeter Grehan static inline int 329ba41c3c1SPeter Grehan vq_ring_ready(struct vqueue_info *vq) 330ba41c3c1SPeter Grehan { 331ba41c3c1SPeter Grehan 332ba41c3c1SPeter Grehan return (vq->vq_flags & VQ_ALLOC); 333ba41c3c1SPeter Grehan } 334ba41c3c1SPeter Grehan 335ba41c3c1SPeter Grehan /* 336ba41c3c1SPeter Grehan * Are there "available" descriptors? (This does not count 337ba41c3c1SPeter Grehan * how many, just returns True if there are some.) 338ba41c3c1SPeter Grehan */ 339ba41c3c1SPeter Grehan static inline int 340ba41c3c1SPeter Grehan vq_has_descs(struct vqueue_info *vq) 341ba41c3c1SPeter Grehan { 342ba41c3c1SPeter Grehan 343ba41c3c1SPeter Grehan return (vq_ring_ready(vq) && vq->vq_last_avail != 34454ac6f72SKa Ho Ng vq->vq_avail->idx); 345ba41c3c1SPeter Grehan } 346ba41c3c1SPeter Grehan 347ba41c3c1SPeter Grehan /* 348c06676beSJohn Baldwin * Deliver an interrupt to the guest for a specific MSI-X queue or 349c06676beSJohn Baldwin * event. 350c06676beSJohn Baldwin */ 351c06676beSJohn Baldwin static inline void 352c06676beSJohn Baldwin vi_interrupt(struct virtio_softc *vs, uint8_t isr, uint16_t msix_idx) 353c06676beSJohn Baldwin { 354c06676beSJohn Baldwin 355c06676beSJohn Baldwin if (pci_msix_enabled(vs->vs_pi)) 356c06676beSJohn Baldwin pci_generate_msix(vs->vs_pi, msix_idx); 357c06676beSJohn Baldwin else { 358c06676beSJohn Baldwin VS_LOCK(vs); 359c06676beSJohn Baldwin vs->vs_isr |= isr; 360c06676beSJohn Baldwin pci_generate_msi(vs->vs_pi, 0); 361c06676beSJohn Baldwin pci_lintr_assert(vs->vs_pi); 362c06676beSJohn Baldwin VS_UNLOCK(vs); 363c06676beSJohn Baldwin } 364c06676beSJohn Baldwin } 365c06676beSJohn Baldwin 366c06676beSJohn Baldwin /* 367c06676beSJohn Baldwin * Deliver an interrupt to the guest on the given virtual queue (if 368c06676beSJohn Baldwin * possible, or a generic MSI interrupt if not using MSI-X). 369ba41c3c1SPeter Grehan */ 370ba41c3c1SPeter Grehan static inline void 371ba41c3c1SPeter Grehan vq_interrupt(struct virtio_softc *vs, struct vqueue_info *vq) 372ba41c3c1SPeter Grehan { 373ba41c3c1SPeter Grehan 374c06676beSJohn Baldwin vi_interrupt(vs, VIRTIO_PCI_ISR_INTR, vq->vq_msix_idx); 375ba41c3c1SPeter Grehan } 376ba41c3c1SPeter Grehan 37717e9052cSVincenzo Maffione static inline void 37817e9052cSVincenzo Maffione vq_kick_enable(struct vqueue_info *vq) 37917e9052cSVincenzo Maffione { 38017e9052cSVincenzo Maffione 38154ac6f72SKa Ho Ng vq->vq_used->flags &= ~VRING_USED_F_NO_NOTIFY; 38217e9052cSVincenzo Maffione /* 38354ac6f72SKa Ho Ng * Full memory barrier to make sure the store to vq_used->flags 38454ac6f72SKa Ho Ng * happens before the load from vq_avail->idx, which results from a 38554ac6f72SKa Ho Ng * subsequent call to vq_has_descs(). 38617e9052cSVincenzo Maffione */ 38717e9052cSVincenzo Maffione atomic_thread_fence_seq_cst(); 38817e9052cSVincenzo Maffione } 38917e9052cSVincenzo Maffione 39017e9052cSVincenzo Maffione static inline void 39117e9052cSVincenzo Maffione vq_kick_disable(struct vqueue_info *vq) 39217e9052cSVincenzo Maffione { 39317e9052cSVincenzo Maffione 39454ac6f72SKa Ho Ng vq->vq_used->flags |= VRING_USED_F_NO_NOTIFY; 39517e9052cSVincenzo Maffione } 39617e9052cSVincenzo Maffione 397ba41c3c1SPeter Grehan struct iovec; 398b0139127SKa Ho Ng 399b0139127SKa Ho Ng /* 400b0139127SKa Ho Ng * Request description returned by vq_getchain. 401b0139127SKa Ho Ng * 402b0139127SKa Ho Ng * Writable iovecs start at iov[req.readable]. 403b0139127SKa Ho Ng */ 404b0139127SKa Ho Ng struct vi_req { 405b0139127SKa Ho Ng int readable; /* num of readable iovecs */ 406b0139127SKa Ho Ng int writable; /* num of writable iovecs */ 407b0139127SKa Ho Ng unsigned int idx; /* ring index */ 408b0139127SKa Ho Ng }; 409b0139127SKa Ho Ng 410ba41c3c1SPeter Grehan void vi_softc_linkup(struct virtio_softc *vs, struct virtio_consts *vc, 411ba41c3c1SPeter Grehan void *dev_softc, struct pci_devinst *pi, 412ba41c3c1SPeter Grehan struct vqueue_info *queues); 413ba41c3c1SPeter Grehan int vi_intr_init(struct virtio_softc *vs, int barnum, int use_msix); 414ba41c3c1SPeter Grehan void vi_reset_dev(struct virtio_softc *); 415ba41c3c1SPeter Grehan void vi_set_io_bar(struct virtio_softc *, int); 416ba41c3c1SPeter Grehan 417b0139127SKa Ho Ng int vq_getchain(struct vqueue_info *vq, struct iovec *iov, int niov, 418b0139127SKa Ho Ng struct vi_req *reqp); 419d55e0373SVincenzo Maffione void vq_retchains(struct vqueue_info *vq, uint16_t n_chains); 420d55e0373SVincenzo Maffione void vq_relchain_prepare(struct vqueue_info *vq, uint16_t idx, 421d55e0373SVincenzo Maffione uint32_t iolen); 422d55e0373SVincenzo Maffione void vq_relchain_publish(struct vqueue_info *vq); 423fdb7e97fSAlexander Motin void vq_relchain(struct vqueue_info *vq, uint16_t idx, uint32_t iolen); 424ba41c3c1SPeter Grehan void vq_endchains(struct vqueue_info *vq, int used_all_avail); 425ba41c3c1SPeter Grehan 4266a284cacSJohn Baldwin uint64_t vi_pci_read(struct pci_devinst *pi, int baridx, uint64_t offset, 4276a284cacSJohn Baldwin int size); 4286a284cacSJohn Baldwin void vi_pci_write(struct pci_devinst *pi, int baridx, uint64_t offset, 4296a284cacSJohn Baldwin int size, uint64_t value); 430483d953aSJohn Baldwin #ifdef BHYVE_SNAPSHOT 431483d953aSJohn Baldwin int vi_pci_snapshot(struct vm_snapshot_meta *meta); 4326a284cacSJohn Baldwin int vi_pci_pause(struct pci_devinst *pi); 4336a284cacSJohn Baldwin int vi_pci_resume(struct pci_devinst *pi); 434483d953aSJohn Baldwin #endif 43554ac6f72SKa Ho Ng #endif /* _BHYVE_VIRTIO_H_ */ 436