1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2022 The FreeBSD Foundation 5 * Copyright (c) 2024 Ruslan Bukin <br@bsdpad.com> 6 * 7 * This software was developed by Andrew Turner under sponsorship from 8 * the FreeBSD Foundation. 9 * 10 * This software was developed by the University of Cambridge Computer 11 * Laboratory (Department of Computer Science and Technology) under Innovate 12 * UK project 105694, "Digital Security by Design (DSbD) Technology Platform 13 * Prototype". 14 * 15 * Redistribution and use in source and binary forms, with or without 16 * modification, are permitted provided that the following conditions 17 * are met: 18 * 1. Redistributions of source code must retain the above copyright 19 * notice, this list of conditions and the following disclaimer. 20 * 2. Redistributions in binary form must reproduce the above copyright 21 * notice, this list of conditions and the following disclaimer in the 22 * documentation and/or other materials provided with the distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 */ 36 37 #include <sys/param.h> 38 39 #include <assert.h> 40 #include <errno.h> 41 #include <stdio.h> 42 #include <unistd.h> 43 44 #include <libfdt.h> 45 #include <vmmapi.h> 46 47 #include "config.h" 48 #include "bhyverun.h" 49 #include "fdt.h" 50 51 #define SET_PROP_U32(prop, idx, val) \ 52 ((uint32_t *)(prop))[(idx)] = cpu_to_fdt32(val) 53 #define SET_PROP_U64(prop, idx, val) \ 54 ((uint64_t *)(prop))[(idx)] = cpu_to_fdt64(val) 55 56 #define IRQ_TYPE_LEVEL_HIGH 4 57 #define IRQ_TYPE_LEVEL_LOW 8 58 59 static void *fdtroot; 60 static uint32_t aplic_phandle = 0; 61 static uint32_t intc0_phandle = 0; 62 63 static uint32_t 64 assign_phandle(void *fdt) 65 { 66 static uint32_t next_phandle = 1; 67 uint32_t phandle; 68 69 phandle = next_phandle; 70 next_phandle++; 71 fdt_property_u32(fdt, "phandle", phandle); 72 73 return (phandle); 74 } 75 76 static void 77 set_single_reg(void *fdt, uint64_t start, uint64_t len) 78 { 79 void *reg; 80 81 fdt_property_placeholder(fdt, "reg", 2 * sizeof(uint64_t), ®); 82 SET_PROP_U64(reg, 0, start); 83 SET_PROP_U64(reg, 1, len); 84 } 85 86 static void 87 add_cpu(void *fdt, int cpuid, const char *isa) 88 { 89 char node_name[16]; 90 91 snprintf(node_name, sizeof(node_name), "cpu@%d", cpuid); 92 93 fdt_begin_node(fdt, node_name); 94 fdt_property_string(fdt, "device_type", "cpu"); 95 fdt_property_string(fdt, "compatible", "riscv"); 96 fdt_property_u32(fdt, "reg", cpuid); 97 fdt_property_string(fdt, "riscv,isa", isa); 98 fdt_property_string(fdt, "mmu-type", "riscv,sv39"); 99 fdt_property_string(fdt, "clock-frequency", "1000000000"); 100 101 fdt_begin_node(fdt, "interrupt-controller"); 102 intc0_phandle = assign_phandle(fdt); 103 fdt_property_u32(fdt, "#address-cells", 2); 104 fdt_property_u32(fdt, "#interrupt-cells", 1); 105 fdt_property(fdt, "interrupt-controller", NULL, 0); 106 fdt_property_string(fdt, "compatible", "riscv,cpu-intc"); 107 fdt_end_node(fdt); 108 109 fdt_end_node(fdt); 110 } 111 112 static void 113 add_cpus(void *fdt, int ncpu, const char *isa) 114 { 115 int cpuid; 116 117 fdt_begin_node(fdt, "cpus"); 118 /* XXX: Needed given the root #address-cells? */ 119 fdt_property_u32(fdt, "#address-cells", 1); 120 fdt_property_u32(fdt, "#size-cells", 0); 121 fdt_property_u32(fdt, "timebase-frequency", 10000000); 122 123 for (cpuid = 0; cpuid < ncpu; cpuid++) 124 add_cpu(fdt, cpuid, isa); 125 126 fdt_end_node(fdt); 127 } 128 129 int 130 fdt_init(struct vmctx *ctx, int ncpu, vm_paddr_t fdtaddr, vm_size_t fdtsize, 131 const char *isa) 132 { 133 void *fdt; 134 const char *bootargs; 135 136 fdt = paddr_guest2host(ctx, fdtaddr, fdtsize); 137 if (fdt == NULL) 138 return (EFAULT); 139 140 fdt_create(fdt, (int)fdtsize); 141 142 /* Add the memory reserve map (needed even if none is reserved) */ 143 fdt_finish_reservemap(fdt); 144 145 /* Create the root node */ 146 fdt_begin_node(fdt, ""); 147 148 fdt_property_string(fdt, "compatible", "freebsd,bhyve"); 149 fdt_property_u32(fdt, "#address-cells", 2); 150 fdt_property_u32(fdt, "#size-cells", 2); 151 152 fdt_begin_node(fdt, "chosen"); 153 fdt_property_string(fdt, "stdout-path", "serial0:115200n8"); 154 bootargs = get_config_value("fdt.bootargs"); 155 if (bootargs != NULL) 156 fdt_property_string(fdt, "bootargs", bootargs); 157 fdt_end_node(fdt); 158 159 fdt_begin_node(fdt, "memory"); 160 fdt_property_string(fdt, "device_type", "memory"); 161 /* There is no lowmem on riscv. */ 162 assert(vm_get_lowmem_size(ctx) == 0); 163 set_single_reg(fdt, vm_get_highmem_base(ctx), vm_get_highmem_size(ctx)); 164 fdt_end_node(fdt); 165 166 add_cpus(fdt, ncpu, isa); 167 168 /* Finalized by fdt_finalized(). */ 169 fdtroot = fdt; 170 171 return (0); 172 } 173 174 void 175 fdt_add_aplic(uint64_t mem_base, uint64_t mem_size) 176 { 177 char node_name[32]; 178 void *fdt, *prop; 179 180 fdt = fdtroot; 181 182 snprintf(node_name, sizeof(node_name), "interrupt-controller@%lx", 183 (unsigned long)mem_base); 184 fdt_begin_node(fdt, node_name); 185 186 aplic_phandle = assign_phandle(fdt); 187 fdt_property_string(fdt, "compatible", "riscv,aplic"); 188 fdt_property(fdt, "interrupt-controller", NULL, 0); 189 #if notyet 190 fdt_property(fdt, "msi-controller", NULL, 0); 191 #endif 192 /* XXX: Needed given the root #address-cells? */ 193 fdt_property_u32(fdt, "#address-cells", 2); 194 fdt_property_u32(fdt, "#interrupt-cells", 2); 195 fdt_property_placeholder(fdt, "reg", 2 * sizeof(uint64_t), &prop); 196 SET_PROP_U64(prop, 0, mem_base); 197 SET_PROP_U64(prop, 1, mem_size); 198 199 fdt_property_placeholder(fdt, "interrupts-extended", 200 2 * sizeof(uint32_t), &prop); 201 SET_PROP_U32(prop, 0, intc0_phandle); 202 SET_PROP_U32(prop, 1, 9); 203 fdt_property_u32(fdt, "riscv,num-sources", 63); 204 205 fdt_end_node(fdt); 206 207 fdt_property_u32(fdt, "interrupt-parent", aplic_phandle); 208 } 209 210 void 211 fdt_add_uart(uint64_t uart_base, uint64_t uart_size, int intr) 212 { 213 void *fdt, *interrupts; 214 char node_name[32]; 215 216 assert(aplic_phandle != 0); 217 218 fdt = fdtroot; 219 220 snprintf(node_name, sizeof(node_name), "serial@%lx", uart_base); 221 fdt_begin_node(fdt, node_name); 222 fdt_property_string(fdt, "compatible", "ns16550"); 223 set_single_reg(fdt, uart_base, uart_size); 224 fdt_property_u32(fdt, "interrupt-parent", aplic_phandle); 225 fdt_property_placeholder(fdt, "interrupts", 2 * sizeof(uint32_t), 226 &interrupts); 227 SET_PROP_U32(interrupts, 0, intr); 228 SET_PROP_U32(interrupts, 1, IRQ_TYPE_LEVEL_HIGH); 229 230 fdt_end_node(fdt); 231 232 snprintf(node_name, sizeof(node_name), "/serial@%lx", uart_base); 233 fdt_begin_node(fdt, "aliases"); 234 fdt_property_string(fdt, "serial0", node_name); 235 fdt_end_node(fdt); 236 } 237 238 void 239 fdt_add_pcie(int intrs[static 4]) 240 { 241 void *fdt, *prop; 242 int slot, pin, intr, i; 243 244 assert(aplic_phandle != 0); 245 246 fdt = fdtroot; 247 248 fdt_begin_node(fdt, "pcie@1f0000000"); 249 fdt_property_string(fdt, "compatible", "pci-host-ecam-generic"); 250 fdt_property_u32(fdt, "#address-cells", 3); 251 fdt_property_u32(fdt, "#size-cells", 2); 252 fdt_property_string(fdt, "device_type", "pci"); 253 fdt_property_u64(fdt, "bus-range", (0ul << 32) | 1); 254 set_single_reg(fdt, 0xe0000000, 0x10000000); 255 fdt_property_placeholder(fdt, "ranges", 256 2 * 7 * sizeof(uint32_t), &prop); 257 SET_PROP_U32(prop, 0, 0x01000000); 258 259 SET_PROP_U32(prop, 1, 0); 260 SET_PROP_U32(prop, 2, 0xdf000000); 261 262 SET_PROP_U32(prop, 3, 0); 263 SET_PROP_U32(prop, 4, 0xdf000000); 264 265 SET_PROP_U32(prop, 5, 0); 266 SET_PROP_U32(prop, 6, 0x01000000); 267 268 SET_PROP_U32(prop, 7, 0x02000000); 269 270 SET_PROP_U32(prop, 8, 0); 271 SET_PROP_U32(prop, 9, 0xa0000000); 272 273 SET_PROP_U32(prop, 10, 0); 274 SET_PROP_U32(prop, 11, 0xa0000000); 275 276 SET_PROP_U32(prop, 12, 0); 277 SET_PROP_U32(prop, 13, 0x3f000000); 278 279 #if notyet 280 fdt_property_placeholder(fdt, "msi-map", 4 * sizeof(uint32_t), &prop); 281 SET_PROP_U32(prop, 0, 0); /* RID base */ 282 SET_PROP_U32(prop, 1, aplic_phandle); /* MSI parent */ 283 SET_PROP_U32(prop, 2, 0); /* MSI base */ 284 SET_PROP_U32(prop, 3, 0x10000); /* RID length */ 285 fdt_property_u32(fdt, "msi-parent", aplic_phandle); 286 #endif 287 288 fdt_property_u32(fdt, "#interrupt-cells", 1); 289 fdt_property_u32(fdt, "interrupt-parent", aplic_phandle); 290 291 /* 292 * Describe standard swizzled interrupts routing (pins rotated by one 293 * for each consecutive slot). Must match pci_irq_route(). 294 */ 295 fdt_property_placeholder(fdt, "interrupt-map-mask", 296 4 * sizeof(uint32_t), &prop); 297 SET_PROP_U32(prop, 0, 3 << 11); 298 SET_PROP_U32(prop, 1, 0); 299 SET_PROP_U32(prop, 2, 0); 300 SET_PROP_U32(prop, 3, 7); 301 fdt_property_placeholder(fdt, "interrupt-map", 302 16 * 9 * sizeof(uint32_t), &prop); 303 for (i = 0; i < 16; ++i) { 304 pin = i % 4; 305 slot = i / 4; 306 intr = intrs[(pin + slot) % 4]; 307 SET_PROP_U32(prop, 10 * i + 0, slot << 11); 308 SET_PROP_U32(prop, 10 * i + 1, 0); 309 SET_PROP_U32(prop, 10 * i + 2, 0); 310 SET_PROP_U32(prop, 10 * i + 3, pin + 1); 311 SET_PROP_U32(prop, 10 * i + 4, aplic_phandle); 312 SET_PROP_U32(prop, 10 * i + 5, 0); 313 SET_PROP_U32(prop, 10 * i + 6, 0); 314 SET_PROP_U32(prop, 10 * i + 7, intr); 315 SET_PROP_U32(prop, 10 * i + 8, IRQ_TYPE_LEVEL_HIGH); 316 } 317 318 fdt_end_node(fdt); 319 } 320 321 void 322 fdt_finalize(void) 323 { 324 fdt_end_node(fdtroot); 325 326 fdt_finish(fdtroot); 327 } 328