1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2022 The FreeBSD Foundation 5 * Copyright (c) 2024 Ruslan Bukin <br@bsdpad.com> 6 * 7 * This software was developed by Andrew Turner under sponsorship from 8 * the FreeBSD Foundation. 9 * 10 * This software was developed by the University of Cambridge Computer 11 * Laboratory (Department of Computer Science and Technology) under Innovate 12 * UK project 105694, "Digital Security by Design (DSbD) Technology Platform 13 * Prototype". 14 * 15 * Redistribution and use in source and binary forms, with or without 16 * modification, are permitted provided that the following conditions 17 * are met: 18 * 1. Redistributions of source code must retain the above copyright 19 * notice, this list of conditions and the following disclaimer. 20 * 2. Redistributions in binary form must reproduce the above copyright 21 * notice, this list of conditions and the following disclaimer in the 22 * documentation and/or other materials provided with the distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 */ 36 37 #include <sys/param.h> 38 39 #include <assert.h> 40 #include <errno.h> 41 #include <stdio.h> 42 #include <unistd.h> 43 44 #include <libfdt.h> 45 #include <vmmapi.h> 46 47 #include "config.h" 48 #include "bhyverun.h" 49 #include "fdt.h" 50 51 #define SET_PROP_U32(prop, idx, val) \ 52 ((uint32_t *)(prop))[(idx)] = cpu_to_fdt32(val) 53 #define SET_PROP_U64(prop, idx, val) \ 54 ((uint64_t *)(prop))[(idx)] = cpu_to_fdt64(val) 55 56 #define IRQ_TYPE_LEVEL_HIGH 4 57 #define IRQ_TYPE_LEVEL_LOW 8 58 59 static void *fdtroot; 60 static uint32_t aplic_phandle = 0; 61 static uint32_t intc0_phandle = 0; 62 63 static uint32_t 64 assign_phandle(void *fdt) 65 { 66 static uint32_t next_phandle = 1; 67 uint32_t phandle; 68 69 phandle = next_phandle; 70 next_phandle++; 71 fdt_property_u32(fdt, "phandle", phandle); 72 73 return (phandle); 74 } 75 76 static void 77 set_single_reg(void *fdt, uint64_t start, uint64_t len) 78 { 79 void *reg; 80 81 fdt_property_placeholder(fdt, "reg", 2 * sizeof(uint64_t), ®); 82 SET_PROP_U64(reg, 0, start); 83 SET_PROP_U64(reg, 1, len); 84 } 85 86 static void 87 add_cpu(void *fdt, int cpuid) 88 { 89 char node_name[16]; 90 91 snprintf(node_name, sizeof(node_name), "cpu@%d", cpuid); 92 93 fdt_begin_node(fdt, node_name); 94 fdt_property_string(fdt, "device_type", "cpu"); 95 fdt_property_string(fdt, "compatible", "riscv"); 96 fdt_property_u32(fdt, "reg", cpuid); 97 fdt_property_string(fdt, "riscv,isa", "rv64imafdc_sstc"); 98 fdt_property_string(fdt, "mmu-type", "riscv,sv39"); 99 fdt_property_string(fdt, "clock-frequency", "1000000000"); 100 101 fdt_begin_node(fdt, "interrupt-controller"); 102 intc0_phandle = assign_phandle(fdt); 103 fdt_property_u32(fdt, "#address-cells", 2); 104 fdt_property_u32(fdt, "#interrupt-cells", 1); 105 fdt_property(fdt, "interrupt-controller", NULL, 0); 106 fdt_property_string(fdt, "compatible", "riscv,cpu-intc"); 107 fdt_end_node(fdt); 108 109 fdt_end_node(fdt); 110 } 111 112 static void 113 add_cpus(void *fdt, int ncpu) 114 { 115 int cpuid; 116 117 fdt_begin_node(fdt, "cpus"); 118 /* XXX: Needed given the root #address-cells? */ 119 fdt_property_u32(fdt, "#address-cells", 1); 120 fdt_property_u32(fdt, "#size-cells", 0); 121 fdt_property_u32(fdt, "timebase-frequency", 10000000); 122 123 for (cpuid = 0; cpuid < ncpu; cpuid++) { 124 add_cpu(fdt, cpuid); 125 } 126 fdt_end_node(fdt); 127 } 128 129 int 130 fdt_init(struct vmctx *ctx, int ncpu, vm_paddr_t fdtaddr, vm_size_t fdtsize) 131 { 132 void *fdt; 133 const char *bootargs; 134 135 fdt = paddr_guest2host(ctx, fdtaddr, fdtsize); 136 if (fdt == NULL) 137 return (EFAULT); 138 139 fdt_create(fdt, (int)fdtsize); 140 141 /* Add the memory reserve map (needed even if none is reserved) */ 142 fdt_finish_reservemap(fdt); 143 144 /* Create the root node */ 145 fdt_begin_node(fdt, ""); 146 147 fdt_property_string(fdt, "compatible", "freebsd,bhyve"); 148 fdt_property_u32(fdt, "#address-cells", 2); 149 fdt_property_u32(fdt, "#size-cells", 2); 150 151 fdt_begin_node(fdt, "chosen"); 152 fdt_property_string(fdt, "stdout-path", "serial0:115200n8"); 153 bootargs = get_config_value("fdt.bootargs"); 154 if (bootargs != NULL) 155 fdt_property_string(fdt, "bootargs", bootargs); 156 fdt_end_node(fdt); 157 158 fdt_begin_node(fdt, "memory"); 159 fdt_property_string(fdt, "device_type", "memory"); 160 /* There is no lowmem on riscv. */ 161 assert(vm_get_lowmem_size(ctx) == 0); 162 set_single_reg(fdt, vm_get_highmem_base(ctx), vm_get_highmem_size(ctx)); 163 fdt_end_node(fdt); 164 165 add_cpus(fdt, ncpu); 166 167 /* Finalized by fdt_finalized(). */ 168 fdtroot = fdt; 169 170 return (0); 171 } 172 173 void 174 fdt_add_aplic(uint64_t mem_base, uint64_t mem_size) 175 { 176 char node_name[32]; 177 void *fdt, *prop; 178 179 fdt = fdtroot; 180 181 snprintf(node_name, sizeof(node_name), "interrupt-controller@%lx", 182 (unsigned long)mem_base); 183 fdt_begin_node(fdt, node_name); 184 185 aplic_phandle = assign_phandle(fdt); 186 fdt_property_string(fdt, "compatible", "riscv,aplic"); 187 fdt_property(fdt, "interrupt-controller", NULL, 0); 188 #if notyet 189 fdt_property(fdt, "msi-controller", NULL, 0); 190 #endif 191 /* XXX: Needed given the root #address-cells? */ 192 fdt_property_u32(fdt, "#address-cells", 2); 193 fdt_property_u32(fdt, "#interrupt-cells", 2); 194 fdt_property_placeholder(fdt, "reg", 2 * sizeof(uint64_t), &prop); 195 SET_PROP_U64(prop, 0, mem_base); 196 SET_PROP_U64(prop, 1, mem_size); 197 198 fdt_property_placeholder(fdt, "interrupts-extended", 199 2 * sizeof(uint32_t), &prop); 200 SET_PROP_U32(prop, 0, intc0_phandle); 201 SET_PROP_U32(prop, 1, 9); 202 fdt_property_u32(fdt, "riscv,num-sources", 63); 203 204 fdt_end_node(fdt); 205 206 fdt_property_u32(fdt, "interrupt-parent", aplic_phandle); 207 } 208 209 void 210 fdt_add_uart(uint64_t uart_base, uint64_t uart_size, int intr) 211 { 212 void *fdt, *interrupts; 213 char node_name[32]; 214 215 assert(aplic_phandle != 0); 216 217 fdt = fdtroot; 218 219 snprintf(node_name, sizeof(node_name), "serial@%lx", uart_base); 220 fdt_begin_node(fdt, node_name); 221 fdt_property_string(fdt, "compatible", "ns16550"); 222 set_single_reg(fdt, uart_base, uart_size); 223 fdt_property_u32(fdt, "interrupt-parent", aplic_phandle); 224 fdt_property_placeholder(fdt, "interrupts", 2 * sizeof(uint32_t), 225 &interrupts); 226 SET_PROP_U32(interrupts, 0, intr); 227 SET_PROP_U32(interrupts, 1, IRQ_TYPE_LEVEL_HIGH); 228 229 fdt_end_node(fdt); 230 231 snprintf(node_name, sizeof(node_name), "/serial@%lx", uart_base); 232 fdt_begin_node(fdt, "aliases"); 233 fdt_property_string(fdt, "serial0", node_name); 234 fdt_end_node(fdt); 235 } 236 237 void 238 fdt_add_pcie(int intrs[static 4]) 239 { 240 void *fdt, *prop; 241 int slot, pin, intr, i; 242 243 assert(aplic_phandle != 0); 244 245 fdt = fdtroot; 246 247 fdt_begin_node(fdt, "pcie@1f0000000"); 248 fdt_property_string(fdt, "compatible", "pci-host-ecam-generic"); 249 fdt_property_u32(fdt, "#address-cells", 3); 250 fdt_property_u32(fdt, "#size-cells", 2); 251 fdt_property_string(fdt, "device_type", "pci"); 252 fdt_property_u64(fdt, "bus-range", (0ul << 32) | 1); 253 set_single_reg(fdt, 0xe0000000, 0x10000000); 254 fdt_property_placeholder(fdt, "ranges", 255 2 * 7 * sizeof(uint32_t), &prop); 256 SET_PROP_U32(prop, 0, 0x01000000); 257 258 SET_PROP_U32(prop, 1, 0); 259 SET_PROP_U32(prop, 2, 0xdf000000); 260 261 SET_PROP_U32(prop, 3, 0); 262 SET_PROP_U32(prop, 4, 0xdf000000); 263 264 SET_PROP_U32(prop, 5, 0); 265 SET_PROP_U32(prop, 6, 0x01000000); 266 267 SET_PROP_U32(prop, 7, 0x02000000); 268 269 SET_PROP_U32(prop, 8, 0); 270 SET_PROP_U32(prop, 9, 0xa0000000); 271 272 SET_PROP_U32(prop, 10, 0); 273 SET_PROP_U32(prop, 11, 0xa0000000); 274 275 SET_PROP_U32(prop, 12, 0); 276 SET_PROP_U32(prop, 13, 0x3f000000); 277 278 #if notyet 279 fdt_property_placeholder(fdt, "msi-map", 4 * sizeof(uint32_t), &prop); 280 SET_PROP_U32(prop, 0, 0); /* RID base */ 281 SET_PROP_U32(prop, 1, aplic_phandle); /* MSI parent */ 282 SET_PROP_U32(prop, 2, 0); /* MSI base */ 283 SET_PROP_U32(prop, 3, 0x10000); /* RID length */ 284 fdt_property_u32(fdt, "msi-parent", aplic_phandle); 285 #endif 286 287 fdt_property_u32(fdt, "#interrupt-cells", 1); 288 fdt_property_u32(fdt, "interrupt-parent", aplic_phandle); 289 290 /* 291 * Describe standard swizzled interrupts routing (pins rotated by one 292 * for each consecutive slot). Must match pci_irq_route(). 293 */ 294 fdt_property_placeholder(fdt, "interrupt-map-mask", 295 4 * sizeof(uint32_t), &prop); 296 SET_PROP_U32(prop, 0, 3 << 11); 297 SET_PROP_U32(prop, 1, 0); 298 SET_PROP_U32(prop, 2, 0); 299 SET_PROP_U32(prop, 3, 7); 300 fdt_property_placeholder(fdt, "interrupt-map", 301 16 * 9 * sizeof(uint32_t), &prop); 302 for (i = 0; i < 16; ++i) { 303 pin = i % 4; 304 slot = i / 4; 305 intr = intrs[(pin + slot) % 4]; 306 SET_PROP_U32(prop, 10 * i + 0, slot << 11); 307 SET_PROP_U32(prop, 10 * i + 1, 0); 308 SET_PROP_U32(prop, 10 * i + 2, 0); 309 SET_PROP_U32(prop, 10 * i + 3, pin + 1); 310 SET_PROP_U32(prop, 10 * i + 4, aplic_phandle); 311 SET_PROP_U32(prop, 10 * i + 5, 0); 312 SET_PROP_U32(prop, 10 * i + 6, 0); 313 SET_PROP_U32(prop, 10 * i + 7, intr); 314 SET_PROP_U32(prop, 10 * i + 8, IRQ_TYPE_LEVEL_HIGH); 315 } 316 317 fdt_end_node(fdt); 318 } 319 320 void 321 fdt_finalize(void) 322 { 323 fdt_end_node(fdtroot); 324 325 fdt_finish(fdtroot); 326 } 327