1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2014 Leon Dang <ldang@nahannisys.com> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 */ 30 31 #ifndef _PCI_XHCI_H_ 32 #define _PCI_XHCI_H_ 33 34 #define PCI_USBREV 0x60 /* USB protocol revision */ 35 36 37 enum { /* dsc_slotstate */ 38 XHCI_ST_DISABLED, 39 XHCI_ST_ENABLED, 40 XHCI_ST_DEFAULT, 41 XHCI_ST_ADDRESSED, 42 XHCI_ST_CONFIGURED, 43 XHCI_ST_MAX 44 }; 45 46 enum { 47 XHCI_ST_SLCTX_DISABLED, 48 XHCI_ST_SLCTX_DEFAULT, 49 XHCI_ST_SLCTX_ADDRESSED, 50 XHCI_ST_SLCTX_CONFIGURED 51 }; 52 53 enum { 54 XHCI_ST_EPCTX_DISABLED, 55 XHCI_ST_EPCTX_RUNNING, 56 XHCI_ST_EPCTX_HALTED, 57 XHCI_ST_EPCTX_STOPPED, 58 XHCI_ST_EPCTX_ERROR 59 }; 60 61 #define XHCI_MAX_DEVICES MIN(USB_MAX_DEVICES, 128) 62 #define XHCI_MAX_ENDPOINTS 32 /* hardcoded - do not change */ 63 #define XHCI_MAX_SCRATCHPADS 32 64 #define XHCI_MAX_EVENTS (16 * 13) 65 #define XHCI_MAX_COMMANDS (16 * 1) 66 #define XHCI_MAX_RSEG 1 67 #define XHCI_MAX_TRANSFERS 4 68 #if USB_MAX_EP_STREAMS == 8 69 #define XHCI_MAX_STREAMS 8 70 #define XHCI_MAX_STREAMS_LOG 3 71 #elif USB_MAX_EP_STREAMS == 1 72 #define XHCI_MAX_STREAMS 1 73 #define XHCI_MAX_STREAMS_LOG 0 74 #else 75 #error "The USB_MAX_EP_STREAMS value is not supported." 76 #endif 77 #define XHCI_DEV_CTX_ADDR_ALIGN 64 /* bytes */ 78 #define XHCI_DEV_CTX_ALIGN 64 /* bytes */ 79 #define XHCI_INPUT_CTX_ALIGN 64 /* bytes */ 80 #define XHCI_SLOT_CTX_ALIGN 32 /* bytes */ 81 #define XHCI_ENDP_CTX_ALIGN 32 /* bytes */ 82 #define XHCI_STREAM_CTX_ALIGN 16 /* bytes */ 83 #define XHCI_TRANS_RING_SEG_ALIGN 16 /* bytes */ 84 #define XHCI_CMD_RING_SEG_ALIGN 64 /* bytes */ 85 #define XHCI_EVENT_RING_SEG_ALIGN 64 /* bytes */ 86 #define XHCI_SCRATCH_BUF_ARRAY_ALIGN 64 /* bytes */ 87 #define XHCI_SCRATCH_BUFFER_ALIGN USB_PAGE_SIZE 88 #define XHCI_TRB_ALIGN 16 /* bytes */ 89 #define XHCI_TD_ALIGN 64 /* bytes */ 90 #define XHCI_PAGE_SIZE 4096 /* bytes */ 91 92 struct xhci_slot_ctx { 93 uint32_t dwSctx0; 94 #define XHCI_SCTX_0_ROUTE_SET(x) ((x) & 0xFFFFF) 95 #define XHCI_SCTX_0_ROUTE_GET(x) ((x) & 0xFFFFF) 96 #define XHCI_SCTX_0_SPEED_SET(x) (((x) & 0xF) << 20) 97 #define XHCI_SCTX_0_SPEED_GET(x) (((x) >> 20) & 0xF) 98 #define XHCI_SCTX_0_MTT_SET(x) (((x) & 0x1) << 25) 99 #define XHCI_SCTX_0_MTT_GET(x) (((x) >> 25) & 0x1) 100 #define XHCI_SCTX_0_HUB_SET(x) (((x) & 0x1) << 26) 101 #define XHCI_SCTX_0_HUB_GET(x) (((x) >> 26) & 0x1) 102 #define XHCI_SCTX_0_CTX_NUM_SET(x) (((x) & 0x1F) << 27) 103 #define XHCI_SCTX_0_CTX_NUM_GET(x) (((x) >> 27) & 0x1F) 104 uint32_t dwSctx1; 105 #define XHCI_SCTX_1_MAX_EL_SET(x) ((x) & 0xFFFF) 106 #define XHCI_SCTX_1_MAX_EL_GET(x) ((x) & 0xFFFF) 107 #define XHCI_SCTX_1_RH_PORT_SET(x) (((x) & 0xFF) << 16) 108 #define XHCI_SCTX_1_RH_PORT_GET(x) (((x) >> 16) & 0xFF) 109 #define XHCI_SCTX_1_NUM_PORTS_SET(x) (((x) & 0xFF) << 24) 110 #define XHCI_SCTX_1_NUM_PORTS_GET(x) (((x) >> 24) & 0xFF) 111 uint32_t dwSctx2; 112 #define XHCI_SCTX_2_TT_HUB_SID_SET(x) ((x) & 0xFF) 113 #define XHCI_SCTX_2_TT_HUB_SID_GET(x) ((x) & 0xFF) 114 #define XHCI_SCTX_2_TT_PORT_NUM_SET(x) (((x) & 0xFF) << 8) 115 #define XHCI_SCTX_2_TT_PORT_NUM_GET(x) (((x) >> 8) & 0xFF) 116 #define XHCI_SCTX_2_TT_THINK_TIME_SET(x) (((x) & 0x3) << 16) 117 #define XHCI_SCTX_2_TT_THINK_TIME_GET(x) (((x) >> 16) & 0x3) 118 #define XHCI_SCTX_2_IRQ_TARGET_SET(x) (((x) & 0x3FF) << 22) 119 #define XHCI_SCTX_2_IRQ_TARGET_GET(x) (((x) >> 22) & 0x3FF) 120 uint32_t dwSctx3; 121 #define XHCI_SCTX_3_DEV_ADDR_SET(x) ((x) & 0xFF) 122 #define XHCI_SCTX_3_DEV_ADDR_GET(x) ((x) & 0xFF) 123 #define XHCI_SCTX_3_SLOT_STATE_SET(x) (((x) & 0x1F) << 27) 124 #define XHCI_SCTX_3_SLOT_STATE_GET(x) (((x) >> 27) & 0x1F) 125 uint32_t dwSctx4; 126 uint32_t dwSctx5; 127 uint32_t dwSctx6; 128 uint32_t dwSctx7; 129 }; 130 131 struct xhci_endp_ctx { 132 uint32_t dwEpCtx0; 133 #define XHCI_EPCTX_0_EPSTATE_SET(x) ((x) & 0x7) 134 #define XHCI_EPCTX_0_EPSTATE_GET(x) ((x) & 0x7) 135 #define XHCI_EPCTX_0_MULT_SET(x) (((x) & 0x3) << 8) 136 #define XHCI_EPCTX_0_MULT_GET(x) (((x) >> 8) & 0x3) 137 #define XHCI_EPCTX_0_MAXP_STREAMS_SET(x) (((x) & 0x1F) << 10) 138 #define XHCI_EPCTX_0_MAXP_STREAMS_GET(x) (((x) >> 10) & 0x1F) 139 #define XHCI_EPCTX_0_LSA_SET(x) (((x) & 0x1) << 15) 140 #define XHCI_EPCTX_0_LSA_GET(x) (((x) >> 15) & 0x1) 141 #define XHCI_EPCTX_0_IVAL_SET(x) (((x) & 0xFF) << 16) 142 #define XHCI_EPCTX_0_IVAL_GET(x) (((x) >> 16) & 0xFF) 143 uint32_t dwEpCtx1; 144 #define XHCI_EPCTX_1_CERR_SET(x) (((x) & 0x3) << 1) 145 #define XHCI_EPCTX_1_CERR_GET(x) (((x) >> 1) & 0x3) 146 #define XHCI_EPCTX_1_EPTYPE_SET(x) (((x) & 0x7) << 3) 147 #define XHCI_EPCTX_1_EPTYPE_GET(x) (((x) >> 3) & 0x7) 148 #define XHCI_EPCTX_1_HID_SET(x) (((x) & 0x1) << 7) 149 #define XHCI_EPCTX_1_HID_GET(x) (((x) >> 7) & 0x1) 150 #define XHCI_EPCTX_1_MAXB_SET(x) (((x) & 0xFF) << 8) 151 #define XHCI_EPCTX_1_MAXB_GET(x) (((x) >> 8) & 0xFF) 152 #define XHCI_EPCTX_1_MAXP_SIZE_SET(x) (((x) & 0xFFFF) << 16) 153 #define XHCI_EPCTX_1_MAXP_SIZE_GET(x) (((x) >> 16) & 0xFFFF) 154 uint64_t qwEpCtx2; 155 #define XHCI_EPCTX_2_DCS_SET(x) ((x) & 0x1) 156 #define XHCI_EPCTX_2_DCS_GET(x) ((x) & 0x1) 157 #define XHCI_EPCTX_2_TR_DQ_PTR_MASK 0xFFFFFFFFFFFFFFF0U 158 uint32_t dwEpCtx4; 159 #define XHCI_EPCTX_4_AVG_TRB_LEN_SET(x) ((x) & 0xFFFF) 160 #define XHCI_EPCTX_4_AVG_TRB_LEN_GET(x) ((x) & 0xFFFF) 161 #define XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(x) (((x) & 0xFFFF) << 16) 162 #define XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_GET(x) (((x) >> 16) & 0xFFFF) 163 uint32_t dwEpCtx5; 164 uint32_t dwEpCtx6; 165 uint32_t dwEpCtx7; 166 }; 167 168 struct xhci_input_ctx { 169 #define XHCI_INCTX_NON_CTRL_MASK 0xFFFFFFFCU 170 uint32_t dwInCtx0; 171 #define XHCI_INCTX_0_DROP_MASK(n) (1U << (n)) 172 uint32_t dwInCtx1; 173 #define XHCI_INCTX_1_ADD_MASK(n) (1U << (n)) 174 uint32_t dwInCtx2; 175 uint32_t dwInCtx3; 176 uint32_t dwInCtx4; 177 uint32_t dwInCtx5; 178 uint32_t dwInCtx6; 179 uint32_t dwInCtx7; 180 }; 181 182 struct xhci_input_dev_ctx { 183 struct xhci_input_ctx ctx_input; 184 union { 185 struct xhci_slot_ctx u_slot; 186 struct xhci_endp_ctx u_ep[XHCI_MAX_ENDPOINTS]; 187 } ctx_dev_slep; 188 }; 189 190 struct xhci_dev_ctx { 191 union { 192 struct xhci_slot_ctx u_slot; 193 struct xhci_endp_ctx u_ep[XHCI_MAX_ENDPOINTS]; 194 } ctx_dev_slep; 195 } __aligned(XHCI_DEV_CTX_ALIGN); 196 #define ctx_slot ctx_dev_slep.u_slot 197 #define ctx_ep ctx_dev_slep.u_ep 198 199 struct xhci_stream_ctx { 200 uint64_t qwSctx0; 201 #define XHCI_SCTX_0_DCS_GET(x) ((x) & 0x1) 202 #define XHCI_SCTX_0_DCS_SET(x) ((x) & 0x1) 203 #define XHCI_SCTX_0_SCT_SET(x) (((x) & 0x7) << 1) 204 #define XHCI_SCTX_0_SCT_GET(x) (((x) >> 1) & 0x7) 205 #define XHCI_SCTX_0_SCT_SEC_TR_RING 0x0 206 #define XHCI_SCTX_0_SCT_PRIM_TR_RING 0x1 207 #define XHCI_SCTX_0_SCT_PRIM_SSA_8 0x2 208 #define XHCI_SCTX_0_SCT_PRIM_SSA_16 0x3 209 #define XHCI_SCTX_0_SCT_PRIM_SSA_32 0x4 210 #define XHCI_SCTX_0_SCT_PRIM_SSA_64 0x5 211 #define XHCI_SCTX_0_SCT_PRIM_SSA_128 0x6 212 #define XHCI_SCTX_0_SCT_PRIM_SSA_256 0x7 213 #define XHCI_SCTX_0_TR_DQ_PTR_MASK 0xFFFFFFFFFFFFFFF0U 214 uint32_t dwSctx2; 215 uint32_t dwSctx3; 216 }; 217 218 struct xhci_trb { 219 uint64_t qwTrb0; 220 #define XHCI_TRB_0_DIR_IN_MASK (0x80ULL << 0) 221 #define XHCI_TRB_0_WLENGTH_MASK (0xFFFFULL << 48) 222 uint32_t dwTrb2; 223 #define XHCI_TRB_2_ERROR_GET(x) (((x) >> 24) & 0xFF) 224 #define XHCI_TRB_2_ERROR_SET(x) (((x) & 0xFF) << 24) 225 #define XHCI_TRB_2_TDSZ_GET(x) (((x) >> 17) & 0x1F) 226 #define XHCI_TRB_2_TDSZ_SET(x) (((x) & 0x1F) << 17) 227 #define XHCI_TRB_2_REM_GET(x) ((x) & 0xFFFFFF) 228 #define XHCI_TRB_2_REM_SET(x) ((x) & 0xFFFFFF) 229 #define XHCI_TRB_2_BYTES_GET(x) ((x) & 0x1FFFF) 230 #define XHCI_TRB_2_BYTES_SET(x) ((x) & 0x1FFFF) 231 #define XHCI_TRB_2_IRQ_GET(x) (((x) >> 22) & 0x3FF) 232 #define XHCI_TRB_2_IRQ_SET(x) (((x) & 0x3FF) << 22) 233 #define XHCI_TRB_2_STREAM_GET(x) (((x) >> 16) & 0xFFFF) 234 #define XHCI_TRB_2_STREAM_SET(x) (((x) & 0xFFFF) << 16) 235 236 uint32_t dwTrb3; 237 #define XHCI_TRB_3_TYPE_GET(x) (((x) >> 10) & 0x3F) 238 #define XHCI_TRB_3_TYPE_SET(x) (((x) & 0x3F) << 10) 239 #define XHCI_TRB_3_CYCLE_BIT (1U << 0) 240 #define XHCI_TRB_3_TC_BIT (1U << 1) /* command ring only */ 241 #define XHCI_TRB_3_ENT_BIT (1U << 1) /* transfer ring only */ 242 #define XHCI_TRB_3_ISP_BIT (1U << 2) 243 #define XHCI_TRB_3_ED_BIT (1U << 2) 244 #define XHCI_TRB_3_NSNOOP_BIT (1U << 3) 245 #define XHCI_TRB_3_CHAIN_BIT (1U << 4) 246 #define XHCI_TRB_3_IOC_BIT (1U << 5) 247 #define XHCI_TRB_3_IDT_BIT (1U << 6) 248 #define XHCI_TRB_3_TBC_GET(x) (((x) >> 7) & 3) 249 #define XHCI_TRB_3_TBC_SET(x) (((x) & 3) << 7) 250 #define XHCI_TRB_3_BEI_BIT (1U << 9) 251 #define XHCI_TRB_3_DCEP_BIT (1U << 9) 252 #define XHCI_TRB_3_PRSV_BIT (1U << 9) 253 #define XHCI_TRB_3_BSR_BIT (1U << 9) 254 #define XHCI_TRB_3_TRT_MASK (3U << 16) 255 #define XHCI_TRB_3_TRT_NONE (0U << 16) 256 #define XHCI_TRB_3_TRT_OUT (2U << 16) 257 #define XHCI_TRB_3_TRT_IN (3U << 16) 258 #define XHCI_TRB_3_DIR_IN (1U << 16) 259 #define XHCI_TRB_3_TLBPC_GET(x) (((x) >> 16) & 0xF) 260 #define XHCI_TRB_3_TLBPC_SET(x) (((x) & 0xF) << 16) 261 #define XHCI_TRB_3_EP_GET(x) (((x) >> 16) & 0x1F) 262 #define XHCI_TRB_3_EP_SET(x) (((x) & 0x1F) << 16) 263 #define XHCI_TRB_3_FRID_GET(x) (((x) >> 20) & 0x7FF) 264 #define XHCI_TRB_3_FRID_SET(x) (((x) & 0x7FF) << 20) 265 #define XHCI_TRB_3_ISO_SIA_BIT (1U << 31) 266 #define XHCI_TRB_3_SUSP_EP_BIT (1U << 23) 267 #define XHCI_TRB_3_SLOT_GET(x) (((x) >> 24) & 0xFF) 268 #define XHCI_TRB_3_SLOT_SET(x) (((x) & 0xFF) << 24) 269 270 /* Commands */ 271 #define XHCI_TRB_TYPE_RESERVED 0x00 272 #define XHCI_TRB_TYPE_NORMAL 0x01 273 #define XHCI_TRB_TYPE_SETUP_STAGE 0x02 274 #define XHCI_TRB_TYPE_DATA_STAGE 0x03 275 #define XHCI_TRB_TYPE_STATUS_STAGE 0x04 276 #define XHCI_TRB_TYPE_ISOCH 0x05 277 #define XHCI_TRB_TYPE_LINK 0x06 278 #define XHCI_TRB_TYPE_EVENT_DATA 0x07 279 #define XHCI_TRB_TYPE_NOOP 0x08 280 #define XHCI_TRB_TYPE_ENABLE_SLOT 0x09 281 #define XHCI_TRB_TYPE_DISABLE_SLOT 0x0A 282 #define XHCI_TRB_TYPE_ADDRESS_DEVICE 0x0B 283 #define XHCI_TRB_TYPE_CONFIGURE_EP 0x0C 284 #define XHCI_TRB_TYPE_EVALUATE_CTX 0x0D 285 #define XHCI_TRB_TYPE_RESET_EP 0x0E 286 #define XHCI_TRB_TYPE_STOP_EP 0x0F 287 #define XHCI_TRB_TYPE_SET_TR_DEQUEUE 0x10 288 #define XHCI_TRB_TYPE_RESET_DEVICE 0x11 289 #define XHCI_TRB_TYPE_FORCE_EVENT 0x12 290 #define XHCI_TRB_TYPE_NEGOTIATE_BW 0x13 291 #define XHCI_TRB_TYPE_SET_LATENCY_TOL 0x14 292 #define XHCI_TRB_TYPE_GET_PORT_BW 0x15 293 #define XHCI_TRB_TYPE_FORCE_HEADER 0x16 294 #define XHCI_TRB_TYPE_NOOP_CMD 0x17 295 296 /* Events */ 297 #define XHCI_TRB_EVENT_TRANSFER 0x20 298 #define XHCI_TRB_EVENT_CMD_COMPLETE 0x21 299 #define XHCI_TRB_EVENT_PORT_STS_CHANGE 0x22 300 #define XHCI_TRB_EVENT_BW_REQUEST 0x23 301 #define XHCI_TRB_EVENT_DOORBELL 0x24 302 #define XHCI_TRB_EVENT_HOST_CTRL 0x25 303 #define XHCI_TRB_EVENT_DEVICE_NOTIFY 0x26 304 #define XHCI_TRB_EVENT_MFINDEX_WRAP 0x27 305 306 /* Error codes */ 307 #define XHCI_TRB_ERROR_INVALID 0x00 308 #define XHCI_TRB_ERROR_SUCCESS 0x01 309 #define XHCI_TRB_ERROR_DATA_BUF 0x02 310 #define XHCI_TRB_ERROR_BABBLE 0x03 311 #define XHCI_TRB_ERROR_XACT 0x04 312 #define XHCI_TRB_ERROR_TRB 0x05 313 #define XHCI_TRB_ERROR_STALL 0x06 314 #define XHCI_TRB_ERROR_RESOURCE 0x07 315 #define XHCI_TRB_ERROR_BANDWIDTH 0x08 316 #define XHCI_TRB_ERROR_NO_SLOTS 0x09 317 #define XHCI_TRB_ERROR_STREAM_TYPE 0x0A 318 #define XHCI_TRB_ERROR_SLOT_NOT_ON 0x0B 319 #define XHCI_TRB_ERROR_ENDP_NOT_ON 0x0C 320 #define XHCI_TRB_ERROR_SHORT_PKT 0x0D 321 #define XHCI_TRB_ERROR_RING_UNDERRUN 0x0E 322 #define XHCI_TRB_ERROR_RING_OVERRUN 0x0F 323 #define XHCI_TRB_ERROR_VF_RING_FULL 0x10 324 #define XHCI_TRB_ERROR_PARAMETER 0x11 325 #define XHCI_TRB_ERROR_BW_OVERRUN 0x12 326 #define XHCI_TRB_ERROR_CONTEXT_STATE 0x13 327 #define XHCI_TRB_ERROR_NO_PING_RESP 0x14 328 #define XHCI_TRB_ERROR_EV_RING_FULL 0x15 329 #define XHCI_TRB_ERROR_INCOMPAT_DEV 0x16 330 #define XHCI_TRB_ERROR_MISSED_SERVICE 0x17 331 #define XHCI_TRB_ERROR_CMD_RING_STOP 0x18 332 #define XHCI_TRB_ERROR_CMD_ABORTED 0x19 333 #define XHCI_TRB_ERROR_STOPPED 0x1A 334 #define XHCI_TRB_ERROR_LENGTH 0x1B 335 #define XHCI_TRB_ERROR_BAD_MELAT 0x1D 336 #define XHCI_TRB_ERROR_ISOC_OVERRUN 0x1F 337 #define XHCI_TRB_ERROR_EVENT_LOST 0x20 338 #define XHCI_TRB_ERROR_UNDEFINED 0x21 339 #define XHCI_TRB_ERROR_INVALID_SID 0x22 340 #define XHCI_TRB_ERROR_SEC_BW 0x23 341 #define XHCI_TRB_ERROR_SPLIT_XACT 0x24 342 } __aligned(4); 343 344 struct xhci_dev_endpoint_trbs { 345 struct xhci_trb trb[(XHCI_MAX_STREAMS * 346 XHCI_MAX_TRANSFERS) + XHCI_MAX_STREAMS]; 347 }; 348 349 struct xhci_event_ring_seg { 350 uint64_t qwEvrsTablePtr; 351 uint32_t dwEvrsTableSize; 352 uint32_t dwEvrsReserved; 353 }; 354 355 #endif /* _PCI_XHCI_H_ */ 356