1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2014 Leon Dang <ldang@nahannisys.com> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 /* 29 XHCI options: 30 -s <n>,xhci,{devices} 31 32 devices: 33 tablet USB tablet mouse 34 */ 35 36 #include <sys/param.h> 37 #include <sys/uio.h> 38 #include <sys/types.h> 39 #include <sys/queue.h> 40 41 #include <stdio.h> 42 #include <stdlib.h> 43 #include <stdint.h> 44 #include <string.h> 45 #include <errno.h> 46 #include <pthread.h> 47 #include <unistd.h> 48 49 #include <dev/usb/usbdi.h> 50 #include <dev/usb/usb.h> 51 #include <dev/usb/usb_freebsd.h> 52 #include <xhcireg.h> 53 54 #include "bhyverun.h" 55 #include "config.h" 56 #include "debug.h" 57 #include "pci_emul.h" 58 #include "pci_xhci.h" 59 #ifdef BHYVE_SNAPSHOT 60 #include "snapshot.h" 61 #endif 62 #include "usb_emul.h" 63 64 65 static int xhci_debug = 0; 66 #define DPRINTF(params) if (xhci_debug) PRINTLN params 67 #define WPRINTF(params) PRINTLN params 68 69 70 #define XHCI_NAME "xhci" 71 #define XHCI_MAX_DEVS 8 /* 4 USB3 + 4 USB2 devs */ 72 73 #define XHCI_MAX_SLOTS 64 /* min allowed by Windows drivers */ 74 75 /* 76 * XHCI data structures can be up to 64k, but limit paddr_guest2host mapping 77 * to 4k to avoid going over the guest physical memory barrier. 78 */ 79 #define XHCI_PADDR_SZ 4096 /* paddr_guest2host max size */ 80 81 #define XHCI_ERST_MAX 0 /* max 2^entries event ring seg tbl */ 82 83 #define XHCI_CAPLEN (4*8) /* offset of op register space */ 84 #define XHCI_HCCPRAMS2 0x1C /* offset of HCCPARAMS2 register */ 85 #define XHCI_PORTREGS_START 0x400 86 #define XHCI_DOORBELL_MAX 256 87 88 #define XHCI_STREAMS_MAX 1 /* 4-15 in XHCI spec */ 89 90 /* caplength and hci-version registers */ 91 #define XHCI_SET_CAPLEN(x) ((x) & 0xFF) 92 #define XHCI_SET_HCIVERSION(x) (((x) & 0xFFFF) << 16) 93 #define XHCI_GET_HCIVERSION(x) (((x) >> 16) & 0xFFFF) 94 95 /* hcsparams1 register */ 96 #define XHCI_SET_HCSP1_MAXSLOTS(x) ((x) & 0xFF) 97 #define XHCI_SET_HCSP1_MAXINTR(x) (((x) & 0x7FF) << 8) 98 #define XHCI_SET_HCSP1_MAXPORTS(x) (((x) & 0xFF) << 24) 99 100 /* hcsparams2 register */ 101 #define XHCI_SET_HCSP2_IST(x) ((x) & 0x0F) 102 #define XHCI_SET_HCSP2_ERSTMAX(x) (((x) & 0x0F) << 4) 103 #define XHCI_SET_HCSP2_MAXSCRATCH_HI(x) (((x) & 0x1F) << 21) 104 #define XHCI_SET_HCSP2_MAXSCRATCH_LO(x) (((x) & 0x1F) << 27) 105 106 /* hcsparams3 register */ 107 #define XHCI_SET_HCSP3_U1EXITLATENCY(x) ((x) & 0xFF) 108 #define XHCI_SET_HCSP3_U2EXITLATENCY(x) (((x) & 0xFFFF) << 16) 109 110 /* hccparams1 register */ 111 #define XHCI_SET_HCCP1_AC64(x) ((x) & 0x01) 112 #define XHCI_SET_HCCP1_BNC(x) (((x) & 0x01) << 1) 113 #define XHCI_SET_HCCP1_CSZ(x) (((x) & 0x01) << 2) 114 #define XHCI_SET_HCCP1_PPC(x) (((x) & 0x01) << 3) 115 #define XHCI_SET_HCCP1_PIND(x) (((x) & 0x01) << 4) 116 #define XHCI_SET_HCCP1_LHRC(x) (((x) & 0x01) << 5) 117 #define XHCI_SET_HCCP1_LTC(x) (((x) & 0x01) << 6) 118 #define XHCI_SET_HCCP1_NSS(x) (((x) & 0x01) << 7) 119 #define XHCI_SET_HCCP1_PAE(x) (((x) & 0x01) << 8) 120 #define XHCI_SET_HCCP1_SPC(x) (((x) & 0x01) << 9) 121 #define XHCI_SET_HCCP1_SEC(x) (((x) & 0x01) << 10) 122 #define XHCI_SET_HCCP1_CFC(x) (((x) & 0x01) << 11) 123 #define XHCI_SET_HCCP1_MAXPSA(x) (((x) & 0x0F) << 12) 124 #define XHCI_SET_HCCP1_XECP(x) (((x) & 0xFFFF) << 16) 125 126 /* hccparams2 register */ 127 #define XHCI_SET_HCCP2_U3C(x) ((x) & 0x01) 128 #define XHCI_SET_HCCP2_CMC(x) (((x) & 0x01) << 1) 129 #define XHCI_SET_HCCP2_FSC(x) (((x) & 0x01) << 2) 130 #define XHCI_SET_HCCP2_CTC(x) (((x) & 0x01) << 3) 131 #define XHCI_SET_HCCP2_LEC(x) (((x) & 0x01) << 4) 132 #define XHCI_SET_HCCP2_CIC(x) (((x) & 0x01) << 5) 133 134 /* other registers */ 135 #define XHCI_SET_DOORBELL(x) ((x) & ~0x03) 136 #define XHCI_SET_RTSOFFSET(x) ((x) & ~0x0F) 137 138 /* register masks */ 139 #define XHCI_PS_PLS_MASK (0xF << 5) /* port link state */ 140 #define XHCI_PS_SPEED_MASK (0xF << 10) /* port speed */ 141 #define XHCI_PS_PIC_MASK (0x3 << 14) /* port indicator */ 142 143 /* port register set */ 144 #define XHCI_PORTREGS_BASE 0x400 /* base offset */ 145 #define XHCI_PORTREGS_PORT0 0x3F0 146 #define XHCI_PORTREGS_SETSZ 0x10 /* size of a set */ 147 148 #define MASK_64_HI(x) ((x) & ~0xFFFFFFFFULL) 149 #define MASK_64_LO(x) ((x) & 0xFFFFFFFFULL) 150 151 #define FIELD_REPLACE(a,b,m,s) (((a) & ~((m) << (s))) | \ 152 (((b) & (m)) << (s))) 153 #define FIELD_COPY(a,b,m,s) (((a) & ~((m) << (s))) | \ 154 (((b) & ((m) << (s))))) 155 156 #define SNAP_DEV_NAME_LEN 128 157 158 struct pci_xhci_trb_ring { 159 uint64_t ringaddr; /* current dequeue guest address */ 160 uint32_t ccs; /* consumer cycle state */ 161 }; 162 163 /* device endpoint transfer/stream rings */ 164 struct pci_xhci_dev_ep { 165 union { 166 struct xhci_trb *_epu_tr; 167 struct xhci_stream_ctx *_epu_sctx; 168 } _ep_trbsctx; 169 #define ep_tr _ep_trbsctx._epu_tr 170 #define ep_sctx _ep_trbsctx._epu_sctx 171 172 /* 173 * Caches the value of MaxPStreams from the endpoint context 174 * when an endpoint is initialized and is used to validate the 175 * use of ep_ringaddr vs ep_sctx_trbs[] as well as the length 176 * of ep_sctx_trbs[]. 177 */ 178 uint32_t ep_MaxPStreams; 179 union { 180 struct pci_xhci_trb_ring _epu_trb; 181 struct pci_xhci_trb_ring *_epu_sctx_trbs; 182 } _ep_trb_rings; 183 #define ep_ringaddr _ep_trb_rings._epu_trb.ringaddr 184 #define ep_ccs _ep_trb_rings._epu_trb.ccs 185 #define ep_sctx_trbs _ep_trb_rings._epu_sctx_trbs 186 187 struct usb_data_xfer *ep_xfer; /* transfer chain */ 188 }; 189 190 /* device context base address array: maps slot->device context */ 191 struct xhci_dcbaa { 192 uint64_t dcba[USB_MAX_DEVICES+1]; /* xhci_dev_ctx ptrs */ 193 }; 194 195 /* port status registers */ 196 struct pci_xhci_portregs { 197 uint32_t portsc; /* port status and control */ 198 uint32_t portpmsc; /* port pwr mgmt status & control */ 199 uint32_t portli; /* port link info */ 200 uint32_t porthlpmc; /* port hardware LPM control */ 201 } __packed; 202 #define XHCI_PS_SPEED_SET(x) (((x) & 0xF) << 10) 203 204 /* xHC operational registers */ 205 struct pci_xhci_opregs { 206 uint32_t usbcmd; /* usb command */ 207 uint32_t usbsts; /* usb status */ 208 uint32_t pgsz; /* page size */ 209 uint32_t dnctrl; /* device notification control */ 210 uint64_t crcr; /* command ring control */ 211 uint64_t dcbaap; /* device ctx base addr array ptr */ 212 uint32_t config; /* configure */ 213 214 /* guest mapped addresses: */ 215 struct xhci_trb *cr_p; /* crcr dequeue */ 216 struct xhci_dcbaa *dcbaa_p; /* dev ctx array ptr */ 217 }; 218 219 /* xHC runtime registers */ 220 struct pci_xhci_rtsregs { 221 uint32_t mfindex; /* microframe index */ 222 struct { /* interrupter register set */ 223 uint32_t iman; /* interrupter management */ 224 uint32_t imod; /* interrupter moderation */ 225 uint32_t erstsz; /* event ring segment table size */ 226 uint32_t rsvd; 227 uint64_t erstba; /* event ring seg-tbl base addr */ 228 uint64_t erdp; /* event ring dequeue ptr */ 229 } intrreg __packed; 230 231 /* guest mapped addresses */ 232 struct xhci_event_ring_seg *erstba_p; 233 struct xhci_trb *erst_p; /* event ring segment tbl */ 234 int er_deq_seg; /* event ring dequeue segment */ 235 int er_enq_idx; /* event ring enqueue index - xHCI */ 236 int er_enq_seg; /* event ring enqueue segment */ 237 uint32_t er_events_cnt; /* number of events in ER */ 238 uint32_t event_pcs; /* producer cycle state flag */ 239 }; 240 241 242 struct pci_xhci_softc; 243 244 245 /* 246 * USB device emulation container. 247 * This is referenced from usb_hci->hci_sc; 1 pci_xhci_dev_emu for each 248 * emulated device instance. 249 */ 250 struct pci_xhci_dev_emu { 251 struct pci_xhci_softc *xsc; 252 253 /* XHCI contexts */ 254 struct xhci_dev_ctx *dev_ctx; 255 struct pci_xhci_dev_ep eps[XHCI_MAX_ENDPOINTS]; 256 int dev_slotstate; 257 258 struct usb_devemu *dev_ue; /* USB emulated dev */ 259 void *dev_sc; /* device's softc */ 260 261 struct usb_hci hci; 262 }; 263 264 struct pci_xhci_softc { 265 struct pci_devinst *xsc_pi; 266 267 pthread_mutex_t mtx; 268 269 uint32_t caplength; /* caplen & hciversion */ 270 uint32_t hcsparams1; /* structural parameters 1 */ 271 uint32_t hcsparams2; /* structural parameters 2 */ 272 uint32_t hcsparams3; /* structural parameters 3 */ 273 uint32_t hccparams1; /* capability parameters 1 */ 274 uint32_t dboff; /* doorbell offset */ 275 uint32_t rtsoff; /* runtime register space offset */ 276 uint32_t hccparams2; /* capability parameters 2 */ 277 278 uint32_t regsend; /* end of configuration registers */ 279 280 struct pci_xhci_opregs opregs; 281 struct pci_xhci_rtsregs rtsregs; 282 283 struct pci_xhci_portregs *portregs; 284 struct pci_xhci_dev_emu **devices; /* XHCI[port] = device */ 285 struct pci_xhci_dev_emu **slots; /* slots assigned from 1 */ 286 287 int usb2_port_start; 288 int usb3_port_start; 289 }; 290 291 292 /* port and slot numbering start from 1 */ 293 #define XHCI_PORTREG_PTR(x,n) &((x)->portregs[(n) - 1]) 294 #define XHCI_DEVINST_PTR(x,n) ((x)->devices[(n) - 1]) 295 #define XHCI_SLOTDEV_PTR(x,n) ((x)->slots[(n) - 1]) 296 297 #define XHCI_HALTED(sc) ((sc)->opregs.usbsts & XHCI_STS_HCH) 298 299 #define XHCI_GADDR_SIZE(a) (XHCI_PADDR_SZ - \ 300 (((uint64_t) (a)) & (XHCI_PADDR_SZ - 1))) 301 #define XHCI_GADDR(sc,a) paddr_guest2host((sc)->xsc_pi->pi_vmctx, \ 302 (a), XHCI_GADDR_SIZE(a)) 303 304 static int xhci_in_use; 305 306 /* map USB errors to XHCI */ 307 static const int xhci_usb_errors[USB_ERR_MAX] = { 308 [USB_ERR_NORMAL_COMPLETION] = XHCI_TRB_ERROR_SUCCESS, 309 [USB_ERR_PENDING_REQUESTS] = XHCI_TRB_ERROR_RESOURCE, 310 [USB_ERR_NOT_STARTED] = XHCI_TRB_ERROR_ENDP_NOT_ON, 311 [USB_ERR_INVAL] = XHCI_TRB_ERROR_INVALID, 312 [USB_ERR_NOMEM] = XHCI_TRB_ERROR_RESOURCE, 313 [USB_ERR_CANCELLED] = XHCI_TRB_ERROR_STOPPED, 314 [USB_ERR_BAD_ADDRESS] = XHCI_TRB_ERROR_PARAMETER, 315 [USB_ERR_BAD_BUFSIZE] = XHCI_TRB_ERROR_PARAMETER, 316 [USB_ERR_BAD_FLAG] = XHCI_TRB_ERROR_PARAMETER, 317 [USB_ERR_NO_CALLBACK] = XHCI_TRB_ERROR_STALL, 318 [USB_ERR_IN_USE] = XHCI_TRB_ERROR_RESOURCE, 319 [USB_ERR_NO_ADDR] = XHCI_TRB_ERROR_RESOURCE, 320 [USB_ERR_NO_PIPE] = XHCI_TRB_ERROR_RESOURCE, 321 [USB_ERR_ZERO_NFRAMES] = XHCI_TRB_ERROR_UNDEFINED, 322 [USB_ERR_ZERO_MAXP] = XHCI_TRB_ERROR_UNDEFINED, 323 [USB_ERR_SET_ADDR_FAILED] = XHCI_TRB_ERROR_RESOURCE, 324 [USB_ERR_NO_POWER] = XHCI_TRB_ERROR_ENDP_NOT_ON, 325 [USB_ERR_TOO_DEEP] = XHCI_TRB_ERROR_RESOURCE, 326 [USB_ERR_IOERROR] = XHCI_TRB_ERROR_TRB, 327 [USB_ERR_NOT_CONFIGURED] = XHCI_TRB_ERROR_ENDP_NOT_ON, 328 [USB_ERR_TIMEOUT] = XHCI_TRB_ERROR_CMD_ABORTED, 329 [USB_ERR_SHORT_XFER] = XHCI_TRB_ERROR_SHORT_PKT, 330 [USB_ERR_STALLED] = XHCI_TRB_ERROR_STALL, 331 [USB_ERR_INTERRUPTED] = XHCI_TRB_ERROR_CMD_ABORTED, 332 [USB_ERR_DMA_LOAD_FAILED] = XHCI_TRB_ERROR_DATA_BUF, 333 [USB_ERR_BAD_CONTEXT] = XHCI_TRB_ERROR_TRB, 334 [USB_ERR_NO_ROOT_HUB] = XHCI_TRB_ERROR_UNDEFINED, 335 [USB_ERR_NO_INTR_THREAD] = XHCI_TRB_ERROR_UNDEFINED, 336 [USB_ERR_NOT_LOCKED] = XHCI_TRB_ERROR_UNDEFINED, 337 }; 338 #define USB_TO_XHCI_ERR(e) ((e) < USB_ERR_MAX ? xhci_usb_errors[(e)] : \ 339 XHCI_TRB_ERROR_INVALID) 340 341 static int pci_xhci_insert_event(struct pci_xhci_softc *sc, 342 struct xhci_trb *evtrb, int do_intr); 343 static void pci_xhci_dump_trb(struct xhci_trb *trb); 344 static void pci_xhci_assert_interrupt(struct pci_xhci_softc *sc); 345 static void pci_xhci_reset_slot(struct pci_xhci_softc *sc, int slot); 346 static void pci_xhci_reset_port(struct pci_xhci_softc *sc, int portn, int warm); 347 static void pci_xhci_update_ep_ring(struct pci_xhci_softc *sc, 348 struct pci_xhci_dev_emu *dev, struct pci_xhci_dev_ep *devep, 349 struct xhci_endp_ctx *ep_ctx, uint32_t streamid, 350 uint64_t ringaddr, int ccs); 351 static int pci_xhci_validate_slot(uint32_t slot); 352 353 static void 354 pci_xhci_set_evtrb(struct xhci_trb *evtrb, uint64_t port, uint32_t errcode, 355 uint32_t evtype) 356 { 357 evtrb->qwTrb0 = port << 24; 358 evtrb->dwTrb2 = XHCI_TRB_2_ERROR_SET(errcode); 359 evtrb->dwTrb3 = XHCI_TRB_3_TYPE_SET(evtype); 360 } 361 362 363 /* controller reset */ 364 static void 365 pci_xhci_reset(struct pci_xhci_softc *sc) 366 { 367 int i; 368 369 sc->rtsregs.er_enq_idx = 0; 370 sc->rtsregs.er_events_cnt = 0; 371 sc->rtsregs.event_pcs = 1; 372 373 for (i = 1; i <= XHCI_MAX_SLOTS; i++) { 374 pci_xhci_reset_slot(sc, i); 375 } 376 } 377 378 static uint32_t 379 pci_xhci_usbcmd_write(struct pci_xhci_softc *sc, uint32_t cmd) 380 { 381 int do_intr = 0; 382 int i; 383 384 if (cmd & XHCI_CMD_RS) { 385 do_intr = (sc->opregs.usbcmd & XHCI_CMD_RS) == 0; 386 387 sc->opregs.usbcmd |= XHCI_CMD_RS; 388 sc->opregs.usbsts &= ~XHCI_STS_HCH; 389 sc->opregs.usbsts |= XHCI_STS_PCD; 390 391 /* Queue port change event on controller run from stop */ 392 if (do_intr) 393 for (i = 1; i <= XHCI_MAX_DEVS; i++) { 394 struct pci_xhci_dev_emu *dev; 395 struct pci_xhci_portregs *port; 396 struct xhci_trb evtrb; 397 398 if ((dev = XHCI_DEVINST_PTR(sc, i)) == NULL) 399 continue; 400 401 port = XHCI_PORTREG_PTR(sc, i); 402 port->portsc |= XHCI_PS_CSC | XHCI_PS_CCS; 403 port->portsc &= ~XHCI_PS_PLS_MASK; 404 405 /* 406 * XHCI 4.19.3 USB2 RxDetect->Polling, 407 * USB3 Polling->U0 408 */ 409 if (dev->dev_ue->ue_usbver == 2) 410 port->portsc |= 411 XHCI_PS_PLS_SET(UPS_PORT_LS_POLL); 412 else 413 port->portsc |= 414 XHCI_PS_PLS_SET(UPS_PORT_LS_U0); 415 416 pci_xhci_set_evtrb(&evtrb, i, 417 XHCI_TRB_ERROR_SUCCESS, 418 XHCI_TRB_EVENT_PORT_STS_CHANGE); 419 420 if (pci_xhci_insert_event(sc, &evtrb, 0) != 421 XHCI_TRB_ERROR_SUCCESS) 422 break; 423 } 424 } else { 425 sc->opregs.usbcmd &= ~XHCI_CMD_RS; 426 sc->opregs.usbsts |= XHCI_STS_HCH; 427 sc->opregs.usbsts &= ~XHCI_STS_PCD; 428 } 429 430 /* start execution of schedule; stop when set to 0 */ 431 cmd |= sc->opregs.usbcmd & XHCI_CMD_RS; 432 433 if (cmd & XHCI_CMD_HCRST) { 434 /* reset controller */ 435 pci_xhci_reset(sc); 436 cmd &= ~XHCI_CMD_HCRST; 437 } 438 439 cmd &= ~(XHCI_CMD_CSS | XHCI_CMD_CRS); 440 441 if (do_intr) 442 pci_xhci_assert_interrupt(sc); 443 444 return (cmd); 445 } 446 447 static void 448 pci_xhci_portregs_write(struct pci_xhci_softc *sc, uint64_t offset, 449 uint64_t value) 450 { 451 struct xhci_trb evtrb; 452 struct pci_xhci_portregs *p; 453 int port; 454 uint32_t oldpls, newpls; 455 456 if (sc->portregs == NULL) 457 return; 458 459 port = (offset - XHCI_PORTREGS_PORT0) / XHCI_PORTREGS_SETSZ; 460 offset = (offset - XHCI_PORTREGS_PORT0) % XHCI_PORTREGS_SETSZ; 461 462 DPRINTF(("pci_xhci: portregs wr offset 0x%lx, port %u: 0x%lx", 463 offset, port, value)); 464 465 assert(port >= 0); 466 467 if (port > XHCI_MAX_DEVS) { 468 DPRINTF(("pci_xhci: portregs_write port %d > ndevices", 469 port)); 470 return; 471 } 472 473 if (XHCI_DEVINST_PTR(sc, port) == NULL) { 474 DPRINTF(("pci_xhci: portregs_write to unattached port %d", 475 port)); 476 } 477 478 p = XHCI_PORTREG_PTR(sc, port); 479 switch (offset) { 480 case 0: 481 /* port reset or warm reset */ 482 if (value & (XHCI_PS_PR | XHCI_PS_WPR)) { 483 pci_xhci_reset_port(sc, port, value & XHCI_PS_WPR); 484 break; 485 } 486 487 if ((p->portsc & XHCI_PS_PP) == 0) { 488 WPRINTF(("pci_xhci: portregs_write to unpowered " 489 "port %d", port)); 490 break; 491 } 492 493 /* Port status and control register */ 494 oldpls = XHCI_PS_PLS_GET(p->portsc); 495 newpls = XHCI_PS_PLS_GET(value); 496 497 p->portsc &= XHCI_PS_PED | XHCI_PS_PLS_MASK | 498 XHCI_PS_SPEED_MASK | XHCI_PS_PIC_MASK; 499 500 if (XHCI_DEVINST_PTR(sc, port)) 501 p->portsc |= XHCI_PS_CCS; 502 503 p->portsc |= (value & 504 ~(XHCI_PS_OCA | 505 XHCI_PS_PR | 506 XHCI_PS_PED | 507 XHCI_PS_PLS_MASK | /* link state */ 508 XHCI_PS_SPEED_MASK | 509 XHCI_PS_PIC_MASK | /* port indicator */ 510 XHCI_PS_LWS | XHCI_PS_DR | XHCI_PS_WPR)); 511 512 /* clear control bits */ 513 p->portsc &= ~(value & 514 (XHCI_PS_CSC | 515 XHCI_PS_PEC | 516 XHCI_PS_WRC | 517 XHCI_PS_OCC | 518 XHCI_PS_PRC | 519 XHCI_PS_PLC | 520 XHCI_PS_CEC | 521 XHCI_PS_CAS)); 522 523 /* port disable request; for USB3, don't care */ 524 if (value & XHCI_PS_PED) 525 DPRINTF(("Disable port %d request", port)); 526 527 if (!(value & XHCI_PS_LWS)) 528 break; 529 530 DPRINTF(("Port new PLS: %d", newpls)); 531 switch (newpls) { 532 case 0: /* U0 */ 533 case 3: /* U3 */ 534 if (oldpls != newpls) { 535 p->portsc &= ~XHCI_PS_PLS_MASK; 536 p->portsc |= XHCI_PS_PLS_SET(newpls) | 537 XHCI_PS_PLC; 538 539 if (oldpls != 0 && newpls == 0) { 540 pci_xhci_set_evtrb(&evtrb, port, 541 XHCI_TRB_ERROR_SUCCESS, 542 XHCI_TRB_EVENT_PORT_STS_CHANGE); 543 544 pci_xhci_insert_event(sc, &evtrb, 1); 545 } 546 } 547 break; 548 549 default: 550 DPRINTF(("Unhandled change port %d PLS %u", 551 port, newpls)); 552 break; 553 } 554 break; 555 case 4: 556 /* Port power management status and control register */ 557 p->portpmsc = value; 558 break; 559 case 8: 560 /* Port link information register */ 561 DPRINTF(("pci_xhci attempted write to PORTLI, port %d", 562 port)); 563 break; 564 case 12: 565 /* 566 * Port hardware LPM control register. 567 * For USB3, this register is reserved. 568 */ 569 p->porthlpmc = value; 570 break; 571 default: 572 DPRINTF(("pci_xhci: unaligned portreg write offset %#lx", 573 offset)); 574 break; 575 } 576 } 577 578 static struct xhci_dev_ctx * 579 pci_xhci_get_dev_ctx(struct pci_xhci_softc *sc, uint32_t slot) 580 { 581 uint64_t devctx_addr; 582 struct xhci_dev_ctx *devctx; 583 584 assert(slot > 0 && slot <= XHCI_MAX_SLOTS); 585 assert(XHCI_SLOTDEV_PTR(sc, slot) != NULL); 586 assert(sc->opregs.dcbaa_p != NULL); 587 588 devctx_addr = sc->opregs.dcbaa_p->dcba[slot]; 589 590 if (devctx_addr == 0) { 591 DPRINTF(("get_dev_ctx devctx_addr == 0")); 592 return (NULL); 593 } 594 595 DPRINTF(("pci_xhci: get dev ctx, slot %u devctx addr %016lx", 596 slot, devctx_addr)); 597 devctx = XHCI_GADDR(sc, devctx_addr & ~0x3FUL); 598 599 return (devctx); 600 } 601 602 static struct xhci_trb * 603 pci_xhci_trb_next(struct pci_xhci_softc *sc, struct xhci_trb *curtrb, 604 uint64_t *guestaddr) 605 { 606 struct xhci_trb *next; 607 608 assert(curtrb != NULL); 609 610 if (XHCI_TRB_3_TYPE_GET(curtrb->dwTrb3) == XHCI_TRB_TYPE_LINK) { 611 if (guestaddr) 612 *guestaddr = curtrb->qwTrb0 & ~0xFUL; 613 614 next = XHCI_GADDR(sc, curtrb->qwTrb0 & ~0xFUL); 615 } else { 616 if (guestaddr) 617 *guestaddr += sizeof(struct xhci_trb) & ~0xFUL; 618 619 next = curtrb + 1; 620 } 621 622 return (next); 623 } 624 625 static void 626 pci_xhci_assert_interrupt(struct pci_xhci_softc *sc) 627 { 628 629 sc->rtsregs.intrreg.erdp |= XHCI_ERDP_LO_BUSY; 630 sc->rtsregs.intrreg.iman |= XHCI_IMAN_INTR_PEND; 631 sc->opregs.usbsts |= XHCI_STS_EINT; 632 633 /* only trigger interrupt if permitted */ 634 if ((sc->opregs.usbcmd & XHCI_CMD_INTE) && 635 (sc->rtsregs.intrreg.iman & XHCI_IMAN_INTR_ENA)) { 636 if (pci_msi_enabled(sc->xsc_pi)) 637 pci_generate_msi(sc->xsc_pi, 0); 638 else 639 pci_lintr_assert(sc->xsc_pi); 640 } 641 } 642 643 static void 644 pci_xhci_deassert_interrupt(struct pci_xhci_softc *sc) 645 { 646 647 if (!pci_msi_enabled(sc->xsc_pi)) 648 pci_lintr_assert(sc->xsc_pi); 649 } 650 651 static void 652 pci_xhci_init_ep(struct pci_xhci_dev_emu *dev, int epid) 653 { 654 struct xhci_dev_ctx *dev_ctx; 655 struct pci_xhci_dev_ep *devep; 656 struct xhci_endp_ctx *ep_ctx; 657 uint32_t i, pstreams; 658 659 dev_ctx = dev->dev_ctx; 660 ep_ctx = &dev_ctx->ctx_ep[epid]; 661 devep = &dev->eps[epid]; 662 pstreams = XHCI_EPCTX_0_MAXP_STREAMS_GET(ep_ctx->dwEpCtx0); 663 if (pstreams > 0) { 664 DPRINTF(("init_ep %d with pstreams %u", epid, pstreams)); 665 assert(devep->ep_sctx_trbs == NULL); 666 667 devep->ep_sctx = XHCI_GADDR(dev->xsc, ep_ctx->qwEpCtx2 & 668 XHCI_EPCTX_2_TR_DQ_PTR_MASK); 669 devep->ep_sctx_trbs = calloc(pstreams, 670 sizeof(struct pci_xhci_trb_ring)); 671 for (i = 0; i < pstreams; i++) { 672 devep->ep_sctx_trbs[i].ringaddr = 673 devep->ep_sctx[i].qwSctx0 & 674 XHCI_SCTX_0_TR_DQ_PTR_MASK; 675 devep->ep_sctx_trbs[i].ccs = 676 XHCI_SCTX_0_DCS_GET(devep->ep_sctx[i].qwSctx0); 677 } 678 } else { 679 DPRINTF(("init_ep %d with no pstreams", epid)); 680 devep->ep_ringaddr = ep_ctx->qwEpCtx2 & 681 XHCI_EPCTX_2_TR_DQ_PTR_MASK; 682 devep->ep_ccs = XHCI_EPCTX_2_DCS_GET(ep_ctx->qwEpCtx2); 683 devep->ep_tr = XHCI_GADDR(dev->xsc, devep->ep_ringaddr); 684 DPRINTF(("init_ep tr DCS %x", devep->ep_ccs)); 685 } 686 devep->ep_MaxPStreams = pstreams; 687 688 if (devep->ep_xfer == NULL) { 689 devep->ep_xfer = malloc(sizeof(struct usb_data_xfer)); 690 USB_DATA_XFER_INIT(devep->ep_xfer); 691 } 692 } 693 694 static void 695 pci_xhci_disable_ep(struct pci_xhci_dev_emu *dev, int epid) 696 { 697 struct xhci_dev_ctx *dev_ctx; 698 struct pci_xhci_dev_ep *devep; 699 struct xhci_endp_ctx *ep_ctx; 700 701 DPRINTF(("pci_xhci disable_ep %d", epid)); 702 703 dev_ctx = dev->dev_ctx; 704 ep_ctx = &dev_ctx->ctx_ep[epid]; 705 ep_ctx->dwEpCtx0 = (ep_ctx->dwEpCtx0 & ~0x7) | XHCI_ST_EPCTX_DISABLED; 706 707 devep = &dev->eps[epid]; 708 if (devep->ep_MaxPStreams > 0) 709 free(devep->ep_sctx_trbs); 710 711 if (devep->ep_xfer != NULL) { 712 free(devep->ep_xfer); 713 devep->ep_xfer = NULL; 714 } 715 716 memset(devep, 0, sizeof(struct pci_xhci_dev_ep)); 717 } 718 719 720 /* reset device at slot and data structures related to it */ 721 static void 722 pci_xhci_reset_slot(struct pci_xhci_softc *sc, int slot) 723 { 724 struct pci_xhci_dev_emu *dev; 725 726 dev = XHCI_SLOTDEV_PTR(sc, slot); 727 728 if (!dev) { 729 DPRINTF(("xhci reset unassigned slot (%d)?", slot)); 730 } else { 731 dev->dev_slotstate = XHCI_ST_DISABLED; 732 } 733 734 /* TODO: reset ring buffer pointers */ 735 } 736 737 static int 738 pci_xhci_insert_event(struct pci_xhci_softc *sc, struct xhci_trb *evtrb, 739 int do_intr) 740 { 741 struct pci_xhci_rtsregs *rts; 742 uint64_t erdp; 743 int erdp_idx; 744 int err; 745 struct xhci_trb *evtrbptr; 746 747 err = XHCI_TRB_ERROR_SUCCESS; 748 749 rts = &sc->rtsregs; 750 751 erdp = rts->intrreg.erdp & ~0xF; 752 erdp_idx = (erdp - rts->erstba_p[rts->er_deq_seg].qwEvrsTablePtr) / 753 sizeof(struct xhci_trb); 754 755 DPRINTF(("pci_xhci: insert event 0[%lx] 2[%x] 3[%x]", 756 evtrb->qwTrb0, evtrb->dwTrb2, evtrb->dwTrb3)); 757 DPRINTF(("\terdp idx %d/seg %d, enq idx %d/seg %d, pcs %u", 758 erdp_idx, rts->er_deq_seg, rts->er_enq_idx, 759 rts->er_enq_seg, rts->event_pcs)); 760 DPRINTF(("\t(erdp=0x%lx, erst=0x%lx, tblsz=%u, do_intr %d)", 761 erdp, rts->erstba_p->qwEvrsTablePtr, 762 rts->erstba_p->dwEvrsTableSize, do_intr)); 763 764 evtrbptr = &rts->erst_p[rts->er_enq_idx]; 765 766 /* TODO: multi-segment table */ 767 if (rts->er_events_cnt >= rts->erstba_p->dwEvrsTableSize) { 768 DPRINTF(("pci_xhci[%d] cannot insert event; ring full", 769 __LINE__)); 770 err = XHCI_TRB_ERROR_EV_RING_FULL; 771 goto done; 772 } 773 774 if (rts->er_events_cnt == rts->erstba_p->dwEvrsTableSize - 1) { 775 struct xhci_trb errev; 776 777 if ((evtrbptr->dwTrb3 & 0x1) == (rts->event_pcs & 0x1)) { 778 779 DPRINTF(("pci_xhci[%d] insert evt err: ring full", 780 __LINE__)); 781 782 errev.qwTrb0 = 0; 783 errev.dwTrb2 = XHCI_TRB_2_ERROR_SET( 784 XHCI_TRB_ERROR_EV_RING_FULL); 785 errev.dwTrb3 = XHCI_TRB_3_TYPE_SET( 786 XHCI_TRB_EVENT_HOST_CTRL) | 787 rts->event_pcs; 788 rts->er_events_cnt++; 789 memcpy(&rts->erst_p[rts->er_enq_idx], &errev, 790 sizeof(struct xhci_trb)); 791 rts->er_enq_idx = (rts->er_enq_idx + 1) % 792 rts->erstba_p->dwEvrsTableSize; 793 err = XHCI_TRB_ERROR_EV_RING_FULL; 794 do_intr = 1; 795 796 goto done; 797 } 798 } else { 799 rts->er_events_cnt++; 800 } 801 802 evtrb->dwTrb3 &= ~XHCI_TRB_3_CYCLE_BIT; 803 evtrb->dwTrb3 |= rts->event_pcs; 804 805 memcpy(&rts->erst_p[rts->er_enq_idx], evtrb, sizeof(struct xhci_trb)); 806 rts->er_enq_idx = (rts->er_enq_idx + 1) % 807 rts->erstba_p->dwEvrsTableSize; 808 809 if (rts->er_enq_idx == 0) 810 rts->event_pcs ^= 1; 811 812 done: 813 if (do_intr) 814 pci_xhci_assert_interrupt(sc); 815 816 return (err); 817 } 818 819 static uint32_t 820 pci_xhci_cmd_enable_slot(struct pci_xhci_softc *sc, uint32_t *slot) 821 { 822 struct pci_xhci_dev_emu *dev; 823 uint32_t cmderr; 824 int i; 825 826 cmderr = XHCI_TRB_ERROR_NO_SLOTS; 827 if (sc->portregs != NULL) 828 for (i = 1; i <= XHCI_MAX_SLOTS; i++) { 829 dev = XHCI_SLOTDEV_PTR(sc, i); 830 if (dev && dev->dev_slotstate == XHCI_ST_DISABLED) { 831 *slot = i; 832 dev->dev_slotstate = XHCI_ST_ENABLED; 833 cmderr = XHCI_TRB_ERROR_SUCCESS; 834 dev->hci.hci_address = i; 835 break; 836 } 837 } 838 839 DPRINTF(("pci_xhci enable slot (error=%d) slot %u", 840 cmderr != XHCI_TRB_ERROR_SUCCESS, *slot)); 841 842 return (cmderr); 843 } 844 845 static uint32_t 846 pci_xhci_cmd_disable_slot(struct pci_xhci_softc *sc, uint32_t slot) 847 { 848 struct pci_xhci_dev_emu *dev; 849 uint32_t cmderr; 850 851 DPRINTF(("pci_xhci disable slot %u", slot)); 852 853 if (sc->portregs == NULL) { 854 cmderr = XHCI_TRB_ERROR_NO_SLOTS; 855 goto done; 856 } 857 858 cmderr = pci_xhci_validate_slot(slot); 859 if (cmderr != XHCI_TRB_ERROR_SUCCESS) 860 goto done; 861 862 dev = XHCI_SLOTDEV_PTR(sc, slot); 863 if (dev) { 864 if (dev->dev_slotstate == XHCI_ST_DISABLED) { 865 cmderr = XHCI_TRB_ERROR_SLOT_NOT_ON; 866 } else { 867 dev->dev_slotstate = XHCI_ST_DISABLED; 868 /* TODO: reset events and endpoints */ 869 } 870 } else 871 cmderr = XHCI_TRB_ERROR_SLOT_NOT_ON; 872 873 done: 874 return (cmderr); 875 } 876 877 static uint32_t 878 pci_xhci_cmd_reset_device(struct pci_xhci_softc *sc, uint32_t slot) 879 { 880 struct pci_xhci_dev_emu *dev; 881 struct xhci_dev_ctx *dev_ctx; 882 struct xhci_endp_ctx *ep_ctx; 883 uint32_t cmderr; 884 int i; 885 886 if (sc->portregs == NULL) { 887 cmderr = XHCI_TRB_ERROR_NO_SLOTS; 888 goto done; 889 } 890 891 DPRINTF(("pci_xhci reset device slot %u", slot)); 892 893 cmderr = pci_xhci_validate_slot(slot); 894 if (cmderr != XHCI_TRB_ERROR_SUCCESS) 895 goto done; 896 897 dev = XHCI_SLOTDEV_PTR(sc, slot); 898 if (!dev || dev->dev_slotstate == XHCI_ST_DISABLED) 899 cmderr = XHCI_TRB_ERROR_SLOT_NOT_ON; 900 else { 901 dev->dev_slotstate = XHCI_ST_DEFAULT; 902 903 dev->hci.hci_address = 0; 904 dev_ctx = pci_xhci_get_dev_ctx(sc, slot); 905 if (dev_ctx == NULL) { 906 cmderr = XHCI_TRB_ERROR_PARAMETER; 907 goto done; 908 } 909 910 /* slot state */ 911 dev_ctx->ctx_slot.dwSctx3 = FIELD_REPLACE( 912 dev_ctx->ctx_slot.dwSctx3, XHCI_ST_SLCTX_DEFAULT, 913 0x1F, 27); 914 915 /* number of contexts */ 916 dev_ctx->ctx_slot.dwSctx0 = FIELD_REPLACE( 917 dev_ctx->ctx_slot.dwSctx0, 1, 0x1F, 27); 918 919 /* reset all eps other than ep-0 */ 920 for (i = 2; i <= 31; i++) { 921 ep_ctx = &dev_ctx->ctx_ep[i]; 922 ep_ctx->dwEpCtx0 = FIELD_REPLACE( ep_ctx->dwEpCtx0, 923 XHCI_ST_EPCTX_DISABLED, 0x7, 0); 924 } 925 } 926 927 pci_xhci_reset_slot(sc, slot); 928 929 done: 930 return (cmderr); 931 } 932 933 static uint32_t 934 pci_xhci_cmd_address_device(struct pci_xhci_softc *sc, uint32_t slot, 935 struct xhci_trb *trb) 936 { 937 struct pci_xhci_dev_emu *dev; 938 struct xhci_input_dev_ctx *input_ctx; 939 struct xhci_slot_ctx *islot_ctx; 940 struct xhci_dev_ctx *dev_ctx; 941 struct xhci_endp_ctx *ep0_ctx; 942 uint32_t cmderr; 943 944 input_ctx = XHCI_GADDR(sc, trb->qwTrb0 & ~0xFUL); 945 islot_ctx = &input_ctx->ctx_slot; 946 ep0_ctx = &input_ctx->ctx_ep[1]; 947 948 DPRINTF(("pci_xhci: address device, input ctl: D 0x%08x A 0x%08x,", 949 input_ctx->ctx_input.dwInCtx0, input_ctx->ctx_input.dwInCtx1)); 950 DPRINTF((" slot %08x %08x %08x %08x", 951 islot_ctx->dwSctx0, islot_ctx->dwSctx1, 952 islot_ctx->dwSctx2, islot_ctx->dwSctx3)); 953 DPRINTF((" ep0 %08x %08x %016lx %08x", 954 ep0_ctx->dwEpCtx0, ep0_ctx->dwEpCtx1, ep0_ctx->qwEpCtx2, 955 ep0_ctx->dwEpCtx4)); 956 957 /* when setting address: drop-ctx=0, add-ctx=slot+ep0 */ 958 if ((input_ctx->ctx_input.dwInCtx0 != 0) || 959 (input_ctx->ctx_input.dwInCtx1 & 0x03) != 0x03) { 960 DPRINTF(("pci_xhci: address device, input ctl invalid")); 961 cmderr = XHCI_TRB_ERROR_TRB; 962 goto done; 963 } 964 965 cmderr = pci_xhci_validate_slot(slot); 966 if (cmderr != XHCI_TRB_ERROR_SUCCESS) 967 goto done; 968 969 /* assign address to slot */ 970 dev_ctx = pci_xhci_get_dev_ctx(sc, slot); 971 if (dev_ctx == NULL) { 972 cmderr = XHCI_TRB_ERROR_PARAMETER; 973 goto done; 974 } 975 976 DPRINTF(("pci_xhci: address device, dev ctx")); 977 DPRINTF((" slot %08x %08x %08x %08x", 978 dev_ctx->ctx_slot.dwSctx0, dev_ctx->ctx_slot.dwSctx1, 979 dev_ctx->ctx_slot.dwSctx2, dev_ctx->ctx_slot.dwSctx3)); 980 981 dev = XHCI_SLOTDEV_PTR(sc, slot); 982 assert(dev != NULL); 983 984 dev->hci.hci_address = slot; 985 dev->dev_ctx = dev_ctx; 986 987 if (dev->dev_ue->ue_reset == NULL || 988 dev->dev_ue->ue_reset(dev->dev_sc) < 0) { 989 cmderr = XHCI_TRB_ERROR_ENDP_NOT_ON; 990 goto done; 991 } 992 993 memcpy(&dev_ctx->ctx_slot, islot_ctx, sizeof(struct xhci_slot_ctx)); 994 995 dev_ctx->ctx_slot.dwSctx3 = 996 XHCI_SCTX_3_SLOT_STATE_SET(XHCI_ST_SLCTX_ADDRESSED) | 997 XHCI_SCTX_3_DEV_ADDR_SET(slot); 998 999 memcpy(&dev_ctx->ctx_ep[1], ep0_ctx, sizeof(struct xhci_endp_ctx)); 1000 ep0_ctx = &dev_ctx->ctx_ep[1]; 1001 ep0_ctx->dwEpCtx0 = (ep0_ctx->dwEpCtx0 & ~0x7) | 1002 XHCI_EPCTX_0_EPSTATE_SET(XHCI_ST_EPCTX_RUNNING); 1003 1004 pci_xhci_init_ep(dev, 1); 1005 1006 dev->dev_slotstate = XHCI_ST_ADDRESSED; 1007 1008 DPRINTF(("pci_xhci: address device, output ctx")); 1009 DPRINTF((" slot %08x %08x %08x %08x", 1010 dev_ctx->ctx_slot.dwSctx0, dev_ctx->ctx_slot.dwSctx1, 1011 dev_ctx->ctx_slot.dwSctx2, dev_ctx->ctx_slot.dwSctx3)); 1012 DPRINTF((" ep0 %08x %08x %016lx %08x", 1013 ep0_ctx->dwEpCtx0, ep0_ctx->dwEpCtx1, ep0_ctx->qwEpCtx2, 1014 ep0_ctx->dwEpCtx4)); 1015 1016 done: 1017 return (cmderr); 1018 } 1019 1020 static uint32_t 1021 pci_xhci_cmd_config_ep(struct pci_xhci_softc *sc, uint32_t slot, 1022 struct xhci_trb *trb) 1023 { 1024 struct xhci_input_dev_ctx *input_ctx; 1025 struct pci_xhci_dev_emu *dev; 1026 struct xhci_dev_ctx *dev_ctx; 1027 struct xhci_endp_ctx *ep_ctx, *iep_ctx; 1028 uint32_t cmderr; 1029 int i; 1030 1031 DPRINTF(("pci_xhci config_ep slot %u", slot)); 1032 1033 cmderr = pci_xhci_validate_slot(slot); 1034 if (cmderr != XHCI_TRB_ERROR_SUCCESS) 1035 goto done; 1036 1037 dev = XHCI_SLOTDEV_PTR(sc, slot); 1038 assert(dev != NULL); 1039 1040 if ((trb->dwTrb3 & XHCI_TRB_3_DCEP_BIT) != 0) { 1041 DPRINTF(("pci_xhci config_ep - deconfigure ep slot %u", 1042 slot)); 1043 if (dev->dev_ue->ue_stop != NULL) 1044 dev->dev_ue->ue_stop(dev->dev_sc); 1045 1046 dev->dev_slotstate = XHCI_ST_ADDRESSED; 1047 1048 dev->hci.hci_address = 0; 1049 dev_ctx = pci_xhci_get_dev_ctx(sc, slot); 1050 if (dev_ctx == NULL) { 1051 cmderr = XHCI_TRB_ERROR_PARAMETER; 1052 goto done; 1053 } 1054 1055 /* number of contexts */ 1056 dev_ctx->ctx_slot.dwSctx0 = FIELD_REPLACE( 1057 dev_ctx->ctx_slot.dwSctx0, 1, 0x1F, 27); 1058 1059 /* slot state */ 1060 dev_ctx->ctx_slot.dwSctx3 = FIELD_REPLACE( 1061 dev_ctx->ctx_slot.dwSctx3, XHCI_ST_SLCTX_ADDRESSED, 1062 0x1F, 27); 1063 1064 /* disable endpoints */ 1065 for (i = 2; i < 32; i++) 1066 pci_xhci_disable_ep(dev, i); 1067 1068 cmderr = XHCI_TRB_ERROR_SUCCESS; 1069 1070 goto done; 1071 } 1072 1073 if (dev->dev_slotstate < XHCI_ST_ADDRESSED) { 1074 DPRINTF(("pci_xhci: config_ep slotstate x%x != addressed", 1075 dev->dev_slotstate)); 1076 cmderr = XHCI_TRB_ERROR_SLOT_NOT_ON; 1077 goto done; 1078 } 1079 1080 /* In addressed/configured state; 1081 * for each drop endpoint ctx flag: 1082 * ep->state = DISABLED 1083 * for each add endpoint ctx flag: 1084 * cp(ep-in, ep-out) 1085 * ep->state = RUNNING 1086 * for each drop+add endpoint flag: 1087 * reset ep resources 1088 * cp(ep-in, ep-out) 1089 * ep->state = RUNNING 1090 * if input->DisabledCtx[2-31] < 30: (at least 1 ep not disabled) 1091 * slot->state = configured 1092 */ 1093 1094 input_ctx = XHCI_GADDR(sc, trb->qwTrb0 & ~0xFUL); 1095 dev_ctx = dev->dev_ctx; 1096 DPRINTF(("pci_xhci: config_ep inputctx: D:x%08x A:x%08x 7:x%08x", 1097 input_ctx->ctx_input.dwInCtx0, input_ctx->ctx_input.dwInCtx1, 1098 input_ctx->ctx_input.dwInCtx7)); 1099 1100 for (i = 2; i <= 31; i++) { 1101 ep_ctx = &dev_ctx->ctx_ep[i]; 1102 1103 if (input_ctx->ctx_input.dwInCtx0 & 1104 XHCI_INCTX_0_DROP_MASK(i)) { 1105 DPRINTF((" config ep - dropping ep %d", i)); 1106 pci_xhci_disable_ep(dev, i); 1107 } 1108 1109 if (input_ctx->ctx_input.dwInCtx1 & 1110 XHCI_INCTX_1_ADD_MASK(i)) { 1111 iep_ctx = &input_ctx->ctx_ep[i]; 1112 1113 DPRINTF((" enable ep[%d] %08x %08x %016lx %08x", 1114 i, iep_ctx->dwEpCtx0, iep_ctx->dwEpCtx1, 1115 iep_ctx->qwEpCtx2, iep_ctx->dwEpCtx4)); 1116 1117 memcpy(ep_ctx, iep_ctx, sizeof(struct xhci_endp_ctx)); 1118 1119 pci_xhci_init_ep(dev, i); 1120 1121 /* ep state */ 1122 ep_ctx->dwEpCtx0 = FIELD_REPLACE( 1123 ep_ctx->dwEpCtx0, XHCI_ST_EPCTX_RUNNING, 0x7, 0); 1124 } 1125 } 1126 1127 /* slot state to configured */ 1128 dev_ctx->ctx_slot.dwSctx3 = FIELD_REPLACE( 1129 dev_ctx->ctx_slot.dwSctx3, XHCI_ST_SLCTX_CONFIGURED, 0x1F, 27); 1130 dev_ctx->ctx_slot.dwSctx0 = FIELD_COPY( 1131 dev_ctx->ctx_slot.dwSctx0, input_ctx->ctx_slot.dwSctx0, 0x1F, 27); 1132 dev->dev_slotstate = XHCI_ST_CONFIGURED; 1133 1134 DPRINTF(("EP configured; slot %u [0]=0x%08x [1]=0x%08x [2]=0x%08x " 1135 "[3]=0x%08x", 1136 slot, dev_ctx->ctx_slot.dwSctx0, dev_ctx->ctx_slot.dwSctx1, 1137 dev_ctx->ctx_slot.dwSctx2, dev_ctx->ctx_slot.dwSctx3)); 1138 1139 done: 1140 return (cmderr); 1141 } 1142 1143 static uint32_t 1144 pci_xhci_cmd_reset_ep(struct pci_xhci_softc *sc, uint32_t slot, 1145 struct xhci_trb *trb) 1146 { 1147 struct pci_xhci_dev_emu *dev; 1148 struct pci_xhci_dev_ep *devep; 1149 struct xhci_dev_ctx *dev_ctx; 1150 struct xhci_endp_ctx *ep_ctx; 1151 uint32_t cmderr, epid; 1152 uint32_t type; 1153 1154 epid = XHCI_TRB_3_EP_GET(trb->dwTrb3); 1155 1156 DPRINTF(("pci_xhci: reset ep %u: slot %u", epid, slot)); 1157 1158 cmderr = pci_xhci_validate_slot(slot); 1159 if (cmderr != XHCI_TRB_ERROR_SUCCESS) 1160 goto done; 1161 1162 dev = XHCI_SLOTDEV_PTR(sc, slot); 1163 assert(dev != NULL); 1164 1165 type = XHCI_TRB_3_TYPE_GET(trb->dwTrb3); 1166 1167 if (type == XHCI_TRB_TYPE_STOP_EP && 1168 (trb->dwTrb3 & XHCI_TRB_3_SUSP_EP_BIT) != 0) { 1169 /* XXX suspend endpoint for 10ms */ 1170 } 1171 1172 if (epid < 1 || epid > 31) { 1173 DPRINTF(("pci_xhci: reset ep: invalid epid %u", epid)); 1174 cmderr = XHCI_TRB_ERROR_TRB; 1175 goto done; 1176 } 1177 1178 devep = &dev->eps[epid]; 1179 if (devep->ep_xfer != NULL) 1180 USB_DATA_XFER_RESET(devep->ep_xfer); 1181 1182 dev_ctx = dev->dev_ctx; 1183 assert(dev_ctx != NULL); 1184 1185 ep_ctx = &dev_ctx->ctx_ep[epid]; 1186 1187 ep_ctx->dwEpCtx0 = (ep_ctx->dwEpCtx0 & ~0x7) | XHCI_ST_EPCTX_STOPPED; 1188 1189 if (devep->ep_MaxPStreams == 0) 1190 ep_ctx->qwEpCtx2 = devep->ep_ringaddr | devep->ep_ccs; 1191 1192 DPRINTF(("pci_xhci: reset ep[%u] %08x %08x %016lx %08x", 1193 epid, ep_ctx->dwEpCtx0, ep_ctx->dwEpCtx1, ep_ctx->qwEpCtx2, 1194 ep_ctx->dwEpCtx4)); 1195 1196 if (type == XHCI_TRB_TYPE_RESET_EP && 1197 (dev->dev_ue->ue_reset == NULL || 1198 dev->dev_ue->ue_reset(dev->dev_sc) < 0)) { 1199 cmderr = XHCI_TRB_ERROR_ENDP_NOT_ON; 1200 goto done; 1201 } 1202 1203 done: 1204 return (cmderr); 1205 } 1206 1207 1208 static uint32_t 1209 pci_xhci_find_stream(struct pci_xhci_softc *sc, struct xhci_endp_ctx *ep, 1210 struct pci_xhci_dev_ep *devep, uint32_t streamid) 1211 { 1212 struct xhci_stream_ctx *sctx; 1213 1214 if (devep->ep_MaxPStreams == 0) 1215 return (XHCI_TRB_ERROR_TRB); 1216 1217 if (devep->ep_MaxPStreams > XHCI_STREAMS_MAX) 1218 return (XHCI_TRB_ERROR_INVALID_SID); 1219 1220 if (XHCI_EPCTX_0_LSA_GET(ep->dwEpCtx0) == 0) { 1221 DPRINTF(("pci_xhci: find_stream; LSA bit not set")); 1222 return (XHCI_TRB_ERROR_INVALID_SID); 1223 } 1224 1225 /* only support primary stream */ 1226 if (streamid >= devep->ep_MaxPStreams) 1227 return (XHCI_TRB_ERROR_STREAM_TYPE); 1228 1229 sctx = (struct xhci_stream_ctx *)XHCI_GADDR(sc, ep->qwEpCtx2 & ~0xFUL) + 1230 streamid; 1231 if (!XHCI_SCTX_0_SCT_GET(sctx->qwSctx0)) 1232 return (XHCI_TRB_ERROR_STREAM_TYPE); 1233 1234 return (XHCI_TRB_ERROR_SUCCESS); 1235 } 1236 1237 1238 static uint32_t 1239 pci_xhci_cmd_set_tr(struct pci_xhci_softc *sc, uint32_t slot, 1240 struct xhci_trb *trb) 1241 { 1242 struct pci_xhci_dev_emu *dev; 1243 struct pci_xhci_dev_ep *devep; 1244 struct xhci_dev_ctx *dev_ctx; 1245 struct xhci_endp_ctx *ep_ctx; 1246 uint32_t cmderr, epid; 1247 uint32_t streamid; 1248 1249 cmderr = pci_xhci_validate_slot(slot); 1250 if (cmderr != XHCI_TRB_ERROR_SUCCESS) 1251 goto done; 1252 1253 dev = XHCI_SLOTDEV_PTR(sc, slot); 1254 assert(dev != NULL); 1255 1256 DPRINTF(("pci_xhci set_tr: new-tr x%016lx, SCT %u DCS %u", 1257 (trb->qwTrb0 & ~0xF), (uint32_t)((trb->qwTrb0 >> 1) & 0x7), 1258 (uint32_t)(trb->qwTrb0 & 0x1))); 1259 DPRINTF((" stream-id %u, slot %u, epid %u, C %u", 1260 (trb->dwTrb2 >> 16) & 0xFFFF, 1261 XHCI_TRB_3_SLOT_GET(trb->dwTrb3), 1262 XHCI_TRB_3_EP_GET(trb->dwTrb3), trb->dwTrb3 & 0x1)); 1263 1264 epid = XHCI_TRB_3_EP_GET(trb->dwTrb3); 1265 if (epid < 1 || epid > 31) { 1266 DPRINTF(("pci_xhci: set_tr_deq: invalid epid %u", epid)); 1267 cmderr = XHCI_TRB_ERROR_TRB; 1268 goto done; 1269 } 1270 1271 dev_ctx = dev->dev_ctx; 1272 assert(dev_ctx != NULL); 1273 1274 ep_ctx = &dev_ctx->ctx_ep[epid]; 1275 devep = &dev->eps[epid]; 1276 1277 switch (XHCI_EPCTX_0_EPSTATE_GET(ep_ctx->dwEpCtx0)) { 1278 case XHCI_ST_EPCTX_STOPPED: 1279 case XHCI_ST_EPCTX_ERROR: 1280 break; 1281 default: 1282 DPRINTF(("pci_xhci cmd set_tr invalid state %x", 1283 XHCI_EPCTX_0_EPSTATE_GET(ep_ctx->dwEpCtx0))); 1284 cmderr = XHCI_TRB_ERROR_CONTEXT_STATE; 1285 goto done; 1286 } 1287 1288 streamid = XHCI_TRB_2_STREAM_GET(trb->dwTrb2); 1289 if (devep->ep_MaxPStreams > 0) { 1290 cmderr = pci_xhci_find_stream(sc, ep_ctx, devep, streamid); 1291 if (cmderr == XHCI_TRB_ERROR_SUCCESS) { 1292 assert(devep->ep_sctx != NULL); 1293 1294 devep->ep_sctx[streamid].qwSctx0 = trb->qwTrb0; 1295 devep->ep_sctx_trbs[streamid].ringaddr = 1296 trb->qwTrb0 & ~0xF; 1297 devep->ep_sctx_trbs[streamid].ccs = 1298 XHCI_EPCTX_2_DCS_GET(trb->qwTrb0); 1299 } 1300 } else { 1301 if (streamid != 0) { 1302 DPRINTF(("pci_xhci cmd set_tr streamid %x != 0", 1303 streamid)); 1304 } 1305 ep_ctx->qwEpCtx2 = trb->qwTrb0 & ~0xFUL; 1306 devep->ep_ringaddr = ep_ctx->qwEpCtx2 & ~0xFUL; 1307 devep->ep_ccs = trb->qwTrb0 & 0x1; 1308 devep->ep_tr = XHCI_GADDR(sc, devep->ep_ringaddr); 1309 1310 DPRINTF(("pci_xhci set_tr first TRB:")); 1311 pci_xhci_dump_trb(devep->ep_tr); 1312 } 1313 ep_ctx->dwEpCtx0 = (ep_ctx->dwEpCtx0 & ~0x7) | XHCI_ST_EPCTX_STOPPED; 1314 1315 done: 1316 return (cmderr); 1317 } 1318 1319 static uint32_t 1320 pci_xhci_cmd_eval_ctx(struct pci_xhci_softc *sc, uint32_t slot, 1321 struct xhci_trb *trb) 1322 { 1323 struct xhci_input_dev_ctx *input_ctx; 1324 struct xhci_slot_ctx *islot_ctx; 1325 struct xhci_dev_ctx *dev_ctx; 1326 struct xhci_endp_ctx *ep0_ctx; 1327 uint32_t cmderr; 1328 1329 input_ctx = XHCI_GADDR(sc, trb->qwTrb0 & ~0xFUL); 1330 islot_ctx = &input_ctx->ctx_slot; 1331 ep0_ctx = &input_ctx->ctx_ep[1]; 1332 1333 DPRINTF(("pci_xhci: eval ctx, input ctl: D 0x%08x A 0x%08x,", 1334 input_ctx->ctx_input.dwInCtx0, input_ctx->ctx_input.dwInCtx1)); 1335 DPRINTF((" slot %08x %08x %08x %08x", 1336 islot_ctx->dwSctx0, islot_ctx->dwSctx1, 1337 islot_ctx->dwSctx2, islot_ctx->dwSctx3)); 1338 DPRINTF((" ep0 %08x %08x %016lx %08x", 1339 ep0_ctx->dwEpCtx0, ep0_ctx->dwEpCtx1, ep0_ctx->qwEpCtx2, 1340 ep0_ctx->dwEpCtx4)); 1341 1342 /* this command expects drop-ctx=0 & add-ctx=slot+ep0 */ 1343 if ((input_ctx->ctx_input.dwInCtx0 != 0) || 1344 (input_ctx->ctx_input.dwInCtx1 & 0x03) == 0) { 1345 DPRINTF(("pci_xhci: eval ctx, input ctl invalid")); 1346 cmderr = XHCI_TRB_ERROR_TRB; 1347 goto done; 1348 } 1349 1350 cmderr = pci_xhci_validate_slot(slot); 1351 if (cmderr != XHCI_TRB_ERROR_SUCCESS) 1352 goto done; 1353 1354 /* assign address to slot; in this emulation, slot_id = address */ 1355 dev_ctx = pci_xhci_get_dev_ctx(sc, slot); 1356 if (dev_ctx == NULL) { 1357 cmderr = XHCI_TRB_ERROR_PARAMETER; 1358 goto done; 1359 } 1360 1361 DPRINTF(("pci_xhci: eval ctx, dev ctx")); 1362 DPRINTF((" slot %08x %08x %08x %08x", 1363 dev_ctx->ctx_slot.dwSctx0, dev_ctx->ctx_slot.dwSctx1, 1364 dev_ctx->ctx_slot.dwSctx2, dev_ctx->ctx_slot.dwSctx3)); 1365 1366 if (input_ctx->ctx_input.dwInCtx1 & 0x01) { /* slot ctx */ 1367 /* set max exit latency */ 1368 dev_ctx->ctx_slot.dwSctx1 = FIELD_COPY( 1369 dev_ctx->ctx_slot.dwSctx1, input_ctx->ctx_slot.dwSctx1, 1370 0xFFFF, 0); 1371 1372 /* set interrupter target */ 1373 dev_ctx->ctx_slot.dwSctx2 = FIELD_COPY( 1374 dev_ctx->ctx_slot.dwSctx2, input_ctx->ctx_slot.dwSctx2, 1375 0x3FF, 22); 1376 } 1377 if (input_ctx->ctx_input.dwInCtx1 & 0x02) { /* control ctx */ 1378 /* set max packet size */ 1379 dev_ctx->ctx_ep[1].dwEpCtx1 = FIELD_COPY( 1380 dev_ctx->ctx_ep[1].dwEpCtx1, ep0_ctx->dwEpCtx1, 1381 0xFFFF, 16); 1382 1383 ep0_ctx = &dev_ctx->ctx_ep[1]; 1384 } 1385 1386 DPRINTF(("pci_xhci: eval ctx, output ctx")); 1387 DPRINTF((" slot %08x %08x %08x %08x", 1388 dev_ctx->ctx_slot.dwSctx0, dev_ctx->ctx_slot.dwSctx1, 1389 dev_ctx->ctx_slot.dwSctx2, dev_ctx->ctx_slot.dwSctx3)); 1390 DPRINTF((" ep0 %08x %08x %016lx %08x", 1391 ep0_ctx->dwEpCtx0, ep0_ctx->dwEpCtx1, ep0_ctx->qwEpCtx2, 1392 ep0_ctx->dwEpCtx4)); 1393 1394 done: 1395 return (cmderr); 1396 } 1397 1398 static int 1399 pci_xhci_complete_commands(struct pci_xhci_softc *sc) 1400 { 1401 struct xhci_trb evtrb; 1402 struct xhci_trb *trb; 1403 uint64_t crcr; 1404 uint32_t ccs; /* cycle state (XHCI 4.9.2) */ 1405 uint32_t type; 1406 uint32_t slot; 1407 uint32_t cmderr; 1408 int error; 1409 1410 error = 0; 1411 sc->opregs.crcr |= XHCI_CRCR_LO_CRR; 1412 1413 trb = sc->opregs.cr_p; 1414 ccs = sc->opregs.crcr & XHCI_CRCR_LO_RCS; 1415 crcr = sc->opregs.crcr & ~0xF; 1416 1417 while (1) { 1418 sc->opregs.cr_p = trb; 1419 1420 type = XHCI_TRB_3_TYPE_GET(trb->dwTrb3); 1421 1422 if ((trb->dwTrb3 & XHCI_TRB_3_CYCLE_BIT) != 1423 (ccs & XHCI_TRB_3_CYCLE_BIT)) 1424 break; 1425 1426 DPRINTF(("pci_xhci: cmd type 0x%x, Trb0 x%016lx dwTrb2 x%08x" 1427 " dwTrb3 x%08x, TRB_CYCLE %u/ccs %u", 1428 type, trb->qwTrb0, trb->dwTrb2, trb->dwTrb3, 1429 trb->dwTrb3 & XHCI_TRB_3_CYCLE_BIT, ccs)); 1430 1431 cmderr = XHCI_TRB_ERROR_SUCCESS; 1432 evtrb.dwTrb2 = 0; 1433 evtrb.dwTrb3 = (ccs & XHCI_TRB_3_CYCLE_BIT) | 1434 XHCI_TRB_3_TYPE_SET(XHCI_TRB_EVENT_CMD_COMPLETE); 1435 slot = 0; 1436 1437 switch (type) { 1438 case XHCI_TRB_TYPE_LINK: /* 0x06 */ 1439 if (trb->dwTrb3 & XHCI_TRB_3_TC_BIT) 1440 ccs ^= XHCI_CRCR_LO_RCS; 1441 break; 1442 1443 case XHCI_TRB_TYPE_ENABLE_SLOT: /* 0x09 */ 1444 cmderr = pci_xhci_cmd_enable_slot(sc, &slot); 1445 break; 1446 1447 case XHCI_TRB_TYPE_DISABLE_SLOT: /* 0x0A */ 1448 slot = XHCI_TRB_3_SLOT_GET(trb->dwTrb3); 1449 cmderr = pci_xhci_cmd_disable_slot(sc, slot); 1450 break; 1451 1452 case XHCI_TRB_TYPE_ADDRESS_DEVICE: /* 0x0B */ 1453 slot = XHCI_TRB_3_SLOT_GET(trb->dwTrb3); 1454 cmderr = pci_xhci_cmd_address_device(sc, slot, trb); 1455 break; 1456 1457 case XHCI_TRB_TYPE_CONFIGURE_EP: /* 0x0C */ 1458 slot = XHCI_TRB_3_SLOT_GET(trb->dwTrb3); 1459 cmderr = pci_xhci_cmd_config_ep(sc, slot, trb); 1460 break; 1461 1462 case XHCI_TRB_TYPE_EVALUATE_CTX: /* 0x0D */ 1463 slot = XHCI_TRB_3_SLOT_GET(trb->dwTrb3); 1464 cmderr = pci_xhci_cmd_eval_ctx(sc, slot, trb); 1465 break; 1466 1467 case XHCI_TRB_TYPE_RESET_EP: /* 0x0E */ 1468 DPRINTF(("Reset Endpoint on slot %d", slot)); 1469 slot = XHCI_TRB_3_SLOT_GET(trb->dwTrb3); 1470 cmderr = pci_xhci_cmd_reset_ep(sc, slot, trb); 1471 break; 1472 1473 case XHCI_TRB_TYPE_STOP_EP: /* 0x0F */ 1474 DPRINTF(("Stop Endpoint on slot %d", slot)); 1475 slot = XHCI_TRB_3_SLOT_GET(trb->dwTrb3); 1476 cmderr = pci_xhci_cmd_reset_ep(sc, slot, trb); 1477 break; 1478 1479 case XHCI_TRB_TYPE_SET_TR_DEQUEUE: /* 0x10 */ 1480 slot = XHCI_TRB_3_SLOT_GET(trb->dwTrb3); 1481 cmderr = pci_xhci_cmd_set_tr(sc, slot, trb); 1482 break; 1483 1484 case XHCI_TRB_TYPE_RESET_DEVICE: /* 0x11 */ 1485 slot = XHCI_TRB_3_SLOT_GET(trb->dwTrb3); 1486 cmderr = pci_xhci_cmd_reset_device(sc, slot); 1487 break; 1488 1489 case XHCI_TRB_TYPE_FORCE_EVENT: /* 0x12 */ 1490 /* TODO: */ 1491 break; 1492 1493 case XHCI_TRB_TYPE_NEGOTIATE_BW: /* 0x13 */ 1494 break; 1495 1496 case XHCI_TRB_TYPE_SET_LATENCY_TOL: /* 0x14 */ 1497 break; 1498 1499 case XHCI_TRB_TYPE_GET_PORT_BW: /* 0x15 */ 1500 break; 1501 1502 case XHCI_TRB_TYPE_FORCE_HEADER: /* 0x16 */ 1503 break; 1504 1505 case XHCI_TRB_TYPE_NOOP_CMD: /* 0x17 */ 1506 break; 1507 1508 default: 1509 DPRINTF(("pci_xhci: unsupported cmd %x", type)); 1510 break; 1511 } 1512 1513 if (type != XHCI_TRB_TYPE_LINK) { 1514 /* 1515 * insert command completion event and assert intr 1516 */ 1517 evtrb.qwTrb0 = crcr; 1518 evtrb.dwTrb2 |= XHCI_TRB_2_ERROR_SET(cmderr); 1519 evtrb.dwTrb3 |= XHCI_TRB_3_SLOT_SET(slot); 1520 DPRINTF(("pci_xhci: command 0x%x result: 0x%x", 1521 type, cmderr)); 1522 pci_xhci_insert_event(sc, &evtrb, 1); 1523 } 1524 1525 trb = pci_xhci_trb_next(sc, trb, &crcr); 1526 } 1527 1528 sc->opregs.crcr = crcr | (sc->opregs.crcr & XHCI_CRCR_LO_CA) | ccs; 1529 sc->opregs.crcr &= ~XHCI_CRCR_LO_CRR; 1530 return (error); 1531 } 1532 1533 static void 1534 pci_xhci_dump_trb(struct xhci_trb *trb) 1535 { 1536 static const char *trbtypes[] = { 1537 "RESERVED", 1538 "NORMAL", 1539 "SETUP_STAGE", 1540 "DATA_STAGE", 1541 "STATUS_STAGE", 1542 "ISOCH", 1543 "LINK", 1544 "EVENT_DATA", 1545 "NOOP", 1546 "ENABLE_SLOT", 1547 "DISABLE_SLOT", 1548 "ADDRESS_DEVICE", 1549 "CONFIGURE_EP", 1550 "EVALUATE_CTX", 1551 "RESET_EP", 1552 "STOP_EP", 1553 "SET_TR_DEQUEUE", 1554 "RESET_DEVICE", 1555 "FORCE_EVENT", 1556 "NEGOTIATE_BW", 1557 "SET_LATENCY_TOL", 1558 "GET_PORT_BW", 1559 "FORCE_HEADER", 1560 "NOOP_CMD" 1561 }; 1562 uint32_t type; 1563 1564 type = XHCI_TRB_3_TYPE_GET(trb->dwTrb3); 1565 DPRINTF(("pci_xhci: trb[@%p] type x%02x %s 0:x%016lx 2:x%08x 3:x%08x", 1566 trb, type, 1567 type <= XHCI_TRB_TYPE_NOOP_CMD ? trbtypes[type] : "INVALID", 1568 trb->qwTrb0, trb->dwTrb2, trb->dwTrb3)); 1569 } 1570 1571 static int 1572 pci_xhci_xfer_complete(struct pci_xhci_softc *sc, struct usb_data_xfer *xfer, 1573 uint32_t slot, uint32_t epid, int *do_intr) 1574 { 1575 struct pci_xhci_dev_emu *dev; 1576 struct pci_xhci_dev_ep *devep; 1577 struct xhci_dev_ctx *dev_ctx; 1578 struct xhci_endp_ctx *ep_ctx; 1579 struct xhci_trb *trb; 1580 struct xhci_trb evtrb; 1581 uint32_t trbflags; 1582 uint32_t edtla; 1583 int i, err; 1584 1585 dev = XHCI_SLOTDEV_PTR(sc, slot); 1586 devep = &dev->eps[epid]; 1587 dev_ctx = pci_xhci_get_dev_ctx(sc, slot); 1588 if (dev_ctx == NULL) { 1589 return XHCI_TRB_ERROR_PARAMETER; 1590 } 1591 1592 ep_ctx = &dev_ctx->ctx_ep[epid]; 1593 1594 err = XHCI_TRB_ERROR_SUCCESS; 1595 *do_intr = 0; 1596 edtla = 0; 1597 1598 /* go through list of TRBs and insert event(s) */ 1599 for (i = xfer->head; xfer->ndata > 0; ) { 1600 evtrb.qwTrb0 = (uint64_t)xfer->data[i].hci_data; 1601 trb = XHCI_GADDR(sc, evtrb.qwTrb0); 1602 trbflags = trb->dwTrb3; 1603 1604 DPRINTF(("pci_xhci: xfer[%d] done?%u:%d trb %x %016lx %x " 1605 "(err %d) IOC?%d", 1606 i, xfer->data[i].processed, xfer->data[i].blen, 1607 XHCI_TRB_3_TYPE_GET(trbflags), evtrb.qwTrb0, 1608 trbflags, err, 1609 trb->dwTrb3 & XHCI_TRB_3_IOC_BIT ? 1 : 0)); 1610 1611 if (!xfer->data[i].processed) { 1612 xfer->head = i; 1613 break; 1614 } 1615 1616 xfer->ndata--; 1617 edtla += xfer->data[i].bdone; 1618 1619 trb->dwTrb3 = (trb->dwTrb3 & ~0x1) | (xfer->data[i].ccs); 1620 1621 pci_xhci_update_ep_ring(sc, dev, devep, ep_ctx, 1622 xfer->data[i].streamid, xfer->data[i].trbnext, 1623 xfer->data[i].ccs); 1624 1625 /* Only interrupt if IOC or short packet */ 1626 if (!(trb->dwTrb3 & XHCI_TRB_3_IOC_BIT) && 1627 !((err == XHCI_TRB_ERROR_SHORT_PKT) && 1628 (trb->dwTrb3 & XHCI_TRB_3_ISP_BIT))) { 1629 1630 i = (i + 1) % USB_MAX_XFER_BLOCKS; 1631 continue; 1632 } 1633 1634 evtrb.dwTrb2 = XHCI_TRB_2_ERROR_SET(err) | 1635 XHCI_TRB_2_REM_SET(xfer->data[i].blen); 1636 1637 evtrb.dwTrb3 = XHCI_TRB_3_TYPE_SET(XHCI_TRB_EVENT_TRANSFER) | 1638 XHCI_TRB_3_SLOT_SET(slot) | XHCI_TRB_3_EP_SET(epid); 1639 1640 if (XHCI_TRB_3_TYPE_GET(trbflags) == XHCI_TRB_TYPE_EVENT_DATA) { 1641 DPRINTF(("pci_xhci EVENT_DATA edtla %u", edtla)); 1642 evtrb.qwTrb0 = trb->qwTrb0; 1643 evtrb.dwTrb2 = (edtla & 0xFFFFF) | 1644 XHCI_TRB_2_ERROR_SET(err); 1645 evtrb.dwTrb3 |= XHCI_TRB_3_ED_BIT; 1646 edtla = 0; 1647 } 1648 1649 *do_intr = 1; 1650 1651 err = pci_xhci_insert_event(sc, &evtrb, 0); 1652 if (err != XHCI_TRB_ERROR_SUCCESS) { 1653 break; 1654 } 1655 1656 i = (i + 1) % USB_MAX_XFER_BLOCKS; 1657 } 1658 1659 return (err); 1660 } 1661 1662 static void 1663 pci_xhci_update_ep_ring(struct pci_xhci_softc *sc, 1664 struct pci_xhci_dev_emu *dev __unused, struct pci_xhci_dev_ep *devep, 1665 struct xhci_endp_ctx *ep_ctx, uint32_t streamid, uint64_t ringaddr, int ccs) 1666 { 1667 1668 if (devep->ep_MaxPStreams != 0) { 1669 devep->ep_sctx[streamid].qwSctx0 = (ringaddr & ~0xFUL) | 1670 (ccs & 0x1); 1671 1672 devep->ep_sctx_trbs[streamid].ringaddr = ringaddr & ~0xFUL; 1673 devep->ep_sctx_trbs[streamid].ccs = ccs & 0x1; 1674 ep_ctx->qwEpCtx2 = (ep_ctx->qwEpCtx2 & ~0x1) | (ccs & 0x1); 1675 1676 DPRINTF(("xhci update ep-ring stream %d, addr %lx", 1677 streamid, devep->ep_sctx[streamid].qwSctx0)); 1678 } else { 1679 devep->ep_ringaddr = ringaddr & ~0xFUL; 1680 devep->ep_ccs = ccs & 0x1; 1681 devep->ep_tr = XHCI_GADDR(sc, ringaddr & ~0xFUL); 1682 ep_ctx->qwEpCtx2 = (ringaddr & ~0xFUL) | (ccs & 0x1); 1683 1684 DPRINTF(("xhci update ep-ring, addr %lx", 1685 (devep->ep_ringaddr | devep->ep_ccs))); 1686 } 1687 } 1688 1689 static int 1690 pci_xhci_validate_slot(uint32_t slot) 1691 { 1692 if (slot == 0) 1693 return (XHCI_TRB_ERROR_TRB); 1694 else if (slot > XHCI_MAX_SLOTS) 1695 return (XHCI_TRB_ERROR_SLOT_NOT_ON); 1696 else 1697 return (XHCI_TRB_ERROR_SUCCESS); 1698 } 1699 1700 /* 1701 * Outstanding transfer still in progress (device NAK'd earlier) so retry 1702 * the transfer again to see if it succeeds. 1703 */ 1704 static int 1705 pci_xhci_try_usb_xfer(struct pci_xhci_softc *sc, 1706 struct pci_xhci_dev_emu *dev, struct pci_xhci_dev_ep *devep, 1707 struct xhci_endp_ctx *ep_ctx, uint32_t slot, uint32_t epid) 1708 { 1709 struct usb_data_xfer *xfer; 1710 int err; 1711 int do_intr; 1712 1713 ep_ctx->dwEpCtx0 = FIELD_REPLACE( 1714 ep_ctx->dwEpCtx0, XHCI_ST_EPCTX_RUNNING, 0x7, 0); 1715 1716 err = 0; 1717 do_intr = 0; 1718 1719 xfer = devep->ep_xfer; 1720 USB_DATA_XFER_LOCK(xfer); 1721 1722 /* outstanding requests queued up */ 1723 if (dev->dev_ue->ue_data != NULL) { 1724 err = dev->dev_ue->ue_data(dev->dev_sc, xfer, 1725 epid & 0x1 ? USB_XFER_IN : USB_XFER_OUT, epid/2); 1726 if (err == USB_ERR_CANCELLED) { 1727 if (USB_DATA_GET_ERRCODE(&xfer->data[xfer->head]) == 1728 USB_NAK) 1729 err = XHCI_TRB_ERROR_SUCCESS; 1730 } else { 1731 err = pci_xhci_xfer_complete(sc, xfer, slot, epid, 1732 &do_intr); 1733 if (err == XHCI_TRB_ERROR_SUCCESS && do_intr) { 1734 pci_xhci_assert_interrupt(sc); 1735 } 1736 1737 1738 /* XXX should not do it if error? */ 1739 USB_DATA_XFER_RESET(xfer); 1740 } 1741 } 1742 1743 USB_DATA_XFER_UNLOCK(xfer); 1744 1745 1746 return (err); 1747 } 1748 1749 1750 static int 1751 pci_xhci_handle_transfer(struct pci_xhci_softc *sc, 1752 struct pci_xhci_dev_emu *dev, struct pci_xhci_dev_ep *devep, 1753 struct xhci_endp_ctx *ep_ctx, struct xhci_trb *trb, uint32_t slot, 1754 uint32_t epid, uint64_t addr, uint32_t ccs, uint32_t streamid) 1755 { 1756 struct xhci_trb *setup_trb; 1757 struct usb_data_xfer *xfer; 1758 struct usb_data_xfer_block *xfer_block; 1759 uint64_t val; 1760 uint32_t trbflags; 1761 int do_intr, err; 1762 int do_retry; 1763 1764 ep_ctx->dwEpCtx0 = FIELD_REPLACE(ep_ctx->dwEpCtx0, 1765 XHCI_ST_EPCTX_RUNNING, 0x7, 0); 1766 1767 xfer = devep->ep_xfer; 1768 USB_DATA_XFER_LOCK(xfer); 1769 1770 DPRINTF(("pci_xhci handle_transfer slot %u", slot)); 1771 1772 retry: 1773 err = XHCI_TRB_ERROR_INVALID; 1774 do_retry = 0; 1775 do_intr = 0; 1776 setup_trb = NULL; 1777 1778 while (1) { 1779 pci_xhci_dump_trb(trb); 1780 1781 trbflags = trb->dwTrb3; 1782 1783 if (XHCI_TRB_3_TYPE_GET(trbflags) != XHCI_TRB_TYPE_LINK && 1784 (trbflags & XHCI_TRB_3_CYCLE_BIT) != 1785 (ccs & XHCI_TRB_3_CYCLE_BIT)) { 1786 DPRINTF(("Cycle-bit changed trbflags %x, ccs %x", 1787 trbflags & XHCI_TRB_3_CYCLE_BIT, ccs)); 1788 break; 1789 } 1790 1791 xfer_block = NULL; 1792 1793 switch (XHCI_TRB_3_TYPE_GET(trbflags)) { 1794 case XHCI_TRB_TYPE_LINK: 1795 if (trb->dwTrb3 & XHCI_TRB_3_TC_BIT) 1796 ccs ^= 0x1; 1797 1798 xfer_block = usb_data_xfer_append(xfer, NULL, 0, 1799 (void *)addr, ccs); 1800 xfer_block->processed = 1; 1801 break; 1802 1803 case XHCI_TRB_TYPE_SETUP_STAGE: 1804 if ((trbflags & XHCI_TRB_3_IDT_BIT) == 0 || 1805 XHCI_TRB_2_BYTES_GET(trb->dwTrb2) != 8) { 1806 DPRINTF(("pci_xhci: invalid setup trb")); 1807 err = XHCI_TRB_ERROR_TRB; 1808 goto errout; 1809 } 1810 setup_trb = trb; 1811 1812 val = trb->qwTrb0; 1813 if (!xfer->ureq) 1814 xfer->ureq = malloc( 1815 sizeof(struct usb_device_request)); 1816 memcpy(xfer->ureq, &val, 1817 sizeof(struct usb_device_request)); 1818 1819 xfer_block = usb_data_xfer_append(xfer, NULL, 0, 1820 (void *)addr, ccs); 1821 xfer_block->processed = 1; 1822 break; 1823 1824 case XHCI_TRB_TYPE_NORMAL: 1825 case XHCI_TRB_TYPE_ISOCH: 1826 if (setup_trb != NULL) { 1827 DPRINTF(("pci_xhci: trb not supposed to be in " 1828 "ctl scope")); 1829 err = XHCI_TRB_ERROR_TRB; 1830 goto errout; 1831 } 1832 /* fall through */ 1833 1834 case XHCI_TRB_TYPE_DATA_STAGE: 1835 xfer_block = usb_data_xfer_append(xfer, 1836 (void *)(trbflags & XHCI_TRB_3_IDT_BIT ? 1837 &trb->qwTrb0 : XHCI_GADDR(sc, trb->qwTrb0)), 1838 trb->dwTrb2 & 0x1FFFF, (void *)addr, ccs); 1839 break; 1840 1841 case XHCI_TRB_TYPE_STATUS_STAGE: 1842 xfer_block = usb_data_xfer_append(xfer, NULL, 0, 1843 (void *)addr, ccs); 1844 break; 1845 1846 case XHCI_TRB_TYPE_NOOP: 1847 xfer_block = usb_data_xfer_append(xfer, NULL, 0, 1848 (void *)addr, ccs); 1849 xfer_block->processed = 1; 1850 break; 1851 1852 case XHCI_TRB_TYPE_EVENT_DATA: 1853 xfer_block = usb_data_xfer_append(xfer, NULL, 0, 1854 (void *)addr, ccs); 1855 if ((epid > 1) && (trbflags & XHCI_TRB_3_IOC_BIT)) { 1856 xfer_block->processed = 1; 1857 } 1858 break; 1859 1860 default: 1861 DPRINTF(("pci_xhci: handle xfer unexpected trb type " 1862 "0x%x", 1863 XHCI_TRB_3_TYPE_GET(trbflags))); 1864 err = XHCI_TRB_ERROR_TRB; 1865 goto errout; 1866 } 1867 1868 trb = pci_xhci_trb_next(sc, trb, &addr); 1869 1870 DPRINTF(("pci_xhci: next trb: 0x%lx", (uint64_t)trb)); 1871 1872 if (xfer_block) { 1873 xfer_block->trbnext = addr; 1874 xfer_block->streamid = streamid; 1875 } 1876 1877 if (!setup_trb && !(trbflags & XHCI_TRB_3_CHAIN_BIT) && 1878 XHCI_TRB_3_TYPE_GET(trbflags) != XHCI_TRB_TYPE_LINK) { 1879 break; 1880 } 1881 1882 /* handle current batch that requires interrupt on complete */ 1883 if (trbflags & XHCI_TRB_3_IOC_BIT) { 1884 DPRINTF(("pci_xhci: trb IOC bit set")); 1885 if (epid == 1) 1886 do_retry = 1; 1887 break; 1888 } 1889 } 1890 1891 DPRINTF(("pci_xhci[%d]: xfer->ndata %u", __LINE__, xfer->ndata)); 1892 1893 if (xfer->ndata <= 0) 1894 goto errout; 1895 1896 if (epid == 1) { 1897 int usberr; 1898 1899 if (dev->dev_ue->ue_request != NULL) 1900 usberr = dev->dev_ue->ue_request(dev->dev_sc, xfer); 1901 else 1902 usberr = USB_ERR_NOT_STARTED; 1903 err = USB_TO_XHCI_ERR(usberr); 1904 if (err == XHCI_TRB_ERROR_SUCCESS || 1905 err == XHCI_TRB_ERROR_STALL || 1906 err == XHCI_TRB_ERROR_SHORT_PKT) { 1907 err = pci_xhci_xfer_complete(sc, xfer, slot, epid, 1908 &do_intr); 1909 if (err != XHCI_TRB_ERROR_SUCCESS) 1910 do_retry = 0; 1911 } 1912 1913 } else { 1914 /* handle data transfer */ 1915 pci_xhci_try_usb_xfer(sc, dev, devep, ep_ctx, slot, epid); 1916 err = XHCI_TRB_ERROR_SUCCESS; 1917 } 1918 1919 errout: 1920 if (err == XHCI_TRB_ERROR_EV_RING_FULL) 1921 DPRINTF(("pci_xhci[%d]: event ring full", __LINE__)); 1922 1923 if (!do_retry) 1924 USB_DATA_XFER_UNLOCK(xfer); 1925 1926 if (do_intr) 1927 pci_xhci_assert_interrupt(sc); 1928 1929 if (do_retry) { 1930 USB_DATA_XFER_RESET(xfer); 1931 DPRINTF(("pci_xhci[%d]: retry:continuing with next TRBs", 1932 __LINE__)); 1933 goto retry; 1934 } 1935 1936 if (epid == 1) 1937 USB_DATA_XFER_RESET(xfer); 1938 1939 return (err); 1940 } 1941 1942 static void 1943 pci_xhci_device_doorbell(struct pci_xhci_softc *sc, uint32_t slot, 1944 uint32_t epid, uint32_t streamid) 1945 { 1946 struct pci_xhci_dev_emu *dev; 1947 struct pci_xhci_dev_ep *devep; 1948 struct xhci_dev_ctx *dev_ctx; 1949 struct xhci_endp_ctx *ep_ctx; 1950 struct pci_xhci_trb_ring *sctx_tr; 1951 struct xhci_trb *trb; 1952 uint64_t ringaddr; 1953 uint32_t ccs; 1954 int error; 1955 1956 DPRINTF(("pci_xhci doorbell slot %u epid %u stream %u", 1957 slot, epid, streamid)); 1958 1959 if (slot == 0 || slot > XHCI_MAX_SLOTS) { 1960 DPRINTF(("pci_xhci: invalid doorbell slot %u", slot)); 1961 return; 1962 } 1963 1964 if (epid == 0 || epid >= XHCI_MAX_ENDPOINTS) { 1965 DPRINTF(("pci_xhci: invalid endpoint %u", epid)); 1966 return; 1967 } 1968 1969 dev = XHCI_SLOTDEV_PTR(sc, slot); 1970 devep = &dev->eps[epid]; 1971 dev_ctx = pci_xhci_get_dev_ctx(sc, slot); 1972 if (!dev_ctx) { 1973 return; 1974 } 1975 ep_ctx = &dev_ctx->ctx_ep[epid]; 1976 1977 sctx_tr = NULL; 1978 1979 DPRINTF(("pci_xhci: device doorbell ep[%u] %08x %08x %016lx %08x", 1980 epid, ep_ctx->dwEpCtx0, ep_ctx->dwEpCtx1, ep_ctx->qwEpCtx2, 1981 ep_ctx->dwEpCtx4)); 1982 1983 if (ep_ctx->qwEpCtx2 == 0) 1984 return; 1985 1986 /* handle pending transfers */ 1987 if (devep->ep_xfer->ndata > 0) { 1988 pci_xhci_try_usb_xfer(sc, dev, devep, ep_ctx, slot, epid); 1989 return; 1990 } 1991 1992 /* get next trb work item */ 1993 if (devep->ep_MaxPStreams != 0) { 1994 /* 1995 * Stream IDs of 0, 65535 (any stream), and 65534 1996 * (prime) are invalid. 1997 */ 1998 if (streamid == 0 || streamid == 65534 || streamid == 65535) { 1999 DPRINTF(("pci_xhci: invalid stream %u", streamid)); 2000 return; 2001 } 2002 2003 error = pci_xhci_find_stream(sc, ep_ctx, devep, streamid); 2004 if (error != XHCI_TRB_ERROR_SUCCESS) { 2005 DPRINTF(("pci_xhci: invalid stream %u: %d", 2006 streamid, error)); 2007 return; 2008 } 2009 sctx_tr = &devep->ep_sctx_trbs[streamid]; 2010 ringaddr = sctx_tr->ringaddr; 2011 ccs = sctx_tr->ccs; 2012 trb = XHCI_GADDR(sc, sctx_tr->ringaddr & ~0xFUL); 2013 DPRINTF(("doorbell, stream %u, ccs %lx, trb ccs %x", 2014 streamid, ep_ctx->qwEpCtx2 & XHCI_TRB_3_CYCLE_BIT, 2015 trb->dwTrb3 & XHCI_TRB_3_CYCLE_BIT)); 2016 } else { 2017 if (streamid != 0) { 2018 DPRINTF(("pci_xhci: invalid stream %u", streamid)); 2019 return; 2020 } 2021 ringaddr = devep->ep_ringaddr; 2022 ccs = devep->ep_ccs; 2023 trb = devep->ep_tr; 2024 DPRINTF(("doorbell, ccs %lx, trb ccs %x", 2025 ep_ctx->qwEpCtx2 & XHCI_TRB_3_CYCLE_BIT, 2026 trb->dwTrb3 & XHCI_TRB_3_CYCLE_BIT)); 2027 } 2028 2029 if (XHCI_TRB_3_TYPE_GET(trb->dwTrb3) == 0) { 2030 DPRINTF(("pci_xhci: ring %lx trb[%lx] EP %u is RESERVED?", 2031 ep_ctx->qwEpCtx2, devep->ep_ringaddr, epid)); 2032 return; 2033 } 2034 2035 pci_xhci_handle_transfer(sc, dev, devep, ep_ctx, trb, slot, epid, 2036 ringaddr, ccs, streamid); 2037 } 2038 2039 static void 2040 pci_xhci_dbregs_write(struct pci_xhci_softc *sc, uint64_t offset, 2041 uint64_t value) 2042 { 2043 2044 offset = (offset - sc->dboff) / sizeof(uint32_t); 2045 2046 DPRINTF(("pci_xhci: doorbell write offset 0x%lx: 0x%lx", 2047 offset, value)); 2048 2049 if (XHCI_HALTED(sc)) { 2050 DPRINTF(("pci_xhci: controller halted")); 2051 return; 2052 } 2053 2054 if (offset == 0) 2055 pci_xhci_complete_commands(sc); 2056 else if (sc->portregs != NULL) 2057 pci_xhci_device_doorbell(sc, offset, 2058 XHCI_DB_TARGET_GET(value), XHCI_DB_SID_GET(value)); 2059 } 2060 2061 static void 2062 pci_xhci_rtsregs_write(struct pci_xhci_softc *sc, uint64_t offset, 2063 uint64_t value) 2064 { 2065 struct pci_xhci_rtsregs *rts; 2066 2067 offset -= sc->rtsoff; 2068 2069 if (offset == 0) { 2070 DPRINTF(("pci_xhci attempted write to MFINDEX")); 2071 return; 2072 } 2073 2074 DPRINTF(("pci_xhci: runtime regs write offset 0x%lx: 0x%lx", 2075 offset, value)); 2076 2077 offset -= 0x20; /* start of intrreg */ 2078 2079 rts = &sc->rtsregs; 2080 2081 switch (offset) { 2082 case 0x00: 2083 if (value & XHCI_IMAN_INTR_PEND) 2084 rts->intrreg.iman &= ~XHCI_IMAN_INTR_PEND; 2085 rts->intrreg.iman = (value & XHCI_IMAN_INTR_ENA) | 2086 (rts->intrreg.iman & XHCI_IMAN_INTR_PEND); 2087 2088 if (!(value & XHCI_IMAN_INTR_ENA)) 2089 pci_xhci_deassert_interrupt(sc); 2090 2091 break; 2092 2093 case 0x04: 2094 rts->intrreg.imod = value; 2095 break; 2096 2097 case 0x08: 2098 rts->intrreg.erstsz = value & 0xFFFF; 2099 break; 2100 2101 case 0x10: 2102 /* ERSTBA low bits */ 2103 rts->intrreg.erstba = MASK_64_HI(sc->rtsregs.intrreg.erstba) | 2104 (value & ~0x3F); 2105 break; 2106 2107 case 0x14: 2108 /* ERSTBA high bits */ 2109 rts->intrreg.erstba = (value << 32) | 2110 MASK_64_LO(sc->rtsregs.intrreg.erstba); 2111 2112 rts->erstba_p = XHCI_GADDR(sc, 2113 sc->rtsregs.intrreg.erstba & ~0x3FUL); 2114 2115 rts->erst_p = XHCI_GADDR(sc, 2116 sc->rtsregs.erstba_p->qwEvrsTablePtr & ~0x3FUL); 2117 2118 rts->er_enq_idx = 0; 2119 rts->er_events_cnt = 0; 2120 2121 DPRINTF(("pci_xhci: wr erstba erst (%p) ptr 0x%lx, sz %u", 2122 rts->erstba_p, 2123 rts->erstba_p->qwEvrsTablePtr, 2124 rts->erstba_p->dwEvrsTableSize)); 2125 break; 2126 2127 case 0x18: 2128 /* ERDP low bits */ 2129 rts->intrreg.erdp = 2130 MASK_64_HI(sc->rtsregs.intrreg.erdp) | 2131 (rts->intrreg.erdp & XHCI_ERDP_LO_BUSY) | 2132 (value & ~0xF); 2133 if (value & XHCI_ERDP_LO_BUSY) { 2134 rts->intrreg.erdp &= ~XHCI_ERDP_LO_BUSY; 2135 rts->intrreg.iman &= ~XHCI_IMAN_INTR_PEND; 2136 } 2137 2138 rts->er_deq_seg = XHCI_ERDP_LO_SINDEX(value); 2139 2140 break; 2141 2142 case 0x1C: 2143 /* ERDP high bits */ 2144 rts->intrreg.erdp = (value << 32) | 2145 MASK_64_LO(sc->rtsregs.intrreg.erdp); 2146 2147 if (rts->er_events_cnt > 0) { 2148 uint64_t erdp; 2149 int erdp_i; 2150 2151 erdp = rts->intrreg.erdp & ~0xF; 2152 erdp_i = (erdp - rts->erstba_p->qwEvrsTablePtr) / 2153 sizeof(struct xhci_trb); 2154 2155 if (erdp_i <= rts->er_enq_idx) 2156 rts->er_events_cnt = rts->er_enq_idx - erdp_i; 2157 else 2158 rts->er_events_cnt = 2159 rts->erstba_p->dwEvrsTableSize - 2160 (erdp_i - rts->er_enq_idx); 2161 2162 DPRINTF(("pci_xhci: erdp 0x%lx, events cnt %u", 2163 erdp, rts->er_events_cnt)); 2164 } 2165 2166 break; 2167 2168 default: 2169 DPRINTF(("pci_xhci attempted write to RTS offset 0x%lx", 2170 offset)); 2171 break; 2172 } 2173 } 2174 2175 static uint64_t 2176 pci_xhci_portregs_read(struct pci_xhci_softc *sc, uint64_t offset) 2177 { 2178 struct pci_xhci_portregs *portregs; 2179 int port; 2180 uint32_t reg; 2181 2182 if (sc->portregs == NULL) 2183 return (0); 2184 2185 port = (offset - XHCI_PORTREGS_PORT0) / XHCI_PORTREGS_SETSZ; 2186 offset = (offset - XHCI_PORTREGS_PORT0) % XHCI_PORTREGS_SETSZ; 2187 2188 if (port > XHCI_MAX_DEVS) { 2189 DPRINTF(("pci_xhci: portregs_read port %d >= XHCI_MAX_DEVS", 2190 port)); 2191 2192 /* return default value for unused port */ 2193 return (XHCI_PS_SPEED_SET(3)); 2194 } 2195 2196 portregs = XHCI_PORTREG_PTR(sc, port); 2197 switch (offset) { 2198 case 0: 2199 reg = portregs->portsc; 2200 break; 2201 case 4: 2202 reg = portregs->portpmsc; 2203 break; 2204 case 8: 2205 reg = portregs->portli; 2206 break; 2207 case 12: 2208 reg = portregs->porthlpmc; 2209 break; 2210 default: 2211 DPRINTF(("pci_xhci: unaligned portregs read offset %#lx", 2212 offset)); 2213 reg = 0xffffffff; 2214 break; 2215 } 2216 2217 DPRINTF(("pci_xhci: portregs read offset 0x%lx port %u -> 0x%x", 2218 offset, port, reg)); 2219 2220 return (reg); 2221 } 2222 2223 static void 2224 pci_xhci_hostop_write(struct pci_xhci_softc *sc, uint64_t offset, 2225 uint64_t value) 2226 { 2227 offset -= XHCI_CAPLEN; 2228 2229 if (offset < 0x400) 2230 DPRINTF(("pci_xhci: hostop write offset 0x%lx: 0x%lx", 2231 offset, value)); 2232 2233 switch (offset) { 2234 case XHCI_USBCMD: 2235 sc->opregs.usbcmd = pci_xhci_usbcmd_write(sc, value & 0x3F0F); 2236 break; 2237 2238 case XHCI_USBSTS: 2239 /* clear bits on write */ 2240 sc->opregs.usbsts &= ~(value & 2241 (XHCI_STS_HSE|XHCI_STS_EINT|XHCI_STS_PCD|XHCI_STS_SSS| 2242 XHCI_STS_RSS|XHCI_STS_SRE|XHCI_STS_CNR)); 2243 break; 2244 2245 case XHCI_PAGESIZE: 2246 /* read only */ 2247 break; 2248 2249 case XHCI_DNCTRL: 2250 sc->opregs.dnctrl = value & 0xFFFF; 2251 break; 2252 2253 case XHCI_CRCR_LO: 2254 if (sc->opregs.crcr & XHCI_CRCR_LO_CRR) { 2255 sc->opregs.crcr &= ~(XHCI_CRCR_LO_CS|XHCI_CRCR_LO_CA); 2256 sc->opregs.crcr |= value & 2257 (XHCI_CRCR_LO_CS|XHCI_CRCR_LO_CA); 2258 } else { 2259 sc->opregs.crcr = MASK_64_HI(sc->opregs.crcr) | 2260 (value & (0xFFFFFFC0 | XHCI_CRCR_LO_RCS)); 2261 } 2262 break; 2263 2264 case XHCI_CRCR_HI: 2265 if (!(sc->opregs.crcr & XHCI_CRCR_LO_CRR)) { 2266 sc->opregs.crcr = MASK_64_LO(sc->opregs.crcr) | 2267 (value << 32); 2268 2269 sc->opregs.cr_p = XHCI_GADDR(sc, 2270 sc->opregs.crcr & ~0xF); 2271 } 2272 2273 if (sc->opregs.crcr & XHCI_CRCR_LO_CS) { 2274 /* Stop operation of Command Ring */ 2275 } 2276 2277 if (sc->opregs.crcr & XHCI_CRCR_LO_CA) { 2278 /* Abort command */ 2279 } 2280 2281 break; 2282 2283 case XHCI_DCBAAP_LO: 2284 sc->opregs.dcbaap = MASK_64_HI(sc->opregs.dcbaap) | 2285 (value & 0xFFFFFFC0); 2286 break; 2287 2288 case XHCI_DCBAAP_HI: 2289 sc->opregs.dcbaap = MASK_64_LO(sc->opregs.dcbaap) | 2290 (value << 32); 2291 sc->opregs.dcbaa_p = XHCI_GADDR(sc, sc->opregs.dcbaap & ~0x3FUL); 2292 2293 DPRINTF(("pci_xhci: opregs dcbaap = 0x%lx (vaddr 0x%lx)", 2294 sc->opregs.dcbaap, (uint64_t)sc->opregs.dcbaa_p)); 2295 break; 2296 2297 case XHCI_CONFIG: 2298 sc->opregs.config = value & 0x03FF; 2299 break; 2300 2301 default: 2302 if (offset >= 0x400) 2303 pci_xhci_portregs_write(sc, offset, value); 2304 2305 break; 2306 } 2307 } 2308 2309 2310 static void 2311 pci_xhci_write(struct pci_devinst *pi, int baridx, uint64_t offset, 2312 int size __unused, uint64_t value) 2313 { 2314 struct pci_xhci_softc *sc; 2315 2316 sc = pi->pi_arg; 2317 2318 assert(baridx == 0); 2319 2320 pthread_mutex_lock(&sc->mtx); 2321 if (offset < XHCI_CAPLEN) /* read only registers */ 2322 WPRINTF(("pci_xhci: write RO-CAPs offset %ld", offset)); 2323 else if (offset < sc->dboff) 2324 pci_xhci_hostop_write(sc, offset, value); 2325 else if (offset < sc->rtsoff) 2326 pci_xhci_dbregs_write(sc, offset, value); 2327 else if (offset < sc->regsend) 2328 pci_xhci_rtsregs_write(sc, offset, value); 2329 else 2330 WPRINTF(("pci_xhci: write invalid offset %ld", offset)); 2331 2332 pthread_mutex_unlock(&sc->mtx); 2333 } 2334 2335 static uint64_t 2336 pci_xhci_hostcap_read(struct pci_xhci_softc *sc, uint64_t offset) 2337 { 2338 uint64_t value; 2339 2340 switch (offset) { 2341 case XHCI_CAPLENGTH: /* 0x00 */ 2342 value = sc->caplength; 2343 break; 2344 2345 case XHCI_HCSPARAMS1: /* 0x04 */ 2346 value = sc->hcsparams1; 2347 break; 2348 2349 case XHCI_HCSPARAMS2: /* 0x08 */ 2350 value = sc->hcsparams2; 2351 break; 2352 2353 case XHCI_HCSPARAMS3: /* 0x0C */ 2354 value = sc->hcsparams3; 2355 break; 2356 2357 case XHCI_HCSPARAMS0: /* 0x10 */ 2358 value = sc->hccparams1; 2359 break; 2360 2361 case XHCI_DBOFF: /* 0x14 */ 2362 value = sc->dboff; 2363 break; 2364 2365 case XHCI_RTSOFF: /* 0x18 */ 2366 value = sc->rtsoff; 2367 break; 2368 2369 case XHCI_HCCPRAMS2: /* 0x1C */ 2370 value = sc->hccparams2; 2371 break; 2372 2373 default: 2374 value = 0; 2375 break; 2376 } 2377 2378 DPRINTF(("pci_xhci: hostcap read offset 0x%lx -> 0x%lx", 2379 offset, value)); 2380 2381 return (value); 2382 } 2383 2384 static uint64_t 2385 pci_xhci_hostop_read(struct pci_xhci_softc *sc, uint64_t offset) 2386 { 2387 uint64_t value; 2388 2389 offset = (offset - XHCI_CAPLEN); 2390 2391 switch (offset) { 2392 case XHCI_USBCMD: /* 0x00 */ 2393 value = sc->opregs.usbcmd; 2394 break; 2395 2396 case XHCI_USBSTS: /* 0x04 */ 2397 value = sc->opregs.usbsts; 2398 break; 2399 2400 case XHCI_PAGESIZE: /* 0x08 */ 2401 value = sc->opregs.pgsz; 2402 break; 2403 2404 case XHCI_DNCTRL: /* 0x14 */ 2405 value = sc->opregs.dnctrl; 2406 break; 2407 2408 case XHCI_CRCR_LO: /* 0x18 */ 2409 value = sc->opregs.crcr & XHCI_CRCR_LO_CRR; 2410 break; 2411 2412 case XHCI_CRCR_HI: /* 0x1C */ 2413 value = 0; 2414 break; 2415 2416 case XHCI_DCBAAP_LO: /* 0x30 */ 2417 value = sc->opregs.dcbaap & 0xFFFFFFFF; 2418 break; 2419 2420 case XHCI_DCBAAP_HI: /* 0x34 */ 2421 value = (sc->opregs.dcbaap >> 32) & 0xFFFFFFFF; 2422 break; 2423 2424 case XHCI_CONFIG: /* 0x38 */ 2425 value = sc->opregs.config; 2426 break; 2427 2428 default: 2429 if (offset >= 0x400) 2430 value = pci_xhci_portregs_read(sc, offset); 2431 else 2432 value = 0; 2433 2434 break; 2435 } 2436 2437 if (offset < 0x400) 2438 DPRINTF(("pci_xhci: hostop read offset 0x%lx -> 0x%lx", 2439 offset, value)); 2440 2441 return (value); 2442 } 2443 2444 static uint64_t 2445 pci_xhci_dbregs_read(struct pci_xhci_softc *sc __unused, 2446 uint64_t offset __unused) 2447 { 2448 /* read doorbell always returns 0 */ 2449 return (0); 2450 } 2451 2452 static uint64_t 2453 pci_xhci_rtsregs_read(struct pci_xhci_softc *sc, uint64_t offset) 2454 { 2455 uint32_t value; 2456 2457 offset -= sc->rtsoff; 2458 value = 0; 2459 2460 if (offset == XHCI_MFINDEX) { 2461 value = sc->rtsregs.mfindex; 2462 } else if (offset >= 0x20) { 2463 int item; 2464 uint32_t *p; 2465 2466 offset -= 0x20; 2467 item = offset % 32; 2468 2469 assert(offset < sizeof(sc->rtsregs.intrreg)); 2470 2471 p = &sc->rtsregs.intrreg.iman; 2472 p += item / sizeof(uint32_t); 2473 value = *p; 2474 } 2475 2476 DPRINTF(("pci_xhci: rtsregs read offset 0x%lx -> 0x%x", 2477 offset, value)); 2478 2479 return (value); 2480 } 2481 2482 static uint64_t 2483 pci_xhci_xecp_read(struct pci_xhci_softc *sc, uint64_t offset) 2484 { 2485 uint32_t value; 2486 2487 offset -= sc->regsend; 2488 value = 0; 2489 2490 switch (offset) { 2491 case 0: 2492 /* rev major | rev minor | next-cap | cap-id */ 2493 value = (0x02 << 24) | (4 << 8) | XHCI_ID_PROTOCOLS; 2494 break; 2495 case 4: 2496 /* name string = "USB" */ 2497 value = 0x20425355; 2498 break; 2499 case 8: 2500 /* psic | proto-defined | compat # | compat offset */ 2501 value = ((XHCI_MAX_DEVS/2) << 8) | sc->usb2_port_start; 2502 break; 2503 case 12: 2504 break; 2505 case 16: 2506 /* rev major | rev minor | next-cap | cap-id */ 2507 value = (0x03 << 24) | XHCI_ID_PROTOCOLS; 2508 break; 2509 case 20: 2510 /* name string = "USB" */ 2511 value = 0x20425355; 2512 break; 2513 case 24: 2514 /* psic | proto-defined | compat # | compat offset */ 2515 value = ((XHCI_MAX_DEVS/2) << 8) | sc->usb3_port_start; 2516 break; 2517 case 28: 2518 break; 2519 default: 2520 DPRINTF(("pci_xhci: xecp invalid offset 0x%lx", offset)); 2521 break; 2522 } 2523 2524 DPRINTF(("pci_xhci: xecp read offset 0x%lx -> 0x%x", 2525 offset, value)); 2526 2527 return (value); 2528 } 2529 2530 2531 static uint64_t 2532 pci_xhci_read(struct pci_devinst *pi, int baridx, uint64_t offset, int size) 2533 { 2534 struct pci_xhci_softc *sc; 2535 uint32_t value; 2536 2537 sc = pi->pi_arg; 2538 2539 assert(baridx == 0); 2540 2541 pthread_mutex_lock(&sc->mtx); 2542 if (offset < XHCI_CAPLEN) 2543 value = pci_xhci_hostcap_read(sc, offset); 2544 else if (offset < sc->dboff) 2545 value = pci_xhci_hostop_read(sc, offset); 2546 else if (offset < sc->rtsoff) 2547 value = pci_xhci_dbregs_read(sc, offset); 2548 else if (offset < sc->regsend) 2549 value = pci_xhci_rtsregs_read(sc, offset); 2550 else if (offset < (sc->regsend + 4*32)) 2551 value = pci_xhci_xecp_read(sc, offset); 2552 else { 2553 value = 0; 2554 WPRINTF(("pci_xhci: read invalid offset %ld", offset)); 2555 } 2556 2557 pthread_mutex_unlock(&sc->mtx); 2558 2559 switch (size) { 2560 case 1: 2561 value &= 0xFF; 2562 break; 2563 case 2: 2564 value &= 0xFFFF; 2565 break; 2566 case 4: 2567 value &= 0xFFFFFFFF; 2568 break; 2569 } 2570 2571 return (value); 2572 } 2573 2574 static void 2575 pci_xhci_reset_port(struct pci_xhci_softc *sc, int portn, int warm) 2576 { 2577 struct pci_xhci_portregs *port; 2578 struct pci_xhci_dev_emu *dev; 2579 struct xhci_trb evtrb; 2580 int error; 2581 2582 assert(portn <= XHCI_MAX_DEVS); 2583 2584 DPRINTF(("xhci reset port %d", portn)); 2585 2586 port = XHCI_PORTREG_PTR(sc, portn); 2587 dev = XHCI_DEVINST_PTR(sc, portn); 2588 if (dev) { 2589 port->portsc &= ~(XHCI_PS_PLS_MASK | XHCI_PS_PR | XHCI_PS_PRC); 2590 port->portsc |= XHCI_PS_PED | 2591 XHCI_PS_SPEED_SET(dev->dev_ue->ue_usbspeed); 2592 2593 if (warm && dev->dev_ue->ue_usbver == 3) { 2594 port->portsc |= XHCI_PS_WRC; 2595 } 2596 2597 if ((port->portsc & XHCI_PS_PRC) == 0) { 2598 port->portsc |= XHCI_PS_PRC; 2599 2600 pci_xhci_set_evtrb(&evtrb, portn, 2601 XHCI_TRB_ERROR_SUCCESS, 2602 XHCI_TRB_EVENT_PORT_STS_CHANGE); 2603 error = pci_xhci_insert_event(sc, &evtrb, 1); 2604 if (error != XHCI_TRB_ERROR_SUCCESS) 2605 DPRINTF(("xhci reset port insert event " 2606 "failed")); 2607 } 2608 } 2609 } 2610 2611 static void 2612 pci_xhci_init_port(struct pci_xhci_softc *sc, int portn) 2613 { 2614 struct pci_xhci_portregs *port; 2615 struct pci_xhci_dev_emu *dev; 2616 2617 port = XHCI_PORTREG_PTR(sc, portn); 2618 dev = XHCI_DEVINST_PTR(sc, portn); 2619 if (dev) { 2620 port->portsc = XHCI_PS_CCS | /* connected */ 2621 XHCI_PS_PP; /* port power */ 2622 2623 if (dev->dev_ue->ue_usbver == 2) { 2624 port->portsc |= XHCI_PS_PLS_SET(UPS_PORT_LS_POLL) | 2625 XHCI_PS_SPEED_SET(dev->dev_ue->ue_usbspeed); 2626 } else { 2627 port->portsc |= XHCI_PS_PLS_SET(UPS_PORT_LS_U0) | 2628 XHCI_PS_PED | /* enabled */ 2629 XHCI_PS_SPEED_SET(dev->dev_ue->ue_usbspeed); 2630 } 2631 2632 DPRINTF(("Init port %d 0x%x", portn, port->portsc)); 2633 } else { 2634 port->portsc = XHCI_PS_PLS_SET(UPS_PORT_LS_RX_DET) | XHCI_PS_PP; 2635 DPRINTF(("Init empty port %d 0x%x", portn, port->portsc)); 2636 } 2637 } 2638 2639 static int 2640 pci_xhci_dev_intr(struct usb_hci *hci, int epctx) 2641 { 2642 struct pci_xhci_dev_emu *dev; 2643 struct xhci_dev_ctx *dev_ctx; 2644 struct xhci_trb evtrb; 2645 struct pci_xhci_softc *sc; 2646 struct pci_xhci_portregs *p; 2647 struct xhci_endp_ctx *ep_ctx; 2648 int error = 0; 2649 int dir_in; 2650 int epid; 2651 2652 dir_in = epctx & 0x80; 2653 epid = epctx & ~0x80; 2654 2655 /* HW endpoint contexts are 0-15; convert to epid based on dir */ 2656 epid = (epid * 2) + (dir_in ? 1 : 0); 2657 2658 assert(epid >= 1 && epid <= 31); 2659 2660 dev = hci->hci_sc; 2661 sc = dev->xsc; 2662 2663 /* check if device is ready; OS has to initialise it */ 2664 if (sc->rtsregs.erstba_p == NULL || 2665 (sc->opregs.usbcmd & XHCI_CMD_RS) == 0 || 2666 dev->dev_ctx == NULL) 2667 return (0); 2668 2669 p = XHCI_PORTREG_PTR(sc, hci->hci_port); 2670 2671 /* raise event if link U3 (suspended) state */ 2672 if (XHCI_PS_PLS_GET(p->portsc) == 3) { 2673 p->portsc &= ~XHCI_PS_PLS_MASK; 2674 p->portsc |= XHCI_PS_PLS_SET(UPS_PORT_LS_RESUME); 2675 if ((p->portsc & XHCI_PS_PLC) != 0) 2676 return (0); 2677 2678 p->portsc |= XHCI_PS_PLC; 2679 2680 pci_xhci_set_evtrb(&evtrb, hci->hci_port, 2681 XHCI_TRB_ERROR_SUCCESS, XHCI_TRB_EVENT_PORT_STS_CHANGE); 2682 error = pci_xhci_insert_event(sc, &evtrb, 0); 2683 if (error != XHCI_TRB_ERROR_SUCCESS) 2684 goto done; 2685 } 2686 2687 dev_ctx = dev->dev_ctx; 2688 ep_ctx = &dev_ctx->ctx_ep[epid]; 2689 if ((ep_ctx->dwEpCtx0 & 0x7) == XHCI_ST_EPCTX_DISABLED) { 2690 DPRINTF(("xhci device interrupt on disabled endpoint %d", 2691 epid)); 2692 return (0); 2693 } 2694 2695 DPRINTF(("xhci device interrupt on endpoint %d", epid)); 2696 2697 pci_xhci_device_doorbell(sc, hci->hci_port, epid, 0); 2698 2699 done: 2700 return (error); 2701 } 2702 2703 static int 2704 pci_xhci_dev_event(struct usb_hci *hci, enum hci_usbev evid __unused, 2705 void *param __unused) 2706 { 2707 DPRINTF(("xhci device event port %d", hci->hci_port)); 2708 return (0); 2709 } 2710 2711 /* 2712 * Each controller contains a "slot" node which contains a list of 2713 * child nodes each of which is a device. Each slot node's name 2714 * corresponds to a specific controller slot. These nodes 2715 * contain a "device" variable identifying the device model of the 2716 * USB device. For example: 2717 * 2718 * pci.0.1.0 2719 * .device="xhci" 2720 * .slot 2721 * .1 2722 * .device="tablet" 2723 */ 2724 static int 2725 pci_xhci_legacy_config(nvlist_t *nvl, const char *opts) 2726 { 2727 char node_name[16]; 2728 nvlist_t *slots_nvl, *slot_nvl; 2729 char *cp, *opt, *str, *tofree; 2730 int slot; 2731 2732 if (opts == NULL) 2733 return (0); 2734 2735 slots_nvl = create_relative_config_node(nvl, "slot"); 2736 slot = 1; 2737 tofree = str = strdup(opts); 2738 while ((opt = strsep(&str, ",")) != NULL) { 2739 /* device[=<config>] */ 2740 cp = strchr(opt, '='); 2741 if (cp != NULL) { 2742 *cp = '\0'; 2743 cp++; 2744 } 2745 2746 snprintf(node_name, sizeof(node_name), "%d", slot); 2747 slot++; 2748 slot_nvl = create_relative_config_node(slots_nvl, node_name); 2749 set_config_value_node(slot_nvl, "device", opt); 2750 2751 /* 2752 * NB: Given that we split on commas above, the legacy 2753 * format only supports a single option. 2754 */ 2755 if (cp != NULL && *cp != '\0') 2756 pci_parse_legacy_config(slot_nvl, cp); 2757 } 2758 free(tofree); 2759 return (0); 2760 } 2761 2762 static int 2763 pci_xhci_parse_devices(struct pci_xhci_softc *sc, nvlist_t *nvl) 2764 { 2765 struct pci_xhci_dev_emu *dev; 2766 struct usb_devemu *ue; 2767 const nvlist_t *slots_nvl, *slot_nvl; 2768 const char *name, *device; 2769 char *cp; 2770 void *devsc, *cookie; 2771 long slot; 2772 int type, usb3_port, usb2_port, i, ndevices; 2773 2774 usb3_port = sc->usb3_port_start; 2775 usb2_port = sc->usb2_port_start; 2776 2777 sc->devices = calloc(XHCI_MAX_DEVS, sizeof(struct pci_xhci_dev_emu *)); 2778 sc->slots = calloc(XHCI_MAX_SLOTS, sizeof(struct pci_xhci_dev_emu *)); 2779 2780 ndevices = 0; 2781 2782 slots_nvl = find_relative_config_node(nvl, "slot"); 2783 if (slots_nvl == NULL) 2784 goto portsfinal; 2785 2786 cookie = NULL; 2787 while ((name = nvlist_next(slots_nvl, &type, &cookie)) != NULL) { 2788 if (usb2_port == ((sc->usb2_port_start) + XHCI_MAX_DEVS/2) || 2789 usb3_port == ((sc->usb3_port_start) + XHCI_MAX_DEVS/2)) { 2790 WPRINTF(("pci_xhci max number of USB 2 or 3 " 2791 "devices reached, max %d", XHCI_MAX_DEVS/2)); 2792 goto bad; 2793 } 2794 2795 if (type != NV_TYPE_NVLIST) { 2796 EPRINTLN( 2797 "pci_xhci: config variable '%s' under slot node", 2798 name); 2799 goto bad; 2800 } 2801 2802 slot = strtol(name, &cp, 0); 2803 if (*cp != '\0' || slot <= 0 || slot > XHCI_MAX_SLOTS) { 2804 EPRINTLN("pci_xhci: invalid slot '%s'", name); 2805 goto bad; 2806 } 2807 2808 if (XHCI_SLOTDEV_PTR(sc, slot) != NULL) { 2809 EPRINTLN("pci_xhci: duplicate slot '%s'", name); 2810 goto bad; 2811 } 2812 2813 slot_nvl = nvlist_get_nvlist(slots_nvl, name); 2814 device = get_config_value_node(slot_nvl, "device"); 2815 if (device == NULL) { 2816 EPRINTLN( 2817 "pci_xhci: missing \"device\" value for slot '%s'", 2818 name); 2819 goto bad; 2820 } 2821 2822 ue = usb_emu_finddev(device); 2823 if (ue == NULL) { 2824 EPRINTLN("pci_xhci: unknown device model \"%s\"", 2825 device); 2826 goto bad; 2827 } 2828 2829 DPRINTF(("pci_xhci adding device %s", device)); 2830 2831 dev = calloc(1, sizeof(struct pci_xhci_dev_emu)); 2832 dev->xsc = sc; 2833 dev->hci.hci_sc = dev; 2834 dev->hci.hci_intr = pci_xhci_dev_intr; 2835 dev->hci.hci_event = pci_xhci_dev_event; 2836 2837 if (ue->ue_usbver == 2) { 2838 if (usb2_port == sc->usb2_port_start + 2839 XHCI_MAX_DEVS / 2) { 2840 WPRINTF(("pci_xhci max number of USB 2 devices " 2841 "reached, max %d", XHCI_MAX_DEVS / 2)); 2842 goto bad; 2843 } 2844 dev->hci.hci_port = usb2_port; 2845 usb2_port++; 2846 } else { 2847 if (usb3_port == sc->usb3_port_start + 2848 XHCI_MAX_DEVS / 2) { 2849 WPRINTF(("pci_xhci max number of USB 3 devices " 2850 "reached, max %d", XHCI_MAX_DEVS / 2)); 2851 goto bad; 2852 } 2853 dev->hci.hci_port = usb3_port; 2854 usb3_port++; 2855 } 2856 XHCI_DEVINST_PTR(sc, dev->hci.hci_port) = dev; 2857 2858 dev->hci.hci_address = 0; 2859 devsc = ue->ue_init(&dev->hci, nvl); 2860 if (devsc == NULL) { 2861 goto bad; 2862 } 2863 2864 dev->dev_ue = ue; 2865 dev->dev_sc = devsc; 2866 2867 XHCI_SLOTDEV_PTR(sc, slot) = dev; 2868 ndevices++; 2869 } 2870 2871 portsfinal: 2872 sc->portregs = calloc(XHCI_MAX_DEVS, sizeof(struct pci_xhci_portregs)); 2873 2874 if (ndevices > 0) { 2875 for (i = 1; i <= XHCI_MAX_DEVS; i++) { 2876 pci_xhci_init_port(sc, i); 2877 } 2878 } else { 2879 WPRINTF(("pci_xhci no USB devices configured")); 2880 } 2881 return (0); 2882 2883 bad: 2884 for (i = 1; i <= XHCI_MAX_DEVS; i++) { 2885 free(XHCI_DEVINST_PTR(sc, i)); 2886 } 2887 2888 free(sc->devices); 2889 free(sc->slots); 2890 2891 return (-1); 2892 } 2893 2894 static int 2895 pci_xhci_init(struct pci_devinst *pi, nvlist_t *nvl) 2896 { 2897 struct pci_xhci_softc *sc; 2898 int error; 2899 2900 if (xhci_in_use) { 2901 WPRINTF(("pci_xhci controller already defined")); 2902 return (-1); 2903 } 2904 xhci_in_use = 1; 2905 2906 sc = calloc(1, sizeof(struct pci_xhci_softc)); 2907 pi->pi_arg = sc; 2908 sc->xsc_pi = pi; 2909 2910 sc->usb2_port_start = (XHCI_MAX_DEVS/2) + 1; 2911 sc->usb3_port_start = 1; 2912 2913 /* discover devices */ 2914 error = pci_xhci_parse_devices(sc, nvl); 2915 if (error < 0) 2916 goto done; 2917 else 2918 error = 0; 2919 2920 sc->caplength = XHCI_SET_CAPLEN(XHCI_CAPLEN) | 2921 XHCI_SET_HCIVERSION(0x0100); 2922 sc->hcsparams1 = XHCI_SET_HCSP1_MAXPORTS(XHCI_MAX_DEVS) | 2923 XHCI_SET_HCSP1_MAXINTR(1) | /* interrupters */ 2924 XHCI_SET_HCSP1_MAXSLOTS(XHCI_MAX_SLOTS); 2925 sc->hcsparams2 = XHCI_SET_HCSP2_ERSTMAX(XHCI_ERST_MAX) | 2926 XHCI_SET_HCSP2_IST(0x04); 2927 sc->hcsparams3 = 0; /* no latency */ 2928 sc->hccparams1 = XHCI_SET_HCCP1_AC64(1) | /* 64-bit addrs */ 2929 XHCI_SET_HCCP1_NSS(1) | /* no 2nd-streams */ 2930 XHCI_SET_HCCP1_SPC(1) | /* short packet */ 2931 XHCI_SET_HCCP1_MAXPSA(XHCI_STREAMS_MAX); 2932 sc->hccparams2 = XHCI_SET_HCCP2_LEC(1) | 2933 XHCI_SET_HCCP2_U3C(1); 2934 sc->dboff = XHCI_SET_DOORBELL(XHCI_CAPLEN + XHCI_PORTREGS_START + 2935 XHCI_MAX_DEVS * sizeof(struct pci_xhci_portregs)); 2936 2937 /* dboff must be 32-bit aligned */ 2938 if (sc->dboff & 0x3) 2939 sc->dboff = (sc->dboff + 0x3) & ~0x3; 2940 2941 /* rtsoff must be 32-bytes aligned */ 2942 sc->rtsoff = XHCI_SET_RTSOFFSET(sc->dboff + (XHCI_MAX_SLOTS+1) * 32); 2943 if (sc->rtsoff & 0x1F) 2944 sc->rtsoff = (sc->rtsoff + 0x1F) & ~0x1F; 2945 2946 DPRINTF(("pci_xhci dboff: 0x%x, rtsoff: 0x%x", sc->dboff, 2947 sc->rtsoff)); 2948 2949 sc->opregs.usbsts = XHCI_STS_HCH; 2950 sc->opregs.pgsz = XHCI_PAGESIZE_4K; 2951 2952 pci_xhci_reset(sc); 2953 2954 sc->regsend = sc->rtsoff + 0x20 + 32; /* only 1 intrpter */ 2955 2956 /* 2957 * Set extended capabilities pointer to be after regsend; 2958 * value of xecp field is 32-bit offset. 2959 */ 2960 sc->hccparams1 |= XHCI_SET_HCCP1_XECP(sc->regsend/4); 2961 2962 pci_set_cfgdata16(pi, PCIR_DEVICE, 0x1E31); 2963 pci_set_cfgdata16(pi, PCIR_VENDOR, 0x8086); 2964 pci_set_cfgdata8(pi, PCIR_CLASS, PCIC_SERIALBUS); 2965 pci_set_cfgdata8(pi, PCIR_SUBCLASS, PCIS_SERIALBUS_USB); 2966 pci_set_cfgdata8(pi, PCIR_PROGIF,PCIP_SERIALBUS_USB_XHCI); 2967 pci_set_cfgdata8(pi, PCI_USBREV, PCI_USB_REV_3_0); 2968 2969 pci_emul_add_msicap(pi, 1); 2970 2971 /* regsend + xecp registers */ 2972 pci_emul_alloc_bar(pi, 0, PCIBAR_MEM32, sc->regsend + 4*32); 2973 DPRINTF(("pci_xhci pci_emu_alloc: %d", sc->regsend + 4*32)); 2974 2975 2976 pci_lintr_request(pi); 2977 2978 pthread_mutex_init(&sc->mtx, NULL); 2979 2980 done: 2981 if (error) { 2982 free(sc); 2983 } 2984 2985 return (error); 2986 } 2987 2988 #ifdef BHYVE_SNAPSHOT 2989 static void 2990 pci_xhci_map_devs_slots(struct pci_xhci_softc *sc, int maps[]) 2991 { 2992 int i, j; 2993 struct pci_xhci_dev_emu *dev, *slot; 2994 2995 memset(maps, 0, sizeof(maps[0]) * XHCI_MAX_SLOTS); 2996 2997 for (i = 1; i <= XHCI_MAX_SLOTS; i++) { 2998 for (j = 1; j <= XHCI_MAX_DEVS; j++) { 2999 slot = XHCI_SLOTDEV_PTR(sc, i); 3000 dev = XHCI_DEVINST_PTR(sc, j); 3001 3002 if (slot == dev) 3003 maps[i] = j; 3004 } 3005 } 3006 } 3007 3008 static int 3009 pci_xhci_snapshot_ep(struct pci_xhci_softc *sc, struct pci_xhci_dev_emu *dev, 3010 int idx, struct vm_snapshot_meta *meta) 3011 { 3012 int k; 3013 int ret; 3014 struct usb_data_xfer *xfer; 3015 struct usb_data_xfer_block *xfer_block; 3016 3017 /* some sanity checks */ 3018 if (meta->op == VM_SNAPSHOT_SAVE) 3019 xfer = dev->eps[idx].ep_xfer; 3020 3021 SNAPSHOT_VAR_OR_LEAVE(xfer, meta, ret, done); 3022 if (xfer == NULL) { 3023 ret = 0; 3024 goto done; 3025 } 3026 3027 if (meta->op == VM_SNAPSHOT_RESTORE) { 3028 pci_xhci_init_ep(dev, idx); 3029 xfer = dev->eps[idx].ep_xfer; 3030 } 3031 3032 /* save / restore proper */ 3033 for (k = 0; k < USB_MAX_XFER_BLOCKS; k++) { 3034 xfer_block = &xfer->data[k]; 3035 3036 SNAPSHOT_GUEST2HOST_ADDR_OR_LEAVE(sc->xsc_pi->pi_vmctx, 3037 xfer_block->buf, XHCI_GADDR_SIZE(xfer_block->buf), true, 3038 meta, ret, done); 3039 SNAPSHOT_VAR_OR_LEAVE(xfer_block->blen, meta, ret, done); 3040 SNAPSHOT_VAR_OR_LEAVE(xfer_block->bdone, meta, ret, done); 3041 SNAPSHOT_VAR_OR_LEAVE(xfer_block->processed, meta, ret, done); 3042 SNAPSHOT_VAR_OR_LEAVE(xfer_block->hci_data, meta, ret, done); 3043 SNAPSHOT_VAR_OR_LEAVE(xfer_block->ccs, meta, ret, done); 3044 SNAPSHOT_VAR_OR_LEAVE(xfer_block->streamid, meta, ret, done); 3045 SNAPSHOT_VAR_OR_LEAVE(xfer_block->trbnext, meta, ret, done); 3046 } 3047 3048 SNAPSHOT_VAR_OR_LEAVE(xfer->ureq, meta, ret, done); 3049 if (xfer->ureq) { 3050 /* xfer->ureq is not allocated at restore time */ 3051 if (meta->op == VM_SNAPSHOT_RESTORE) 3052 xfer->ureq = malloc(sizeof(struct usb_device_request)); 3053 3054 SNAPSHOT_BUF_OR_LEAVE(xfer->ureq, 3055 sizeof(struct usb_device_request), 3056 meta, ret, done); 3057 } 3058 3059 SNAPSHOT_VAR_OR_LEAVE(xfer->ndata, meta, ret, done); 3060 SNAPSHOT_VAR_OR_LEAVE(xfer->head, meta, ret, done); 3061 SNAPSHOT_VAR_OR_LEAVE(xfer->tail, meta, ret, done); 3062 3063 done: 3064 return (ret); 3065 } 3066 3067 static int 3068 pci_xhci_snapshot(struct vm_snapshot_meta *meta) 3069 { 3070 int i, j; 3071 int ret; 3072 int restore_idx; 3073 struct pci_devinst *pi; 3074 struct pci_xhci_softc *sc; 3075 struct pci_xhci_portregs *port; 3076 struct pci_xhci_dev_emu *dev; 3077 char dname[SNAP_DEV_NAME_LEN]; 3078 int maps[XHCI_MAX_SLOTS + 1]; 3079 3080 pi = meta->dev_data; 3081 sc = pi->pi_arg; 3082 3083 SNAPSHOT_VAR_OR_LEAVE(sc->caplength, meta, ret, done); 3084 SNAPSHOT_VAR_OR_LEAVE(sc->hcsparams1, meta, ret, done); 3085 SNAPSHOT_VAR_OR_LEAVE(sc->hcsparams2, meta, ret, done); 3086 SNAPSHOT_VAR_OR_LEAVE(sc->hcsparams3, meta, ret, done); 3087 SNAPSHOT_VAR_OR_LEAVE(sc->hccparams1, meta, ret, done); 3088 SNAPSHOT_VAR_OR_LEAVE(sc->dboff, meta, ret, done); 3089 SNAPSHOT_VAR_OR_LEAVE(sc->rtsoff, meta, ret, done); 3090 SNAPSHOT_VAR_OR_LEAVE(sc->hccparams2, meta, ret, done); 3091 SNAPSHOT_VAR_OR_LEAVE(sc->regsend, meta, ret, done); 3092 3093 /* opregs */ 3094 SNAPSHOT_VAR_OR_LEAVE(sc->opregs.usbcmd, meta, ret, done); 3095 SNAPSHOT_VAR_OR_LEAVE(sc->opregs.usbsts, meta, ret, done); 3096 SNAPSHOT_VAR_OR_LEAVE(sc->opregs.pgsz, meta, ret, done); 3097 SNAPSHOT_VAR_OR_LEAVE(sc->opregs.dnctrl, meta, ret, done); 3098 SNAPSHOT_VAR_OR_LEAVE(sc->opregs.crcr, meta, ret, done); 3099 SNAPSHOT_VAR_OR_LEAVE(sc->opregs.dcbaap, meta, ret, done); 3100 SNAPSHOT_VAR_OR_LEAVE(sc->opregs.config, meta, ret, done); 3101 3102 /* opregs.cr_p */ 3103 SNAPSHOT_GUEST2HOST_ADDR_OR_LEAVE(pi->pi_vmctx, sc->opregs.cr_p, 3104 XHCI_GADDR_SIZE(sc->opregs.cr_p), true, meta, ret, done); 3105 3106 /* opregs.dcbaa_p */ 3107 SNAPSHOT_GUEST2HOST_ADDR_OR_LEAVE(pi->pi_vmctx, sc->opregs.dcbaa_p, 3108 XHCI_GADDR_SIZE(sc->opregs.dcbaa_p), true, meta, ret, done); 3109 3110 /* rtsregs */ 3111 SNAPSHOT_VAR_OR_LEAVE(sc->rtsregs.mfindex, meta, ret, done); 3112 3113 /* rtsregs.intrreg */ 3114 SNAPSHOT_VAR_OR_LEAVE(sc->rtsregs.intrreg.iman, meta, ret, done); 3115 SNAPSHOT_VAR_OR_LEAVE(sc->rtsregs.intrreg.imod, meta, ret, done); 3116 SNAPSHOT_VAR_OR_LEAVE(sc->rtsregs.intrreg.erstsz, meta, ret, done); 3117 SNAPSHOT_VAR_OR_LEAVE(sc->rtsregs.intrreg.rsvd, meta, ret, done); 3118 SNAPSHOT_VAR_OR_LEAVE(sc->rtsregs.intrreg.erstba, meta, ret, done); 3119 SNAPSHOT_VAR_OR_LEAVE(sc->rtsregs.intrreg.erdp, meta, ret, done); 3120 3121 /* rtsregs.erstba_p */ 3122 SNAPSHOT_GUEST2HOST_ADDR_OR_LEAVE(pi->pi_vmctx, sc->rtsregs.erstba_p, 3123 XHCI_GADDR_SIZE(sc->rtsregs.erstba_p), true, meta, ret, done); 3124 3125 /* rtsregs.erst_p */ 3126 SNAPSHOT_GUEST2HOST_ADDR_OR_LEAVE(pi->pi_vmctx, sc->rtsregs.erst_p, 3127 XHCI_GADDR_SIZE(sc->rtsregs.erst_p), true, meta, ret, done); 3128 3129 SNAPSHOT_VAR_OR_LEAVE(sc->rtsregs.er_deq_seg, meta, ret, done); 3130 SNAPSHOT_VAR_OR_LEAVE(sc->rtsregs.er_enq_idx, meta, ret, done); 3131 SNAPSHOT_VAR_OR_LEAVE(sc->rtsregs.er_enq_seg, meta, ret, done); 3132 SNAPSHOT_VAR_OR_LEAVE(sc->rtsregs.er_events_cnt, meta, ret, done); 3133 SNAPSHOT_VAR_OR_LEAVE(sc->rtsregs.event_pcs, meta, ret, done); 3134 3135 /* sanity checking */ 3136 for (i = 1; i <= XHCI_MAX_DEVS; i++) { 3137 dev = XHCI_DEVINST_PTR(sc, i); 3138 if (dev == NULL) 3139 continue; 3140 3141 if (meta->op == VM_SNAPSHOT_SAVE) 3142 restore_idx = i; 3143 SNAPSHOT_VAR_OR_LEAVE(restore_idx, meta, ret, done); 3144 3145 /* check if the restored device (when restoring) is sane */ 3146 if (restore_idx != i) { 3147 EPRINTLN("%s: idx not matching: actual: %d, " 3148 "expected: %d", __func__, restore_idx, i); 3149 ret = EINVAL; 3150 goto done; 3151 } 3152 3153 if (meta->op == VM_SNAPSHOT_SAVE) { 3154 memset(dname, 0, sizeof(dname)); 3155 strncpy(dname, dev->dev_ue->ue_emu, sizeof(dname) - 1); 3156 } 3157 3158 SNAPSHOT_BUF_OR_LEAVE(dname, sizeof(dname), meta, ret, done); 3159 3160 if (meta->op == VM_SNAPSHOT_RESTORE) { 3161 dname[sizeof(dname) - 1] = '\0'; 3162 if (strcmp(dev->dev_ue->ue_emu, dname)) { 3163 EPRINTLN("%s: device names mismatch: " 3164 "actual: %s, expected: %s", 3165 __func__, dname, dev->dev_ue->ue_emu); 3166 3167 ret = EINVAL; 3168 goto done; 3169 } 3170 } 3171 } 3172 3173 /* portregs */ 3174 for (i = 1; i <= XHCI_MAX_DEVS; i++) { 3175 port = XHCI_PORTREG_PTR(sc, i); 3176 dev = XHCI_DEVINST_PTR(sc, i); 3177 3178 if (dev == NULL) 3179 continue; 3180 3181 SNAPSHOT_VAR_OR_LEAVE(port->portsc, meta, ret, done); 3182 SNAPSHOT_VAR_OR_LEAVE(port->portpmsc, meta, ret, done); 3183 SNAPSHOT_VAR_OR_LEAVE(port->portli, meta, ret, done); 3184 SNAPSHOT_VAR_OR_LEAVE(port->porthlpmc, meta, ret, done); 3185 } 3186 3187 /* slots */ 3188 if (meta->op == VM_SNAPSHOT_SAVE) 3189 pci_xhci_map_devs_slots(sc, maps); 3190 3191 for (i = 1; i <= XHCI_MAX_SLOTS; i++) { 3192 SNAPSHOT_VAR_OR_LEAVE(maps[i], meta, ret, done); 3193 3194 if (meta->op == VM_SNAPSHOT_SAVE) { 3195 dev = XHCI_SLOTDEV_PTR(sc, i); 3196 } else if (meta->op == VM_SNAPSHOT_RESTORE) { 3197 if (maps[i] != 0) 3198 dev = XHCI_DEVINST_PTR(sc, maps[i]); 3199 else 3200 dev = NULL; 3201 3202 XHCI_SLOTDEV_PTR(sc, i) = dev; 3203 } else { 3204 /* error */ 3205 ret = EINVAL; 3206 goto done; 3207 } 3208 3209 if (dev == NULL) 3210 continue; 3211 3212 SNAPSHOT_GUEST2HOST_ADDR_OR_LEAVE(pi->pi_vmctx, dev->dev_ctx, 3213 XHCI_GADDR_SIZE(dev->dev_ctx), true, meta, ret, done); 3214 3215 if (dev->dev_ctx != NULL) { 3216 for (j = 1; j < XHCI_MAX_ENDPOINTS; j++) { 3217 ret = pci_xhci_snapshot_ep(sc, dev, j, meta); 3218 if (ret != 0) 3219 goto done; 3220 } 3221 } 3222 3223 SNAPSHOT_VAR_OR_LEAVE(dev->dev_slotstate, meta, ret, done); 3224 3225 /* devices[i]->dev_sc */ 3226 dev->dev_ue->ue_snapshot(dev->dev_sc, meta); 3227 3228 /* devices[i]->hci */ 3229 SNAPSHOT_VAR_OR_LEAVE(dev->hci.hci_address, meta, ret, done); 3230 SNAPSHOT_VAR_OR_LEAVE(dev->hci.hci_port, meta, ret, done); 3231 } 3232 3233 SNAPSHOT_VAR_OR_LEAVE(sc->usb2_port_start, meta, ret, done); 3234 SNAPSHOT_VAR_OR_LEAVE(sc->usb3_port_start, meta, ret, done); 3235 3236 done: 3237 return (ret); 3238 } 3239 #endif 3240 3241 static const struct pci_devemu pci_de_xhci = { 3242 .pe_emu = "xhci", 3243 .pe_init = pci_xhci_init, 3244 .pe_legacy_config = pci_xhci_legacy_config, 3245 .pe_barwrite = pci_xhci_write, 3246 .pe_barread = pci_xhci_read, 3247 #ifdef BHYVE_SNAPSHOT 3248 .pe_snapshot = pci_xhci_snapshot, 3249 #endif 3250 }; 3251 PCI_EMUL_SET(pci_de_xhci); 3252