xref: /freebsd/usr.sbin/bhyve/pci_uart.c (revision 81bdc9ebe3d55a4ee30ee123ada62e1fe1ea9b63)
1 /*-
2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3  *
4  * Copyright (c) 2012 NetApp, Inc.
5  * All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  * 1. Redistributions of source code must retain the above copyright
11  *    notice, this list of conditions and the following disclaimer.
12  * 2. Redistributions in binary form must reproduce the above copyright
13  *    notice, this list of conditions and the following disclaimer in the
14  *    documentation and/or other materials provided with the distribution.
15  *
16  * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19  * ARE DISCLAIMED.  IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
20  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26  * SUCH DAMAGE.
27  *
28  * $FreeBSD$
29  */
30 
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
33 
34 #include <sys/types.h>
35 
36 #include <stdio.h>
37 
38 #include "bhyverun.h"
39 #include "config.h"
40 #include "debug.h"
41 #include "pci_emul.h"
42 #include "uart_emul.h"
43 
44 /*
45  * Pick a PCI vid/did of a chip with a single uart at
46  * BAR0, that most versions of FreeBSD can understand:
47  * Siig CyberSerial 1-port.
48  */
49 #define COM_VENDOR	0x131f
50 #define COM_DEV		0x2000
51 
52 static void
53 pci_uart_intr_assert(void *arg)
54 {
55 	struct pci_devinst *pi = arg;
56 
57 	pci_lintr_assert(pi);
58 }
59 
60 static void
61 pci_uart_intr_deassert(void *arg)
62 {
63 	struct pci_devinst *pi = arg;
64 
65 	pci_lintr_deassert(pi);
66 }
67 
68 static void
69 pci_uart_write(struct vmctx *ctx __unused, int vcpu __unused,
70     struct pci_devinst *pi, int baridx, uint64_t offset, int size,
71     uint64_t value)
72 {
73 	assert(baridx == 0);
74 	assert(size == 1);
75 
76 	uart_write(pi->pi_arg, offset, value);
77 }
78 
79 static uint64_t
80 pci_uart_read(struct vmctx *ctx __unused, int vcpu __unused,
81     struct pci_devinst *pi, int baridx, uint64_t offset, int size)
82 {
83 	uint8_t val;
84 
85 	assert(baridx == 0);
86 	assert(size == 1);
87 
88 	val = uart_read(pi->pi_arg, offset);
89 	return (val);
90 }
91 
92 static int
93 pci_uart_legacy_config(nvlist_t *nvl, const char *opts)
94 {
95 
96 	if (opts != NULL)
97 		set_config_value_node(nvl, "path", opts);
98 	return (0);
99 }
100 
101 static int
102 pci_uart_init(struct vmctx *ctx __unused, struct pci_devinst *pi, nvlist_t *nvl)
103 {
104 	struct uart_softc *sc;
105 	const char *device;
106 
107 	pci_emul_alloc_bar(pi, 0, PCIBAR_IO, UART_IO_BAR_SIZE);
108 	pci_lintr_request(pi);
109 
110 	/* initialize config space */
111 	pci_set_cfgdata16(pi, PCIR_DEVICE, COM_DEV);
112 	pci_set_cfgdata16(pi, PCIR_VENDOR, COM_VENDOR);
113 	pci_set_cfgdata8(pi, PCIR_CLASS, PCIC_SIMPLECOMM);
114 
115 	sc = uart_init(pci_uart_intr_assert, pci_uart_intr_deassert, pi);
116 	pi->pi_arg = sc;
117 
118 	device = get_config_value_node(nvl, "path");
119 	if (uart_set_backend(sc, device) != 0) {
120 		EPRINTLN("Unable to initialize backend '%s' for "
121 		    "pci uart at %d:%d", device, pi->pi_slot, pi->pi_func);
122 		return (-1);
123 	}
124 
125 	return (0);
126 }
127 
128 static const struct pci_devemu pci_de_com = {
129 	.pe_emu =	"uart",
130 	.pe_init =	pci_uart_init,
131 	.pe_legacy_config = pci_uart_legacy_config,
132 	.pe_barwrite =	pci_uart_write,
133 	.pe_barread =	pci_uart_read
134 };
135 PCI_EMUL_SET(pci_de_com);
136