1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2011 NetApp, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/param.h> 30 #ifndef WITHOUT_CAPSICUM 31 #include <sys/capsicum.h> 32 #endif 33 #include <sys/types.h> 34 #include <sys/mman.h> 35 #include <sys/pciio.h> 36 #include <sys/ioctl.h> 37 #include <sys/stat.h> 38 39 #include <dev/io/iodev.h> 40 #include <dev/pci/pcireg.h> 41 42 #include <vm/vm.h> 43 44 #include <machine/iodev.h> 45 #include <machine/vm.h> 46 47 #ifndef WITHOUT_CAPSICUM 48 #include <capsicum_helpers.h> 49 #endif 50 #include <ctype.h> 51 #include <stdio.h> 52 #include <stdlib.h> 53 #include <string.h> 54 #include <err.h> 55 #include <errno.h> 56 #include <fcntl.h> 57 #include <sysexits.h> 58 #include <unistd.h> 59 60 #include <machine/vmm.h> 61 62 #include "debug.h" 63 #include "mem.h" 64 #include "pci_passthru.h" 65 66 #ifndef _PATH_DEVPCI 67 #define _PATH_DEVPCI "/dev/pci" 68 #endif 69 70 #define LEGACY_SUPPORT 1 71 72 #define MSIX_TABLE_COUNT(ctrl) (((ctrl) & PCIM_MSIXCTRL_TABLE_SIZE) + 1) 73 #define MSIX_CAPLEN 12 74 75 #define PASSTHRU_MMIO_MAX 2 76 77 static int pcifd = -1; 78 79 SET_DECLARE(passthru_dev_set, struct passthru_dev); 80 81 struct passthru_softc { 82 struct pci_devinst *psc_pi; 83 /* ROM is handled like a BAR */ 84 struct pcibar psc_bar[PCI_BARMAX_WITH_ROM + 1]; 85 struct { 86 int capoff; 87 int msgctrl; 88 int emulated; 89 } psc_msi; 90 struct { 91 int capoff; 92 } psc_msix; 93 struct pcisel psc_sel; 94 95 struct passthru_mmio_mapping psc_mmio_map[PASSTHRU_MMIO_MAX]; 96 cfgread_handler psc_pcir_rhandler[PCI_REGMAX + 1]; 97 cfgwrite_handler psc_pcir_whandler[PCI_REGMAX + 1]; 98 }; 99 100 static int 101 msi_caplen(int msgctrl) 102 { 103 int len; 104 105 len = 10; /* minimum length of msi capability */ 106 107 if (msgctrl & PCIM_MSICTRL_64BIT) 108 len += 4; 109 110 #if 0 111 /* 112 * Ignore the 'mask' and 'pending' bits in the MSI capability. 113 * We'll let the guest manipulate them directly. 114 */ 115 if (msgctrl & PCIM_MSICTRL_VECTOR) 116 len += 10; 117 #endif 118 119 return (len); 120 } 121 122 static int 123 pcifd_init(void) 124 { 125 pcifd = open(_PATH_DEVPCI, O_RDWR, 0); 126 if (pcifd < 0) { 127 warn("failed to open %s", _PATH_DEVPCI); 128 return (1); 129 } 130 131 #ifndef WITHOUT_CAPSICUM 132 cap_rights_t pcifd_rights; 133 cap_rights_init(&pcifd_rights, CAP_IOCTL, CAP_READ, CAP_WRITE); 134 if (caph_rights_limit(pcifd, &pcifd_rights) == -1) 135 errx(EX_OSERR, "Unable to apply rights for sandbox"); 136 137 const cap_ioctl_t pcifd_ioctls[] = { PCIOCREAD, PCIOCWRITE, PCIOCGETBAR, 138 PCIOCBARIO, PCIOCBARMMAP, PCIOCGETCONF }; 139 if (caph_ioctls_limit(pcifd, pcifd_ioctls, nitems(pcifd_ioctls)) == -1) 140 errx(EX_OSERR, "Unable to apply rights for sandbox"); 141 #endif 142 143 return (0); 144 } 145 146 uint32_t 147 pci_host_read_config(const struct pcisel *sel, long reg, int width) 148 { 149 struct pci_io pi; 150 151 if (pcifd < 0 && pcifd_init()) { 152 return (0); 153 } 154 155 bzero(&pi, sizeof(pi)); 156 pi.pi_sel = *sel; 157 pi.pi_reg = reg; 158 pi.pi_width = width; 159 160 if (ioctl(pcifd, PCIOCREAD, &pi) < 0) 161 return (0); /* XXX */ 162 else 163 return (pi.pi_data); 164 } 165 166 void 167 pci_host_write_config(const struct pcisel *sel, long reg, int width, 168 uint32_t data) 169 { 170 struct pci_io pi; 171 172 if (pcifd < 0 && pcifd_init()) { 173 return; 174 } 175 176 bzero(&pi, sizeof(pi)); 177 pi.pi_sel = *sel; 178 pi.pi_reg = reg; 179 pi.pi_width = width; 180 pi.pi_data = data; 181 182 (void)ioctl(pcifd, PCIOCWRITE, &pi); /* XXX */ 183 } 184 185 #ifdef LEGACY_SUPPORT 186 static int 187 passthru_add_msicap(struct pci_devinst *pi, int msgnum, int nextptr) 188 { 189 int capoff; 190 struct msicap msicap; 191 u_char *capdata; 192 193 pci_populate_msicap(&msicap, msgnum, nextptr); 194 195 /* 196 * XXX 197 * Copy the msi capability structure in the last 16 bytes of the 198 * config space. This is wrong because it could shadow something 199 * useful to the device. 200 */ 201 capoff = 256 - roundup(sizeof(msicap), 4); 202 capdata = (u_char *)&msicap; 203 for (size_t i = 0; i < sizeof(msicap); i++) 204 pci_set_cfgdata8(pi, capoff + i, capdata[i]); 205 206 return (capoff); 207 } 208 #endif /* LEGACY_SUPPORT */ 209 210 static int 211 cfginitmsi(struct passthru_softc *sc) 212 { 213 int i, ptr, capptr, cap, sts, caplen, table_size; 214 uint32_t u32; 215 struct pcisel sel; 216 struct pci_devinst *pi; 217 struct msixcap msixcap; 218 char *msixcap_ptr; 219 220 pi = sc->psc_pi; 221 sel = sc->psc_sel; 222 223 /* 224 * Parse the capabilities and cache the location of the MSI 225 * and MSI-X capabilities. 226 */ 227 sts = pci_host_read_config(&sel, PCIR_STATUS, 2); 228 if (sts & PCIM_STATUS_CAPPRESENT) { 229 ptr = pci_host_read_config(&sel, PCIR_CAP_PTR, 1); 230 while (ptr != 0 && ptr != 0xff) { 231 cap = pci_host_read_config(&sel, ptr + PCICAP_ID, 1); 232 if (cap == PCIY_MSI) { 233 /* 234 * Copy the MSI capability into the config 235 * space of the emulated pci device 236 */ 237 sc->psc_msi.capoff = ptr; 238 sc->psc_msi.msgctrl = pci_host_read_config(&sel, 239 ptr + 2, 2); 240 sc->psc_msi.emulated = 0; 241 caplen = msi_caplen(sc->psc_msi.msgctrl); 242 capptr = ptr; 243 while (caplen > 0) { 244 u32 = pci_host_read_config(&sel, capptr, 245 4); 246 pci_set_cfgdata32(pi, capptr, u32); 247 caplen -= 4; 248 capptr += 4; 249 } 250 } else if (cap == PCIY_MSIX) { 251 /* 252 * Copy the MSI-X capability 253 */ 254 sc->psc_msix.capoff = ptr; 255 caplen = 12; 256 msixcap_ptr = (char *)&msixcap; 257 capptr = ptr; 258 while (caplen > 0) { 259 u32 = pci_host_read_config(&sel, capptr, 260 4); 261 memcpy(msixcap_ptr, &u32, 4); 262 pci_set_cfgdata32(pi, capptr, u32); 263 caplen -= 4; 264 capptr += 4; 265 msixcap_ptr += 4; 266 } 267 } 268 ptr = pci_host_read_config(&sel, ptr + PCICAP_NEXTPTR, 269 1); 270 } 271 } 272 273 if (sc->psc_msix.capoff != 0) { 274 pi->pi_msix.pba_bar = 275 msixcap.pba_info & PCIM_MSIX_BIR_MASK; 276 pi->pi_msix.pba_offset = 277 msixcap.pba_info & ~PCIM_MSIX_BIR_MASK; 278 pi->pi_msix.table_bar = 279 msixcap.table_info & PCIM_MSIX_BIR_MASK; 280 pi->pi_msix.table_offset = 281 msixcap.table_info & ~PCIM_MSIX_BIR_MASK; 282 pi->pi_msix.table_count = MSIX_TABLE_COUNT(msixcap.msgctrl); 283 pi->pi_msix.pba_size = PBA_SIZE(pi->pi_msix.table_count); 284 285 /* Allocate the emulated MSI-X table array */ 286 table_size = pi->pi_msix.table_count * MSIX_TABLE_ENTRY_SIZE; 287 pi->pi_msix.table = calloc(1, table_size); 288 289 /* Mask all table entries */ 290 for (i = 0; i < pi->pi_msix.table_count; i++) { 291 pi->pi_msix.table[i].vector_control |= 292 PCIM_MSIX_VCTRL_MASK; 293 } 294 } 295 296 #ifdef LEGACY_SUPPORT 297 /* 298 * If the passthrough device does not support MSI then craft a 299 * MSI capability for it. We link the new MSI capability at the 300 * head of the list of capabilities. 301 */ 302 if ((sts & PCIM_STATUS_CAPPRESENT) != 0 && sc->psc_msi.capoff == 0) { 303 int origptr, msiptr; 304 origptr = pci_host_read_config(&sel, PCIR_CAP_PTR, 1); 305 msiptr = passthru_add_msicap(pi, 1, origptr); 306 sc->psc_msi.capoff = msiptr; 307 sc->psc_msi.msgctrl = pci_get_cfgdata16(pi, msiptr + 2); 308 sc->psc_msi.emulated = 1; 309 pci_set_cfgdata8(pi, PCIR_CAP_PTR, msiptr); 310 } 311 #endif 312 313 /* Make sure one of the capabilities is present */ 314 if (sc->psc_msi.capoff == 0 && sc->psc_msix.capoff == 0) 315 return (-1); 316 else 317 return (0); 318 } 319 320 static uint64_t 321 msix_table_read(struct passthru_softc *sc, uint64_t offset, int size) 322 { 323 struct pci_devinst *pi; 324 struct msix_table_entry *entry; 325 uint8_t *src8; 326 uint16_t *src16; 327 uint32_t *src32; 328 uint64_t *src64; 329 uint64_t data; 330 size_t entry_offset; 331 uint32_t table_offset; 332 int index, table_count; 333 334 pi = sc->psc_pi; 335 336 table_offset = pi->pi_msix.table_offset; 337 table_count = pi->pi_msix.table_count; 338 if (offset < table_offset || 339 offset >= table_offset + table_count * MSIX_TABLE_ENTRY_SIZE) { 340 switch (size) { 341 case 1: 342 src8 = (uint8_t *)(pi->pi_msix.mapped_addr + offset); 343 data = *src8; 344 break; 345 case 2: 346 src16 = (uint16_t *)(pi->pi_msix.mapped_addr + offset); 347 data = *src16; 348 break; 349 case 4: 350 src32 = (uint32_t *)(pi->pi_msix.mapped_addr + offset); 351 data = *src32; 352 break; 353 case 8: 354 src64 = (uint64_t *)(pi->pi_msix.mapped_addr + offset); 355 data = *src64; 356 break; 357 default: 358 return (-1); 359 } 360 return (data); 361 } 362 363 offset -= table_offset; 364 index = offset / MSIX_TABLE_ENTRY_SIZE; 365 assert(index < table_count); 366 367 entry = &pi->pi_msix.table[index]; 368 entry_offset = offset % MSIX_TABLE_ENTRY_SIZE; 369 370 switch (size) { 371 case 1: 372 src8 = (uint8_t *)((uint8_t *)entry + entry_offset); 373 data = *src8; 374 break; 375 case 2: 376 src16 = (uint16_t *)((uint8_t *)entry + entry_offset); 377 data = *src16; 378 break; 379 case 4: 380 src32 = (uint32_t *)((uint8_t *)entry + entry_offset); 381 data = *src32; 382 break; 383 case 8: 384 src64 = (uint64_t *)((uint8_t *)entry + entry_offset); 385 data = *src64; 386 break; 387 default: 388 return (-1); 389 } 390 391 return (data); 392 } 393 394 static void 395 msix_table_write(struct passthru_softc *sc, uint64_t offset, int size, 396 uint64_t data) 397 { 398 struct pci_devinst *pi; 399 struct msix_table_entry *entry; 400 uint8_t *dest8; 401 uint16_t *dest16; 402 uint32_t *dest32; 403 uint64_t *dest64; 404 size_t entry_offset; 405 uint32_t table_offset, vector_control; 406 int index, table_count; 407 408 pi = sc->psc_pi; 409 410 table_offset = pi->pi_msix.table_offset; 411 table_count = pi->pi_msix.table_count; 412 if (offset < table_offset || 413 offset >= table_offset + table_count * MSIX_TABLE_ENTRY_SIZE) { 414 switch (size) { 415 case 1: 416 dest8 = (uint8_t *)(pi->pi_msix.mapped_addr + offset); 417 *dest8 = data; 418 break; 419 case 2: 420 dest16 = (uint16_t *)(pi->pi_msix.mapped_addr + offset); 421 *dest16 = data; 422 break; 423 case 4: 424 dest32 = (uint32_t *)(pi->pi_msix.mapped_addr + offset); 425 *dest32 = data; 426 break; 427 case 8: 428 dest64 = (uint64_t *)(pi->pi_msix.mapped_addr + offset); 429 *dest64 = data; 430 break; 431 } 432 return; 433 } 434 435 offset -= table_offset; 436 index = offset / MSIX_TABLE_ENTRY_SIZE; 437 assert(index < table_count); 438 439 entry = &pi->pi_msix.table[index]; 440 entry_offset = offset % MSIX_TABLE_ENTRY_SIZE; 441 442 /* Only 4 byte naturally-aligned writes are supported */ 443 assert(size == 4); 444 assert(entry_offset % 4 == 0); 445 446 vector_control = entry->vector_control; 447 dest32 = (uint32_t *)((uint8_t *)entry + entry_offset); 448 *dest32 = data; 449 /* If MSI-X hasn't been enabled, do nothing */ 450 if (pi->pi_msix.enabled) { 451 /* If the entry is masked, don't set it up */ 452 if ((entry->vector_control & PCIM_MSIX_VCTRL_MASK) == 0 || 453 (vector_control & PCIM_MSIX_VCTRL_MASK) == 0) { 454 (void)vm_setup_pptdev_msix(sc->psc_pi->pi_vmctx, 455 sc->psc_sel.pc_bus, sc->psc_sel.pc_dev, 456 sc->psc_sel.pc_func, index, entry->addr, 457 entry->msg_data, entry->vector_control); 458 } 459 } 460 } 461 462 static int 463 init_msix_table(struct passthru_softc *sc) 464 { 465 struct pci_devinst *pi = sc->psc_pi; 466 struct pci_bar_mmap pbm; 467 int b, s, f; 468 uint32_t table_size, table_offset; 469 470 assert(pci_msix_table_bar(pi) >= 0 && pci_msix_pba_bar(pi) >= 0); 471 472 b = sc->psc_sel.pc_bus; 473 s = sc->psc_sel.pc_dev; 474 f = sc->psc_sel.pc_func; 475 476 /* 477 * Map the region of the BAR containing the MSI-X table. This is 478 * necessary for two reasons: 479 * 1. The PBA may reside in the first or last page containing the MSI-X 480 * table. 481 * 2. While PCI devices are not supposed to use the page(s) containing 482 * the MSI-X table for other purposes, some do in practice. 483 */ 484 memset(&pbm, 0, sizeof(pbm)); 485 pbm.pbm_sel = sc->psc_sel; 486 pbm.pbm_flags = PCIIO_BAR_MMAP_RW; 487 pbm.pbm_reg = PCIR_BAR(pi->pi_msix.table_bar); 488 pbm.pbm_memattr = VM_MEMATTR_DEVICE; 489 490 if (ioctl(pcifd, PCIOCBARMMAP, &pbm) != 0) { 491 warn("Failed to map MSI-X table BAR on %d/%d/%d", b, s, f); 492 return (-1); 493 } 494 assert(pbm.pbm_bar_off == 0); 495 pi->pi_msix.mapped_addr = (uint8_t *)(uintptr_t)pbm.pbm_map_base; 496 pi->pi_msix.mapped_size = pbm.pbm_map_length; 497 498 table_offset = rounddown2(pi->pi_msix.table_offset, 4096); 499 500 table_size = pi->pi_msix.table_offset - table_offset; 501 table_size += pi->pi_msix.table_count * MSIX_TABLE_ENTRY_SIZE; 502 table_size = roundup2(table_size, 4096); 503 504 /* 505 * Unmap any pages not containing the table, we do not need to emulate 506 * accesses to them. Avoid releasing address space to help ensure that 507 * a buggy out-of-bounds access causes a crash. 508 */ 509 if (table_offset != 0) 510 if (mprotect(pi->pi_msix.mapped_addr, table_offset, 511 PROT_NONE) != 0) 512 warn("Failed to unmap MSI-X table BAR region"); 513 if (table_offset + table_size != pi->pi_msix.mapped_size) 514 if (mprotect( 515 pi->pi_msix.mapped_addr + table_offset + table_size, 516 pi->pi_msix.mapped_size - (table_offset + table_size), 517 PROT_NONE) != 0) 518 warn("Failed to unmap MSI-X table BAR region"); 519 520 return (0); 521 } 522 523 static int 524 cfginitbar(struct passthru_softc *sc) 525 { 526 int i, error; 527 struct pci_devinst *pi; 528 struct pci_bar_io bar; 529 enum pcibar_type bartype; 530 uint64_t base, size; 531 532 pi = sc->psc_pi; 533 534 /* 535 * Initialize BAR registers 536 */ 537 for (i = 0; i <= PCI_BARMAX; i++) { 538 bzero(&bar, sizeof(bar)); 539 bar.pbi_sel = sc->psc_sel; 540 bar.pbi_reg = PCIR_BAR(i); 541 542 if (ioctl(pcifd, PCIOCGETBAR, &bar) < 0) 543 continue; 544 545 if (PCI_BAR_IO(bar.pbi_base)) { 546 bartype = PCIBAR_IO; 547 base = bar.pbi_base & PCIM_BAR_IO_BASE; 548 } else { 549 switch (bar.pbi_base & PCIM_BAR_MEM_TYPE) { 550 case PCIM_BAR_MEM_64: 551 bartype = PCIBAR_MEM64; 552 break; 553 default: 554 bartype = PCIBAR_MEM32; 555 break; 556 } 557 base = bar.pbi_base & PCIM_BAR_MEM_BASE; 558 } 559 size = bar.pbi_length; 560 561 if (bartype != PCIBAR_IO) { 562 if (((base | size) & PAGE_MASK) != 0) { 563 warnx("passthru device %d/%d/%d BAR %d: " 564 "base %#lx or size %#lx not page aligned\n", 565 sc->psc_sel.pc_bus, sc->psc_sel.pc_dev, 566 sc->psc_sel.pc_func, i, base, size); 567 return (-1); 568 } 569 } 570 571 /* Cache information about the "real" BAR */ 572 sc->psc_bar[i].type = bartype; 573 sc->psc_bar[i].size = size; 574 sc->psc_bar[i].addr = base; 575 sc->psc_bar[i].lobits = 0; 576 577 /* Allocate the BAR in the guest I/O or MMIO space */ 578 error = pci_emul_alloc_bar(pi, i, bartype, size); 579 if (error) 580 return (-1); 581 582 /* Use same lobits as physical bar */ 583 uint8_t lobits = pci_host_read_config(&sc->psc_sel, PCIR_BAR(i), 584 0x01); 585 if (bartype == PCIBAR_MEM32 || bartype == PCIBAR_MEM64) { 586 lobits &= ~PCIM_BAR_MEM_BASE; 587 } else { 588 lobits &= ~PCIM_BAR_IO_BASE; 589 } 590 sc->psc_bar[i].lobits = lobits; 591 pi->pi_bar[i].lobits = lobits; 592 593 /* 594 * 64-bit BAR takes up two slots so skip the next one. 595 */ 596 if (bartype == PCIBAR_MEM64) { 597 i++; 598 assert(i <= PCI_BARMAX); 599 sc->psc_bar[i].type = PCIBAR_MEMHI64; 600 } 601 } 602 return (0); 603 } 604 605 static int 606 cfginit(struct pci_devinst *pi, int bus, int slot, int func) 607 { 608 int error; 609 struct passthru_softc *sc; 610 uint16_t cmd; 611 uint8_t intline, intpin; 612 613 error = 1; 614 sc = pi->pi_arg; 615 616 bzero(&sc->psc_sel, sizeof(struct pcisel)); 617 sc->psc_sel.pc_bus = bus; 618 sc->psc_sel.pc_dev = slot; 619 sc->psc_sel.pc_func = func; 620 621 /* 622 * Copy physical PCI header to virtual config space. COMMAND, 623 * INTLINE, and INTPIN shouldn't be aligned with their 624 * physical value and they are already set by pci_emul_init(). 625 */ 626 cmd = pci_get_cfgdata16(pi, PCIR_COMMAND); 627 intline = pci_get_cfgdata8(pi, PCIR_INTLINE); 628 intpin = pci_get_cfgdata8(pi, PCIR_INTPIN); 629 for (int i = 0; i <= PCIR_MAXLAT; i += 4) { 630 pci_set_cfgdata32(pi, i, 631 pci_host_read_config(&sc->psc_sel, i, 4)); 632 } 633 pci_set_cfgdata16(pi, PCIR_COMMAND, cmd); 634 pci_set_cfgdata8(pi, PCIR_INTLINE, intline); 635 pci_set_cfgdata8(pi, PCIR_INTPIN, intpin); 636 637 if (cfginitmsi(sc) != 0) { 638 warnx("failed to initialize MSI for PCI %d/%d/%d", 639 bus, slot, func); 640 goto done; 641 } 642 643 if (cfginitbar(sc) != 0) { 644 warnx("failed to initialize BARs for PCI %d/%d/%d", 645 bus, slot, func); 646 goto done; 647 } 648 649 if (pci_msix_table_bar(pi) >= 0) { 650 error = init_msix_table(sc); 651 if (error != 0) { 652 warnx( 653 "failed to initialize MSI-X table for PCI %d/%d/%d: %d", 654 bus, slot, func, error); 655 goto done; 656 } 657 } 658 659 error = 0; /* success */ 660 done: 661 return (error); 662 } 663 664 struct passthru_mmio_mapping * 665 passthru_get_mmio(struct passthru_softc *sc, int num) 666 { 667 assert(sc != NULL); 668 assert(num < PASSTHRU_MMIO_MAX); 669 670 return (&sc->psc_mmio_map[num]); 671 } 672 673 struct pcisel * 674 passthru_get_sel(struct passthru_softc *sc) 675 { 676 assert(sc != NULL); 677 678 return (&sc->psc_sel); 679 } 680 681 int 682 set_pcir_handler(struct passthru_softc *sc, int reg, int len, 683 cfgread_handler rhandler, cfgwrite_handler whandler) 684 { 685 if (reg > PCI_REGMAX || reg + len > PCI_REGMAX + 1) 686 return (-1); 687 688 for (int i = reg; i < reg + len; ++i) { 689 assert(sc->psc_pcir_rhandler[i] == NULL || rhandler == NULL); 690 assert(sc->psc_pcir_whandler[i] == NULL || whandler == NULL); 691 sc->psc_pcir_rhandler[i] = rhandler; 692 sc->psc_pcir_whandler[i] = whandler; 693 } 694 695 return (0); 696 } 697 698 static int 699 passthru_legacy_config(nvlist_t *nvl, const char *opts) 700 { 701 const char *cp; 702 char *tofree; 703 char value[16]; 704 int bus, slot, func; 705 706 if (opts == NULL) 707 return (0); 708 709 cp = strchr(opts, ','); 710 711 if (strncmp(opts, "ppt", strlen("ppt")) == 0) { 712 tofree = strndup(opts, cp - opts); 713 set_config_value_node(nvl, "pptdev", tofree); 714 free(tofree); 715 } else if (sscanf(opts, "pci0:%d:%d:%d", &bus, &slot, &func) == 3 || 716 sscanf(opts, "pci%d:%d:%d", &bus, &slot, &func) == 3 || 717 sscanf(opts, "%d/%d/%d", &bus, &slot, &func) == 3) { 718 snprintf(value, sizeof(value), "%d", bus); 719 set_config_value_node(nvl, "bus", value); 720 snprintf(value, sizeof(value), "%d", slot); 721 set_config_value_node(nvl, "slot", value); 722 snprintf(value, sizeof(value), "%d", func); 723 set_config_value_node(nvl, "func", value); 724 } else { 725 EPRINTLN("passthru: invalid options \"%s\"", opts); 726 return (-1); 727 } 728 729 if (cp == NULL) { 730 return (0); 731 } 732 733 return (pci_parse_legacy_config(nvl, cp + 1)); 734 } 735 736 static int 737 passthru_init_rom(struct passthru_softc *const sc, const char *const romfile) 738 { 739 if (romfile == NULL) { 740 return (0); 741 } 742 743 const int fd = open(romfile, O_RDONLY); 744 if (fd < 0) { 745 warnx("%s: can't open romfile \"%s\"", __func__, romfile); 746 return (-1); 747 } 748 749 struct stat sbuf; 750 if (fstat(fd, &sbuf) < 0) { 751 warnx("%s: can't fstat romfile \"%s\"", __func__, romfile); 752 close(fd); 753 return (-1); 754 } 755 const uint64_t rom_size = sbuf.st_size; 756 757 void *const rom_data = mmap(NULL, rom_size, PROT_READ, MAP_SHARED, fd, 758 0); 759 if (rom_data == MAP_FAILED) { 760 warnx("%s: unable to mmap romfile \"%s\" (%d)", __func__, 761 romfile, errno); 762 close(fd); 763 return (-1); 764 } 765 766 void *rom_addr; 767 int error = pci_emul_alloc_rom(sc->psc_pi, rom_size, &rom_addr); 768 if (error) { 769 warnx("%s: failed to alloc rom segment", __func__); 770 munmap(rom_data, rom_size); 771 close(fd); 772 return (error); 773 } 774 memcpy(rom_addr, rom_data, rom_size); 775 776 sc->psc_bar[PCI_ROM_IDX].type = PCIBAR_ROM; 777 sc->psc_bar[PCI_ROM_IDX].addr = (uint64_t)rom_addr; 778 sc->psc_bar[PCI_ROM_IDX].size = rom_size; 779 780 munmap(rom_data, rom_size); 781 close(fd); 782 783 return (0); 784 } 785 786 static bool 787 passthru_lookup_pptdev(const char *name, int *bus, int *slot, int *func) 788 { 789 struct pci_conf_io pc; 790 struct pci_conf conf[1]; 791 struct pci_match_conf patterns[1]; 792 char *cp; 793 794 bzero(&pc, sizeof(struct pci_conf_io)); 795 pc.match_buf_len = sizeof(conf); 796 pc.matches = conf; 797 798 bzero(&patterns, sizeof(patterns)); 799 800 /* 801 * The pattern structure requires the unit to be split out from 802 * the driver name. Walk backwards from the end of the name to 803 * find the start of the unit. 804 */ 805 cp = strchr(name, '\0'); 806 assert(cp != NULL); 807 while (cp != name && isdigit(cp[-1])) 808 cp--; 809 if (cp == name || !isdigit(*cp)) { 810 EPRINTLN("Invalid passthru device name %s", name); 811 return (false); 812 } 813 if ((size_t)(cp - name) + 1 > sizeof(patterns[0].pd_name)) { 814 EPRINTLN("Passthru device name %s is too long", name); 815 return (false); 816 } 817 memcpy(patterns[0].pd_name, name, cp - name); 818 patterns[0].pd_unit = strtol(cp, &cp, 10); 819 if (*cp != '\0') { 820 EPRINTLN("Invalid passthru device name %s", name); 821 return (false); 822 } 823 patterns[0].flags = PCI_GETCONF_MATCH_NAME | PCI_GETCONF_MATCH_UNIT; 824 pc.num_patterns = 1; 825 pc.pat_buf_len = sizeof(patterns); 826 pc.patterns = patterns; 827 828 if (ioctl(pcifd, PCIOCGETCONF, &pc) == -1) { 829 EPRINTLN("ioctl(PCIOCGETCONF): %s", strerror(errno)); 830 return (false); 831 } 832 if (pc.status != PCI_GETCONF_LAST_DEVICE && 833 pc.status != PCI_GETCONF_MORE_DEVS) { 834 EPRINTLN("error returned from PCIOCGETCONF ioctl"); 835 return (false); 836 } 837 if (pc.num_matches == 0) { 838 EPRINTLN("Passthru device %s not found", name); 839 return (false); 840 } 841 842 if (conf[0].pc_sel.pc_domain != 0) { 843 EPRINTLN("Passthru device %s on unsupported domain", name); 844 return (false); 845 } 846 *bus = conf[0].pc_sel.pc_bus; 847 *slot = conf[0].pc_sel.pc_dev; 848 *func = conf[0].pc_sel.pc_func; 849 return (true); 850 } 851 852 static int 853 passthru_init(struct pci_devinst *pi, nvlist_t *nvl) 854 { 855 int bus, slot, func, error, memflags; 856 struct passthru_softc *sc; 857 struct passthru_dev **devpp; 858 struct passthru_dev *devp, *dev = NULL; 859 const char *value; 860 861 sc = NULL; 862 error = 1; 863 864 memflags = vm_get_memflags(pi->pi_vmctx); 865 if (!(memflags & VM_MEM_F_WIRED)) { 866 warnx("passthru requires guest memory to be wired"); 867 return (error); 868 } 869 870 if (pcifd < 0 && pcifd_init()) { 871 return (error); 872 } 873 874 #define GET_INT_CONFIG(var, name) do { \ 875 value = get_config_value_node(nvl, name); \ 876 if (value == NULL) { \ 877 EPRINTLN("passthru: missing required %s setting", name); \ 878 return (error); \ 879 } \ 880 var = atoi(value); \ 881 } while (0) 882 883 value = get_config_value_node(nvl, "pptdev"); 884 if (value != NULL) { 885 if (!passthru_lookup_pptdev(value, &bus, &slot, &func)) 886 return (error); 887 } else { 888 GET_INT_CONFIG(bus, "bus"); 889 GET_INT_CONFIG(slot, "slot"); 890 GET_INT_CONFIG(func, "func"); 891 } 892 893 if (vm_assign_pptdev(pi->pi_vmctx, bus, slot, func) != 0) { 894 warnx("PCI device at %d/%d/%d is not using the ppt(4) driver", 895 bus, slot, func); 896 goto done; 897 } 898 899 sc = calloc(1, sizeof(struct passthru_softc)); 900 901 pi->pi_arg = sc; 902 sc->psc_pi = pi; 903 904 /* initialize config space */ 905 if ((error = cfginit(pi, bus, slot, func)) != 0) 906 goto done; 907 908 /* initialize ROM */ 909 if ((error = passthru_init_rom(sc, 910 get_config_value_node(nvl, "rom"))) != 0) 911 goto done; 912 913 /* Emulate most PCI header register. */ 914 if ((error = set_pcir_handler(sc, 0, PCIR_MAXLAT + 1, 915 passthru_cfgread_emulate, passthru_cfgwrite_emulate)) != 0) 916 goto done; 917 918 /* Allow access to the physical status register. */ 919 if ((error = set_pcir_handler(sc, PCIR_COMMAND, 0x04, NULL, NULL)) != 0) 920 goto done; 921 922 SET_FOREACH(devpp, passthru_dev_set) { 923 devp = *devpp; 924 assert(devp->probe != NULL); 925 if (devp->probe(pi) == 0) { 926 dev = devp; 927 break; 928 } 929 } 930 931 if (dev != NULL) { 932 error = dev->init(pi, nvl); 933 if (error != 0) 934 goto done; 935 } 936 937 error = 0; /* success */ 938 done: 939 if (error) { 940 if (dev != NULL) 941 dev->deinit(pi); 942 free(sc); 943 vm_unassign_pptdev(pi->pi_vmctx, bus, slot, func); 944 } 945 return (error); 946 } 947 948 static int 949 msicap_access(struct passthru_softc *sc, int coff) 950 { 951 int caplen; 952 953 if (sc->psc_msi.capoff == 0) 954 return (0); 955 956 caplen = msi_caplen(sc->psc_msi.msgctrl); 957 958 if (coff >= sc->psc_msi.capoff && coff < sc->psc_msi.capoff + caplen) 959 return (1); 960 else 961 return (0); 962 } 963 964 static int 965 msixcap_access(struct passthru_softc *sc, int coff) 966 { 967 if (sc->psc_msix.capoff == 0) 968 return (0); 969 970 return (coff >= sc->psc_msix.capoff && 971 coff < sc->psc_msix.capoff + MSIX_CAPLEN); 972 } 973 974 static int 975 passthru_cfgread_default(struct passthru_softc *sc, 976 struct pci_devinst *pi __unused, int coff, int bytes, uint32_t *rv) 977 { 978 /* 979 * MSI capability is emulated. 980 */ 981 if (msicap_access(sc, coff) || msixcap_access(sc, coff)) 982 return (-1); 983 984 /* 985 * Emulate the command register. If a single read reads both the 986 * command and status registers, read the status register from the 987 * device's config space. 988 */ 989 if (coff == PCIR_COMMAND) { 990 if (bytes <= 2) 991 return (-1); 992 *rv = pci_host_read_config(&sc->psc_sel, PCIR_STATUS, 2) << 16 | 993 pci_get_cfgdata16(pi, PCIR_COMMAND); 994 return (0); 995 } 996 997 /* Everything else just read from the device's config space */ 998 *rv = pci_host_read_config(&sc->psc_sel, coff, bytes); 999 1000 return (0); 1001 } 1002 1003 int 1004 passthru_cfgread_emulate(struct passthru_softc *sc __unused, 1005 struct pci_devinst *pi __unused, int coff __unused, int bytes __unused, 1006 uint32_t *rv __unused) 1007 { 1008 return (-1); 1009 } 1010 1011 static int 1012 passthru_cfgread(struct pci_devinst *pi, int coff, int bytes, uint32_t *rv) 1013 { 1014 struct passthru_softc *sc; 1015 1016 sc = pi->pi_arg; 1017 1018 if (sc->psc_pcir_rhandler[coff] != NULL) 1019 return (sc->psc_pcir_rhandler[coff](sc, pi, coff, bytes, rv)); 1020 1021 return (passthru_cfgread_default(sc, pi, coff, bytes, rv)); 1022 } 1023 1024 static int 1025 passthru_cfgwrite_default(struct passthru_softc *sc, struct pci_devinst *pi, 1026 int coff, int bytes, uint32_t val) 1027 { 1028 int error, msix_table_entries, i; 1029 uint16_t cmd_old; 1030 1031 /* 1032 * MSI capability is emulated 1033 */ 1034 if (msicap_access(sc, coff)) { 1035 pci_emul_capwrite(pi, coff, bytes, val, sc->psc_msi.capoff, 1036 PCIY_MSI); 1037 error = vm_setup_pptdev_msi(pi->pi_vmctx, sc->psc_sel.pc_bus, 1038 sc->psc_sel.pc_dev, sc->psc_sel.pc_func, 1039 pi->pi_msi.addr, pi->pi_msi.msg_data, 1040 pi->pi_msi.maxmsgnum); 1041 if (error != 0) 1042 err(1, "vm_setup_pptdev_msi"); 1043 return (0); 1044 } 1045 1046 if (msixcap_access(sc, coff)) { 1047 pci_emul_capwrite(pi, coff, bytes, val, sc->psc_msix.capoff, 1048 PCIY_MSIX); 1049 if (pi->pi_msix.enabled) { 1050 msix_table_entries = pi->pi_msix.table_count; 1051 for (i = 0; i < msix_table_entries; i++) { 1052 error = vm_setup_pptdev_msix(pi->pi_vmctx, 1053 sc->psc_sel.pc_bus, sc->psc_sel.pc_dev, 1054 sc->psc_sel.pc_func, i, 1055 pi->pi_msix.table[i].addr, 1056 pi->pi_msix.table[i].msg_data, 1057 pi->pi_msix.table[i].vector_control); 1058 1059 if (error) 1060 err(1, "vm_setup_pptdev_msix"); 1061 } 1062 } else { 1063 error = vm_disable_pptdev_msix(pi->pi_vmctx, 1064 sc->psc_sel.pc_bus, sc->psc_sel.pc_dev, 1065 sc->psc_sel.pc_func); 1066 if (error) 1067 err(1, "vm_disable_pptdev_msix"); 1068 } 1069 return (0); 1070 } 1071 1072 /* 1073 * The command register is emulated, but the status register 1074 * is passed through. 1075 */ 1076 if (coff == PCIR_COMMAND) { 1077 if (bytes <= 2) 1078 return (-1); 1079 1080 /* Update the physical status register. */ 1081 pci_host_write_config(&sc->psc_sel, PCIR_STATUS, val >> 16, 2); 1082 1083 /* Update the virtual command register. */ 1084 cmd_old = pci_get_cfgdata16(pi, PCIR_COMMAND); 1085 pci_set_cfgdata16(pi, PCIR_COMMAND, val & 0xffff); 1086 pci_emul_cmd_changed(pi, cmd_old); 1087 return (0); 1088 } 1089 1090 pci_host_write_config(&sc->psc_sel, coff, bytes, val); 1091 1092 return (0); 1093 } 1094 1095 int 1096 passthru_cfgwrite_emulate(struct passthru_softc *sc __unused, 1097 struct pci_devinst *pi __unused, int coff __unused, int bytes __unused, 1098 uint32_t val __unused) 1099 { 1100 return (-1); 1101 } 1102 1103 static int 1104 passthru_cfgwrite(struct pci_devinst *pi, int coff, int bytes, uint32_t val) 1105 { 1106 struct passthru_softc *sc; 1107 1108 sc = pi->pi_arg; 1109 1110 if (sc->psc_pcir_whandler[coff] != NULL) 1111 return (sc->psc_pcir_whandler[coff](sc, pi, coff, bytes, val)); 1112 1113 return (passthru_cfgwrite_default(sc, pi, coff, bytes, val)); 1114 } 1115 1116 static void 1117 passthru_write(struct pci_devinst *pi, int baridx, uint64_t offset, int size, 1118 uint64_t value) 1119 { 1120 struct passthru_softc *sc; 1121 struct pci_bar_ioreq pio; 1122 1123 sc = pi->pi_arg; 1124 1125 if (baridx == pci_msix_table_bar(pi)) { 1126 msix_table_write(sc, offset, size, value); 1127 } else { 1128 assert(pi->pi_bar[baridx].type == PCIBAR_IO); 1129 assert(size == 1 || size == 2 || size == 4); 1130 assert(offset <= UINT32_MAX && offset + size <= UINT32_MAX); 1131 1132 bzero(&pio, sizeof(pio)); 1133 pio.pbi_sel = sc->psc_sel; 1134 pio.pbi_op = PCIBARIO_WRITE; 1135 pio.pbi_bar = baridx; 1136 pio.pbi_offset = (uint32_t)offset; 1137 pio.pbi_width = size; 1138 pio.pbi_value = (uint32_t)value; 1139 1140 (void)ioctl(pcifd, PCIOCBARIO, &pio); 1141 } 1142 } 1143 1144 static uint64_t 1145 passthru_read(struct pci_devinst *pi, int baridx, uint64_t offset, int size) 1146 { 1147 struct passthru_softc *sc; 1148 struct pci_bar_ioreq pio; 1149 uint64_t val; 1150 1151 sc = pi->pi_arg; 1152 1153 if (baridx == pci_msix_table_bar(pi)) { 1154 val = msix_table_read(sc, offset, size); 1155 } else { 1156 assert(pi->pi_bar[baridx].type == PCIBAR_IO); 1157 assert(size == 1 || size == 2 || size == 4); 1158 assert(offset <= UINT32_MAX && offset + size <= UINT32_MAX); 1159 1160 bzero(&pio, sizeof(pio)); 1161 pio.pbi_sel = sc->psc_sel; 1162 pio.pbi_op = PCIBARIO_READ; 1163 pio.pbi_bar = baridx; 1164 pio.pbi_offset = (uint32_t)offset; 1165 pio.pbi_width = size; 1166 1167 (void)ioctl(pcifd, PCIOCBARIO, &pio); 1168 1169 val = pio.pbi_value; 1170 } 1171 1172 return (val); 1173 } 1174 1175 static void 1176 passthru_msix_addr(struct pci_devinst *pi, int baridx, int enabled, 1177 uint64_t address) 1178 { 1179 struct passthru_softc *sc; 1180 size_t remaining; 1181 uint32_t table_size, table_offset; 1182 1183 sc = pi->pi_arg; 1184 table_offset = rounddown2(pi->pi_msix.table_offset, 4096); 1185 if (table_offset > 0) { 1186 if (!enabled) { 1187 if (vm_unmap_pptdev_mmio(pi->pi_vmctx, 1188 sc->psc_sel.pc_bus, 1189 sc->psc_sel.pc_dev, 1190 sc->psc_sel.pc_func, address, 1191 table_offset) != 0) 1192 warnx("pci_passthru: unmap_pptdev_mmio failed"); 1193 } else { 1194 if (vm_map_pptdev_mmio(pi->pi_vmctx, sc->psc_sel.pc_bus, 1195 sc->psc_sel.pc_dev, 1196 sc->psc_sel.pc_func, address, 1197 table_offset, 1198 sc->psc_bar[baridx].addr) != 0) 1199 warnx("pci_passthru: map_pptdev_mmio failed"); 1200 } 1201 } 1202 table_size = pi->pi_msix.table_offset - table_offset; 1203 table_size += pi->pi_msix.table_count * MSIX_TABLE_ENTRY_SIZE; 1204 table_size = roundup2(table_size, 4096); 1205 remaining = pi->pi_bar[baridx].size - table_offset - table_size; 1206 if (remaining > 0) { 1207 address += table_offset + table_size; 1208 if (!enabled) { 1209 if (vm_unmap_pptdev_mmio(pi->pi_vmctx, 1210 sc->psc_sel.pc_bus, 1211 sc->psc_sel.pc_dev, 1212 sc->psc_sel.pc_func, address, 1213 remaining) != 0) 1214 warnx("pci_passthru: unmap_pptdev_mmio failed"); 1215 } else { 1216 if (vm_map_pptdev_mmio(pi->pi_vmctx, sc->psc_sel.pc_bus, 1217 sc->psc_sel.pc_dev, 1218 sc->psc_sel.pc_func, address, 1219 remaining, 1220 sc->psc_bar[baridx].addr + 1221 table_offset + table_size) != 0) 1222 warnx("pci_passthru: map_pptdev_mmio failed"); 1223 } 1224 } 1225 } 1226 1227 static void 1228 passthru_mmio_addr(struct pci_devinst *pi, int baridx, int enabled, 1229 uint64_t address) 1230 { 1231 struct passthru_softc *sc; 1232 1233 sc = pi->pi_arg; 1234 if (!enabled) { 1235 if (vm_unmap_pptdev_mmio(pi->pi_vmctx, sc->psc_sel.pc_bus, 1236 sc->psc_sel.pc_dev, 1237 sc->psc_sel.pc_func, address, 1238 sc->psc_bar[baridx].size) != 0) 1239 warnx("pci_passthru: unmap_pptdev_mmio failed"); 1240 } else { 1241 if (vm_map_pptdev_mmio(pi->pi_vmctx, sc->psc_sel.pc_bus, 1242 sc->psc_sel.pc_dev, 1243 sc->psc_sel.pc_func, address, 1244 sc->psc_bar[baridx].size, 1245 sc->psc_bar[baridx].addr) != 0) 1246 warnx("pci_passthru: map_pptdev_mmio failed"); 1247 } 1248 } 1249 1250 static void 1251 passthru_addr_rom(struct pci_devinst *const pi, const int idx, 1252 const int enabled) 1253 { 1254 const uint64_t addr = pi->pi_bar[idx].addr; 1255 const uint64_t size = pi->pi_bar[idx].size; 1256 1257 if (!enabled) { 1258 if (vm_munmap_memseg(pi->pi_vmctx, addr, size) != 0) { 1259 errx(4, "%s: munmap_memseg @ [%016lx - %016lx] failed", 1260 __func__, addr, addr + size); 1261 } 1262 1263 } else { 1264 if (vm_mmap_memseg(pi->pi_vmctx, addr, VM_PCIROM, 1265 pi->pi_romoffset, size, PROT_READ | PROT_EXEC) != 0) { 1266 errx(4, "%s: mmap_memseg @ [%016lx - %016lx] failed", 1267 __func__, addr, addr + size); 1268 } 1269 } 1270 } 1271 1272 static void 1273 passthru_addr(struct pci_devinst *pi, int baridx, int enabled, uint64_t address) 1274 { 1275 switch (pi->pi_bar[baridx].type) { 1276 case PCIBAR_IO: 1277 /* IO BARs are emulated */ 1278 break; 1279 case PCIBAR_ROM: 1280 passthru_addr_rom(pi, baridx, enabled); 1281 break; 1282 case PCIBAR_MEM32: 1283 case PCIBAR_MEM64: 1284 if (baridx == pci_msix_table_bar(pi)) 1285 passthru_msix_addr(pi, baridx, enabled, address); 1286 else 1287 passthru_mmio_addr(pi, baridx, enabled, address); 1288 break; 1289 default: 1290 errx(4, "%s: invalid BAR type %d", __func__, 1291 pi->pi_bar[baridx].type); 1292 } 1293 } 1294 1295 static const struct pci_devemu passthru = { 1296 .pe_emu = "passthru", 1297 .pe_init = passthru_init, 1298 .pe_legacy_config = passthru_legacy_config, 1299 .pe_cfgwrite = passthru_cfgwrite, 1300 .pe_cfgread = passthru_cfgread, 1301 .pe_barwrite = passthru_write, 1302 .pe_barread = passthru_read, 1303 .pe_baraddr = passthru_addr, 1304 }; 1305 PCI_EMUL_SET(passthru); 1306