1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2011 NetApp, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 #include <sys/param.h> 33 #ifndef WITHOUT_CAPSICUM 34 #include <sys/capsicum.h> 35 #endif 36 #include <sys/types.h> 37 #include <sys/mman.h> 38 #include <sys/pciio.h> 39 #include <sys/ioctl.h> 40 #include <sys/stat.h> 41 42 #include <dev/io/iodev.h> 43 #include <dev/pci/pcireg.h> 44 45 #include <vm/vm.h> 46 47 #include <machine/iodev.h> 48 #include <machine/vm.h> 49 50 #ifndef WITHOUT_CAPSICUM 51 #include <capsicum_helpers.h> 52 #endif 53 #include <ctype.h> 54 #include <stdio.h> 55 #include <stdlib.h> 56 #include <string.h> 57 #include <err.h> 58 #include <errno.h> 59 #include <fcntl.h> 60 #include <sysexits.h> 61 #include <unistd.h> 62 63 #include <machine/vmm.h> 64 65 #include "debug.h" 66 #include "mem.h" 67 #include "pci_passthru.h" 68 69 #ifndef _PATH_DEVPCI 70 #define _PATH_DEVPCI "/dev/pci" 71 #endif 72 73 #define LEGACY_SUPPORT 1 74 75 #define MSIX_TABLE_COUNT(ctrl) (((ctrl) & PCIM_MSIXCTRL_TABLE_SIZE) + 1) 76 #define MSIX_CAPLEN 12 77 78 #define PASSTHRU_MMIO_MAX 2 79 80 static int pcifd = -1; 81 82 SET_DECLARE(passthru_dev_set, struct passthru_dev); 83 84 struct passthru_softc { 85 struct pci_devinst *psc_pi; 86 /* ROM is handled like a BAR */ 87 struct pcibar psc_bar[PCI_BARMAX_WITH_ROM + 1]; 88 struct { 89 int capoff; 90 int msgctrl; 91 int emulated; 92 } psc_msi; 93 struct { 94 int capoff; 95 } psc_msix; 96 struct pcisel psc_sel; 97 98 struct passthru_mmio_mapping psc_mmio_map[PASSTHRU_MMIO_MAX]; 99 cfgread_handler psc_pcir_rhandler[PCI_REGMAX + 1]; 100 cfgwrite_handler psc_pcir_whandler[PCI_REGMAX + 1]; 101 }; 102 103 static int 104 msi_caplen(int msgctrl) 105 { 106 int len; 107 108 len = 10; /* minimum length of msi capability */ 109 110 if (msgctrl & PCIM_MSICTRL_64BIT) 111 len += 4; 112 113 #if 0 114 /* 115 * Ignore the 'mask' and 'pending' bits in the MSI capability. 116 * We'll let the guest manipulate them directly. 117 */ 118 if (msgctrl & PCIM_MSICTRL_VECTOR) 119 len += 10; 120 #endif 121 122 return (len); 123 } 124 125 static int 126 pcifd_init(void) 127 { 128 pcifd = open(_PATH_DEVPCI, O_RDWR, 0); 129 if (pcifd < 0) { 130 warn("failed to open %s", _PATH_DEVPCI); 131 return (1); 132 } 133 134 #ifndef WITHOUT_CAPSICUM 135 cap_rights_t pcifd_rights; 136 cap_rights_init(&pcifd_rights, CAP_IOCTL, CAP_READ, CAP_WRITE); 137 if (caph_rights_limit(pcifd, &pcifd_rights) == -1) 138 errx(EX_OSERR, "Unable to apply rights for sandbox"); 139 140 const cap_ioctl_t pcifd_ioctls[] = { PCIOCREAD, PCIOCWRITE, PCIOCGETBAR, 141 PCIOCBARIO, PCIOCBARMMAP, PCIOCGETCONF }; 142 if (caph_ioctls_limit(pcifd, pcifd_ioctls, nitems(pcifd_ioctls)) == -1) 143 errx(EX_OSERR, "Unable to apply rights for sandbox"); 144 #endif 145 146 return (0); 147 } 148 149 uint32_t 150 read_config(const struct pcisel *sel, long reg, int width) 151 { 152 struct pci_io pi; 153 154 if (pcifd < 0 && pcifd_init()) { 155 return (0); 156 } 157 158 bzero(&pi, sizeof(pi)); 159 pi.pi_sel = *sel; 160 pi.pi_reg = reg; 161 pi.pi_width = width; 162 163 if (ioctl(pcifd, PCIOCREAD, &pi) < 0) 164 return (0); /* XXX */ 165 else 166 return (pi.pi_data); 167 } 168 169 void 170 write_config(const struct pcisel *sel, long reg, int width, uint32_t data) 171 { 172 struct pci_io pi; 173 174 if (pcifd < 0 && pcifd_init()) { 175 return; 176 } 177 178 bzero(&pi, sizeof(pi)); 179 pi.pi_sel = *sel; 180 pi.pi_reg = reg; 181 pi.pi_width = width; 182 pi.pi_data = data; 183 184 (void)ioctl(pcifd, PCIOCWRITE, &pi); /* XXX */ 185 } 186 187 #ifdef LEGACY_SUPPORT 188 static int 189 passthru_add_msicap(struct pci_devinst *pi, int msgnum, int nextptr) 190 { 191 int capoff; 192 struct msicap msicap; 193 u_char *capdata; 194 195 pci_populate_msicap(&msicap, msgnum, nextptr); 196 197 /* 198 * XXX 199 * Copy the msi capability structure in the last 16 bytes of the 200 * config space. This is wrong because it could shadow something 201 * useful to the device. 202 */ 203 capoff = 256 - roundup(sizeof(msicap), 4); 204 capdata = (u_char *)&msicap; 205 for (size_t i = 0; i < sizeof(msicap); i++) 206 pci_set_cfgdata8(pi, capoff + i, capdata[i]); 207 208 return (capoff); 209 } 210 #endif /* LEGACY_SUPPORT */ 211 212 static int 213 cfginitmsi(struct passthru_softc *sc) 214 { 215 int i, ptr, capptr, cap, sts, caplen, table_size; 216 uint32_t u32; 217 struct pcisel sel; 218 struct pci_devinst *pi; 219 struct msixcap msixcap; 220 char *msixcap_ptr; 221 222 pi = sc->psc_pi; 223 sel = sc->psc_sel; 224 225 /* 226 * Parse the capabilities and cache the location of the MSI 227 * and MSI-X capabilities. 228 */ 229 sts = read_config(&sel, PCIR_STATUS, 2); 230 if (sts & PCIM_STATUS_CAPPRESENT) { 231 ptr = read_config(&sel, PCIR_CAP_PTR, 1); 232 while (ptr != 0 && ptr != 0xff) { 233 cap = read_config(&sel, ptr + PCICAP_ID, 1); 234 if (cap == PCIY_MSI) { 235 /* 236 * Copy the MSI capability into the config 237 * space of the emulated pci device 238 */ 239 sc->psc_msi.capoff = ptr; 240 sc->psc_msi.msgctrl = read_config(&sel, 241 ptr + 2, 2); 242 sc->psc_msi.emulated = 0; 243 caplen = msi_caplen(sc->psc_msi.msgctrl); 244 capptr = ptr; 245 while (caplen > 0) { 246 u32 = read_config(&sel, capptr, 4); 247 pci_set_cfgdata32(pi, capptr, u32); 248 caplen -= 4; 249 capptr += 4; 250 } 251 } else if (cap == PCIY_MSIX) { 252 /* 253 * Copy the MSI-X capability 254 */ 255 sc->psc_msix.capoff = ptr; 256 caplen = 12; 257 msixcap_ptr = (char *)&msixcap; 258 capptr = ptr; 259 while (caplen > 0) { 260 u32 = read_config(&sel, capptr, 4); 261 memcpy(msixcap_ptr, &u32, 4); 262 pci_set_cfgdata32(pi, capptr, u32); 263 caplen -= 4; 264 capptr += 4; 265 msixcap_ptr += 4; 266 } 267 } 268 ptr = read_config(&sel, ptr + PCICAP_NEXTPTR, 1); 269 } 270 } 271 272 if (sc->psc_msix.capoff != 0) { 273 pi->pi_msix.pba_bar = 274 msixcap.pba_info & PCIM_MSIX_BIR_MASK; 275 pi->pi_msix.pba_offset = 276 msixcap.pba_info & ~PCIM_MSIX_BIR_MASK; 277 pi->pi_msix.table_bar = 278 msixcap.table_info & PCIM_MSIX_BIR_MASK; 279 pi->pi_msix.table_offset = 280 msixcap.table_info & ~PCIM_MSIX_BIR_MASK; 281 pi->pi_msix.table_count = MSIX_TABLE_COUNT(msixcap.msgctrl); 282 pi->pi_msix.pba_size = PBA_SIZE(pi->pi_msix.table_count); 283 284 /* Allocate the emulated MSI-X table array */ 285 table_size = pi->pi_msix.table_count * MSIX_TABLE_ENTRY_SIZE; 286 pi->pi_msix.table = calloc(1, table_size); 287 288 /* Mask all table entries */ 289 for (i = 0; i < pi->pi_msix.table_count; i++) { 290 pi->pi_msix.table[i].vector_control |= 291 PCIM_MSIX_VCTRL_MASK; 292 } 293 } 294 295 #ifdef LEGACY_SUPPORT 296 /* 297 * If the passthrough device does not support MSI then craft a 298 * MSI capability for it. We link the new MSI capability at the 299 * head of the list of capabilities. 300 */ 301 if ((sts & PCIM_STATUS_CAPPRESENT) != 0 && sc->psc_msi.capoff == 0) { 302 int origptr, msiptr; 303 origptr = read_config(&sel, PCIR_CAP_PTR, 1); 304 msiptr = passthru_add_msicap(pi, 1, origptr); 305 sc->psc_msi.capoff = msiptr; 306 sc->psc_msi.msgctrl = pci_get_cfgdata16(pi, msiptr + 2); 307 sc->psc_msi.emulated = 1; 308 pci_set_cfgdata8(pi, PCIR_CAP_PTR, msiptr); 309 } 310 #endif 311 312 /* Make sure one of the capabilities is present */ 313 if (sc->psc_msi.capoff == 0 && sc->psc_msix.capoff == 0) 314 return (-1); 315 else 316 return (0); 317 } 318 319 static uint64_t 320 msix_table_read(struct passthru_softc *sc, uint64_t offset, int size) 321 { 322 struct pci_devinst *pi; 323 struct msix_table_entry *entry; 324 uint8_t *src8; 325 uint16_t *src16; 326 uint32_t *src32; 327 uint64_t *src64; 328 uint64_t data; 329 size_t entry_offset; 330 uint32_t table_offset; 331 int index, table_count; 332 333 pi = sc->psc_pi; 334 335 table_offset = pi->pi_msix.table_offset; 336 table_count = pi->pi_msix.table_count; 337 if (offset < table_offset || 338 offset >= table_offset + table_count * MSIX_TABLE_ENTRY_SIZE) { 339 switch (size) { 340 case 1: 341 src8 = (uint8_t *)(pi->pi_msix.mapped_addr + offset); 342 data = *src8; 343 break; 344 case 2: 345 src16 = (uint16_t *)(pi->pi_msix.mapped_addr + offset); 346 data = *src16; 347 break; 348 case 4: 349 src32 = (uint32_t *)(pi->pi_msix.mapped_addr + offset); 350 data = *src32; 351 break; 352 case 8: 353 src64 = (uint64_t *)(pi->pi_msix.mapped_addr + offset); 354 data = *src64; 355 break; 356 default: 357 return (-1); 358 } 359 return (data); 360 } 361 362 offset -= table_offset; 363 index = offset / MSIX_TABLE_ENTRY_SIZE; 364 assert(index < table_count); 365 366 entry = &pi->pi_msix.table[index]; 367 entry_offset = offset % MSIX_TABLE_ENTRY_SIZE; 368 369 switch (size) { 370 case 1: 371 src8 = (uint8_t *)((uint8_t *)entry + entry_offset); 372 data = *src8; 373 break; 374 case 2: 375 src16 = (uint16_t *)((uint8_t *)entry + entry_offset); 376 data = *src16; 377 break; 378 case 4: 379 src32 = (uint32_t *)((uint8_t *)entry + entry_offset); 380 data = *src32; 381 break; 382 case 8: 383 src64 = (uint64_t *)((uint8_t *)entry + entry_offset); 384 data = *src64; 385 break; 386 default: 387 return (-1); 388 } 389 390 return (data); 391 } 392 393 static void 394 msix_table_write(struct passthru_softc *sc, uint64_t offset, int size, 395 uint64_t data) 396 { 397 struct pci_devinst *pi; 398 struct msix_table_entry *entry; 399 uint8_t *dest8; 400 uint16_t *dest16; 401 uint32_t *dest32; 402 uint64_t *dest64; 403 size_t entry_offset; 404 uint32_t table_offset, vector_control; 405 int index, table_count; 406 407 pi = sc->psc_pi; 408 409 table_offset = pi->pi_msix.table_offset; 410 table_count = pi->pi_msix.table_count; 411 if (offset < table_offset || 412 offset >= table_offset + table_count * MSIX_TABLE_ENTRY_SIZE) { 413 switch (size) { 414 case 1: 415 dest8 = (uint8_t *)(pi->pi_msix.mapped_addr + offset); 416 *dest8 = data; 417 break; 418 case 2: 419 dest16 = (uint16_t *)(pi->pi_msix.mapped_addr + offset); 420 *dest16 = data; 421 break; 422 case 4: 423 dest32 = (uint32_t *)(pi->pi_msix.mapped_addr + offset); 424 *dest32 = data; 425 break; 426 case 8: 427 dest64 = (uint64_t *)(pi->pi_msix.mapped_addr + offset); 428 *dest64 = data; 429 break; 430 } 431 return; 432 } 433 434 offset -= table_offset; 435 index = offset / MSIX_TABLE_ENTRY_SIZE; 436 assert(index < table_count); 437 438 entry = &pi->pi_msix.table[index]; 439 entry_offset = offset % MSIX_TABLE_ENTRY_SIZE; 440 441 /* Only 4 byte naturally-aligned writes are supported */ 442 assert(size == 4); 443 assert(entry_offset % 4 == 0); 444 445 vector_control = entry->vector_control; 446 dest32 = (uint32_t *)((uint8_t *)entry + entry_offset); 447 *dest32 = data; 448 /* If MSI-X hasn't been enabled, do nothing */ 449 if (pi->pi_msix.enabled) { 450 /* If the entry is masked, don't set it up */ 451 if ((entry->vector_control & PCIM_MSIX_VCTRL_MASK) == 0 || 452 (vector_control & PCIM_MSIX_VCTRL_MASK) == 0) { 453 (void)vm_setup_pptdev_msix(sc->psc_pi->pi_vmctx, 454 sc->psc_sel.pc_bus, sc->psc_sel.pc_dev, 455 sc->psc_sel.pc_func, index, entry->addr, 456 entry->msg_data, entry->vector_control); 457 } 458 } 459 } 460 461 static int 462 init_msix_table(struct passthru_softc *sc) 463 { 464 struct pci_devinst *pi = sc->psc_pi; 465 struct pci_bar_mmap pbm; 466 int b, s, f; 467 uint32_t table_size, table_offset; 468 469 assert(pci_msix_table_bar(pi) >= 0 && pci_msix_pba_bar(pi) >= 0); 470 471 b = sc->psc_sel.pc_bus; 472 s = sc->psc_sel.pc_dev; 473 f = sc->psc_sel.pc_func; 474 475 /* 476 * Map the region of the BAR containing the MSI-X table. This is 477 * necessary for two reasons: 478 * 1. The PBA may reside in the first or last page containing the MSI-X 479 * table. 480 * 2. While PCI devices are not supposed to use the page(s) containing 481 * the MSI-X table for other purposes, some do in practice. 482 */ 483 memset(&pbm, 0, sizeof(pbm)); 484 pbm.pbm_sel = sc->psc_sel; 485 pbm.pbm_flags = PCIIO_BAR_MMAP_RW; 486 pbm.pbm_reg = PCIR_BAR(pi->pi_msix.table_bar); 487 pbm.pbm_memattr = VM_MEMATTR_DEVICE; 488 489 if (ioctl(pcifd, PCIOCBARMMAP, &pbm) != 0) { 490 warn("Failed to map MSI-X table BAR on %d/%d/%d", b, s, f); 491 return (-1); 492 } 493 assert(pbm.pbm_bar_off == 0); 494 pi->pi_msix.mapped_addr = (uint8_t *)(uintptr_t)pbm.pbm_map_base; 495 pi->pi_msix.mapped_size = pbm.pbm_map_length; 496 497 table_offset = rounddown2(pi->pi_msix.table_offset, 4096); 498 499 table_size = pi->pi_msix.table_offset - table_offset; 500 table_size += pi->pi_msix.table_count * MSIX_TABLE_ENTRY_SIZE; 501 table_size = roundup2(table_size, 4096); 502 503 /* 504 * Unmap any pages not containing the table, we do not need to emulate 505 * accesses to them. Avoid releasing address space to help ensure that 506 * a buggy out-of-bounds access causes a crash. 507 */ 508 if (table_offset != 0) 509 if (mprotect(pi->pi_msix.mapped_addr, table_offset, 510 PROT_NONE) != 0) 511 warn("Failed to unmap MSI-X table BAR region"); 512 if (table_offset + table_size != pi->pi_msix.mapped_size) 513 if (mprotect( 514 pi->pi_msix.mapped_addr + table_offset + table_size, 515 pi->pi_msix.mapped_size - (table_offset + table_size), 516 PROT_NONE) != 0) 517 warn("Failed to unmap MSI-X table BAR region"); 518 519 return (0); 520 } 521 522 static int 523 cfginitbar(struct passthru_softc *sc) 524 { 525 int i, error; 526 struct pci_devinst *pi; 527 struct pci_bar_io bar; 528 enum pcibar_type bartype; 529 uint64_t base, size; 530 531 pi = sc->psc_pi; 532 533 /* 534 * Initialize BAR registers 535 */ 536 for (i = 0; i <= PCI_BARMAX; i++) { 537 bzero(&bar, sizeof(bar)); 538 bar.pbi_sel = sc->psc_sel; 539 bar.pbi_reg = PCIR_BAR(i); 540 541 if (ioctl(pcifd, PCIOCGETBAR, &bar) < 0) 542 continue; 543 544 if (PCI_BAR_IO(bar.pbi_base)) { 545 bartype = PCIBAR_IO; 546 base = bar.pbi_base & PCIM_BAR_IO_BASE; 547 } else { 548 switch (bar.pbi_base & PCIM_BAR_MEM_TYPE) { 549 case PCIM_BAR_MEM_64: 550 bartype = PCIBAR_MEM64; 551 break; 552 default: 553 bartype = PCIBAR_MEM32; 554 break; 555 } 556 base = bar.pbi_base & PCIM_BAR_MEM_BASE; 557 } 558 size = bar.pbi_length; 559 560 if (bartype != PCIBAR_IO) { 561 if (((base | size) & PAGE_MASK) != 0) { 562 warnx("passthru device %d/%d/%d BAR %d: " 563 "base %#lx or size %#lx not page aligned\n", 564 sc->psc_sel.pc_bus, sc->psc_sel.pc_dev, 565 sc->psc_sel.pc_func, i, base, size); 566 return (-1); 567 } 568 } 569 570 /* Cache information about the "real" BAR */ 571 sc->psc_bar[i].type = bartype; 572 sc->psc_bar[i].size = size; 573 sc->psc_bar[i].addr = base; 574 sc->psc_bar[i].lobits = 0; 575 576 /* Allocate the BAR in the guest I/O or MMIO space */ 577 error = pci_emul_alloc_bar(pi, i, bartype, size); 578 if (error) 579 return (-1); 580 581 /* Use same lobits as physical bar */ 582 uint8_t lobits = read_config(&sc->psc_sel, PCIR_BAR(i), 0x01); 583 if (bartype == PCIBAR_MEM32 || bartype == PCIBAR_MEM64) { 584 lobits &= ~PCIM_BAR_MEM_BASE; 585 } else { 586 lobits &= ~PCIM_BAR_IO_BASE; 587 } 588 sc->psc_bar[i].lobits = lobits; 589 pi->pi_bar[i].lobits = lobits; 590 591 /* 592 * 64-bit BAR takes up two slots so skip the next one. 593 */ 594 if (bartype == PCIBAR_MEM64) { 595 i++; 596 assert(i <= PCI_BARMAX); 597 sc->psc_bar[i].type = PCIBAR_MEMHI64; 598 } 599 } 600 return (0); 601 } 602 603 static int 604 cfginit(struct pci_devinst *pi, int bus, int slot, int func) 605 { 606 int error; 607 struct passthru_softc *sc; 608 uint8_t intline, intpin; 609 610 error = 1; 611 sc = pi->pi_arg; 612 613 bzero(&sc->psc_sel, sizeof(struct pcisel)); 614 sc->psc_sel.pc_bus = bus; 615 sc->psc_sel.pc_dev = slot; 616 sc->psc_sel.pc_func = func; 617 618 /* 619 * Copy physical PCI header to virtual config space. INTLINE and INTPIN 620 * shouldn't be aligned with their physical value and they are already set by 621 * pci_emul_init(). 622 */ 623 intline = pci_get_cfgdata8(pi, PCIR_INTLINE); 624 intpin = pci_get_cfgdata8(pi, PCIR_INTPIN); 625 for (int i = 0; i <= PCIR_MAXLAT; i += 4) { 626 pci_set_cfgdata32(pi, i, read_config(&sc->psc_sel, i, 4)); 627 } 628 pci_set_cfgdata8(pi, PCIR_INTLINE, intline); 629 pci_set_cfgdata8(pi, PCIR_INTPIN, intpin); 630 631 if (cfginitmsi(sc) != 0) { 632 warnx("failed to initialize MSI for PCI %d/%d/%d", 633 bus, slot, func); 634 goto done; 635 } 636 637 if (cfginitbar(sc) != 0) { 638 warnx("failed to initialize BARs for PCI %d/%d/%d", 639 bus, slot, func); 640 goto done; 641 } 642 643 write_config(&sc->psc_sel, PCIR_COMMAND, 2, 644 pci_get_cfgdata16(pi, PCIR_COMMAND)); 645 646 /* 647 * We need to do this after PCIR_COMMAND got possibly updated, e.g., 648 * a BAR was enabled, as otherwise the PCIOCBARMMAP might fail on us. 649 */ 650 if (pci_msix_table_bar(pi) >= 0) { 651 error = init_msix_table(sc); 652 if (error != 0) { 653 warnx( 654 "failed to initialize MSI-X table for PCI %d/%d/%d: %d", 655 bus, slot, func, error); 656 goto done; 657 } 658 } 659 660 error = 0; /* success */ 661 done: 662 return (error); 663 } 664 665 struct passthru_mmio_mapping * 666 passthru_get_mmio(struct passthru_softc *sc, int num) 667 { 668 assert(sc != NULL); 669 assert(num < PASSTHRU_MMIO_MAX); 670 671 return (&sc->psc_mmio_map[num]); 672 } 673 674 struct pcisel * 675 passthru_get_sel(struct passthru_softc *sc) 676 { 677 assert(sc != NULL); 678 679 return (&sc->psc_sel); 680 } 681 682 int 683 set_pcir_handler(struct passthru_softc *sc, int reg, int len, 684 cfgread_handler rhandler, cfgwrite_handler whandler) 685 { 686 if (reg > PCI_REGMAX || reg + len > PCI_REGMAX + 1) 687 return (-1); 688 689 for (int i = reg; i < reg + len; ++i) { 690 assert(sc->psc_pcir_rhandler[i] == NULL || rhandler == NULL); 691 assert(sc->psc_pcir_whandler[i] == NULL || whandler == NULL); 692 sc->psc_pcir_rhandler[i] = rhandler; 693 sc->psc_pcir_whandler[i] = whandler; 694 } 695 696 return (0); 697 } 698 699 static int 700 passthru_legacy_config(nvlist_t *nvl, const char *opts) 701 { 702 const char *cp; 703 char *tofree; 704 char value[16]; 705 int bus, slot, func; 706 707 if (opts == NULL) 708 return (0); 709 710 cp = strchr(opts, ','); 711 712 if (strncmp(opts, "ppt", strlen("ppt")) == 0) { 713 tofree = strndup(opts, cp - opts); 714 set_config_value_node(nvl, "pptdev", tofree); 715 free(tofree); 716 } else if (sscanf(opts, "pci0:%d:%d:%d", &bus, &slot, &func) == 3 || 717 sscanf(opts, "pci%d:%d:%d", &bus, &slot, &func) == 3 || 718 sscanf(opts, "%d/%d/%d", &bus, &slot, &func) == 3) { 719 snprintf(value, sizeof(value), "%d", bus); 720 set_config_value_node(nvl, "bus", value); 721 snprintf(value, sizeof(value), "%d", slot); 722 set_config_value_node(nvl, "slot", value); 723 snprintf(value, sizeof(value), "%d", func); 724 set_config_value_node(nvl, "func", value); 725 } else { 726 EPRINTLN("passthru: invalid options \"%s\"", opts); 727 return (-1); 728 } 729 730 if (cp == NULL) { 731 return (0); 732 } 733 734 return (pci_parse_legacy_config(nvl, cp + 1)); 735 } 736 737 static int 738 passthru_init_rom(struct passthru_softc *const sc, const char *const romfile) 739 { 740 if (romfile == NULL) { 741 return (0); 742 } 743 744 const int fd = open(romfile, O_RDONLY); 745 if (fd < 0) { 746 warnx("%s: can't open romfile \"%s\"", __func__, romfile); 747 return (-1); 748 } 749 750 struct stat sbuf; 751 if (fstat(fd, &sbuf) < 0) { 752 warnx("%s: can't fstat romfile \"%s\"", __func__, romfile); 753 close(fd); 754 return (-1); 755 } 756 const uint64_t rom_size = sbuf.st_size; 757 758 void *const rom_data = mmap(NULL, rom_size, PROT_READ, MAP_SHARED, fd, 759 0); 760 if (rom_data == MAP_FAILED) { 761 warnx("%s: unable to mmap romfile \"%s\" (%d)", __func__, 762 romfile, errno); 763 close(fd); 764 return (-1); 765 } 766 767 void *rom_addr; 768 int error = pci_emul_alloc_rom(sc->psc_pi, rom_size, &rom_addr); 769 if (error) { 770 warnx("%s: failed to alloc rom segment", __func__); 771 munmap(rom_data, rom_size); 772 close(fd); 773 return (error); 774 } 775 memcpy(rom_addr, rom_data, rom_size); 776 777 sc->psc_bar[PCI_ROM_IDX].type = PCIBAR_ROM; 778 sc->psc_bar[PCI_ROM_IDX].addr = (uint64_t)rom_addr; 779 sc->psc_bar[PCI_ROM_IDX].size = rom_size; 780 781 munmap(rom_data, rom_size); 782 close(fd); 783 784 return (0); 785 } 786 787 static bool 788 passthru_lookup_pptdev(const char *name, int *bus, int *slot, int *func) 789 { 790 struct pci_conf_io pc; 791 struct pci_conf conf[1]; 792 struct pci_match_conf patterns[1]; 793 char *cp; 794 795 bzero(&pc, sizeof(struct pci_conf_io)); 796 pc.match_buf_len = sizeof(conf); 797 pc.matches = conf; 798 799 bzero(&patterns, sizeof(patterns)); 800 801 /* 802 * The pattern structure requires the unit to be split out from 803 * the driver name. Walk backwards from the end of the name to 804 * find the start of the unit. 805 */ 806 cp = strchr(name, '\0'); 807 assert(cp != NULL); 808 while (cp != name && isdigit(cp[-1])) 809 cp--; 810 if (cp == name || !isdigit(*cp)) { 811 EPRINTLN("Invalid passthru device name %s", name); 812 return (false); 813 } 814 if ((size_t)(cp - name) + 1 > sizeof(patterns[0].pd_name)) { 815 EPRINTLN("Passthru device name %s is too long", name); 816 return (false); 817 } 818 memcpy(patterns[0].pd_name, name, cp - name); 819 patterns[0].pd_unit = strtol(cp, &cp, 10); 820 if (*cp != '\0') { 821 EPRINTLN("Invalid passthru device name %s", name); 822 return (false); 823 } 824 patterns[0].flags = PCI_GETCONF_MATCH_NAME | PCI_GETCONF_MATCH_UNIT; 825 pc.num_patterns = 1; 826 pc.pat_buf_len = sizeof(patterns); 827 pc.patterns = patterns; 828 829 if (ioctl(pcifd, PCIOCGETCONF, &pc) == -1) { 830 EPRINTLN("ioctl(PCIOCGETCONF): %s", strerror(errno)); 831 return (false); 832 } 833 if (pc.status != PCI_GETCONF_LAST_DEVICE && 834 pc.status != PCI_GETCONF_MORE_DEVS) { 835 EPRINTLN("error returned from PCIOCGETCONF ioctl"); 836 return (false); 837 } 838 if (pc.num_matches == 0) { 839 EPRINTLN("Passthru device %s not found", name); 840 return (false); 841 } 842 843 if (conf[0].pc_sel.pc_domain != 0) { 844 EPRINTLN("Passthru device %s on unsupported domain", name); 845 return (false); 846 } 847 *bus = conf[0].pc_sel.pc_bus; 848 *slot = conf[0].pc_sel.pc_dev; 849 *func = conf[0].pc_sel.pc_func; 850 return (true); 851 } 852 853 static int 854 passthru_init(struct pci_devinst *pi, nvlist_t *nvl) 855 { 856 int bus, slot, func, error, memflags; 857 struct passthru_softc *sc; 858 struct passthru_dev **devpp; 859 struct passthru_dev *devp, *dev = NULL; 860 const char *value; 861 862 sc = NULL; 863 error = 1; 864 865 memflags = vm_get_memflags(pi->pi_vmctx); 866 if (!(memflags & VM_MEM_F_WIRED)) { 867 warnx("passthru requires guest memory to be wired"); 868 return (error); 869 } 870 871 if (pcifd < 0 && pcifd_init()) { 872 return (error); 873 } 874 875 #define GET_INT_CONFIG(var, name) do { \ 876 value = get_config_value_node(nvl, name); \ 877 if (value == NULL) { \ 878 EPRINTLN("passthru: missing required %s setting", name); \ 879 return (error); \ 880 } \ 881 var = atoi(value); \ 882 } while (0) 883 884 value = get_config_value_node(nvl, "pptdev"); 885 if (value != NULL) { 886 if (!passthru_lookup_pptdev(value, &bus, &slot, &func)) 887 return (error); 888 } else { 889 GET_INT_CONFIG(bus, "bus"); 890 GET_INT_CONFIG(slot, "slot"); 891 GET_INT_CONFIG(func, "func"); 892 } 893 894 if (vm_assign_pptdev(pi->pi_vmctx, bus, slot, func) != 0) { 895 warnx("PCI device at %d/%d/%d is not using the ppt(4) driver", 896 bus, slot, func); 897 goto done; 898 } 899 900 sc = calloc(1, sizeof(struct passthru_softc)); 901 902 pi->pi_arg = sc; 903 sc->psc_pi = pi; 904 905 /* initialize config space */ 906 if ((error = cfginit(pi, bus, slot, func)) != 0) 907 goto done; 908 909 /* initialize ROM */ 910 if ((error = passthru_init_rom(sc, 911 get_config_value_node(nvl, "rom"))) != 0) 912 goto done; 913 914 /* Emulate most PCI header register. */ 915 if ((error = set_pcir_handler(sc, 0, PCIR_MAXLAT + 1, 916 passthru_cfgread_emulate, passthru_cfgwrite_emulate)) != 0) 917 goto done; 918 919 /* Allow access to the physical command and status register. */ 920 if ((error = set_pcir_handler(sc, PCIR_COMMAND, 0x04, NULL, NULL)) != 0) 921 goto done; 922 923 SET_FOREACH(devpp, passthru_dev_set) { 924 devp = *devpp; 925 assert(devp->probe != NULL); 926 if (devp->probe(pi) == 0) { 927 dev = devp; 928 break; 929 } 930 } 931 932 if (dev != NULL) { 933 error = dev->init(pi, nvl); 934 if (error != 0) 935 goto done; 936 } 937 938 error = 0; /* success */ 939 done: 940 if (error) { 941 if (dev != NULL) 942 dev->deinit(pi); 943 free(sc); 944 vm_unassign_pptdev(pi->pi_vmctx, bus, slot, func); 945 } 946 return (error); 947 } 948 949 static int 950 msicap_access(struct passthru_softc *sc, int coff) 951 { 952 int caplen; 953 954 if (sc->psc_msi.capoff == 0) 955 return (0); 956 957 caplen = msi_caplen(sc->psc_msi.msgctrl); 958 959 if (coff >= sc->psc_msi.capoff && coff < sc->psc_msi.capoff + caplen) 960 return (1); 961 else 962 return (0); 963 } 964 965 static int 966 msixcap_access(struct passthru_softc *sc, int coff) 967 { 968 if (sc->psc_msix.capoff == 0) 969 return (0); 970 971 return (coff >= sc->psc_msix.capoff && 972 coff < sc->psc_msix.capoff + MSIX_CAPLEN); 973 } 974 975 static int 976 passthru_cfgread_default(struct passthru_softc *sc, 977 struct pci_devinst *pi __unused, int coff, int bytes, uint32_t *rv) 978 { 979 /* 980 * MSI capability is emulated. 981 */ 982 if (msicap_access(sc, coff) || msixcap_access(sc, coff)) 983 return (-1); 984 985 /* 986 * Emulate the command register. If a single read reads both the 987 * command and status registers, read the status register from the 988 * device's config space. 989 */ 990 if (coff == PCIR_COMMAND) { 991 if (bytes <= 2) 992 return (-1); 993 *rv = read_config(&sc->psc_sel, PCIR_STATUS, 2) << 16 | 994 pci_get_cfgdata16(pi, PCIR_COMMAND); 995 return (0); 996 } 997 998 /* Everything else just read from the device's config space */ 999 *rv = read_config(&sc->psc_sel, coff, bytes); 1000 1001 return (0); 1002 } 1003 1004 int 1005 passthru_cfgread_emulate(struct passthru_softc *sc __unused, 1006 struct pci_devinst *pi __unused, int coff __unused, int bytes __unused, 1007 uint32_t *rv __unused) 1008 { 1009 return (-1); 1010 } 1011 1012 static int 1013 passthru_cfgread(struct pci_devinst *pi, int coff, int bytes, uint32_t *rv) 1014 { 1015 struct passthru_softc *sc; 1016 1017 sc = pi->pi_arg; 1018 1019 if (sc->psc_pcir_rhandler[coff] != NULL) 1020 return (sc->psc_pcir_rhandler[coff](sc, pi, coff, bytes, rv)); 1021 1022 return (passthru_cfgread_default(sc, pi, coff, bytes, rv)); 1023 } 1024 1025 static int 1026 passthru_cfgwrite_default(struct passthru_softc *sc, struct pci_devinst *pi, 1027 int coff, int bytes, uint32_t val) 1028 { 1029 int error, msix_table_entries, i; 1030 uint16_t cmd_old; 1031 1032 /* 1033 * MSI capability is emulated 1034 */ 1035 if (msicap_access(sc, coff)) { 1036 pci_emul_capwrite(pi, coff, bytes, val, sc->psc_msi.capoff, 1037 PCIY_MSI); 1038 error = vm_setup_pptdev_msi(pi->pi_vmctx, sc->psc_sel.pc_bus, 1039 sc->psc_sel.pc_dev, sc->psc_sel.pc_func, 1040 pi->pi_msi.addr, pi->pi_msi.msg_data, 1041 pi->pi_msi.maxmsgnum); 1042 if (error != 0) 1043 err(1, "vm_setup_pptdev_msi"); 1044 return (0); 1045 } 1046 1047 if (msixcap_access(sc, coff)) { 1048 pci_emul_capwrite(pi, coff, bytes, val, sc->psc_msix.capoff, 1049 PCIY_MSIX); 1050 if (pi->pi_msix.enabled) { 1051 msix_table_entries = pi->pi_msix.table_count; 1052 for (i = 0; i < msix_table_entries; i++) { 1053 error = vm_setup_pptdev_msix(pi->pi_vmctx, 1054 sc->psc_sel.pc_bus, sc->psc_sel.pc_dev, 1055 sc->psc_sel.pc_func, i, 1056 pi->pi_msix.table[i].addr, 1057 pi->pi_msix.table[i].msg_data, 1058 pi->pi_msix.table[i].vector_control); 1059 1060 if (error) 1061 err(1, "vm_setup_pptdev_msix"); 1062 } 1063 } else { 1064 error = vm_disable_pptdev_msix(pi->pi_vmctx, 1065 sc->psc_sel.pc_bus, sc->psc_sel.pc_dev, 1066 sc->psc_sel.pc_func); 1067 if (error) 1068 err(1, "vm_disable_pptdev_msix"); 1069 } 1070 return (0); 1071 } 1072 1073 #ifdef LEGACY_SUPPORT 1074 /* 1075 * If this device does not support MSI natively then we cannot let 1076 * the guest disable legacy interrupts from the device. It is the 1077 * legacy interrupt that is triggering the virtual MSI to the guest. 1078 */ 1079 if (sc->psc_msi.emulated && pci_msi_enabled(pi)) { 1080 if (coff == PCIR_COMMAND && bytes == 2) 1081 val &= ~PCIM_CMD_INTxDIS; 1082 } 1083 #endif 1084 1085 write_config(&sc->psc_sel, coff, bytes, val); 1086 if (coff == PCIR_COMMAND) { 1087 cmd_old = pci_get_cfgdata16(pi, PCIR_COMMAND); 1088 if (bytes == 1) 1089 pci_set_cfgdata8(pi, PCIR_COMMAND, val); 1090 else if (bytes == 2) 1091 pci_set_cfgdata16(pi, PCIR_COMMAND, val); 1092 pci_emul_cmd_changed(pi, cmd_old); 1093 } 1094 1095 return (0); 1096 } 1097 1098 int 1099 passthru_cfgwrite_emulate(struct passthru_softc *sc __unused, 1100 struct pci_devinst *pi __unused, int coff __unused, int bytes __unused, 1101 uint32_t val __unused) 1102 { 1103 return (-1); 1104 } 1105 1106 static int 1107 passthru_cfgwrite(struct pci_devinst *pi, int coff, int bytes, uint32_t val) 1108 { 1109 struct passthru_softc *sc; 1110 1111 sc = pi->pi_arg; 1112 1113 if (sc->psc_pcir_whandler[coff] != NULL) 1114 return (sc->psc_pcir_whandler[coff](sc, pi, coff, bytes, val)); 1115 1116 return (passthru_cfgwrite_default(sc, pi, coff, bytes, val)); 1117 } 1118 1119 static void 1120 passthru_write(struct pci_devinst *pi, int baridx, uint64_t offset, int size, 1121 uint64_t value) 1122 { 1123 struct passthru_softc *sc; 1124 struct pci_bar_ioreq pio; 1125 1126 sc = pi->pi_arg; 1127 1128 if (baridx == pci_msix_table_bar(pi)) { 1129 msix_table_write(sc, offset, size, value); 1130 } else { 1131 assert(pi->pi_bar[baridx].type == PCIBAR_IO); 1132 assert(size == 1 || size == 2 || size == 4); 1133 assert(offset <= UINT32_MAX && offset + size <= UINT32_MAX); 1134 1135 bzero(&pio, sizeof(pio)); 1136 pio.pbi_sel = sc->psc_sel; 1137 pio.pbi_op = PCIBARIO_WRITE; 1138 pio.pbi_bar = baridx; 1139 pio.pbi_offset = (uint32_t)offset; 1140 pio.pbi_width = size; 1141 pio.pbi_value = (uint32_t)value; 1142 1143 (void)ioctl(pcifd, PCIOCBARIO, &pio); 1144 } 1145 } 1146 1147 static uint64_t 1148 passthru_read(struct pci_devinst *pi, int baridx, uint64_t offset, int size) 1149 { 1150 struct passthru_softc *sc; 1151 struct pci_bar_ioreq pio; 1152 uint64_t val; 1153 1154 sc = pi->pi_arg; 1155 1156 if (baridx == pci_msix_table_bar(pi)) { 1157 val = msix_table_read(sc, offset, size); 1158 } else { 1159 assert(pi->pi_bar[baridx].type == PCIBAR_IO); 1160 assert(size == 1 || size == 2 || size == 4); 1161 assert(offset <= UINT32_MAX && offset + size <= UINT32_MAX); 1162 1163 bzero(&pio, sizeof(pio)); 1164 pio.pbi_sel = sc->psc_sel; 1165 pio.pbi_op = PCIBARIO_READ; 1166 pio.pbi_bar = baridx; 1167 pio.pbi_offset = (uint32_t)offset; 1168 pio.pbi_width = size; 1169 1170 (void)ioctl(pcifd, PCIOCBARIO, &pio); 1171 1172 val = pio.pbi_value; 1173 } 1174 1175 return (val); 1176 } 1177 1178 static void 1179 passthru_msix_addr(struct pci_devinst *pi, int baridx, int enabled, 1180 uint64_t address) 1181 { 1182 struct passthru_softc *sc; 1183 size_t remaining; 1184 uint32_t table_size, table_offset; 1185 1186 sc = pi->pi_arg; 1187 table_offset = rounddown2(pi->pi_msix.table_offset, 4096); 1188 if (table_offset > 0) { 1189 if (!enabled) { 1190 if (vm_unmap_pptdev_mmio(pi->pi_vmctx, 1191 sc->psc_sel.pc_bus, 1192 sc->psc_sel.pc_dev, 1193 sc->psc_sel.pc_func, address, 1194 table_offset) != 0) 1195 warnx("pci_passthru: unmap_pptdev_mmio failed"); 1196 } else { 1197 if (vm_map_pptdev_mmio(pi->pi_vmctx, sc->psc_sel.pc_bus, 1198 sc->psc_sel.pc_dev, 1199 sc->psc_sel.pc_func, address, 1200 table_offset, 1201 sc->psc_bar[baridx].addr) != 0) 1202 warnx("pci_passthru: map_pptdev_mmio failed"); 1203 } 1204 } 1205 table_size = pi->pi_msix.table_offset - table_offset; 1206 table_size += pi->pi_msix.table_count * MSIX_TABLE_ENTRY_SIZE; 1207 table_size = roundup2(table_size, 4096); 1208 remaining = pi->pi_bar[baridx].size - table_offset - table_size; 1209 if (remaining > 0) { 1210 address += table_offset + table_size; 1211 if (!enabled) { 1212 if (vm_unmap_pptdev_mmio(pi->pi_vmctx, 1213 sc->psc_sel.pc_bus, 1214 sc->psc_sel.pc_dev, 1215 sc->psc_sel.pc_func, address, 1216 remaining) != 0) 1217 warnx("pci_passthru: unmap_pptdev_mmio failed"); 1218 } else { 1219 if (vm_map_pptdev_mmio(pi->pi_vmctx, sc->psc_sel.pc_bus, 1220 sc->psc_sel.pc_dev, 1221 sc->psc_sel.pc_func, address, 1222 remaining, 1223 sc->psc_bar[baridx].addr + 1224 table_offset + table_size) != 0) 1225 warnx("pci_passthru: map_pptdev_mmio failed"); 1226 } 1227 } 1228 } 1229 1230 static void 1231 passthru_mmio_addr(struct pci_devinst *pi, int baridx, int enabled, 1232 uint64_t address) 1233 { 1234 struct passthru_softc *sc; 1235 1236 sc = pi->pi_arg; 1237 if (!enabled) { 1238 if (vm_unmap_pptdev_mmio(pi->pi_vmctx, sc->psc_sel.pc_bus, 1239 sc->psc_sel.pc_dev, 1240 sc->psc_sel.pc_func, address, 1241 sc->psc_bar[baridx].size) != 0) 1242 warnx("pci_passthru: unmap_pptdev_mmio failed"); 1243 } else { 1244 if (vm_map_pptdev_mmio(pi->pi_vmctx, sc->psc_sel.pc_bus, 1245 sc->psc_sel.pc_dev, 1246 sc->psc_sel.pc_func, address, 1247 sc->psc_bar[baridx].size, 1248 sc->psc_bar[baridx].addr) != 0) 1249 warnx("pci_passthru: map_pptdev_mmio failed"); 1250 } 1251 } 1252 1253 static void 1254 passthru_addr_rom(struct pci_devinst *const pi, const int idx, 1255 const int enabled) 1256 { 1257 const uint64_t addr = pi->pi_bar[idx].addr; 1258 const uint64_t size = pi->pi_bar[idx].size; 1259 1260 if (!enabled) { 1261 if (vm_munmap_memseg(pi->pi_vmctx, addr, size) != 0) { 1262 errx(4, "%s: munmap_memseg @ [%016lx - %016lx] failed", 1263 __func__, addr, addr + size); 1264 } 1265 1266 } else { 1267 if (vm_mmap_memseg(pi->pi_vmctx, addr, VM_PCIROM, 1268 pi->pi_romoffset, size, PROT_READ | PROT_EXEC) != 0) { 1269 errx(4, "%s: mmap_memseg @ [%016lx - %016lx] failed", 1270 __func__, addr, addr + size); 1271 } 1272 } 1273 } 1274 1275 static void 1276 passthru_addr(struct pci_devinst *pi, int baridx, int enabled, uint64_t address) 1277 { 1278 switch (pi->pi_bar[baridx].type) { 1279 case PCIBAR_IO: 1280 /* IO BARs are emulated */ 1281 break; 1282 case PCIBAR_ROM: 1283 passthru_addr_rom(pi, baridx, enabled); 1284 break; 1285 case PCIBAR_MEM32: 1286 case PCIBAR_MEM64: 1287 if (baridx == pci_msix_table_bar(pi)) 1288 passthru_msix_addr(pi, baridx, enabled, address); 1289 else 1290 passthru_mmio_addr(pi, baridx, enabled, address); 1291 break; 1292 default: 1293 errx(4, "%s: invalid BAR type %d", __func__, 1294 pi->pi_bar[baridx].type); 1295 } 1296 } 1297 1298 static const struct pci_devemu passthru = { 1299 .pe_emu = "passthru", 1300 .pe_init = passthru_init, 1301 .pe_legacy_config = passthru_legacy_config, 1302 .pe_cfgwrite = passthru_cfgwrite, 1303 .pe_cfgread = passthru_cfgread, 1304 .pe_barwrite = passthru_write, 1305 .pe_barread = passthru_read, 1306 .pe_baraddr = passthru_addr, 1307 }; 1308 PCI_EMUL_SET(passthru); 1309