1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2011 NetApp, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 #include <sys/param.h> 31 #ifndef WITHOUT_CAPSICUM 32 #include <sys/capsicum.h> 33 #endif 34 #include <sys/types.h> 35 #include <sys/mman.h> 36 #include <sys/pciio.h> 37 #include <sys/ioctl.h> 38 #include <sys/stat.h> 39 40 #include <dev/io/iodev.h> 41 #include <dev/pci/pcireg.h> 42 43 #include <vm/vm.h> 44 45 #include <machine/iodev.h> 46 #include <machine/vm.h> 47 48 #ifndef WITHOUT_CAPSICUM 49 #include <capsicum_helpers.h> 50 #endif 51 #include <ctype.h> 52 #include <stdio.h> 53 #include <stdlib.h> 54 #include <string.h> 55 #include <err.h> 56 #include <errno.h> 57 #include <fcntl.h> 58 #include <sysexits.h> 59 #include <unistd.h> 60 61 #include <machine/vmm.h> 62 63 #include "debug.h" 64 #include "mem.h" 65 #include "pci_passthru.h" 66 67 #ifndef _PATH_DEVPCI 68 #define _PATH_DEVPCI "/dev/pci" 69 #endif 70 71 #define LEGACY_SUPPORT 1 72 73 #define MSIX_TABLE_COUNT(ctrl) (((ctrl) & PCIM_MSIXCTRL_TABLE_SIZE) + 1) 74 #define MSIX_CAPLEN 12 75 76 #define PASSTHRU_MMIO_MAX 2 77 78 static int pcifd = -1; 79 80 SET_DECLARE(passthru_dev_set, struct passthru_dev); 81 82 struct passthru_softc { 83 struct pci_devinst *psc_pi; 84 /* ROM is handled like a BAR */ 85 struct pcibar psc_bar[PCI_BARMAX_WITH_ROM + 1]; 86 struct { 87 int capoff; 88 int msgctrl; 89 int emulated; 90 } psc_msi; 91 struct { 92 int capoff; 93 } psc_msix; 94 struct pcisel psc_sel; 95 96 struct passthru_mmio_mapping psc_mmio_map[PASSTHRU_MMIO_MAX]; 97 cfgread_handler psc_pcir_rhandler[PCI_REGMAX + 1]; 98 cfgwrite_handler psc_pcir_whandler[PCI_REGMAX + 1]; 99 }; 100 101 static int 102 msi_caplen(int msgctrl) 103 { 104 int len; 105 106 len = 10; /* minimum length of msi capability */ 107 108 if (msgctrl & PCIM_MSICTRL_64BIT) 109 len += 4; 110 111 #if 0 112 /* 113 * Ignore the 'mask' and 'pending' bits in the MSI capability. 114 * We'll let the guest manipulate them directly. 115 */ 116 if (msgctrl & PCIM_MSICTRL_VECTOR) 117 len += 10; 118 #endif 119 120 return (len); 121 } 122 123 static int 124 pcifd_init(void) 125 { 126 pcifd = open(_PATH_DEVPCI, O_RDWR, 0); 127 if (pcifd < 0) { 128 warn("failed to open %s", _PATH_DEVPCI); 129 return (1); 130 } 131 132 #ifndef WITHOUT_CAPSICUM 133 cap_rights_t pcifd_rights; 134 cap_rights_init(&pcifd_rights, CAP_IOCTL, CAP_READ, CAP_WRITE); 135 if (caph_rights_limit(pcifd, &pcifd_rights) == -1) 136 errx(EX_OSERR, "Unable to apply rights for sandbox"); 137 138 const cap_ioctl_t pcifd_ioctls[] = { PCIOCREAD, PCIOCWRITE, PCIOCGETBAR, 139 PCIOCBARIO, PCIOCBARMMAP, PCIOCGETCONF }; 140 if (caph_ioctls_limit(pcifd, pcifd_ioctls, nitems(pcifd_ioctls)) == -1) 141 errx(EX_OSERR, "Unable to apply rights for sandbox"); 142 #endif 143 144 return (0); 145 } 146 147 uint32_t 148 pci_host_read_config(const struct pcisel *sel, long reg, int width) 149 { 150 struct pci_io pi; 151 152 if (pcifd < 0 && pcifd_init()) { 153 return (0); 154 } 155 156 bzero(&pi, sizeof(pi)); 157 pi.pi_sel = *sel; 158 pi.pi_reg = reg; 159 pi.pi_width = width; 160 161 if (ioctl(pcifd, PCIOCREAD, &pi) < 0) 162 return (0); /* XXX */ 163 else 164 return (pi.pi_data); 165 } 166 167 void 168 pci_host_write_config(const struct pcisel *sel, long reg, int width, 169 uint32_t data) 170 { 171 struct pci_io pi; 172 173 if (pcifd < 0 && pcifd_init()) { 174 return; 175 } 176 177 bzero(&pi, sizeof(pi)); 178 pi.pi_sel = *sel; 179 pi.pi_reg = reg; 180 pi.pi_width = width; 181 pi.pi_data = data; 182 183 (void)ioctl(pcifd, PCIOCWRITE, &pi); /* XXX */ 184 } 185 186 #ifdef LEGACY_SUPPORT 187 static int 188 passthru_add_msicap(struct pci_devinst *pi, int msgnum, int nextptr) 189 { 190 int capoff; 191 struct msicap msicap; 192 u_char *capdata; 193 194 pci_populate_msicap(&msicap, msgnum, nextptr); 195 196 /* 197 * XXX 198 * Copy the msi capability structure in the last 16 bytes of the 199 * config space. This is wrong because it could shadow something 200 * useful to the device. 201 */ 202 capoff = 256 - roundup(sizeof(msicap), 4); 203 capdata = (u_char *)&msicap; 204 for (size_t i = 0; i < sizeof(msicap); i++) 205 pci_set_cfgdata8(pi, capoff + i, capdata[i]); 206 207 return (capoff); 208 } 209 #endif /* LEGACY_SUPPORT */ 210 211 static int 212 cfginitmsi(struct passthru_softc *sc) 213 { 214 int i, ptr, capptr, cap, sts, caplen, table_size; 215 uint32_t u32; 216 struct pcisel sel; 217 struct pci_devinst *pi; 218 struct msixcap msixcap; 219 char *msixcap_ptr; 220 221 pi = sc->psc_pi; 222 sel = sc->psc_sel; 223 224 /* 225 * Parse the capabilities and cache the location of the MSI 226 * and MSI-X capabilities. 227 */ 228 sts = pci_host_read_config(&sel, PCIR_STATUS, 2); 229 if (sts & PCIM_STATUS_CAPPRESENT) { 230 ptr = pci_host_read_config(&sel, PCIR_CAP_PTR, 1); 231 while (ptr != 0 && ptr != 0xff) { 232 cap = pci_host_read_config(&sel, ptr + PCICAP_ID, 1); 233 if (cap == PCIY_MSI) { 234 /* 235 * Copy the MSI capability into the config 236 * space of the emulated pci device 237 */ 238 sc->psc_msi.capoff = ptr; 239 sc->psc_msi.msgctrl = pci_host_read_config(&sel, 240 ptr + 2, 2); 241 sc->psc_msi.emulated = 0; 242 caplen = msi_caplen(sc->psc_msi.msgctrl); 243 capptr = ptr; 244 while (caplen > 0) { 245 u32 = pci_host_read_config(&sel, capptr, 246 4); 247 pci_set_cfgdata32(pi, capptr, u32); 248 caplen -= 4; 249 capptr += 4; 250 } 251 } else if (cap == PCIY_MSIX) { 252 /* 253 * Copy the MSI-X capability 254 */ 255 sc->psc_msix.capoff = ptr; 256 caplen = 12; 257 msixcap_ptr = (char *)&msixcap; 258 capptr = ptr; 259 while (caplen > 0) { 260 u32 = pci_host_read_config(&sel, capptr, 261 4); 262 memcpy(msixcap_ptr, &u32, 4); 263 pci_set_cfgdata32(pi, capptr, u32); 264 caplen -= 4; 265 capptr += 4; 266 msixcap_ptr += 4; 267 } 268 } 269 ptr = pci_host_read_config(&sel, ptr + PCICAP_NEXTPTR, 270 1); 271 } 272 } 273 274 if (sc->psc_msix.capoff != 0) { 275 pi->pi_msix.pba_bar = 276 msixcap.pba_info & PCIM_MSIX_BIR_MASK; 277 pi->pi_msix.pba_offset = 278 msixcap.pba_info & ~PCIM_MSIX_BIR_MASK; 279 pi->pi_msix.table_bar = 280 msixcap.table_info & PCIM_MSIX_BIR_MASK; 281 pi->pi_msix.table_offset = 282 msixcap.table_info & ~PCIM_MSIX_BIR_MASK; 283 pi->pi_msix.table_count = MSIX_TABLE_COUNT(msixcap.msgctrl); 284 pi->pi_msix.pba_size = PBA_SIZE(pi->pi_msix.table_count); 285 286 /* Allocate the emulated MSI-X table array */ 287 table_size = pi->pi_msix.table_count * MSIX_TABLE_ENTRY_SIZE; 288 pi->pi_msix.table = calloc(1, table_size); 289 290 /* Mask all table entries */ 291 for (i = 0; i < pi->pi_msix.table_count; i++) { 292 pi->pi_msix.table[i].vector_control |= 293 PCIM_MSIX_VCTRL_MASK; 294 } 295 } 296 297 #ifdef LEGACY_SUPPORT 298 /* 299 * If the passthrough device does not support MSI then craft a 300 * MSI capability for it. We link the new MSI capability at the 301 * head of the list of capabilities. 302 */ 303 if ((sts & PCIM_STATUS_CAPPRESENT) != 0 && sc->psc_msi.capoff == 0) { 304 int origptr, msiptr; 305 origptr = pci_host_read_config(&sel, PCIR_CAP_PTR, 1); 306 msiptr = passthru_add_msicap(pi, 1, origptr); 307 sc->psc_msi.capoff = msiptr; 308 sc->psc_msi.msgctrl = pci_get_cfgdata16(pi, msiptr + 2); 309 sc->psc_msi.emulated = 1; 310 pci_set_cfgdata8(pi, PCIR_CAP_PTR, msiptr); 311 } 312 #endif 313 314 /* Make sure one of the capabilities is present */ 315 if (sc->psc_msi.capoff == 0 && sc->psc_msix.capoff == 0) 316 return (-1); 317 else 318 return (0); 319 } 320 321 static uint64_t 322 msix_table_read(struct passthru_softc *sc, uint64_t offset, int size) 323 { 324 struct pci_devinst *pi; 325 struct msix_table_entry *entry; 326 uint8_t *src8; 327 uint16_t *src16; 328 uint32_t *src32; 329 uint64_t *src64; 330 uint64_t data; 331 size_t entry_offset; 332 uint32_t table_offset; 333 int index, table_count; 334 335 pi = sc->psc_pi; 336 337 table_offset = pi->pi_msix.table_offset; 338 table_count = pi->pi_msix.table_count; 339 if (offset < table_offset || 340 offset >= table_offset + table_count * MSIX_TABLE_ENTRY_SIZE) { 341 switch (size) { 342 case 1: 343 src8 = (uint8_t *)(pi->pi_msix.mapped_addr + offset); 344 data = *src8; 345 break; 346 case 2: 347 src16 = (uint16_t *)(pi->pi_msix.mapped_addr + offset); 348 data = *src16; 349 break; 350 case 4: 351 src32 = (uint32_t *)(pi->pi_msix.mapped_addr + offset); 352 data = *src32; 353 break; 354 case 8: 355 src64 = (uint64_t *)(pi->pi_msix.mapped_addr + offset); 356 data = *src64; 357 break; 358 default: 359 return (-1); 360 } 361 return (data); 362 } 363 364 offset -= table_offset; 365 index = offset / MSIX_TABLE_ENTRY_SIZE; 366 assert(index < table_count); 367 368 entry = &pi->pi_msix.table[index]; 369 entry_offset = offset % MSIX_TABLE_ENTRY_SIZE; 370 371 switch (size) { 372 case 1: 373 src8 = (uint8_t *)((uint8_t *)entry + entry_offset); 374 data = *src8; 375 break; 376 case 2: 377 src16 = (uint16_t *)((uint8_t *)entry + entry_offset); 378 data = *src16; 379 break; 380 case 4: 381 src32 = (uint32_t *)((uint8_t *)entry + entry_offset); 382 data = *src32; 383 break; 384 case 8: 385 src64 = (uint64_t *)((uint8_t *)entry + entry_offset); 386 data = *src64; 387 break; 388 default: 389 return (-1); 390 } 391 392 return (data); 393 } 394 395 static void 396 msix_table_write(struct passthru_softc *sc, uint64_t offset, int size, 397 uint64_t data) 398 { 399 struct pci_devinst *pi; 400 struct msix_table_entry *entry; 401 uint8_t *dest8; 402 uint16_t *dest16; 403 uint32_t *dest32; 404 uint64_t *dest64; 405 size_t entry_offset; 406 uint32_t table_offset, vector_control; 407 int index, table_count; 408 409 pi = sc->psc_pi; 410 411 table_offset = pi->pi_msix.table_offset; 412 table_count = pi->pi_msix.table_count; 413 if (offset < table_offset || 414 offset >= table_offset + table_count * MSIX_TABLE_ENTRY_SIZE) { 415 switch (size) { 416 case 1: 417 dest8 = (uint8_t *)(pi->pi_msix.mapped_addr + offset); 418 *dest8 = data; 419 break; 420 case 2: 421 dest16 = (uint16_t *)(pi->pi_msix.mapped_addr + offset); 422 *dest16 = data; 423 break; 424 case 4: 425 dest32 = (uint32_t *)(pi->pi_msix.mapped_addr + offset); 426 *dest32 = data; 427 break; 428 case 8: 429 dest64 = (uint64_t *)(pi->pi_msix.mapped_addr + offset); 430 *dest64 = data; 431 break; 432 } 433 return; 434 } 435 436 offset -= table_offset; 437 index = offset / MSIX_TABLE_ENTRY_SIZE; 438 assert(index < table_count); 439 440 entry = &pi->pi_msix.table[index]; 441 entry_offset = offset % MSIX_TABLE_ENTRY_SIZE; 442 443 /* Only 4 byte naturally-aligned writes are supported */ 444 assert(size == 4); 445 assert(entry_offset % 4 == 0); 446 447 vector_control = entry->vector_control; 448 dest32 = (uint32_t *)((uint8_t *)entry + entry_offset); 449 *dest32 = data; 450 /* If MSI-X hasn't been enabled, do nothing */ 451 if (pi->pi_msix.enabled) { 452 /* If the entry is masked, don't set it up */ 453 if ((entry->vector_control & PCIM_MSIX_VCTRL_MASK) == 0 || 454 (vector_control & PCIM_MSIX_VCTRL_MASK) == 0) { 455 (void)vm_setup_pptdev_msix(sc->psc_pi->pi_vmctx, 456 sc->psc_sel.pc_bus, sc->psc_sel.pc_dev, 457 sc->psc_sel.pc_func, index, entry->addr, 458 entry->msg_data, entry->vector_control); 459 } 460 } 461 } 462 463 static int 464 init_msix_table(struct passthru_softc *sc) 465 { 466 struct pci_devinst *pi = sc->psc_pi; 467 struct pci_bar_mmap pbm; 468 int b, s, f; 469 uint32_t table_size, table_offset; 470 471 assert(pci_msix_table_bar(pi) >= 0 && pci_msix_pba_bar(pi) >= 0); 472 473 b = sc->psc_sel.pc_bus; 474 s = sc->psc_sel.pc_dev; 475 f = sc->psc_sel.pc_func; 476 477 /* 478 * Map the region of the BAR containing the MSI-X table. This is 479 * necessary for two reasons: 480 * 1. The PBA may reside in the first or last page containing the MSI-X 481 * table. 482 * 2. While PCI devices are not supposed to use the page(s) containing 483 * the MSI-X table for other purposes, some do in practice. 484 */ 485 memset(&pbm, 0, sizeof(pbm)); 486 pbm.pbm_sel = sc->psc_sel; 487 pbm.pbm_flags = PCIIO_BAR_MMAP_RW; 488 pbm.pbm_reg = PCIR_BAR(pi->pi_msix.table_bar); 489 pbm.pbm_memattr = VM_MEMATTR_DEVICE; 490 491 if (ioctl(pcifd, PCIOCBARMMAP, &pbm) != 0) { 492 warn("Failed to map MSI-X table BAR on %d/%d/%d", b, s, f); 493 return (-1); 494 } 495 assert(pbm.pbm_bar_off == 0); 496 pi->pi_msix.mapped_addr = (uint8_t *)(uintptr_t)pbm.pbm_map_base; 497 pi->pi_msix.mapped_size = pbm.pbm_map_length; 498 499 table_offset = rounddown2(pi->pi_msix.table_offset, 4096); 500 501 table_size = pi->pi_msix.table_offset - table_offset; 502 table_size += pi->pi_msix.table_count * MSIX_TABLE_ENTRY_SIZE; 503 table_size = roundup2(table_size, 4096); 504 505 /* 506 * Unmap any pages not containing the table, we do not need to emulate 507 * accesses to them. Avoid releasing address space to help ensure that 508 * a buggy out-of-bounds access causes a crash. 509 */ 510 if (table_offset != 0) 511 if (mprotect(pi->pi_msix.mapped_addr, table_offset, 512 PROT_NONE) != 0) 513 warn("Failed to unmap MSI-X table BAR region"); 514 if (table_offset + table_size != pi->pi_msix.mapped_size) 515 if (mprotect( 516 pi->pi_msix.mapped_addr + table_offset + table_size, 517 pi->pi_msix.mapped_size - (table_offset + table_size), 518 PROT_NONE) != 0) 519 warn("Failed to unmap MSI-X table BAR region"); 520 521 return (0); 522 } 523 524 static int 525 cfginitbar(struct passthru_softc *sc) 526 { 527 int i, error; 528 struct pci_devinst *pi; 529 struct pci_bar_io bar; 530 enum pcibar_type bartype; 531 uint64_t base, size; 532 533 pi = sc->psc_pi; 534 535 /* 536 * Initialize BAR registers 537 */ 538 for (i = 0; i <= PCI_BARMAX; i++) { 539 bzero(&bar, sizeof(bar)); 540 bar.pbi_sel = sc->psc_sel; 541 bar.pbi_reg = PCIR_BAR(i); 542 543 if (ioctl(pcifd, PCIOCGETBAR, &bar) < 0) 544 continue; 545 546 if (PCI_BAR_IO(bar.pbi_base)) { 547 bartype = PCIBAR_IO; 548 base = bar.pbi_base & PCIM_BAR_IO_BASE; 549 } else { 550 switch (bar.pbi_base & PCIM_BAR_MEM_TYPE) { 551 case PCIM_BAR_MEM_64: 552 bartype = PCIBAR_MEM64; 553 break; 554 default: 555 bartype = PCIBAR_MEM32; 556 break; 557 } 558 base = bar.pbi_base & PCIM_BAR_MEM_BASE; 559 } 560 size = bar.pbi_length; 561 562 if (bartype != PCIBAR_IO) { 563 if (((base | size) & PAGE_MASK) != 0) { 564 warnx("passthru device %d/%d/%d BAR %d: " 565 "base %#lx or size %#lx not page aligned\n", 566 sc->psc_sel.pc_bus, sc->psc_sel.pc_dev, 567 sc->psc_sel.pc_func, i, base, size); 568 return (-1); 569 } 570 } 571 572 /* Cache information about the "real" BAR */ 573 sc->psc_bar[i].type = bartype; 574 sc->psc_bar[i].size = size; 575 sc->psc_bar[i].addr = base; 576 sc->psc_bar[i].lobits = 0; 577 578 /* Allocate the BAR in the guest I/O or MMIO space */ 579 error = pci_emul_alloc_bar(pi, i, bartype, size); 580 if (error) 581 return (-1); 582 583 /* Use same lobits as physical bar */ 584 uint8_t lobits = pci_host_read_config(&sc->psc_sel, PCIR_BAR(i), 585 0x01); 586 if (bartype == PCIBAR_MEM32 || bartype == PCIBAR_MEM64) { 587 lobits &= ~PCIM_BAR_MEM_BASE; 588 } else { 589 lobits &= ~PCIM_BAR_IO_BASE; 590 } 591 sc->psc_bar[i].lobits = lobits; 592 pi->pi_bar[i].lobits = lobits; 593 594 /* 595 * 64-bit BAR takes up two slots so skip the next one. 596 */ 597 if (bartype == PCIBAR_MEM64) { 598 i++; 599 assert(i <= PCI_BARMAX); 600 sc->psc_bar[i].type = PCIBAR_MEMHI64; 601 } 602 } 603 return (0); 604 } 605 606 static int 607 cfginit(struct pci_devinst *pi, int bus, int slot, int func) 608 { 609 int error; 610 struct passthru_softc *sc; 611 uint8_t intline, intpin; 612 613 error = 1; 614 sc = pi->pi_arg; 615 616 bzero(&sc->psc_sel, sizeof(struct pcisel)); 617 sc->psc_sel.pc_bus = bus; 618 sc->psc_sel.pc_dev = slot; 619 sc->psc_sel.pc_func = func; 620 621 /* 622 * Copy physical PCI header to virtual config space. INTLINE and INTPIN 623 * shouldn't be aligned with their physical value and they are already set by 624 * pci_emul_init(). 625 */ 626 intline = pci_get_cfgdata8(pi, PCIR_INTLINE); 627 intpin = pci_get_cfgdata8(pi, PCIR_INTPIN); 628 for (int i = 0; i <= PCIR_MAXLAT; i += 4) { 629 pci_set_cfgdata32(pi, i, 630 pci_host_read_config(&sc->psc_sel, i, 4)); 631 } 632 pci_set_cfgdata8(pi, PCIR_INTLINE, intline); 633 pci_set_cfgdata8(pi, PCIR_INTPIN, intpin); 634 635 if (cfginitmsi(sc) != 0) { 636 warnx("failed to initialize MSI for PCI %d/%d/%d", 637 bus, slot, func); 638 goto done; 639 } 640 641 if (cfginitbar(sc) != 0) { 642 warnx("failed to initialize BARs for PCI %d/%d/%d", 643 bus, slot, func); 644 goto done; 645 } 646 647 pci_host_write_config(&sc->psc_sel, PCIR_COMMAND, 2, 648 pci_get_cfgdata16(pi, PCIR_COMMAND)); 649 650 /* 651 * We need to do this after PCIR_COMMAND got possibly updated, e.g., 652 * a BAR was enabled, as otherwise the PCIOCBARMMAP might fail on us. 653 */ 654 if (pci_msix_table_bar(pi) >= 0) { 655 error = init_msix_table(sc); 656 if (error != 0) { 657 warnx( 658 "failed to initialize MSI-X table for PCI %d/%d/%d: %d", 659 bus, slot, func, error); 660 goto done; 661 } 662 } 663 664 error = 0; /* success */ 665 done: 666 return (error); 667 } 668 669 struct passthru_mmio_mapping * 670 passthru_get_mmio(struct passthru_softc *sc, int num) 671 { 672 assert(sc != NULL); 673 assert(num < PASSTHRU_MMIO_MAX); 674 675 return (&sc->psc_mmio_map[num]); 676 } 677 678 struct pcisel * 679 passthru_get_sel(struct passthru_softc *sc) 680 { 681 assert(sc != NULL); 682 683 return (&sc->psc_sel); 684 } 685 686 int 687 set_pcir_handler(struct passthru_softc *sc, int reg, int len, 688 cfgread_handler rhandler, cfgwrite_handler whandler) 689 { 690 if (reg > PCI_REGMAX || reg + len > PCI_REGMAX + 1) 691 return (-1); 692 693 for (int i = reg; i < reg + len; ++i) { 694 assert(sc->psc_pcir_rhandler[i] == NULL || rhandler == NULL); 695 assert(sc->psc_pcir_whandler[i] == NULL || whandler == NULL); 696 sc->psc_pcir_rhandler[i] = rhandler; 697 sc->psc_pcir_whandler[i] = whandler; 698 } 699 700 return (0); 701 } 702 703 static int 704 passthru_legacy_config(nvlist_t *nvl, const char *opts) 705 { 706 const char *cp; 707 char *tofree; 708 char value[16]; 709 int bus, slot, func; 710 711 if (opts == NULL) 712 return (0); 713 714 cp = strchr(opts, ','); 715 716 if (strncmp(opts, "ppt", strlen("ppt")) == 0) { 717 tofree = strndup(opts, cp - opts); 718 set_config_value_node(nvl, "pptdev", tofree); 719 free(tofree); 720 } else if (sscanf(opts, "pci0:%d:%d:%d", &bus, &slot, &func) == 3 || 721 sscanf(opts, "pci%d:%d:%d", &bus, &slot, &func) == 3 || 722 sscanf(opts, "%d/%d/%d", &bus, &slot, &func) == 3) { 723 snprintf(value, sizeof(value), "%d", bus); 724 set_config_value_node(nvl, "bus", value); 725 snprintf(value, sizeof(value), "%d", slot); 726 set_config_value_node(nvl, "slot", value); 727 snprintf(value, sizeof(value), "%d", func); 728 set_config_value_node(nvl, "func", value); 729 } else { 730 EPRINTLN("passthru: invalid options \"%s\"", opts); 731 return (-1); 732 } 733 734 if (cp == NULL) { 735 return (0); 736 } 737 738 return (pci_parse_legacy_config(nvl, cp + 1)); 739 } 740 741 static int 742 passthru_init_rom(struct passthru_softc *const sc, const char *const romfile) 743 { 744 if (romfile == NULL) { 745 return (0); 746 } 747 748 const int fd = open(romfile, O_RDONLY); 749 if (fd < 0) { 750 warnx("%s: can't open romfile \"%s\"", __func__, romfile); 751 return (-1); 752 } 753 754 struct stat sbuf; 755 if (fstat(fd, &sbuf) < 0) { 756 warnx("%s: can't fstat romfile \"%s\"", __func__, romfile); 757 close(fd); 758 return (-1); 759 } 760 const uint64_t rom_size = sbuf.st_size; 761 762 void *const rom_data = mmap(NULL, rom_size, PROT_READ, MAP_SHARED, fd, 763 0); 764 if (rom_data == MAP_FAILED) { 765 warnx("%s: unable to mmap romfile \"%s\" (%d)", __func__, 766 romfile, errno); 767 close(fd); 768 return (-1); 769 } 770 771 void *rom_addr; 772 int error = pci_emul_alloc_rom(sc->psc_pi, rom_size, &rom_addr); 773 if (error) { 774 warnx("%s: failed to alloc rom segment", __func__); 775 munmap(rom_data, rom_size); 776 close(fd); 777 return (error); 778 } 779 memcpy(rom_addr, rom_data, rom_size); 780 781 sc->psc_bar[PCI_ROM_IDX].type = PCIBAR_ROM; 782 sc->psc_bar[PCI_ROM_IDX].addr = (uint64_t)rom_addr; 783 sc->psc_bar[PCI_ROM_IDX].size = rom_size; 784 785 munmap(rom_data, rom_size); 786 close(fd); 787 788 return (0); 789 } 790 791 static bool 792 passthru_lookup_pptdev(const char *name, int *bus, int *slot, int *func) 793 { 794 struct pci_conf_io pc; 795 struct pci_conf conf[1]; 796 struct pci_match_conf patterns[1]; 797 char *cp; 798 799 bzero(&pc, sizeof(struct pci_conf_io)); 800 pc.match_buf_len = sizeof(conf); 801 pc.matches = conf; 802 803 bzero(&patterns, sizeof(patterns)); 804 805 /* 806 * The pattern structure requires the unit to be split out from 807 * the driver name. Walk backwards from the end of the name to 808 * find the start of the unit. 809 */ 810 cp = strchr(name, '\0'); 811 assert(cp != NULL); 812 while (cp != name && isdigit(cp[-1])) 813 cp--; 814 if (cp == name || !isdigit(*cp)) { 815 EPRINTLN("Invalid passthru device name %s", name); 816 return (false); 817 } 818 if ((size_t)(cp - name) + 1 > sizeof(patterns[0].pd_name)) { 819 EPRINTLN("Passthru device name %s is too long", name); 820 return (false); 821 } 822 memcpy(patterns[0].pd_name, name, cp - name); 823 patterns[0].pd_unit = strtol(cp, &cp, 10); 824 if (*cp != '\0') { 825 EPRINTLN("Invalid passthru device name %s", name); 826 return (false); 827 } 828 patterns[0].flags = PCI_GETCONF_MATCH_NAME | PCI_GETCONF_MATCH_UNIT; 829 pc.num_patterns = 1; 830 pc.pat_buf_len = sizeof(patterns); 831 pc.patterns = patterns; 832 833 if (ioctl(pcifd, PCIOCGETCONF, &pc) == -1) { 834 EPRINTLN("ioctl(PCIOCGETCONF): %s", strerror(errno)); 835 return (false); 836 } 837 if (pc.status != PCI_GETCONF_LAST_DEVICE && 838 pc.status != PCI_GETCONF_MORE_DEVS) { 839 EPRINTLN("error returned from PCIOCGETCONF ioctl"); 840 return (false); 841 } 842 if (pc.num_matches == 0) { 843 EPRINTLN("Passthru device %s not found", name); 844 return (false); 845 } 846 847 if (conf[0].pc_sel.pc_domain != 0) { 848 EPRINTLN("Passthru device %s on unsupported domain", name); 849 return (false); 850 } 851 *bus = conf[0].pc_sel.pc_bus; 852 *slot = conf[0].pc_sel.pc_dev; 853 *func = conf[0].pc_sel.pc_func; 854 return (true); 855 } 856 857 static int 858 passthru_init(struct pci_devinst *pi, nvlist_t *nvl) 859 { 860 int bus, slot, func, error, memflags; 861 struct passthru_softc *sc; 862 struct passthru_dev **devpp; 863 struct passthru_dev *devp, *dev = NULL; 864 const char *value; 865 866 sc = NULL; 867 error = 1; 868 869 memflags = vm_get_memflags(pi->pi_vmctx); 870 if (!(memflags & VM_MEM_F_WIRED)) { 871 warnx("passthru requires guest memory to be wired"); 872 return (error); 873 } 874 875 if (pcifd < 0 && pcifd_init()) { 876 return (error); 877 } 878 879 #define GET_INT_CONFIG(var, name) do { \ 880 value = get_config_value_node(nvl, name); \ 881 if (value == NULL) { \ 882 EPRINTLN("passthru: missing required %s setting", name); \ 883 return (error); \ 884 } \ 885 var = atoi(value); \ 886 } while (0) 887 888 value = get_config_value_node(nvl, "pptdev"); 889 if (value != NULL) { 890 if (!passthru_lookup_pptdev(value, &bus, &slot, &func)) 891 return (error); 892 } else { 893 GET_INT_CONFIG(bus, "bus"); 894 GET_INT_CONFIG(slot, "slot"); 895 GET_INT_CONFIG(func, "func"); 896 } 897 898 if (vm_assign_pptdev(pi->pi_vmctx, bus, slot, func) != 0) { 899 warnx("PCI device at %d/%d/%d is not using the ppt(4) driver", 900 bus, slot, func); 901 goto done; 902 } 903 904 sc = calloc(1, sizeof(struct passthru_softc)); 905 906 pi->pi_arg = sc; 907 sc->psc_pi = pi; 908 909 /* initialize config space */ 910 if ((error = cfginit(pi, bus, slot, func)) != 0) 911 goto done; 912 913 /* initialize ROM */ 914 if ((error = passthru_init_rom(sc, 915 get_config_value_node(nvl, "rom"))) != 0) 916 goto done; 917 918 /* Emulate most PCI header register. */ 919 if ((error = set_pcir_handler(sc, 0, PCIR_MAXLAT + 1, 920 passthru_cfgread_emulate, passthru_cfgwrite_emulate)) != 0) 921 goto done; 922 923 /* Allow access to the physical command and status register. */ 924 if ((error = set_pcir_handler(sc, PCIR_COMMAND, 0x04, NULL, NULL)) != 0) 925 goto done; 926 927 SET_FOREACH(devpp, passthru_dev_set) { 928 devp = *devpp; 929 assert(devp->probe != NULL); 930 if (devp->probe(pi) == 0) { 931 dev = devp; 932 break; 933 } 934 } 935 936 if (dev != NULL) { 937 error = dev->init(pi, nvl); 938 if (error != 0) 939 goto done; 940 } 941 942 error = 0; /* success */ 943 done: 944 if (error) { 945 if (dev != NULL) 946 dev->deinit(pi); 947 free(sc); 948 vm_unassign_pptdev(pi->pi_vmctx, bus, slot, func); 949 } 950 return (error); 951 } 952 953 static int 954 msicap_access(struct passthru_softc *sc, int coff) 955 { 956 int caplen; 957 958 if (sc->psc_msi.capoff == 0) 959 return (0); 960 961 caplen = msi_caplen(sc->psc_msi.msgctrl); 962 963 if (coff >= sc->psc_msi.capoff && coff < sc->psc_msi.capoff + caplen) 964 return (1); 965 else 966 return (0); 967 } 968 969 static int 970 msixcap_access(struct passthru_softc *sc, int coff) 971 { 972 if (sc->psc_msix.capoff == 0) 973 return (0); 974 975 return (coff >= sc->psc_msix.capoff && 976 coff < sc->psc_msix.capoff + MSIX_CAPLEN); 977 } 978 979 static int 980 passthru_cfgread_default(struct passthru_softc *sc, 981 struct pci_devinst *pi __unused, int coff, int bytes, uint32_t *rv) 982 { 983 /* 984 * MSI capability is emulated. 985 */ 986 if (msicap_access(sc, coff) || msixcap_access(sc, coff)) 987 return (-1); 988 989 /* 990 * Emulate the command register. If a single read reads both the 991 * command and status registers, read the status register from the 992 * device's config space. 993 */ 994 if (coff == PCIR_COMMAND) { 995 if (bytes <= 2) 996 return (-1); 997 *rv = pci_host_read_config(&sc->psc_sel, PCIR_STATUS, 2) << 16 | 998 pci_get_cfgdata16(pi, PCIR_COMMAND); 999 return (0); 1000 } 1001 1002 /* Everything else just read from the device's config space */ 1003 *rv = pci_host_read_config(&sc->psc_sel, coff, bytes); 1004 1005 return (0); 1006 } 1007 1008 int 1009 passthru_cfgread_emulate(struct passthru_softc *sc __unused, 1010 struct pci_devinst *pi __unused, int coff __unused, int bytes __unused, 1011 uint32_t *rv __unused) 1012 { 1013 return (-1); 1014 } 1015 1016 static int 1017 passthru_cfgread(struct pci_devinst *pi, int coff, int bytes, uint32_t *rv) 1018 { 1019 struct passthru_softc *sc; 1020 1021 sc = pi->pi_arg; 1022 1023 if (sc->psc_pcir_rhandler[coff] != NULL) 1024 return (sc->psc_pcir_rhandler[coff](sc, pi, coff, bytes, rv)); 1025 1026 return (passthru_cfgread_default(sc, pi, coff, bytes, rv)); 1027 } 1028 1029 static int 1030 passthru_cfgwrite_default(struct passthru_softc *sc, struct pci_devinst *pi, 1031 int coff, int bytes, uint32_t val) 1032 { 1033 int error, msix_table_entries, i; 1034 uint16_t cmd_old; 1035 1036 /* 1037 * MSI capability is emulated 1038 */ 1039 if (msicap_access(sc, coff)) { 1040 pci_emul_capwrite(pi, coff, bytes, val, sc->psc_msi.capoff, 1041 PCIY_MSI); 1042 error = vm_setup_pptdev_msi(pi->pi_vmctx, sc->psc_sel.pc_bus, 1043 sc->psc_sel.pc_dev, sc->psc_sel.pc_func, 1044 pi->pi_msi.addr, pi->pi_msi.msg_data, 1045 pi->pi_msi.maxmsgnum); 1046 if (error != 0) 1047 err(1, "vm_setup_pptdev_msi"); 1048 return (0); 1049 } 1050 1051 if (msixcap_access(sc, coff)) { 1052 pci_emul_capwrite(pi, coff, bytes, val, sc->psc_msix.capoff, 1053 PCIY_MSIX); 1054 if (pi->pi_msix.enabled) { 1055 msix_table_entries = pi->pi_msix.table_count; 1056 for (i = 0; i < msix_table_entries; i++) { 1057 error = vm_setup_pptdev_msix(pi->pi_vmctx, 1058 sc->psc_sel.pc_bus, sc->psc_sel.pc_dev, 1059 sc->psc_sel.pc_func, i, 1060 pi->pi_msix.table[i].addr, 1061 pi->pi_msix.table[i].msg_data, 1062 pi->pi_msix.table[i].vector_control); 1063 1064 if (error) 1065 err(1, "vm_setup_pptdev_msix"); 1066 } 1067 } else { 1068 error = vm_disable_pptdev_msix(pi->pi_vmctx, 1069 sc->psc_sel.pc_bus, sc->psc_sel.pc_dev, 1070 sc->psc_sel.pc_func); 1071 if (error) 1072 err(1, "vm_disable_pptdev_msix"); 1073 } 1074 return (0); 1075 } 1076 1077 #ifdef LEGACY_SUPPORT 1078 /* 1079 * If this device does not support MSI natively then we cannot let 1080 * the guest disable legacy interrupts from the device. It is the 1081 * legacy interrupt that is triggering the virtual MSI to the guest. 1082 */ 1083 if (sc->psc_msi.emulated && pci_msi_enabled(pi)) { 1084 if (coff == PCIR_COMMAND && bytes == 2) 1085 val &= ~PCIM_CMD_INTxDIS; 1086 } 1087 #endif 1088 1089 pci_host_write_config(&sc->psc_sel, coff, bytes, val); 1090 if (coff == PCIR_COMMAND) { 1091 cmd_old = pci_get_cfgdata16(pi, PCIR_COMMAND); 1092 if (bytes == 1) 1093 pci_set_cfgdata8(pi, PCIR_COMMAND, val); 1094 else if (bytes == 2) 1095 pci_set_cfgdata16(pi, PCIR_COMMAND, val); 1096 pci_emul_cmd_changed(pi, cmd_old); 1097 } 1098 1099 return (0); 1100 } 1101 1102 int 1103 passthru_cfgwrite_emulate(struct passthru_softc *sc __unused, 1104 struct pci_devinst *pi __unused, int coff __unused, int bytes __unused, 1105 uint32_t val __unused) 1106 { 1107 return (-1); 1108 } 1109 1110 static int 1111 passthru_cfgwrite(struct pci_devinst *pi, int coff, int bytes, uint32_t val) 1112 { 1113 struct passthru_softc *sc; 1114 1115 sc = pi->pi_arg; 1116 1117 if (sc->psc_pcir_whandler[coff] != NULL) 1118 return (sc->psc_pcir_whandler[coff](sc, pi, coff, bytes, val)); 1119 1120 return (passthru_cfgwrite_default(sc, pi, coff, bytes, val)); 1121 } 1122 1123 static void 1124 passthru_write(struct pci_devinst *pi, int baridx, uint64_t offset, int size, 1125 uint64_t value) 1126 { 1127 struct passthru_softc *sc; 1128 struct pci_bar_ioreq pio; 1129 1130 sc = pi->pi_arg; 1131 1132 if (baridx == pci_msix_table_bar(pi)) { 1133 msix_table_write(sc, offset, size, value); 1134 } else { 1135 assert(pi->pi_bar[baridx].type == PCIBAR_IO); 1136 assert(size == 1 || size == 2 || size == 4); 1137 assert(offset <= UINT32_MAX && offset + size <= UINT32_MAX); 1138 1139 bzero(&pio, sizeof(pio)); 1140 pio.pbi_sel = sc->psc_sel; 1141 pio.pbi_op = PCIBARIO_WRITE; 1142 pio.pbi_bar = baridx; 1143 pio.pbi_offset = (uint32_t)offset; 1144 pio.pbi_width = size; 1145 pio.pbi_value = (uint32_t)value; 1146 1147 (void)ioctl(pcifd, PCIOCBARIO, &pio); 1148 } 1149 } 1150 1151 static uint64_t 1152 passthru_read(struct pci_devinst *pi, int baridx, uint64_t offset, int size) 1153 { 1154 struct passthru_softc *sc; 1155 struct pci_bar_ioreq pio; 1156 uint64_t val; 1157 1158 sc = pi->pi_arg; 1159 1160 if (baridx == pci_msix_table_bar(pi)) { 1161 val = msix_table_read(sc, offset, size); 1162 } else { 1163 assert(pi->pi_bar[baridx].type == PCIBAR_IO); 1164 assert(size == 1 || size == 2 || size == 4); 1165 assert(offset <= UINT32_MAX && offset + size <= UINT32_MAX); 1166 1167 bzero(&pio, sizeof(pio)); 1168 pio.pbi_sel = sc->psc_sel; 1169 pio.pbi_op = PCIBARIO_READ; 1170 pio.pbi_bar = baridx; 1171 pio.pbi_offset = (uint32_t)offset; 1172 pio.pbi_width = size; 1173 1174 (void)ioctl(pcifd, PCIOCBARIO, &pio); 1175 1176 val = pio.pbi_value; 1177 } 1178 1179 return (val); 1180 } 1181 1182 static void 1183 passthru_msix_addr(struct pci_devinst *pi, int baridx, int enabled, 1184 uint64_t address) 1185 { 1186 struct passthru_softc *sc; 1187 size_t remaining; 1188 uint32_t table_size, table_offset; 1189 1190 sc = pi->pi_arg; 1191 table_offset = rounddown2(pi->pi_msix.table_offset, 4096); 1192 if (table_offset > 0) { 1193 if (!enabled) { 1194 if (vm_unmap_pptdev_mmio(pi->pi_vmctx, 1195 sc->psc_sel.pc_bus, 1196 sc->psc_sel.pc_dev, 1197 sc->psc_sel.pc_func, address, 1198 table_offset) != 0) 1199 warnx("pci_passthru: unmap_pptdev_mmio failed"); 1200 } else { 1201 if (vm_map_pptdev_mmio(pi->pi_vmctx, sc->psc_sel.pc_bus, 1202 sc->psc_sel.pc_dev, 1203 sc->psc_sel.pc_func, address, 1204 table_offset, 1205 sc->psc_bar[baridx].addr) != 0) 1206 warnx("pci_passthru: map_pptdev_mmio failed"); 1207 } 1208 } 1209 table_size = pi->pi_msix.table_offset - table_offset; 1210 table_size += pi->pi_msix.table_count * MSIX_TABLE_ENTRY_SIZE; 1211 table_size = roundup2(table_size, 4096); 1212 remaining = pi->pi_bar[baridx].size - table_offset - table_size; 1213 if (remaining > 0) { 1214 address += table_offset + table_size; 1215 if (!enabled) { 1216 if (vm_unmap_pptdev_mmio(pi->pi_vmctx, 1217 sc->psc_sel.pc_bus, 1218 sc->psc_sel.pc_dev, 1219 sc->psc_sel.pc_func, address, 1220 remaining) != 0) 1221 warnx("pci_passthru: unmap_pptdev_mmio failed"); 1222 } else { 1223 if (vm_map_pptdev_mmio(pi->pi_vmctx, sc->psc_sel.pc_bus, 1224 sc->psc_sel.pc_dev, 1225 sc->psc_sel.pc_func, address, 1226 remaining, 1227 sc->psc_bar[baridx].addr + 1228 table_offset + table_size) != 0) 1229 warnx("pci_passthru: map_pptdev_mmio failed"); 1230 } 1231 } 1232 } 1233 1234 static void 1235 passthru_mmio_addr(struct pci_devinst *pi, int baridx, int enabled, 1236 uint64_t address) 1237 { 1238 struct passthru_softc *sc; 1239 1240 sc = pi->pi_arg; 1241 if (!enabled) { 1242 if (vm_unmap_pptdev_mmio(pi->pi_vmctx, sc->psc_sel.pc_bus, 1243 sc->psc_sel.pc_dev, 1244 sc->psc_sel.pc_func, address, 1245 sc->psc_bar[baridx].size) != 0) 1246 warnx("pci_passthru: unmap_pptdev_mmio failed"); 1247 } else { 1248 if (vm_map_pptdev_mmio(pi->pi_vmctx, sc->psc_sel.pc_bus, 1249 sc->psc_sel.pc_dev, 1250 sc->psc_sel.pc_func, address, 1251 sc->psc_bar[baridx].size, 1252 sc->psc_bar[baridx].addr) != 0) 1253 warnx("pci_passthru: map_pptdev_mmio failed"); 1254 } 1255 } 1256 1257 static void 1258 passthru_addr_rom(struct pci_devinst *const pi, const int idx, 1259 const int enabled) 1260 { 1261 const uint64_t addr = pi->pi_bar[idx].addr; 1262 const uint64_t size = pi->pi_bar[idx].size; 1263 1264 if (!enabled) { 1265 if (vm_munmap_memseg(pi->pi_vmctx, addr, size) != 0) { 1266 errx(4, "%s: munmap_memseg @ [%016lx - %016lx] failed", 1267 __func__, addr, addr + size); 1268 } 1269 1270 } else { 1271 if (vm_mmap_memseg(pi->pi_vmctx, addr, VM_PCIROM, 1272 pi->pi_romoffset, size, PROT_READ | PROT_EXEC) != 0) { 1273 errx(4, "%s: mmap_memseg @ [%016lx - %016lx] failed", 1274 __func__, addr, addr + size); 1275 } 1276 } 1277 } 1278 1279 static void 1280 passthru_addr(struct pci_devinst *pi, int baridx, int enabled, uint64_t address) 1281 { 1282 switch (pi->pi_bar[baridx].type) { 1283 case PCIBAR_IO: 1284 /* IO BARs are emulated */ 1285 break; 1286 case PCIBAR_ROM: 1287 passthru_addr_rom(pi, baridx, enabled); 1288 break; 1289 case PCIBAR_MEM32: 1290 case PCIBAR_MEM64: 1291 if (baridx == pci_msix_table_bar(pi)) 1292 passthru_msix_addr(pi, baridx, enabled, address); 1293 else 1294 passthru_mmio_addr(pi, baridx, enabled, address); 1295 break; 1296 default: 1297 errx(4, "%s: invalid BAR type %d", __func__, 1298 pi->pi_bar[baridx].type); 1299 } 1300 } 1301 1302 static const struct pci_devemu passthru = { 1303 .pe_emu = "passthru", 1304 .pe_init = passthru_init, 1305 .pe_legacy_config = passthru_legacy_config, 1306 .pe_cfgwrite = passthru_cfgwrite, 1307 .pe_cfgread = passthru_cfgread, 1308 .pe_barwrite = passthru_write, 1309 .pe_barread = passthru_read, 1310 .pe_baraddr = passthru_addr, 1311 }; 1312 PCI_EMUL_SET(passthru); 1313