1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2015 Nahanni Systems, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 #include <sys/types.h> 31 #include <sys/mman.h> 32 33 #include <machine/vmm.h> 34 #include <machine/vmm_snapshot.h> 35 #include <vmmapi.h> 36 37 #include <stdio.h> 38 #include <stdlib.h> 39 #include <string.h> 40 41 #include <errno.h> 42 #include <unistd.h> 43 44 #include "bhyvegc.h" 45 #include "bhyverun.h" 46 #include "config.h" 47 #include "debug.h" 48 #include "console.h" 49 #include "inout.h" 50 #include "pci_emul.h" 51 #include "rfb.h" 52 #include "vga.h" 53 54 /* 55 * bhyve Framebuffer device emulation. 56 * BAR0 points to the current mode information. 57 * BAR1 is the 32-bit framebuffer address. 58 * 59 * -s <b>,fbuf,wait,vga=on|io|off,rfb=<ip>:port,w=width,h=height 60 */ 61 62 static int fbuf_debug = 1; 63 #define DEBUG_INFO 1 64 #define DEBUG_VERBOSE 4 65 #define DPRINTF(level, params) if (level <= fbuf_debug) PRINTLN params 66 67 68 #define KB (1024UL) 69 #define MB (1024 * 1024UL) 70 71 #define DMEMSZ 128 72 73 #define FB_SIZE (16*MB) 74 75 #define COLS_MAX 1920 76 #define ROWS_MAX 1200 77 78 #define COLS_DEFAULT 1024 79 #define ROWS_DEFAULT 768 80 81 #define COLS_MIN 640 82 #define ROWS_MIN 480 83 84 struct pci_fbuf_softc { 85 struct pci_devinst *fsc_pi; 86 struct { 87 uint32_t fbsize; 88 uint16_t width; 89 uint16_t height; 90 uint16_t depth; 91 uint16_t refreshrate; 92 uint8_t reserved[116]; 93 } __packed memregs; 94 95 /* rfb server */ 96 char *rfb_host; 97 char *rfb_password; 98 int rfb_port; 99 int rfb_wait; 100 int vga_enabled; 101 int vga_full; 102 103 uint32_t fbaddr; 104 char *fb_base; 105 uint16_t gc_width; 106 uint16_t gc_height; 107 void *vgasc; 108 struct bhyvegc_image *gc_image; 109 }; 110 111 static struct pci_fbuf_softc *fbuf_sc; 112 113 #define PCI_FBUF_MSI_MSGS 4 114 115 static void 116 pci_fbuf_write(struct pci_devinst *pi, int baridx, uint64_t offset, int size, 117 uint64_t value) 118 { 119 struct pci_fbuf_softc *sc; 120 uint8_t *p; 121 122 assert(baridx == 0); 123 124 sc = pi->pi_arg; 125 126 DPRINTF(DEBUG_VERBOSE, 127 ("fbuf wr: offset 0x%lx, size: %d, value: 0x%lx", 128 offset, size, value)); 129 130 if (offset + size > DMEMSZ) { 131 printf("fbuf: write too large, offset %ld size %d\n", 132 offset, size); 133 return; 134 } 135 136 p = (uint8_t *)&sc->memregs + offset; 137 138 switch (size) { 139 case 1: 140 *p = value; 141 break; 142 case 2: 143 *(uint16_t *)p = value; 144 break; 145 case 4: 146 *(uint32_t *)p = value; 147 break; 148 case 8: 149 *(uint64_t *)p = value; 150 break; 151 default: 152 printf("fbuf: write unknown size %d\n", size); 153 break; 154 } 155 156 if (!sc->gc_image->vgamode && sc->memregs.width == 0 && 157 sc->memregs.height == 0) { 158 DPRINTF(DEBUG_INFO, ("switching to VGA mode")); 159 sc->gc_image->vgamode = 1; 160 sc->gc_width = 0; 161 sc->gc_height = 0; 162 } else if (sc->gc_image->vgamode && sc->memregs.width != 0 && 163 sc->memregs.height != 0) { 164 DPRINTF(DEBUG_INFO, ("switching to VESA mode")); 165 sc->gc_image->vgamode = 0; 166 } 167 } 168 169 static uint64_t 170 pci_fbuf_read(struct pci_devinst *pi, int baridx, uint64_t offset, int size) 171 { 172 struct pci_fbuf_softc *sc; 173 uint8_t *p; 174 uint64_t value; 175 176 assert(baridx == 0); 177 178 sc = pi->pi_arg; 179 180 181 if (offset + size > DMEMSZ) { 182 printf("fbuf: read too large, offset %ld size %d\n", 183 offset, size); 184 return (0); 185 } 186 187 p = (uint8_t *)&sc->memregs + offset; 188 value = 0; 189 switch (size) { 190 case 1: 191 value = *p; 192 break; 193 case 2: 194 value = *(uint16_t *)p; 195 break; 196 case 4: 197 value = *(uint32_t *)p; 198 break; 199 case 8: 200 value = *(uint64_t *)p; 201 break; 202 default: 203 printf("fbuf: read unknown size %d\n", size); 204 break; 205 } 206 207 DPRINTF(DEBUG_VERBOSE, 208 ("fbuf rd: offset 0x%lx, size: %d, value: 0x%lx", 209 offset, size, value)); 210 211 return (value); 212 } 213 214 static void 215 pci_fbuf_baraddr(struct pci_devinst *pi, int baridx, int enabled, 216 uint64_t address) 217 { 218 struct pci_fbuf_softc *sc; 219 int prot; 220 221 if (baridx != 1) 222 return; 223 224 sc = pi->pi_arg; 225 if (!enabled) { 226 if (vm_munmap_memseg(pi->pi_vmctx, sc->fbaddr, FB_SIZE) != 0) 227 EPRINTLN("pci_fbuf: munmap_memseg failed"); 228 sc->fbaddr = 0; 229 } else { 230 prot = PROT_READ | PROT_WRITE; 231 if (vm_mmap_memseg(pi->pi_vmctx, address, VM_FRAMEBUFFER, 0, 232 FB_SIZE, prot) != 0) 233 EPRINTLN("pci_fbuf: mmap_memseg failed"); 234 sc->fbaddr = address; 235 } 236 } 237 238 239 static int 240 pci_fbuf_parse_config(struct pci_fbuf_softc *sc, nvlist_t *nvl) 241 { 242 const char *value; 243 char *cp; 244 245 sc->rfb_wait = get_config_bool_node_default(nvl, "wait", false); 246 247 /* Prefer "rfb" to "tcp". */ 248 value = get_config_value_node(nvl, "rfb"); 249 if (value == NULL) 250 value = get_config_value_node(nvl, "tcp"); 251 if (value != NULL) { 252 /* 253 * IPv4 -- host-ip:port 254 * IPv6 -- [host-ip%zone]:port 255 * XXX for now port is mandatory for IPv4. 256 */ 257 if (value[0] == '[') { 258 cp = strchr(value + 1, ']'); 259 if (cp == NULL || cp == value + 1) { 260 EPRINTLN("fbuf: Invalid IPv6 address: \"%s\"", 261 value); 262 return (-1); 263 } 264 sc->rfb_host = strndup(value + 1, cp - (value + 1)); 265 cp++; 266 if (*cp == ':') { 267 cp++; 268 if (*cp == '\0') { 269 EPRINTLN( 270 "fbuf: Missing port number: \"%s\"", 271 value); 272 return (-1); 273 } 274 sc->rfb_port = atoi(cp); 275 } else if (*cp != '\0') { 276 EPRINTLN("fbuf: Invalid IPv6 address: \"%s\"", 277 value); 278 return (-1); 279 } 280 } else { 281 cp = strchr(value, ':'); 282 if (cp == NULL) { 283 sc->rfb_port = atoi(value); 284 } else { 285 sc->rfb_host = strndup(value, cp - value); 286 cp++; 287 if (*cp == '\0') { 288 EPRINTLN( 289 "fbuf: Missing port number: \"%s\"", 290 value); 291 return (-1); 292 } 293 sc->rfb_port = atoi(cp); 294 } 295 } 296 } 297 298 value = get_config_value_node(nvl, "vga"); 299 if (value != NULL) { 300 if (strcmp(value, "off") == 0) { 301 sc->vga_enabled = 0; 302 } else if (strcmp(value, "io") == 0) { 303 sc->vga_enabled = 1; 304 sc->vga_full = 0; 305 } else if (strcmp(value, "on") == 0) { 306 sc->vga_enabled = 1; 307 sc->vga_full = 1; 308 } else { 309 EPRINTLN("fbuf: Invalid vga setting: \"%s\"", value); 310 return (-1); 311 } 312 } 313 314 value = get_config_value_node(nvl, "w"); 315 if (value != NULL) { 316 sc->memregs.width = atoi(value); 317 if (sc->memregs.width > COLS_MAX) { 318 EPRINTLN("fbuf: width %d too large", sc->memregs.width); 319 return (-1); 320 } 321 if (sc->memregs.width == 0) 322 sc->memregs.width = 1920; 323 } 324 325 value = get_config_value_node(nvl, "h"); 326 if (value != NULL) { 327 sc->memregs.height = atoi(value); 328 if (sc->memregs.height > ROWS_MAX) { 329 EPRINTLN("fbuf: height %d too large", 330 sc->memregs.height); 331 return (-1); 332 } 333 if (sc->memregs.height == 0) 334 sc->memregs.height = 1080; 335 } 336 337 value = get_config_value_node(nvl, "password"); 338 if (value != NULL) 339 sc->rfb_password = strdup(value); 340 341 return (0); 342 } 343 344 static void 345 pci_fbuf_render(struct bhyvegc *gc, void *arg) 346 { 347 struct pci_fbuf_softc *sc; 348 349 sc = arg; 350 351 if (sc->vga_full && sc->gc_image->vgamode) { 352 /* TODO: mode switching to vga and vesa should use the special 353 * EFI-bhyve protocol port. 354 */ 355 vga_render(gc, sc->vgasc); 356 return; 357 } 358 if (sc->gc_width != sc->memregs.width || 359 sc->gc_height != sc->memregs.height) { 360 bhyvegc_resize(gc, sc->memregs.width, sc->memregs.height); 361 sc->gc_width = sc->memregs.width; 362 sc->gc_height = sc->memregs.height; 363 } 364 } 365 366 static int 367 pci_fbuf_init(struct pci_devinst *pi, nvlist_t *nvl) 368 { 369 int error; 370 struct pci_fbuf_softc *sc; 371 372 if (fbuf_sc != NULL) { 373 EPRINTLN("Only one frame buffer device is allowed."); 374 return (-1); 375 } 376 377 sc = calloc(1, sizeof(struct pci_fbuf_softc)); 378 379 pi->pi_arg = sc; 380 381 /* initialize config space */ 382 pci_set_cfgdata16(pi, PCIR_DEVICE, 0x40FB); 383 pci_set_cfgdata16(pi, PCIR_VENDOR, 0xFB5D); 384 pci_set_cfgdata8(pi, PCIR_CLASS, PCIC_DISPLAY); 385 pci_set_cfgdata8(pi, PCIR_SUBCLASS, PCIS_DISPLAY_VGA); 386 387 sc->fb_base = vm_create_devmem(pi->pi_vmctx, VM_FRAMEBUFFER, 388 "framebuffer", FB_SIZE); 389 if (sc->fb_base == MAP_FAILED) { 390 error = -1; 391 goto done; 392 } 393 394 error = pci_emul_alloc_bar(pi, 0, PCIBAR_MEM32, DMEMSZ); 395 assert(error == 0); 396 397 error = pci_emul_alloc_bar(pi, 1, PCIBAR_MEM32, FB_SIZE); 398 assert(error == 0); 399 400 error = pci_emul_add_msicap(pi, PCI_FBUF_MSI_MSGS); 401 assert(error == 0); 402 403 sc->memregs.fbsize = FB_SIZE; 404 sc->memregs.width = COLS_DEFAULT; 405 sc->memregs.height = ROWS_DEFAULT; 406 sc->memregs.depth = 32; 407 408 sc->vga_enabled = 1; 409 sc->vga_full = 0; 410 411 sc->fsc_pi = pi; 412 413 error = pci_fbuf_parse_config(sc, nvl); 414 if (error != 0) 415 goto done; 416 417 /* XXX until VGA rendering is enabled */ 418 if (sc->vga_full != 0) { 419 EPRINTLN("pci_fbuf: VGA rendering not enabled"); 420 goto done; 421 } 422 423 DPRINTF(DEBUG_INFO, ("fbuf frame buffer base: %p [sz %lu]", 424 sc->fb_base, FB_SIZE)); 425 426 console_init(sc->memregs.width, sc->memregs.height, sc->fb_base); 427 console_fb_register(pci_fbuf_render, sc); 428 429 if (sc->vga_enabled) 430 sc->vgasc = vga_init(!sc->vga_full); 431 sc->gc_image = console_get_image(); 432 433 fbuf_sc = sc; 434 435 memset((void *)sc->fb_base, 0, FB_SIZE); 436 437 error = rfb_init(sc->rfb_host, sc->rfb_port, sc->rfb_wait, sc->rfb_password); 438 done: 439 if (error) 440 free(sc); 441 442 return (error); 443 } 444 445 #ifdef BHYVE_SNAPSHOT 446 static int 447 pci_fbuf_snapshot(struct vm_snapshot_meta *meta) 448 { 449 int ret; 450 451 SNAPSHOT_BUF_OR_LEAVE(fbuf_sc->fb_base, FB_SIZE, meta, ret, err); 452 453 err: 454 return (ret); 455 } 456 #endif 457 458 static const struct pci_devemu pci_fbuf = { 459 .pe_emu = "fbuf", 460 .pe_init = pci_fbuf_init, 461 .pe_barwrite = pci_fbuf_write, 462 .pe_barread = pci_fbuf_read, 463 .pe_baraddr = pci_fbuf_baraddr, 464 #ifdef BHYVE_SNAPSHOT 465 .pe_snapshot = pci_fbuf_snapshot, 466 #endif 467 }; 468 PCI_EMUL_SET(pci_fbuf); 469