1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2015 Nahanni Systems, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/types.h> 30 #include <sys/mman.h> 31 32 #include <machine/vmm.h> 33 #include <machine/vmm_snapshot.h> 34 #include <vmmapi.h> 35 36 #include <stdio.h> 37 #include <stdlib.h> 38 #include <string.h> 39 40 #include <errno.h> 41 #include <unistd.h> 42 43 #include "bhyvegc.h" 44 #include "bhyverun.h" 45 #include "config.h" 46 #include "debug.h" 47 #include "console.h" 48 #include "pci_emul.h" 49 #include "rfb.h" 50 #ifdef __amd64__ 51 #include "amd64/vga.h" 52 #endif 53 54 /* 55 * bhyve Framebuffer device emulation. 56 * BAR0 points to the current mode information. 57 * BAR1 is the 32-bit framebuffer address. 58 * 59 * -s <b>,fbuf,wait,vga=on|io|off,rfb=<ip>:port,w=width,h=height 60 */ 61 62 static int fbuf_debug = 1; 63 #define DEBUG_INFO 1 64 #define DEBUG_VERBOSE 4 65 #define DPRINTF(level, params) if (level <= fbuf_debug) PRINTLN params 66 67 68 #define KB (1024UL) 69 #define MB (1024 * 1024UL) 70 71 #define DMEMSZ 128 72 73 #define FB_SIZE (32*MB) 74 75 #define COLS_MAX 3840 76 #define ROWS_MAX 2160 77 78 #define COLS_DEFAULT 1024 79 #define ROWS_DEFAULT 768 80 81 #define COLS_MIN 640 82 #define ROWS_MIN 480 83 84 struct pci_fbuf_softc { 85 struct pci_devinst *fsc_pi; 86 struct { 87 uint32_t fbsize; 88 uint16_t width; 89 uint16_t height; 90 uint16_t depth; 91 uint16_t refreshrate; 92 uint8_t reserved[116]; 93 } __packed memregs; 94 95 /* rfb server */ 96 char *rfb_host; 97 char *rfb_password; 98 int rfb_port; 99 int rfb_wait; 100 int vga_enabled; 101 int vga_full; 102 103 uint32_t fbaddr; 104 char *fb_base; 105 uint16_t gc_width; 106 uint16_t gc_height; 107 void *vgasc; 108 struct bhyvegc_image *gc_image; 109 }; 110 111 static struct pci_fbuf_softc *fbuf_sc; 112 113 #define PCI_FBUF_MSI_MSGS 4 114 115 static void 116 pci_fbuf_write(struct pci_devinst *pi, int baridx, uint64_t offset, int size, 117 uint64_t value) 118 { 119 struct pci_fbuf_softc *sc; 120 uint8_t *p; 121 122 assert(baridx == 0); 123 124 sc = pi->pi_arg; 125 126 DPRINTF(DEBUG_VERBOSE, 127 ("fbuf wr: offset 0x%lx, size: %d, value: 0x%lx", 128 offset, size, value)); 129 130 if (offset + size > DMEMSZ) { 131 printf("fbuf: write too large, offset %ld size %d\n", 132 offset, size); 133 return; 134 } 135 136 p = (uint8_t *)&sc->memregs + offset; 137 138 switch (size) { 139 case 1: 140 *p = value; 141 break; 142 case 2: 143 *(uint16_t *)p = value; 144 break; 145 case 4: 146 *(uint32_t *)p = value; 147 break; 148 case 8: 149 *(uint64_t *)p = value; 150 break; 151 default: 152 printf("fbuf: write unknown size %d\n", size); 153 break; 154 } 155 156 if (!sc->gc_image->vgamode && sc->memregs.width == 0 && 157 sc->memregs.height == 0) { 158 DPRINTF(DEBUG_INFO, ("switching to VGA mode")); 159 sc->gc_image->vgamode = 1; 160 sc->gc_width = 0; 161 sc->gc_height = 0; 162 } else if (sc->gc_image->vgamode && sc->memregs.width != 0 && 163 sc->memregs.height != 0) { 164 DPRINTF(DEBUG_INFO, ("switching to VESA mode")); 165 sc->gc_image->vgamode = 0; 166 } 167 } 168 169 static uint64_t 170 pci_fbuf_read(struct pci_devinst *pi, int baridx, uint64_t offset, int size) 171 { 172 struct pci_fbuf_softc *sc; 173 uint8_t *p; 174 uint64_t value; 175 176 assert(baridx == 0); 177 178 sc = pi->pi_arg; 179 180 181 if (offset + size > DMEMSZ) { 182 printf("fbuf: read too large, offset %ld size %d\n", 183 offset, size); 184 return (0); 185 } 186 187 p = (uint8_t *)&sc->memregs + offset; 188 value = 0; 189 switch (size) { 190 case 1: 191 value = *p; 192 break; 193 case 2: 194 value = *(uint16_t *)p; 195 break; 196 case 4: 197 value = *(uint32_t *)p; 198 break; 199 case 8: 200 value = *(uint64_t *)p; 201 break; 202 default: 203 printf("fbuf: read unknown size %d\n", size); 204 break; 205 } 206 207 DPRINTF(DEBUG_VERBOSE, 208 ("fbuf rd: offset 0x%lx, size: %d, value: 0x%lx", 209 offset, size, value)); 210 211 return (value); 212 } 213 214 static void 215 pci_fbuf_baraddr(struct pci_devinst *pi, int baridx, int enabled, 216 uint64_t address) 217 { 218 struct pci_fbuf_softc *sc; 219 int prot; 220 221 if (baridx != 1) 222 return; 223 224 sc = pi->pi_arg; 225 if (!enabled) { 226 if (vm_munmap_memseg(pi->pi_vmctx, sc->fbaddr, FB_SIZE) != 0) 227 EPRINTLN("pci_fbuf: munmap_memseg failed"); 228 sc->fbaddr = 0; 229 } else { 230 prot = PROT_READ | PROT_WRITE; 231 if (vm_mmap_memseg(pi->pi_vmctx, address, VM_FRAMEBUFFER, 0, 232 FB_SIZE, prot) != 0) 233 EPRINTLN("pci_fbuf: mmap_memseg failed"); 234 else 235 sc->fbaddr = address; 236 } 237 } 238 239 240 static int 241 pci_fbuf_parse_config(struct pci_fbuf_softc *sc, nvlist_t *nvl) 242 { 243 const char *value; 244 char *cp; 245 246 sc->rfb_wait = get_config_bool_node_default(nvl, "wait", false); 247 248 /* Prefer "rfb" to "tcp". */ 249 value = get_config_value_node(nvl, "rfb"); 250 if (value == NULL) 251 value = get_config_value_node(nvl, "tcp"); 252 if (value != NULL) { 253 /* 254 * IPv4 -- host-ip:port 255 * IPv6 -- [host-ip%zone]:port 256 * XXX for now port is mandatory for IPv4. 257 */ 258 if (value[0] == '[') { 259 cp = strchr(value + 1, ']'); 260 if (cp == NULL || cp == value + 1) { 261 EPRINTLN("fbuf: Invalid IPv6 address: \"%s\"", 262 value); 263 return (-1); 264 } 265 sc->rfb_host = strndup(value + 1, cp - (value + 1)); 266 cp++; 267 if (*cp == ':') { 268 cp++; 269 if (*cp == '\0') { 270 EPRINTLN( 271 "fbuf: Missing port number: \"%s\"", 272 value); 273 return (-1); 274 } 275 sc->rfb_port = atoi(cp); 276 } else if (*cp != '\0') { 277 EPRINTLN("fbuf: Invalid IPv6 address: \"%s\"", 278 value); 279 return (-1); 280 } 281 } else { 282 cp = strchr(value, ':'); 283 if (cp == NULL) { 284 sc->rfb_port = atoi(value); 285 } else { 286 sc->rfb_host = strndup(value, cp - value); 287 cp++; 288 if (*cp == '\0') { 289 EPRINTLN( 290 "fbuf: Missing port number: \"%s\"", 291 value); 292 return (-1); 293 } 294 sc->rfb_port = atoi(cp); 295 } 296 } 297 } 298 299 value = get_config_value_node(nvl, "vga"); 300 if (value != NULL) { 301 if (strcmp(value, "off") == 0) { 302 sc->vga_enabled = 0; 303 } else if (strcmp(value, "io") == 0) { 304 sc->vga_enabled = 1; 305 sc->vga_full = 0; 306 } else if (strcmp(value, "on") == 0) { 307 sc->vga_enabled = 1; 308 sc->vga_full = 1; 309 } else { 310 EPRINTLN("fbuf: Invalid vga setting: \"%s\"", value); 311 return (-1); 312 } 313 } 314 315 value = get_config_value_node(nvl, "w"); 316 if (value != NULL) 317 sc->memregs.width = strtol(value, NULL, 10); 318 319 value = get_config_value_node(nvl, "h"); 320 if (value != NULL) 321 sc->memregs.height = strtol(value, NULL, 10); 322 323 if (sc->memregs.width > COLS_MAX || 324 sc->memregs.height > ROWS_MAX) { 325 EPRINTLN("fbuf: max resolution is %ux%u", COLS_MAX, ROWS_MAX); 326 return (-1); 327 } 328 if (sc->memregs.width < COLS_MIN || 329 sc->memregs.height < ROWS_MIN) { 330 EPRINTLN("fbuf: minimum resolution is %ux%u", 331 COLS_MIN, ROWS_MIN); 332 return (-1); 333 } 334 335 value = get_config_value_node(nvl, "password"); 336 if (value != NULL) 337 sc->rfb_password = strdup(value); 338 339 return (0); 340 } 341 342 static void 343 pci_fbuf_render(struct bhyvegc *gc, void *arg) 344 { 345 struct pci_fbuf_softc *sc; 346 347 sc = arg; 348 349 if (sc->vga_full && sc->gc_image->vgamode) { 350 /* TODO: mode switching to vga and vesa should use the special 351 * EFI-bhyve protocol port. 352 */ 353 vga_render(gc, sc->vgasc); 354 return; 355 } 356 if (sc->gc_width != sc->memregs.width || 357 sc->gc_height != sc->memregs.height) { 358 bhyvegc_resize(gc, sc->memregs.width, sc->memregs.height); 359 sc->gc_width = sc->memregs.width; 360 sc->gc_height = sc->memregs.height; 361 } 362 } 363 364 static int 365 pci_fbuf_init(struct pci_devinst *pi, nvlist_t *nvl) 366 { 367 int error; 368 struct pci_fbuf_softc *sc; 369 370 if (fbuf_sc != NULL) { 371 EPRINTLN("Only one frame buffer device is allowed."); 372 return (-1); 373 } 374 375 sc = calloc(1, sizeof(struct pci_fbuf_softc)); 376 377 pi->pi_arg = sc; 378 379 /* initialize config space */ 380 pci_set_cfgdata16(pi, PCIR_DEVICE, 0x40FB); 381 pci_set_cfgdata16(pi, PCIR_VENDOR, 0xFB5D); 382 pci_set_cfgdata8(pi, PCIR_CLASS, PCIC_DISPLAY); 383 pci_set_cfgdata8(pi, PCIR_SUBCLASS, PCIS_DISPLAY_VGA); 384 385 sc->fb_base = vm_create_devmem(pi->pi_vmctx, VM_FRAMEBUFFER, 386 "framebuffer", FB_SIZE); 387 if (sc->fb_base == MAP_FAILED) { 388 error = -1; 389 goto done; 390 } 391 392 error = pci_emul_alloc_bar(pi, 0, PCIBAR_MEM32, DMEMSZ); 393 assert(error == 0); 394 395 error = pci_emul_alloc_bar(pi, 1, PCIBAR_MEM32, FB_SIZE); 396 assert(error == 0); 397 398 error = pci_emul_add_msicap(pi, PCI_FBUF_MSI_MSGS); 399 assert(error == 0); 400 401 sc->memregs.fbsize = FB_SIZE; 402 sc->memregs.width = COLS_DEFAULT; 403 sc->memregs.height = ROWS_DEFAULT; 404 sc->memregs.depth = 32; 405 406 sc->vga_enabled = 1; 407 sc->vga_full = 0; 408 409 sc->fsc_pi = pi; 410 411 error = pci_fbuf_parse_config(sc, nvl); 412 if (error != 0) 413 goto done; 414 415 /* XXX until VGA rendering is enabled */ 416 if (sc->vga_full != 0) { 417 EPRINTLN("pci_fbuf: VGA rendering not enabled"); 418 goto done; 419 } 420 421 DPRINTF(DEBUG_INFO, ("fbuf frame buffer base: %p [sz %lu]", 422 sc->fb_base, FB_SIZE)); 423 424 console_init(sc->memregs.width, sc->memregs.height, sc->fb_base); 425 console_fb_register(pci_fbuf_render, sc); 426 427 if (sc->vga_enabled) 428 sc->vgasc = vga_init(!sc->vga_full); 429 sc->gc_image = console_get_image(); 430 431 fbuf_sc = sc; 432 433 memset((void *)sc->fb_base, 0, FB_SIZE); 434 435 error = rfb_init(sc->rfb_host, sc->rfb_port, sc->rfb_wait, sc->rfb_password); 436 done: 437 if (error) 438 free(sc); 439 440 return (error); 441 } 442 443 #ifdef BHYVE_SNAPSHOT 444 static int 445 pci_fbuf_snapshot(struct vm_snapshot_meta *meta) 446 { 447 int ret; 448 449 SNAPSHOT_BUF_OR_LEAVE(fbuf_sc->fb_base, FB_SIZE, meta, ret, err); 450 451 err: 452 return (ret); 453 } 454 #endif 455 456 static const struct pci_devemu pci_fbuf = { 457 .pe_emu = "fbuf", 458 .pe_init = pci_fbuf_init, 459 .pe_barwrite = pci_fbuf_write, 460 .pe_barread = pci_fbuf_read, 461 .pe_baraddr = pci_fbuf_baraddr, 462 #ifdef BHYVE_SNAPSHOT 463 .pe_snapshot = pci_fbuf_snapshot, 464 #endif 465 }; 466 PCI_EMUL_SET(pci_fbuf); 467