1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2015 Nahanni Systems, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 #include <sys/types.h> 31 #include <sys/mman.h> 32 33 #include <machine/vmm.h> 34 #include <machine/vmm_snapshot.h> 35 #include <vmmapi.h> 36 37 #include <stdio.h> 38 #include <stdlib.h> 39 #include <string.h> 40 41 #include <errno.h> 42 #include <unistd.h> 43 44 #include "bhyvegc.h" 45 #include "bhyverun.h" 46 #include "config.h" 47 #include "debug.h" 48 #include "console.h" 49 #include "pci_emul.h" 50 #include "rfb.h" 51 #ifdef __amd64__ 52 #include "amd64/vga.h" 53 #endif 54 55 /* 56 * bhyve Framebuffer device emulation. 57 * BAR0 points to the current mode information. 58 * BAR1 is the 32-bit framebuffer address. 59 * 60 * -s <b>,fbuf,wait,vga=on|io|off,rfb=<ip>:port,w=width,h=height 61 */ 62 63 static int fbuf_debug = 1; 64 #define DEBUG_INFO 1 65 #define DEBUG_VERBOSE 4 66 #define DPRINTF(level, params) if (level <= fbuf_debug) PRINTLN params 67 68 69 #define KB (1024UL) 70 #define MB (1024 * 1024UL) 71 72 #define DMEMSZ 128 73 74 #define FB_SIZE (16*MB) 75 76 #define COLS_MAX 1920 77 #define ROWS_MAX 1200 78 79 #define COLS_DEFAULT 1024 80 #define ROWS_DEFAULT 768 81 82 #define COLS_MIN 640 83 #define ROWS_MIN 480 84 85 struct pci_fbuf_softc { 86 struct pci_devinst *fsc_pi; 87 struct { 88 uint32_t fbsize; 89 uint16_t width; 90 uint16_t height; 91 uint16_t depth; 92 uint16_t refreshrate; 93 uint8_t reserved[116]; 94 } __packed memregs; 95 96 /* rfb server */ 97 char *rfb_host; 98 char *rfb_password; 99 int rfb_port; 100 int rfb_wait; 101 int vga_enabled; 102 int vga_full; 103 104 uint32_t fbaddr; 105 char *fb_base; 106 uint16_t gc_width; 107 uint16_t gc_height; 108 void *vgasc; 109 struct bhyvegc_image *gc_image; 110 }; 111 112 static struct pci_fbuf_softc *fbuf_sc; 113 114 #define PCI_FBUF_MSI_MSGS 4 115 116 static void 117 pci_fbuf_write(struct pci_devinst *pi, int baridx, uint64_t offset, int size, 118 uint64_t value) 119 { 120 struct pci_fbuf_softc *sc; 121 uint8_t *p; 122 123 assert(baridx == 0); 124 125 sc = pi->pi_arg; 126 127 DPRINTF(DEBUG_VERBOSE, 128 ("fbuf wr: offset 0x%lx, size: %d, value: 0x%lx", 129 offset, size, value)); 130 131 if (offset + size > DMEMSZ) { 132 printf("fbuf: write too large, offset %ld size %d\n", 133 offset, size); 134 return; 135 } 136 137 p = (uint8_t *)&sc->memregs + offset; 138 139 switch (size) { 140 case 1: 141 *p = value; 142 break; 143 case 2: 144 *(uint16_t *)p = value; 145 break; 146 case 4: 147 *(uint32_t *)p = value; 148 break; 149 case 8: 150 *(uint64_t *)p = value; 151 break; 152 default: 153 printf("fbuf: write unknown size %d\n", size); 154 break; 155 } 156 157 if (!sc->gc_image->vgamode && sc->memregs.width == 0 && 158 sc->memregs.height == 0) { 159 DPRINTF(DEBUG_INFO, ("switching to VGA mode")); 160 sc->gc_image->vgamode = 1; 161 sc->gc_width = 0; 162 sc->gc_height = 0; 163 } else if (sc->gc_image->vgamode && sc->memregs.width != 0 && 164 sc->memregs.height != 0) { 165 DPRINTF(DEBUG_INFO, ("switching to VESA mode")); 166 sc->gc_image->vgamode = 0; 167 } 168 } 169 170 static uint64_t 171 pci_fbuf_read(struct pci_devinst *pi, int baridx, uint64_t offset, int size) 172 { 173 struct pci_fbuf_softc *sc; 174 uint8_t *p; 175 uint64_t value; 176 177 assert(baridx == 0); 178 179 sc = pi->pi_arg; 180 181 182 if (offset + size > DMEMSZ) { 183 printf("fbuf: read too large, offset %ld size %d\n", 184 offset, size); 185 return (0); 186 } 187 188 p = (uint8_t *)&sc->memregs + offset; 189 value = 0; 190 switch (size) { 191 case 1: 192 value = *p; 193 break; 194 case 2: 195 value = *(uint16_t *)p; 196 break; 197 case 4: 198 value = *(uint32_t *)p; 199 break; 200 case 8: 201 value = *(uint64_t *)p; 202 break; 203 default: 204 printf("fbuf: read unknown size %d\n", size); 205 break; 206 } 207 208 DPRINTF(DEBUG_VERBOSE, 209 ("fbuf rd: offset 0x%lx, size: %d, value: 0x%lx", 210 offset, size, value)); 211 212 return (value); 213 } 214 215 static void 216 pci_fbuf_baraddr(struct pci_devinst *pi, int baridx, int enabled, 217 uint64_t address) 218 { 219 struct pci_fbuf_softc *sc; 220 int prot; 221 222 if (baridx != 1) 223 return; 224 225 sc = pi->pi_arg; 226 if (!enabled) { 227 if (vm_munmap_memseg(pi->pi_vmctx, sc->fbaddr, FB_SIZE) != 0) 228 EPRINTLN("pci_fbuf: munmap_memseg failed"); 229 sc->fbaddr = 0; 230 } else { 231 prot = PROT_READ | PROT_WRITE; 232 if (vm_mmap_memseg(pi->pi_vmctx, address, VM_FRAMEBUFFER, 0, 233 FB_SIZE, prot) != 0) 234 EPRINTLN("pci_fbuf: mmap_memseg failed"); 235 sc->fbaddr = address; 236 } 237 } 238 239 240 static int 241 pci_fbuf_parse_config(struct pci_fbuf_softc *sc, nvlist_t *nvl) 242 { 243 const char *value; 244 char *cp; 245 246 sc->rfb_wait = get_config_bool_node_default(nvl, "wait", false); 247 248 /* Prefer "rfb" to "tcp". */ 249 value = get_config_value_node(nvl, "rfb"); 250 if (value == NULL) 251 value = get_config_value_node(nvl, "tcp"); 252 if (value != NULL) { 253 /* 254 * IPv4 -- host-ip:port 255 * IPv6 -- [host-ip%zone]:port 256 * XXX for now port is mandatory for IPv4. 257 */ 258 if (value[0] == '[') { 259 cp = strchr(value + 1, ']'); 260 if (cp == NULL || cp == value + 1) { 261 EPRINTLN("fbuf: Invalid IPv6 address: \"%s\"", 262 value); 263 return (-1); 264 } 265 sc->rfb_host = strndup(value + 1, cp - (value + 1)); 266 cp++; 267 if (*cp == ':') { 268 cp++; 269 if (*cp == '\0') { 270 EPRINTLN( 271 "fbuf: Missing port number: \"%s\"", 272 value); 273 return (-1); 274 } 275 sc->rfb_port = atoi(cp); 276 } else if (*cp != '\0') { 277 EPRINTLN("fbuf: Invalid IPv6 address: \"%s\"", 278 value); 279 return (-1); 280 } 281 } else { 282 cp = strchr(value, ':'); 283 if (cp == NULL) { 284 sc->rfb_port = atoi(value); 285 } else { 286 sc->rfb_host = strndup(value, cp - value); 287 cp++; 288 if (*cp == '\0') { 289 EPRINTLN( 290 "fbuf: Missing port number: \"%s\"", 291 value); 292 return (-1); 293 } 294 sc->rfb_port = atoi(cp); 295 } 296 } 297 } 298 299 value = get_config_value_node(nvl, "vga"); 300 if (value != NULL) { 301 if (strcmp(value, "off") == 0) { 302 sc->vga_enabled = 0; 303 } else if (strcmp(value, "io") == 0) { 304 sc->vga_enabled = 1; 305 sc->vga_full = 0; 306 } else if (strcmp(value, "on") == 0) { 307 sc->vga_enabled = 1; 308 sc->vga_full = 1; 309 } else { 310 EPRINTLN("fbuf: Invalid vga setting: \"%s\"", value); 311 return (-1); 312 } 313 } 314 315 value = get_config_value_node(nvl, "w"); 316 if (value != NULL) { 317 sc->memregs.width = atoi(value); 318 if (sc->memregs.width > COLS_MAX) { 319 EPRINTLN("fbuf: width %d too large", sc->memregs.width); 320 return (-1); 321 } 322 if (sc->memregs.width == 0) 323 sc->memregs.width = 1920; 324 } 325 326 value = get_config_value_node(nvl, "h"); 327 if (value != NULL) { 328 sc->memregs.height = atoi(value); 329 if (sc->memregs.height > ROWS_MAX) { 330 EPRINTLN("fbuf: height %d too large", 331 sc->memregs.height); 332 return (-1); 333 } 334 if (sc->memregs.height == 0) 335 sc->memregs.height = 1080; 336 } 337 338 value = get_config_value_node(nvl, "password"); 339 if (value != NULL) 340 sc->rfb_password = strdup(value); 341 342 return (0); 343 } 344 345 static void 346 pci_fbuf_render(struct bhyvegc *gc, void *arg) 347 { 348 struct pci_fbuf_softc *sc; 349 350 sc = arg; 351 352 if (sc->vga_full && sc->gc_image->vgamode) { 353 /* TODO: mode switching to vga and vesa should use the special 354 * EFI-bhyve protocol port. 355 */ 356 vga_render(gc, sc->vgasc); 357 return; 358 } 359 if (sc->gc_width != sc->memregs.width || 360 sc->gc_height != sc->memregs.height) { 361 bhyvegc_resize(gc, sc->memregs.width, sc->memregs.height); 362 sc->gc_width = sc->memregs.width; 363 sc->gc_height = sc->memregs.height; 364 } 365 } 366 367 static int 368 pci_fbuf_init(struct pci_devinst *pi, nvlist_t *nvl) 369 { 370 int error; 371 struct pci_fbuf_softc *sc; 372 373 if (fbuf_sc != NULL) { 374 EPRINTLN("Only one frame buffer device is allowed."); 375 return (-1); 376 } 377 378 sc = calloc(1, sizeof(struct pci_fbuf_softc)); 379 380 pi->pi_arg = sc; 381 382 /* initialize config space */ 383 pci_set_cfgdata16(pi, PCIR_DEVICE, 0x40FB); 384 pci_set_cfgdata16(pi, PCIR_VENDOR, 0xFB5D); 385 pci_set_cfgdata8(pi, PCIR_CLASS, PCIC_DISPLAY); 386 pci_set_cfgdata8(pi, PCIR_SUBCLASS, PCIS_DISPLAY_VGA); 387 388 sc->fb_base = vm_create_devmem(pi->pi_vmctx, VM_FRAMEBUFFER, 389 "framebuffer", FB_SIZE); 390 if (sc->fb_base == MAP_FAILED) { 391 error = -1; 392 goto done; 393 } 394 395 error = pci_emul_alloc_bar(pi, 0, PCIBAR_MEM32, DMEMSZ); 396 assert(error == 0); 397 398 error = pci_emul_alloc_bar(pi, 1, PCIBAR_MEM32, FB_SIZE); 399 assert(error == 0); 400 401 error = pci_emul_add_msicap(pi, PCI_FBUF_MSI_MSGS); 402 assert(error == 0); 403 404 sc->memregs.fbsize = FB_SIZE; 405 sc->memregs.width = COLS_DEFAULT; 406 sc->memregs.height = ROWS_DEFAULT; 407 sc->memregs.depth = 32; 408 409 sc->vga_enabled = 1; 410 sc->vga_full = 0; 411 412 sc->fsc_pi = pi; 413 414 error = pci_fbuf_parse_config(sc, nvl); 415 if (error != 0) 416 goto done; 417 418 /* XXX until VGA rendering is enabled */ 419 if (sc->vga_full != 0) { 420 EPRINTLN("pci_fbuf: VGA rendering not enabled"); 421 goto done; 422 } 423 424 DPRINTF(DEBUG_INFO, ("fbuf frame buffer base: %p [sz %lu]", 425 sc->fb_base, FB_SIZE)); 426 427 console_init(sc->memregs.width, sc->memregs.height, sc->fb_base); 428 console_fb_register(pci_fbuf_render, sc); 429 430 if (sc->vga_enabled) 431 sc->vgasc = vga_init(!sc->vga_full); 432 sc->gc_image = console_get_image(); 433 434 fbuf_sc = sc; 435 436 memset((void *)sc->fb_base, 0, FB_SIZE); 437 438 error = rfb_init(sc->rfb_host, sc->rfb_port, sc->rfb_wait, sc->rfb_password); 439 done: 440 if (error) 441 free(sc); 442 443 return (error); 444 } 445 446 #ifdef BHYVE_SNAPSHOT 447 static int 448 pci_fbuf_snapshot(struct vm_snapshot_meta *meta) 449 { 450 int ret; 451 452 SNAPSHOT_BUF_OR_LEAVE(fbuf_sc->fb_base, FB_SIZE, meta, ret, err); 453 454 err: 455 return (ret); 456 } 457 #endif 458 459 static const struct pci_devemu pci_fbuf = { 460 .pe_emu = "fbuf", 461 .pe_init = pci_fbuf_init, 462 .pe_barwrite = pci_fbuf_write, 463 .pe_barread = pci_fbuf_read, 464 .pe_baraddr = pci_fbuf_baraddr, 465 #ifdef BHYVE_SNAPSHOT 466 .pe_snapshot = pci_fbuf_snapshot, 467 #endif 468 }; 469 PCI_EMUL_SET(pci_fbuf); 470