1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2011 NetApp, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #ifndef _PCI_EMUL_H_ 30 #define _PCI_EMUL_H_ 31 32 #include <sys/types.h> 33 #include <sys/queue.h> 34 #include <sys/kernel.h> 35 #include <sys/nv.h> 36 #include <sys/pciio.h> 37 #include <sys/_pthreadtypes.h> 38 39 #include <dev/pci/pcireg.h> 40 41 #include <assert.h> 42 43 #define PCI_BARMAX PCIR_MAX_BAR_0 /* BAR registers in a Type 0 header */ 44 #define PCI_BARMAX_WITH_ROM (PCI_BARMAX + 1) 45 #define PCI_ROM_IDX (PCI_BARMAX + 1) 46 47 struct vmctx; 48 struct pci_devinst; 49 struct memory_region; 50 struct vm_snapshot_meta; 51 52 struct pci_devemu { 53 const char *pe_emu; /* Name of device emulation */ 54 55 /* instance creation */ 56 int (*pe_init)(struct pci_devinst *, nvlist_t *); 57 int (*pe_legacy_config)(nvlist_t *, const char *); 58 const char *pe_alias; 59 60 /* ACPI DSDT enumeration */ 61 void (*pe_write_dsdt)(struct pci_devinst *); 62 63 /* config space read/write callbacks */ 64 int (*pe_cfgwrite)(struct pci_devinst *pi, int offset, 65 int bytes, uint32_t val); 66 int (*pe_cfgread)(struct pci_devinst *pi, int offset, 67 int bytes, uint32_t *retval); 68 69 /* BAR read/write callbacks */ 70 void (*pe_barwrite)(struct pci_devinst *pi, int baridx, 71 uint64_t offset, int size, uint64_t value); 72 uint64_t (*pe_barread)(struct pci_devinst *pi, int baridx, 73 uint64_t offset, int size); 74 75 void (*pe_baraddr)(struct pci_devinst *pi, 76 int baridx, int enabled, uint64_t address); 77 78 /* Save/restore device state */ 79 int (*pe_snapshot)(struct vm_snapshot_meta *meta); 80 int (*pe_pause)(struct pci_devinst *pi); 81 int (*pe_resume)(struct pci_devinst *pi); 82 83 }; 84 #define PCI_EMUL_SET(x) DATA_SET(pci_devemu_set, x) 85 86 enum pcibar_type { 87 PCIBAR_NONE, 88 PCIBAR_IO, 89 PCIBAR_MEM32, 90 PCIBAR_MEM64, 91 PCIBAR_MEMHI64, 92 PCIBAR_ROM, 93 }; 94 95 struct pcibar { 96 enum pcibar_type type; /* io or memory */ 97 uint64_t size; 98 uint64_t addr; 99 uint8_t lobits; 100 }; 101 102 #define PI_NAMESZ 40 103 104 struct msix_table_entry { 105 uint64_t addr; 106 uint32_t msg_data; 107 uint32_t vector_control; 108 } __packed; 109 110 /* 111 * In case the structure is modified to hold extra information, use a define 112 * for the size that should be emulated. 113 */ 114 #define MSIX_TABLE_ENTRY_SIZE 16 115 #define MAX_MSIX_TABLE_ENTRIES 2048 116 #define PBA_SIZE(msgnum) (roundup2((msgnum), 64) / 8) 117 118 struct pci_devinst { 119 struct pci_devemu *pi_d; 120 struct vmctx *pi_vmctx; 121 uint8_t pi_bus, pi_slot, pi_func; 122 char pi_name[PI_NAMESZ]; 123 int pi_bar_getsize; 124 int pi_prevcap; 125 int pi_capend; 126 127 #ifdef __amd64__ 128 struct { 129 int8_t pin; 130 enum { 131 IDLE, 132 ASSERTED, 133 PENDING, 134 } state; 135 int pirq_pin; 136 int ioapic_irq; 137 pthread_mutex_t lock; 138 } pi_lintr; 139 #endif 140 141 struct { 142 int enabled; 143 uint64_t addr; 144 uint64_t msg_data; 145 int maxmsgnum; 146 } pi_msi; 147 148 struct { 149 int enabled; 150 int table_bar; 151 int pba_bar; 152 uint32_t table_offset; 153 int table_count; 154 uint32_t pba_offset; 155 int pba_size; 156 int function_mask; 157 struct msix_table_entry *table; /* allocated at runtime */ 158 uint8_t *mapped_addr; 159 size_t mapped_size; 160 } pi_msix; 161 162 void *pi_arg; /* devemu-private data */ 163 164 u_char pi_cfgdata[PCI_REGMAX + 1]; 165 /* ROM is handled like a BAR */ 166 struct pcibar pi_bar[PCI_BARMAX_WITH_ROM + 1]; 167 uint64_t pi_romoffset; 168 }; 169 170 struct msicap { 171 uint8_t capid; 172 uint8_t nextptr; 173 uint16_t msgctrl; 174 uint32_t addrlo; 175 uint32_t addrhi; 176 uint16_t msgdata; 177 } __packed; 178 static_assert(sizeof(struct msicap) == 14, "compile-time assertion failed"); 179 180 struct msixcap { 181 uint8_t capid; 182 uint8_t nextptr; 183 uint16_t msgctrl; 184 uint32_t table_info; /* bar index and offset within it */ 185 uint32_t pba_info; /* bar index and offset within it */ 186 } __packed; 187 static_assert(sizeof(struct msixcap) == 12, "compile-time assertion failed"); 188 189 struct pciecap { 190 uint8_t capid; 191 uint8_t nextptr; 192 uint16_t pcie_capabilities; 193 194 uint32_t dev_capabilities; /* all devices */ 195 uint16_t dev_control; 196 uint16_t dev_status; 197 198 uint32_t link_capabilities; /* devices with links */ 199 uint16_t link_control; 200 uint16_t link_status; 201 202 uint32_t slot_capabilities; /* ports with slots */ 203 uint16_t slot_control; 204 uint16_t slot_status; 205 206 uint16_t root_control; /* root ports */ 207 uint16_t root_capabilities; 208 uint32_t root_status; 209 210 uint32_t dev_capabilities2; /* all devices */ 211 uint16_t dev_control2; 212 uint16_t dev_status2; 213 214 uint32_t link_capabilities2; /* devices with links */ 215 uint16_t link_control2; 216 uint16_t link_status2; 217 218 uint32_t slot_capabilities2; /* ports with slots */ 219 uint16_t slot_control2; 220 uint16_t slot_status2; 221 } __packed; 222 static_assert(sizeof(struct pciecap) == 60, "compile-time assertion failed"); 223 224 #ifdef __amd64__ 225 typedef void (*pci_lintr_cb)(int b, int s, int pin, int pirq_pin, 226 int ioapic_irq, void *arg); 227 void pci_lintr_assert(struct pci_devinst *pi); 228 void pci_lintr_deassert(struct pci_devinst *pi); 229 void pci_lintr_request(struct pci_devinst *pi); 230 int pci_count_lintr(int bus); 231 void pci_walk_lintr(int bus, pci_lintr_cb cb, void *arg); 232 #endif 233 234 int init_pci(struct vmctx *ctx); 235 void pci_callback(void); 236 uint32_t pci_config_read_reg(const struct pcisel *host_sel, nvlist_t *nvl, 237 uint32_t reg, uint8_t size, uint32_t def); 238 int pci_emul_alloc_bar(struct pci_devinst *pdi, int idx, 239 enum pcibar_type type, uint64_t size); 240 int pci_emul_alloc_rom(struct pci_devinst *const pdi, const uint64_t size, 241 void **const addr); 242 int pci_emul_add_boot_device(struct pci_devinst *const pi, 243 const int bootindex); 244 int pci_emul_add_msicap(struct pci_devinst *pi, int msgnum); 245 int pci_emul_add_pciecap(struct pci_devinst *pi, int pcie_device_type); 246 void pci_emul_capwrite(struct pci_devinst *pi, int offset, int bytes, 247 uint32_t val, uint8_t capoff, int capid); 248 void pci_emul_cmd_changed(struct pci_devinst *pi, uint16_t old); 249 void pci_generate_msi(struct pci_devinst *pi, int msgnum); 250 void pci_generate_msix(struct pci_devinst *pi, int msgnum); 251 int pci_msi_enabled(struct pci_devinst *pi); 252 int pci_msix_enabled(struct pci_devinst *pi); 253 int pci_msix_table_bar(struct pci_devinst *pi); 254 int pci_msix_pba_bar(struct pci_devinst *pi); 255 int pci_msi_maxmsgnum(struct pci_devinst *pi); 256 int pci_parse_legacy_config(nvlist_t *nvl, const char *opt); 257 int pci_parse_slot(char *opt); 258 void pci_print_supported_devices(void); 259 void pci_populate_msicap(struct msicap *cap, int msgs, int nextptr); 260 int pci_emul_add_msixcap(struct pci_devinst *pi, int msgnum, int barnum); 261 int pci_emul_msix_twrite(struct pci_devinst *pi, uint64_t offset, int size, 262 uint64_t value); 263 uint64_t pci_emul_msix_tread(struct pci_devinst *pi, uint64_t offset, int size); 264 void pci_write_dsdt(void); 265 uint64_t pci_ecfg_base(void); 266 int pci_bus_configured(int bus); 267 268 #ifdef BHYVE_SNAPSHOT 269 struct pci_devinst *pci_next(const struct pci_devinst *cursor); 270 int pci_snapshot(struct vm_snapshot_meta *meta); 271 int pci_pause(struct pci_devinst *pdi); 272 int pci_resume(struct pci_devinst *pdi); 273 #endif 274 275 static __inline void 276 pci_set_cfgdata8(struct pci_devinst *pi, int offset, uint8_t val) 277 { 278 assert(offset <= PCI_REGMAX); 279 *(uint8_t *)(pi->pi_cfgdata + offset) = val; 280 } 281 282 static __inline void 283 pci_set_cfgdata16(struct pci_devinst *pi, int offset, uint16_t val) 284 { 285 assert(offset <= (PCI_REGMAX - 1) && (offset & 1) == 0); 286 *(uint16_t *)(pi->pi_cfgdata + offset) = val; 287 } 288 289 static __inline void 290 pci_set_cfgdata32(struct pci_devinst *pi, int offset, uint32_t val) 291 { 292 assert(offset <= (PCI_REGMAX - 3) && (offset & 3) == 0); 293 *(uint32_t *)(pi->pi_cfgdata + offset) = val; 294 } 295 296 static __inline uint8_t 297 pci_get_cfgdata8(struct pci_devinst *pi, int offset) 298 { 299 assert(offset <= PCI_REGMAX); 300 return (*(uint8_t *)(pi->pi_cfgdata + offset)); 301 } 302 303 static __inline uint16_t 304 pci_get_cfgdata16(struct pci_devinst *pi, int offset) 305 { 306 assert(offset <= (PCI_REGMAX - 1) && (offset & 1) == 0); 307 return (*(uint16_t *)(pi->pi_cfgdata + offset)); 308 } 309 310 static __inline uint32_t 311 pci_get_cfgdata32(struct pci_devinst *pi, int offset) 312 { 313 assert(offset <= (PCI_REGMAX - 3) && (offset & 3) == 0); 314 return (*(uint32_t *)(pi->pi_cfgdata + offset)); 315 } 316 317 #endif /* _PCI_EMUL_H_ */ 318