1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2011 NetApp, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 */ 30 31 #ifndef _PCI_EMUL_H_ 32 #define _PCI_EMUL_H_ 33 34 #include <sys/types.h> 35 #include <sys/queue.h> 36 #include <sys/kernel.h> 37 #include <sys/nv.h> 38 #include <sys/_pthreadtypes.h> 39 40 #include <dev/pci/pcireg.h> 41 42 #include <assert.h> 43 44 #define PCI_BARMAX PCIR_MAX_BAR_0 /* BAR registers in a Type 0 header */ 45 #define PCI_BARMAX_WITH_ROM (PCI_BARMAX + 1) 46 #define PCI_ROM_IDX (PCI_BARMAX + 1) 47 48 struct vmctx; 49 struct pci_devinst; 50 struct memory_region; 51 struct vm_snapshot_meta; 52 53 struct pci_devemu { 54 const char *pe_emu; /* Name of device emulation */ 55 56 /* instance creation */ 57 int (*pe_init)(struct pci_devinst *, nvlist_t *); 58 int (*pe_legacy_config)(nvlist_t *, const char *); 59 const char *pe_alias; 60 61 /* ACPI DSDT enumeration */ 62 void (*pe_write_dsdt)(struct pci_devinst *); 63 64 /* config space read/write callbacks */ 65 int (*pe_cfgwrite)(struct pci_devinst *pi, int offset, 66 int bytes, uint32_t val); 67 int (*pe_cfgread)(struct pci_devinst *pi, int offset, 68 int bytes, uint32_t *retval); 69 70 /* BAR read/write callbacks */ 71 void (*pe_barwrite)(struct pci_devinst *pi, int baridx, 72 uint64_t offset, int size, uint64_t value); 73 uint64_t (*pe_barread)(struct pci_devinst *pi, int baridx, 74 uint64_t offset, int size); 75 76 void (*pe_baraddr)(struct pci_devinst *pi, 77 int baridx, int enabled, uint64_t address); 78 79 /* Save/restore device state */ 80 int (*pe_snapshot)(struct vm_snapshot_meta *meta); 81 int (*pe_pause)(struct pci_devinst *pi); 82 int (*pe_resume)(struct pci_devinst *pi); 83 84 }; 85 #define PCI_EMUL_SET(x) DATA_SET(pci_devemu_set, x); 86 87 enum pcibar_type { 88 PCIBAR_NONE, 89 PCIBAR_IO, 90 PCIBAR_MEM32, 91 PCIBAR_MEM64, 92 PCIBAR_MEMHI64, 93 PCIBAR_ROM, 94 }; 95 96 struct pcibar { 97 enum pcibar_type type; /* io or memory */ 98 uint64_t size; 99 uint64_t addr; 100 uint8_t lobits; 101 }; 102 103 #define PI_NAMESZ 40 104 105 struct msix_table_entry { 106 uint64_t addr; 107 uint32_t msg_data; 108 uint32_t vector_control; 109 } __packed; 110 111 /* 112 * In case the structure is modified to hold extra information, use a define 113 * for the size that should be emulated. 114 */ 115 #define MSIX_TABLE_ENTRY_SIZE 16 116 #define MAX_MSIX_TABLE_ENTRIES 2048 117 #define PBA_SIZE(msgnum) (roundup2((msgnum), 64) / 8) 118 119 enum lintr_stat { 120 IDLE, 121 ASSERTED, 122 PENDING 123 }; 124 125 struct pci_devinst { 126 struct pci_devemu *pi_d; 127 struct vmctx *pi_vmctx; 128 uint8_t pi_bus, pi_slot, pi_func; 129 char pi_name[PI_NAMESZ]; 130 int pi_bar_getsize; 131 int pi_prevcap; 132 int pi_capend; 133 134 struct { 135 int8_t pin; 136 enum lintr_stat state; 137 int pirq_pin; 138 int ioapic_irq; 139 pthread_mutex_t lock; 140 } pi_lintr; 141 142 struct { 143 int enabled; 144 uint64_t addr; 145 uint64_t msg_data; 146 int maxmsgnum; 147 } pi_msi; 148 149 struct { 150 int enabled; 151 int table_bar; 152 int pba_bar; 153 uint32_t table_offset; 154 int table_count; 155 uint32_t pba_offset; 156 int pba_size; 157 int function_mask; 158 struct msix_table_entry *table; /* allocated at runtime */ 159 uint8_t *mapped_addr; 160 size_t mapped_size; 161 } pi_msix; 162 163 void *pi_arg; /* devemu-private data */ 164 165 u_char pi_cfgdata[PCI_REGMAX + 1]; 166 /* ROM is handled like a BAR */ 167 struct pcibar pi_bar[PCI_BARMAX_WITH_ROM + 1]; 168 uint64_t pi_romoffset; 169 }; 170 171 struct msicap { 172 uint8_t capid; 173 uint8_t nextptr; 174 uint16_t msgctrl; 175 uint32_t addrlo; 176 uint32_t addrhi; 177 uint16_t msgdata; 178 } __packed; 179 static_assert(sizeof(struct msicap) == 14, "compile-time assertion failed"); 180 181 struct msixcap { 182 uint8_t capid; 183 uint8_t nextptr; 184 uint16_t msgctrl; 185 uint32_t table_info; /* bar index and offset within it */ 186 uint32_t pba_info; /* bar index and offset within it */ 187 } __packed; 188 static_assert(sizeof(struct msixcap) == 12, "compile-time assertion failed"); 189 190 struct pciecap { 191 uint8_t capid; 192 uint8_t nextptr; 193 uint16_t pcie_capabilities; 194 195 uint32_t dev_capabilities; /* all devices */ 196 uint16_t dev_control; 197 uint16_t dev_status; 198 199 uint32_t link_capabilities; /* devices with links */ 200 uint16_t link_control; 201 uint16_t link_status; 202 203 uint32_t slot_capabilities; /* ports with slots */ 204 uint16_t slot_control; 205 uint16_t slot_status; 206 207 uint16_t root_control; /* root ports */ 208 uint16_t root_capabilities; 209 uint32_t root_status; 210 211 uint32_t dev_capabilities2; /* all devices */ 212 uint16_t dev_control2; 213 uint16_t dev_status2; 214 215 uint32_t link_capabilities2; /* devices with links */ 216 uint16_t link_control2; 217 uint16_t link_status2; 218 219 uint32_t slot_capabilities2; /* ports with slots */ 220 uint16_t slot_control2; 221 uint16_t slot_status2; 222 } __packed; 223 static_assert(sizeof(struct pciecap) == 60, "compile-time assertion failed"); 224 225 typedef void (*pci_lintr_cb)(int b, int s, int pin, int pirq_pin, 226 int ioapic_irq, void *arg); 227 228 int init_pci(struct vmctx *ctx); 229 void pci_callback(void); 230 int pci_emul_alloc_bar(struct pci_devinst *pdi, int idx, 231 enum pcibar_type type, uint64_t size); 232 int pci_emul_alloc_rom(struct pci_devinst *const pdi, const uint64_t size, 233 void **const addr); 234 int pci_emul_add_msicap(struct pci_devinst *pi, int msgnum); 235 int pci_emul_add_pciecap(struct pci_devinst *pi, int pcie_device_type); 236 void pci_emul_capwrite(struct pci_devinst *pi, int offset, int bytes, 237 uint32_t val, uint8_t capoff, int capid); 238 void pci_emul_cmd_changed(struct pci_devinst *pi, uint16_t old); 239 void pci_generate_msi(struct pci_devinst *pi, int msgnum); 240 void pci_generate_msix(struct pci_devinst *pi, int msgnum); 241 void pci_lintr_assert(struct pci_devinst *pi); 242 void pci_lintr_deassert(struct pci_devinst *pi); 243 void pci_lintr_request(struct pci_devinst *pi); 244 int pci_msi_enabled(struct pci_devinst *pi); 245 int pci_msix_enabled(struct pci_devinst *pi); 246 int pci_msix_table_bar(struct pci_devinst *pi); 247 int pci_msix_pba_bar(struct pci_devinst *pi); 248 int pci_msi_maxmsgnum(struct pci_devinst *pi); 249 int pci_parse_legacy_config(nvlist_t *nvl, const char *opt); 250 int pci_parse_slot(char *opt); 251 void pci_print_supported_devices(void); 252 void pci_populate_msicap(struct msicap *cap, int msgs, int nextptr); 253 int pci_emul_add_msixcap(struct pci_devinst *pi, int msgnum, int barnum); 254 int pci_emul_msix_twrite(struct pci_devinst *pi, uint64_t offset, int size, 255 uint64_t value); 256 uint64_t pci_emul_msix_tread(struct pci_devinst *pi, uint64_t offset, int size); 257 int pci_count_lintr(int bus); 258 void pci_walk_lintr(int bus, pci_lintr_cb cb, void *arg); 259 void pci_write_dsdt(void); 260 uint64_t pci_ecfg_base(void); 261 int pci_bus_configured(int bus); 262 #ifdef BHYVE_SNAPSHOT 263 int pci_snapshot(struct vm_snapshot_meta *meta); 264 int pci_pause(const char *dev_name); 265 int pci_resume(const char *dev_name); 266 #endif 267 268 static __inline void 269 pci_set_cfgdata8(struct pci_devinst *pi, int offset, uint8_t val) 270 { 271 assert(offset <= PCI_REGMAX); 272 *(uint8_t *)(pi->pi_cfgdata + offset) = val; 273 } 274 275 static __inline void 276 pci_set_cfgdata16(struct pci_devinst *pi, int offset, uint16_t val) 277 { 278 assert(offset <= (PCI_REGMAX - 1) && (offset & 1) == 0); 279 *(uint16_t *)(pi->pi_cfgdata + offset) = val; 280 } 281 282 static __inline void 283 pci_set_cfgdata32(struct pci_devinst *pi, int offset, uint32_t val) 284 { 285 assert(offset <= (PCI_REGMAX - 3) && (offset & 3) == 0); 286 *(uint32_t *)(pi->pi_cfgdata + offset) = val; 287 } 288 289 static __inline uint8_t 290 pci_get_cfgdata8(struct pci_devinst *pi, int offset) 291 { 292 assert(offset <= PCI_REGMAX); 293 return (*(uint8_t *)(pi->pi_cfgdata + offset)); 294 } 295 296 static __inline uint16_t 297 pci_get_cfgdata16(struct pci_devinst *pi, int offset) 298 { 299 assert(offset <= (PCI_REGMAX - 1) && (offset & 1) == 0); 300 return (*(uint16_t *)(pi->pi_cfgdata + offset)); 301 } 302 303 static __inline uint32_t 304 pci_get_cfgdata32(struct pci_devinst *pi, int offset) 305 { 306 assert(offset <= (PCI_REGMAX - 3) && (offset & 3) == 0); 307 return (*(uint32_t *)(pi->pi_cfgdata + offset)); 308 } 309 310 #endif /* _PCI_EMUL_H_ */ 311