xref: /freebsd/usr.sbin/bhyve/pci_emul.h (revision a5921bc3653e2e286715e6fe8d473ec0d02da38c)
1 /*-
2  * Copyright (c) 2011 NetApp, Inc.
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
7  * are met:
8  * 1. Redistributions of source code must retain the above copyright
9  *    notice, this list of conditions and the following disclaimer.
10  * 2. Redistributions in binary form must reproduce the above copyright
11  *    notice, this list of conditions and the following disclaimer in the
12  *    documentation and/or other materials provided with the distribution.
13  *
14  * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17  * ARE DISCLAIMED.  IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24  * SUCH DAMAGE.
25  *
26  * $FreeBSD$
27  */
28 
29 #ifndef _PCI_EMUL_H_
30 #define _PCI_EMUL_H_
31 
32 #include <sys/types.h>
33 #include <sys/queue.h>
34 #include <sys/kernel.h>
35 #include <sys/_pthreadtypes.h>
36 
37 #include <dev/pci/pcireg.h>
38 
39 #include <assert.h>
40 
41 #define	PCI_BARMAX	PCIR_MAX_BAR_0	/* BAR registers in a Type 0 header */
42 
43 struct vmctx;
44 struct pci_devinst;
45 struct memory_region;
46 
47 struct pci_devemu {
48 	char      *pe_emu;		/* Name of device emulation */
49 
50 	/* instance creation */
51 	int       (*pe_init)(struct vmctx *, struct pci_devinst *,
52 			     char *opts);
53 
54 	/* ACPI DSDT enumeration */
55 	void	(*pe_write_dsdt)(struct pci_devinst *);
56 
57 	/* config space read/write callbacks */
58 	int	(*pe_cfgwrite)(struct vmctx *ctx, int vcpu,
59 			       struct pci_devinst *pi, int offset,
60 			       int bytes, uint32_t val);
61 	int	(*pe_cfgread)(struct vmctx *ctx, int vcpu,
62 			      struct pci_devinst *pi, int offset,
63 			      int bytes, uint32_t *retval);
64 
65 	/* BAR read/write callbacks */
66 	void      (*pe_barwrite)(struct vmctx *ctx, int vcpu,
67 				 struct pci_devinst *pi, int baridx,
68 				 uint64_t offset, int size, uint64_t value);
69 	uint64_t  (*pe_barread)(struct vmctx *ctx, int vcpu,
70 				struct pci_devinst *pi, int baridx,
71 				uint64_t offset, int size);
72 };
73 #define PCI_EMUL_SET(x)   DATA_SET(pci_devemu_set, x);
74 
75 enum pcibar_type {
76 	PCIBAR_NONE,
77 	PCIBAR_IO,
78 	PCIBAR_MEM32,
79 	PCIBAR_MEM64,
80 	PCIBAR_MEMHI64
81 };
82 
83 struct pcibar {
84 	enum pcibar_type	type;		/* io or memory */
85 	uint64_t		size;
86 	uint64_t		addr;
87 };
88 
89 #define PI_NAMESZ	40
90 
91 struct msix_table_entry {
92 	uint64_t	addr;
93 	uint32_t	msg_data;
94 	uint32_t	vector_control;
95 } __packed;
96 
97 /*
98  * In case the structure is modified to hold extra information, use a define
99  * for the size that should be emulated.
100  */
101 #define	MSIX_TABLE_ENTRY_SIZE	16
102 #define MAX_MSIX_TABLE_ENTRIES	2048
103 #define	PBA_SIZE(msgnum)	(roundup2((msgnum), 64) / 8)
104 
105 enum lintr_stat {
106 	IDLE,
107 	ASSERTED,
108 	PENDING
109 };
110 
111 struct pci_devinst {
112 	struct pci_devemu *pi_d;
113 	struct vmctx *pi_vmctx;
114 	uint8_t	  pi_bus, pi_slot, pi_func;
115 	char	  pi_name[PI_NAMESZ];
116 	int	  pi_bar_getsize;
117 	int	  pi_prevcap;
118 	int	  pi_capend;
119 
120 	struct {
121 		int8_t    	pin;
122 		enum lintr_stat	state;
123 		int		pirq_pin;
124 		int	  	ioapic_irq;
125 		pthread_mutex_t	lock;
126 	} pi_lintr;
127 
128 	struct {
129 		int		enabled;
130 		uint64_t	addr;
131 		uint64_t	msg_data;
132 		int		maxmsgnum;
133 	} pi_msi;
134 
135 	struct {
136 		int	enabled;
137 		int	table_bar;
138 		int	pba_bar;
139 		uint32_t table_offset;
140 		int	table_count;
141 		uint32_t pba_offset;
142 		int	pba_size;
143 		int	function_mask;
144 		struct msix_table_entry *table;	/* allocated at runtime */
145 		void	*pba_page;
146 		int	pba_page_offset;
147 	} pi_msix;
148 
149 	void      *pi_arg;		/* devemu-private data */
150 
151 	u_char	  pi_cfgdata[PCI_REGMAX + 1];
152 	struct pcibar pi_bar[PCI_BARMAX + 1];
153 };
154 
155 struct msicap {
156 	uint8_t		capid;
157 	uint8_t		nextptr;
158 	uint16_t	msgctrl;
159 	uint32_t	addrlo;
160 	uint32_t	addrhi;
161 	uint16_t	msgdata;
162 } __packed;
163 
164 struct msixcap {
165 	uint8_t		capid;
166 	uint8_t		nextptr;
167 	uint16_t	msgctrl;
168 	uint32_t	table_info;	/* bar index and offset within it */
169 	uint32_t	pba_info;	/* bar index and offset within it */
170 } __packed;
171 
172 struct pciecap {
173 	uint8_t		capid;
174 	uint8_t		nextptr;
175 	uint16_t	pcie_capabilities;
176 
177 	uint32_t	dev_capabilities;	/* all devices */
178 	uint16_t	dev_control;
179 	uint16_t	dev_status;
180 
181 	uint32_t	link_capabilities;	/* devices with links */
182 	uint16_t	link_control;
183 	uint16_t	link_status;
184 
185 	uint32_t	slot_capabilities;	/* ports with slots */
186 	uint16_t	slot_control;
187 	uint16_t	slot_status;
188 
189 	uint16_t	root_control;		/* root ports */
190 	uint16_t	root_capabilities;
191 	uint32_t	root_status;
192 
193 	uint32_t	dev_capabilities2;	/* all devices */
194 	uint16_t	dev_control2;
195 	uint16_t	dev_status2;
196 
197 	uint32_t	link_capabilities2;	/* devices with links */
198 	uint16_t	link_control2;
199 	uint16_t	link_status2;
200 
201 	uint32_t	slot_capabilities2;	/* ports with slots */
202 	uint16_t	slot_control2;
203 	uint16_t	slot_status2;
204 } __packed;
205 
206 typedef void (*pci_lintr_cb)(int b, int s, int pin, int pirq_pin,
207     int ioapic_irq, void *arg);
208 
209 int	init_pci(struct vmctx *ctx);
210 void	msicap_cfgwrite(struct pci_devinst *pi, int capoff, int offset,
211 	    int bytes, uint32_t val);
212 void	msixcap_cfgwrite(struct pci_devinst *pi, int capoff, int offset,
213 	    int bytes, uint32_t val);
214 void	pci_callback(void);
215 int	pci_emul_alloc_bar(struct pci_devinst *pdi, int idx,
216 	    enum pcibar_type type, uint64_t size);
217 int	pci_emul_alloc_pbar(struct pci_devinst *pdi, int idx,
218 	    uint64_t hostbase, enum pcibar_type type, uint64_t size);
219 int	pci_emul_add_msicap(struct pci_devinst *pi, int msgnum);
220 int	pci_emul_add_pciecap(struct pci_devinst *pi, int pcie_device_type);
221 void	pci_generate_msi(struct pci_devinst *pi, int msgnum);
222 void	pci_generate_msix(struct pci_devinst *pi, int msgnum);
223 void	pci_lintr_assert(struct pci_devinst *pi);
224 void	pci_lintr_deassert(struct pci_devinst *pi);
225 void	pci_lintr_request(struct pci_devinst *pi);
226 int	pci_msi_enabled(struct pci_devinst *pi);
227 int	pci_msix_enabled(struct pci_devinst *pi);
228 int	pci_msix_table_bar(struct pci_devinst *pi);
229 int	pci_msix_pba_bar(struct pci_devinst *pi);
230 int	pci_msi_msgnum(struct pci_devinst *pi);
231 int	pci_parse_slot(char *opt);
232 void	pci_populate_msicap(struct msicap *cap, int msgs, int nextptr);
233 int	pci_emul_add_msixcap(struct pci_devinst *pi, int msgnum, int barnum);
234 int	pci_emul_msix_twrite(struct pci_devinst *pi, uint64_t offset, int size,
235 			     uint64_t value);
236 uint64_t pci_emul_msix_tread(struct pci_devinst *pi, uint64_t offset, int size);
237 int	pci_count_lintr(int bus);
238 void	pci_walk_lintr(int bus, pci_lintr_cb cb, void *arg);
239 void	pci_write_dsdt(void);
240 uint64_t pci_ecfg_base(void);
241 int	pci_bus_configured(int bus);
242 
243 static __inline void
244 pci_set_cfgdata8(struct pci_devinst *pi, int offset, uint8_t val)
245 {
246 	assert(offset <= PCI_REGMAX);
247 	*(uint8_t *)(pi->pi_cfgdata + offset) = val;
248 }
249 
250 static __inline void
251 pci_set_cfgdata16(struct pci_devinst *pi, int offset, uint16_t val)
252 {
253 	assert(offset <= (PCI_REGMAX - 1) && (offset & 1) == 0);
254 	*(uint16_t *)(pi->pi_cfgdata + offset) = val;
255 }
256 
257 static __inline void
258 pci_set_cfgdata32(struct pci_devinst *pi, int offset, uint32_t val)
259 {
260 	assert(offset <= (PCI_REGMAX - 3) && (offset & 3) == 0);
261 	*(uint32_t *)(pi->pi_cfgdata + offset) = val;
262 }
263 
264 static __inline uint8_t
265 pci_get_cfgdata8(struct pci_devinst *pi, int offset)
266 {
267 	assert(offset <= PCI_REGMAX);
268 	return (*(uint8_t *)(pi->pi_cfgdata + offset));
269 }
270 
271 static __inline uint16_t
272 pci_get_cfgdata16(struct pci_devinst *pi, int offset)
273 {
274 	assert(offset <= (PCI_REGMAX - 1) && (offset & 1) == 0);
275 	return (*(uint16_t *)(pi->pi_cfgdata + offset));
276 }
277 
278 static __inline uint32_t
279 pci_get_cfgdata32(struct pci_devinst *pi, int offset)
280 {
281 	assert(offset <= (PCI_REGMAX - 3) && (offset & 3) == 0);
282 	return (*(uint32_t *)(pi->pi_cfgdata + offset));
283 }
284 
285 #endif /* _PCI_EMUL_H_ */
286