1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2011 NetApp, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 */ 30 31 #ifndef _PCI_EMUL_H_ 32 #define _PCI_EMUL_H_ 33 34 #include <sys/types.h> 35 #include <sys/queue.h> 36 #include <sys/kernel.h> 37 #include <sys/nv.h> 38 #include <sys/_pthreadtypes.h> 39 40 #include <dev/pci/pcireg.h> 41 42 #include <assert.h> 43 44 #define PCI_BARMAX PCIR_MAX_BAR_0 /* BAR registers in a Type 0 header */ 45 #define PCI_BARMAX_WITH_ROM (PCI_BARMAX + 1) 46 #define PCI_ROM_IDX (PCI_BARMAX + 1) 47 48 struct vmctx; 49 struct pci_devinst; 50 struct memory_region; 51 struct vm_snapshot_meta; 52 53 struct pci_devemu { 54 char *pe_emu; /* Name of device emulation */ 55 56 /* instance creation */ 57 int (*pe_init)(struct vmctx *, struct pci_devinst *, 58 nvlist_t *); 59 int (*pe_legacy_config)(nvlist_t *, const char *); 60 const char *pe_alias; 61 62 /* ACPI DSDT enumeration */ 63 void (*pe_write_dsdt)(struct pci_devinst *); 64 65 /* config space read/write callbacks */ 66 int (*pe_cfgwrite)(struct vmctx *ctx, int vcpu, 67 struct pci_devinst *pi, int offset, 68 int bytes, uint32_t val); 69 int (*pe_cfgread)(struct vmctx *ctx, int vcpu, 70 struct pci_devinst *pi, int offset, 71 int bytes, uint32_t *retval); 72 73 /* BAR read/write callbacks */ 74 void (*pe_barwrite)(struct vmctx *ctx, int vcpu, 75 struct pci_devinst *pi, int baridx, 76 uint64_t offset, int size, uint64_t value); 77 uint64_t (*pe_barread)(struct vmctx *ctx, int vcpu, 78 struct pci_devinst *pi, int baridx, 79 uint64_t offset, int size); 80 81 void (*pe_baraddr)(struct vmctx *ctx, struct pci_devinst *pi, 82 int baridx, int enabled, uint64_t address); 83 84 /* Save/restore device state */ 85 int (*pe_snapshot)(struct vm_snapshot_meta *meta); 86 int (*pe_pause)(struct vmctx *ctx, struct pci_devinst *pi); 87 int (*pe_resume)(struct vmctx *ctx, struct pci_devinst *pi); 88 89 }; 90 #define PCI_EMUL_SET(x) DATA_SET(pci_devemu_set, x); 91 92 enum pcibar_type { 93 PCIBAR_NONE, 94 PCIBAR_IO, 95 PCIBAR_MEM32, 96 PCIBAR_MEM64, 97 PCIBAR_MEMHI64, 98 PCIBAR_ROM, 99 }; 100 101 struct pcibar { 102 enum pcibar_type type; /* io or memory */ 103 uint64_t size; 104 uint64_t addr; 105 uint8_t lobits; 106 }; 107 108 #define PI_NAMESZ 40 109 110 struct msix_table_entry { 111 uint64_t addr; 112 uint32_t msg_data; 113 uint32_t vector_control; 114 } __packed; 115 116 /* 117 * In case the structure is modified to hold extra information, use a define 118 * for the size that should be emulated. 119 */ 120 #define MSIX_TABLE_ENTRY_SIZE 16 121 #define MAX_MSIX_TABLE_ENTRIES 2048 122 #define PBA_SIZE(msgnum) (roundup2((msgnum), 64) / 8) 123 124 enum lintr_stat { 125 IDLE, 126 ASSERTED, 127 PENDING 128 }; 129 130 struct pci_devinst { 131 struct pci_devemu *pi_d; 132 struct vmctx *pi_vmctx; 133 uint8_t pi_bus, pi_slot, pi_func; 134 char pi_name[PI_NAMESZ]; 135 int pi_bar_getsize; 136 int pi_prevcap; 137 int pi_capend; 138 139 struct { 140 int8_t pin; 141 enum lintr_stat state; 142 int pirq_pin; 143 int ioapic_irq; 144 pthread_mutex_t lock; 145 } pi_lintr; 146 147 struct { 148 int enabled; 149 uint64_t addr; 150 uint64_t msg_data; 151 int maxmsgnum; 152 } pi_msi; 153 154 struct { 155 int enabled; 156 int table_bar; 157 int pba_bar; 158 uint32_t table_offset; 159 int table_count; 160 uint32_t pba_offset; 161 int pba_size; 162 int function_mask; 163 struct msix_table_entry *table; /* allocated at runtime */ 164 uint8_t *mapped_addr; 165 size_t mapped_size; 166 } pi_msix; 167 168 void *pi_arg; /* devemu-private data */ 169 170 u_char pi_cfgdata[PCI_REGMAX + 1]; 171 /* ROM is handled like a BAR */ 172 struct pcibar pi_bar[PCI_BARMAX_WITH_ROM + 1]; 173 uint64_t pi_romoffset; 174 }; 175 176 struct msicap { 177 uint8_t capid; 178 uint8_t nextptr; 179 uint16_t msgctrl; 180 uint32_t addrlo; 181 uint32_t addrhi; 182 uint16_t msgdata; 183 } __packed; 184 static_assert(sizeof(struct msicap) == 14, "compile-time assertion failed"); 185 186 struct msixcap { 187 uint8_t capid; 188 uint8_t nextptr; 189 uint16_t msgctrl; 190 uint32_t table_info; /* bar index and offset within it */ 191 uint32_t pba_info; /* bar index and offset within it */ 192 } __packed; 193 static_assert(sizeof(struct msixcap) == 12, "compile-time assertion failed"); 194 195 struct pciecap { 196 uint8_t capid; 197 uint8_t nextptr; 198 uint16_t pcie_capabilities; 199 200 uint32_t dev_capabilities; /* all devices */ 201 uint16_t dev_control; 202 uint16_t dev_status; 203 204 uint32_t link_capabilities; /* devices with links */ 205 uint16_t link_control; 206 uint16_t link_status; 207 208 uint32_t slot_capabilities; /* ports with slots */ 209 uint16_t slot_control; 210 uint16_t slot_status; 211 212 uint16_t root_control; /* root ports */ 213 uint16_t root_capabilities; 214 uint32_t root_status; 215 216 uint32_t dev_capabilities2; /* all devices */ 217 uint16_t dev_control2; 218 uint16_t dev_status2; 219 220 uint32_t link_capabilities2; /* devices with links */ 221 uint16_t link_control2; 222 uint16_t link_status2; 223 224 uint32_t slot_capabilities2; /* ports with slots */ 225 uint16_t slot_control2; 226 uint16_t slot_status2; 227 } __packed; 228 static_assert(sizeof(struct pciecap) == 60, "compile-time assertion failed"); 229 230 typedef void (*pci_lintr_cb)(int b, int s, int pin, int pirq_pin, 231 int ioapic_irq, void *arg); 232 233 int init_pci(struct vmctx *ctx); 234 void pci_callback(void); 235 int pci_emul_alloc_bar(struct pci_devinst *pdi, int idx, 236 enum pcibar_type type, uint64_t size); 237 int pci_emul_alloc_rom(struct pci_devinst *const pdi, const uint64_t size, 238 void **const addr); 239 int pci_emul_add_msicap(struct pci_devinst *pi, int msgnum); 240 int pci_emul_add_pciecap(struct pci_devinst *pi, int pcie_device_type); 241 void pci_emul_capwrite(struct pci_devinst *pi, int offset, int bytes, 242 uint32_t val, uint8_t capoff, int capid); 243 void pci_emul_cmd_changed(struct pci_devinst *pi, uint16_t old); 244 void pci_generate_msi(struct pci_devinst *pi, int msgnum); 245 void pci_generate_msix(struct pci_devinst *pi, int msgnum); 246 void pci_lintr_assert(struct pci_devinst *pi); 247 void pci_lintr_deassert(struct pci_devinst *pi); 248 void pci_lintr_request(struct pci_devinst *pi); 249 int pci_msi_enabled(struct pci_devinst *pi); 250 int pci_msix_enabled(struct pci_devinst *pi); 251 int pci_msix_table_bar(struct pci_devinst *pi); 252 int pci_msix_pba_bar(struct pci_devinst *pi); 253 int pci_msi_maxmsgnum(struct pci_devinst *pi); 254 int pci_parse_legacy_config(nvlist_t *nvl, const char *opt); 255 int pci_parse_slot(char *opt); 256 void pci_print_supported_devices(); 257 void pci_populate_msicap(struct msicap *cap, int msgs, int nextptr); 258 int pci_emul_add_msixcap(struct pci_devinst *pi, int msgnum, int barnum); 259 int pci_emul_msix_twrite(struct pci_devinst *pi, uint64_t offset, int size, 260 uint64_t value); 261 uint64_t pci_emul_msix_tread(struct pci_devinst *pi, uint64_t offset, int size); 262 int pci_count_lintr(int bus); 263 void pci_walk_lintr(int bus, pci_lintr_cb cb, void *arg); 264 void pci_write_dsdt(void); 265 uint64_t pci_ecfg_base(void); 266 int pci_bus_configured(int bus); 267 #ifdef BHYVE_SNAPSHOT 268 int pci_snapshot(struct vm_snapshot_meta *meta); 269 int pci_pause(struct vmctx *ctx, const char *dev_name); 270 int pci_resume(struct vmctx *ctx, const char *dev_name); 271 #endif 272 273 static __inline void 274 pci_set_cfgdata8(struct pci_devinst *pi, int offset, uint8_t val) 275 { 276 assert(offset <= PCI_REGMAX); 277 *(uint8_t *)(pi->pi_cfgdata + offset) = val; 278 } 279 280 static __inline void 281 pci_set_cfgdata16(struct pci_devinst *pi, int offset, uint16_t val) 282 { 283 assert(offset <= (PCI_REGMAX - 1) && (offset & 1) == 0); 284 *(uint16_t *)(pi->pi_cfgdata + offset) = val; 285 } 286 287 static __inline void 288 pci_set_cfgdata32(struct pci_devinst *pi, int offset, uint32_t val) 289 { 290 assert(offset <= (PCI_REGMAX - 3) && (offset & 3) == 0); 291 *(uint32_t *)(pi->pi_cfgdata + offset) = val; 292 } 293 294 static __inline uint8_t 295 pci_get_cfgdata8(struct pci_devinst *pi, int offset) 296 { 297 assert(offset <= PCI_REGMAX); 298 return (*(uint8_t *)(pi->pi_cfgdata + offset)); 299 } 300 301 static __inline uint16_t 302 pci_get_cfgdata16(struct pci_devinst *pi, int offset) 303 { 304 assert(offset <= (PCI_REGMAX - 1) && (offset & 1) == 0); 305 return (*(uint16_t *)(pi->pi_cfgdata + offset)); 306 } 307 308 static __inline uint32_t 309 pci_get_cfgdata32(struct pci_devinst *pi, int offset) 310 { 311 assert(offset <= (PCI_REGMAX - 3) && (offset & 3) == 0); 312 return (*(uint32_t *)(pi->pi_cfgdata + offset)); 313 } 314 315 #endif /* _PCI_EMUL_H_ */ 316