xref: /freebsd/usr.sbin/bhyve/pci_emul.h (revision 621b5090487de9fed1b503769702a9a2a27cc7bb)
1 /*-
2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3  *
4  * Copyright (c) 2011 NetApp, Inc.
5  * All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  * 1. Redistributions of source code must retain the above copyright
11  *    notice, this list of conditions and the following disclaimer.
12  * 2. Redistributions in binary form must reproduce the above copyright
13  *    notice, this list of conditions and the following disclaimer in the
14  *    documentation and/or other materials provided with the distribution.
15  *
16  * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19  * ARE DISCLAIMED.  IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
20  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26  * SUCH DAMAGE.
27  *
28  * $FreeBSD$
29  */
30 
31 #ifndef _PCI_EMUL_H_
32 #define _PCI_EMUL_H_
33 
34 #include <sys/types.h>
35 #include <sys/queue.h>
36 #include <sys/kernel.h>
37 #include <sys/nv.h>
38 #include <sys/_pthreadtypes.h>
39 
40 #include <dev/pci/pcireg.h>
41 
42 #include <assert.h>
43 
44 #define	PCI_BARMAX	PCIR_MAX_BAR_0	/* BAR registers in a Type 0 header */
45 
46 struct vmctx;
47 struct pci_devinst;
48 struct memory_region;
49 struct vm_snapshot_meta;
50 
51 struct pci_devemu {
52 	char      *pe_emu;		/* Name of device emulation */
53 
54 	/* instance creation */
55 	int       (*pe_init)(struct vmctx *, struct pci_devinst *,
56 			     nvlist_t *);
57 	int	(*pe_legacy_config)(nvlist_t *, const char *);
58 	const char *pe_alias;
59 
60 	/* ACPI DSDT enumeration */
61 	void	(*pe_write_dsdt)(struct pci_devinst *);
62 
63 	/* config space read/write callbacks */
64 	int	(*pe_cfgwrite)(struct vmctx *ctx, int vcpu,
65 			       struct pci_devinst *pi, int offset,
66 			       int bytes, uint32_t val);
67 	int	(*pe_cfgread)(struct vmctx *ctx, int vcpu,
68 			      struct pci_devinst *pi, int offset,
69 			      int bytes, uint32_t *retval);
70 
71 	/* BAR read/write callbacks */
72 	void      (*pe_barwrite)(struct vmctx *ctx, int vcpu,
73 				 struct pci_devinst *pi, int baridx,
74 				 uint64_t offset, int size, uint64_t value);
75 	uint64_t  (*pe_barread)(struct vmctx *ctx, int vcpu,
76 				struct pci_devinst *pi, int baridx,
77 				uint64_t offset, int size);
78 
79 	/* Save/restore device state */
80 	int	(*pe_snapshot)(struct vm_snapshot_meta *meta);
81 	int	(*pe_pause)(struct vmctx *ctx, struct pci_devinst *pi);
82 	int	(*pe_resume)(struct vmctx *ctx, struct pci_devinst *pi);
83 
84 };
85 #define PCI_EMUL_SET(x)   DATA_SET(pci_devemu_set, x);
86 
87 enum pcibar_type {
88 	PCIBAR_NONE,
89 	PCIBAR_IO,
90 	PCIBAR_MEM32,
91 	PCIBAR_MEM64,
92 	PCIBAR_MEMHI64
93 };
94 
95 struct pcibar {
96 	enum pcibar_type	type;		/* io or memory */
97 	uint64_t		size;
98 	uint64_t		addr;
99 };
100 
101 #define PI_NAMESZ	40
102 
103 struct msix_table_entry {
104 	uint64_t	addr;
105 	uint32_t	msg_data;
106 	uint32_t	vector_control;
107 } __packed;
108 
109 /*
110  * In case the structure is modified to hold extra information, use a define
111  * for the size that should be emulated.
112  */
113 #define	MSIX_TABLE_ENTRY_SIZE	16
114 #define MAX_MSIX_TABLE_ENTRIES	2048
115 #define	PBA_SIZE(msgnum)	(roundup2((msgnum), 64) / 8)
116 
117 enum lintr_stat {
118 	IDLE,
119 	ASSERTED,
120 	PENDING
121 };
122 
123 struct pci_devinst {
124 	struct pci_devemu *pi_d;
125 	struct vmctx *pi_vmctx;
126 	uint8_t	  pi_bus, pi_slot, pi_func;
127 	char	  pi_name[PI_NAMESZ];
128 	int	  pi_bar_getsize;
129 	int	  pi_prevcap;
130 	int	  pi_capend;
131 
132 	struct {
133 		int8_t    	pin;
134 		enum lintr_stat	state;
135 		int		pirq_pin;
136 		int	  	ioapic_irq;
137 		pthread_mutex_t	lock;
138 	} pi_lintr;
139 
140 	struct {
141 		int		enabled;
142 		uint64_t	addr;
143 		uint64_t	msg_data;
144 		int		maxmsgnum;
145 	} pi_msi;
146 
147 	struct {
148 		int	enabled;
149 		int	table_bar;
150 		int	pba_bar;
151 		uint32_t table_offset;
152 		int	table_count;
153 		uint32_t pba_offset;
154 		int	pba_size;
155 		int	function_mask;
156 		struct msix_table_entry *table;	/* allocated at runtime */
157 		void	*pba_page;
158 		int	pba_page_offset;
159 	} pi_msix;
160 
161 	void      *pi_arg;		/* devemu-private data */
162 
163 	u_char	  pi_cfgdata[PCI_REGMAX + 1];
164 	struct pcibar pi_bar[PCI_BARMAX + 1];
165 };
166 
167 struct msicap {
168 	uint8_t		capid;
169 	uint8_t		nextptr;
170 	uint16_t	msgctrl;
171 	uint32_t	addrlo;
172 	uint32_t	addrhi;
173 	uint16_t	msgdata;
174 } __packed;
175 static_assert(sizeof(struct msicap) == 14, "compile-time assertion failed");
176 
177 struct msixcap {
178 	uint8_t		capid;
179 	uint8_t		nextptr;
180 	uint16_t	msgctrl;
181 	uint32_t	table_info;	/* bar index and offset within it */
182 	uint32_t	pba_info;	/* bar index and offset within it */
183 } __packed;
184 static_assert(sizeof(struct msixcap) == 12, "compile-time assertion failed");
185 
186 struct pciecap {
187 	uint8_t		capid;
188 	uint8_t		nextptr;
189 	uint16_t	pcie_capabilities;
190 
191 	uint32_t	dev_capabilities;	/* all devices */
192 	uint16_t	dev_control;
193 	uint16_t	dev_status;
194 
195 	uint32_t	link_capabilities;	/* devices with links */
196 	uint16_t	link_control;
197 	uint16_t	link_status;
198 
199 	uint32_t	slot_capabilities;	/* ports with slots */
200 	uint16_t	slot_control;
201 	uint16_t	slot_status;
202 
203 	uint16_t	root_control;		/* root ports */
204 	uint16_t	root_capabilities;
205 	uint32_t	root_status;
206 
207 	uint32_t	dev_capabilities2;	/* all devices */
208 	uint16_t	dev_control2;
209 	uint16_t	dev_status2;
210 
211 	uint32_t	link_capabilities2;	/* devices with links */
212 	uint16_t	link_control2;
213 	uint16_t	link_status2;
214 
215 	uint32_t	slot_capabilities2;	/* ports with slots */
216 	uint16_t	slot_control2;
217 	uint16_t	slot_status2;
218 } __packed;
219 static_assert(sizeof(struct pciecap) == 60, "compile-time assertion failed");
220 
221 typedef void (*pci_lintr_cb)(int b, int s, int pin, int pirq_pin,
222     int ioapic_irq, void *arg);
223 
224 int	init_pci(struct vmctx *ctx);
225 void	pci_callback(void);
226 int	pci_emul_alloc_bar(struct pci_devinst *pdi, int idx,
227 	    enum pcibar_type type, uint64_t size);
228 int	pci_emul_add_msicap(struct pci_devinst *pi, int msgnum);
229 int	pci_emul_add_pciecap(struct pci_devinst *pi, int pcie_device_type);
230 void	pci_emul_capwrite(struct pci_devinst *pi, int offset, int bytes,
231 	    uint32_t val, uint8_t capoff, int capid);
232 void	pci_emul_cmd_changed(struct pci_devinst *pi, uint16_t old);
233 void	pci_generate_msi(struct pci_devinst *pi, int msgnum);
234 void	pci_generate_msix(struct pci_devinst *pi, int msgnum);
235 void	pci_lintr_assert(struct pci_devinst *pi);
236 void	pci_lintr_deassert(struct pci_devinst *pi);
237 void	pci_lintr_request(struct pci_devinst *pi);
238 int	pci_msi_enabled(struct pci_devinst *pi);
239 int	pci_msix_enabled(struct pci_devinst *pi);
240 int	pci_msix_table_bar(struct pci_devinst *pi);
241 int	pci_msix_pba_bar(struct pci_devinst *pi);
242 int	pci_msi_maxmsgnum(struct pci_devinst *pi);
243 int	pci_parse_legacy_config(nvlist_t *nvl, const char *opt);
244 int	pci_parse_slot(char *opt);
245 void    pci_print_supported_devices();
246 void	pci_populate_msicap(struct msicap *cap, int msgs, int nextptr);
247 int	pci_emul_add_msixcap(struct pci_devinst *pi, int msgnum, int barnum);
248 int	pci_emul_msix_twrite(struct pci_devinst *pi, uint64_t offset, int size,
249 			     uint64_t value);
250 uint64_t pci_emul_msix_tread(struct pci_devinst *pi, uint64_t offset, int size);
251 int	pci_count_lintr(int bus);
252 void	pci_walk_lintr(int bus, pci_lintr_cb cb, void *arg);
253 void	pci_write_dsdt(void);
254 uint64_t pci_ecfg_base(void);
255 int	pci_bus_configured(int bus);
256 #ifdef BHYVE_SNAPSHOT
257 int	pci_snapshot(struct vm_snapshot_meta *meta);
258 int	pci_pause(struct vmctx *ctx, const char *dev_name);
259 int	pci_resume(struct vmctx *ctx, const char *dev_name);
260 #endif
261 
262 static __inline void
263 pci_set_cfgdata8(struct pci_devinst *pi, int offset, uint8_t val)
264 {
265 	assert(offset <= PCI_REGMAX);
266 	*(uint8_t *)(pi->pi_cfgdata + offset) = val;
267 }
268 
269 static __inline void
270 pci_set_cfgdata16(struct pci_devinst *pi, int offset, uint16_t val)
271 {
272 	assert(offset <= (PCI_REGMAX - 1) && (offset & 1) == 0);
273 	*(uint16_t *)(pi->pi_cfgdata + offset) = val;
274 }
275 
276 static __inline void
277 pci_set_cfgdata32(struct pci_devinst *pi, int offset, uint32_t val)
278 {
279 	assert(offset <= (PCI_REGMAX - 3) && (offset & 3) == 0);
280 	*(uint32_t *)(pi->pi_cfgdata + offset) = val;
281 }
282 
283 static __inline uint8_t
284 pci_get_cfgdata8(struct pci_devinst *pi, int offset)
285 {
286 	assert(offset <= PCI_REGMAX);
287 	return (*(uint8_t *)(pi->pi_cfgdata + offset));
288 }
289 
290 static __inline uint16_t
291 pci_get_cfgdata16(struct pci_devinst *pi, int offset)
292 {
293 	assert(offset <= (PCI_REGMAX - 1) && (offset & 1) == 0);
294 	return (*(uint16_t *)(pi->pi_cfgdata + offset));
295 }
296 
297 static __inline uint32_t
298 pci_get_cfgdata32(struct pci_devinst *pi, int offset)
299 {
300 	assert(offset <= (PCI_REGMAX - 3) && (offset & 3) == 0);
301 	return (*(uint32_t *)(pi->pi_cfgdata + offset));
302 }
303 
304 #endif /* _PCI_EMUL_H_ */
305