1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2011 NetApp, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/param.h> 30 #include <sys/linker_set.h> 31 #include <sys/mman.h> 32 33 #include <ctype.h> 34 #include <err.h> 35 #include <errno.h> 36 #include <pthread.h> 37 #include <stdio.h> 38 #include <stdlib.h> 39 #include <string.h> 40 #include <strings.h> 41 #include <assert.h> 42 #include <stdbool.h> 43 #include <sysexits.h> 44 45 #include <machine/vmm.h> 46 #include <machine/vmm_snapshot.h> 47 #include <vmmapi.h> 48 49 #include "acpi.h" 50 #include "bhyverun.h" 51 #include "config.h" 52 #include "debug.h" 53 #ifdef __amd64__ 54 #include "amd64/inout.h" 55 #include "amd64/ioapic.h" 56 #endif 57 #include "mem.h" 58 #include "pci_emul.h" 59 #ifdef __amd64__ 60 #include "amd64/pci_irq.h" 61 #include "amd64/pci_lpc.h" 62 #endif 63 #include "pci_passthru.h" 64 #include "qemu_fwcfg.h" 65 66 #define CONF1_ADDR_PORT 0x0cf8 67 #define CONF1_DATA_PORT 0x0cfc 68 69 #define CONF1_ENABLE 0x80000000ul 70 71 #define MAXBUSES (PCI_BUSMAX + 1) 72 #define MAXSLOTS (PCI_SLOTMAX + 1) 73 #define MAXFUNCS (PCI_FUNCMAX + 1) 74 75 #define GB (1024 * 1024 * 1024UL) 76 77 struct funcinfo { 78 nvlist_t *fi_config; 79 struct pci_devemu *fi_pde; 80 struct pci_devinst *fi_devi; 81 }; 82 83 struct intxinfo { 84 int ii_count; 85 int ii_pirq_pin; 86 int ii_ioapic_irq; 87 }; 88 89 struct slotinfo { 90 struct intxinfo si_intpins[4]; 91 struct funcinfo si_funcs[MAXFUNCS]; 92 }; 93 94 struct businfo { 95 uint16_t iobase, iolimit; /* I/O window */ 96 uint32_t membase32, memlimit32; /* mmio window below 4GB */ 97 uint64_t membase64, memlimit64; /* mmio window above 4GB */ 98 struct slotinfo slotinfo[MAXSLOTS]; 99 }; 100 101 static struct businfo *pci_businfo[MAXBUSES]; 102 103 SET_DECLARE(pci_devemu_set, struct pci_devemu); 104 105 static uint64_t pci_emul_iobase; 106 static uint8_t *pci_emul_rombase; 107 static uint64_t pci_emul_romoffset; 108 static uint8_t *pci_emul_romlim; 109 static uint64_t pci_emul_membase32; 110 static uint64_t pci_emul_membase64; 111 static uint64_t pci_emul_memlim64; 112 113 struct pci_bar_allocation { 114 TAILQ_ENTRY(pci_bar_allocation) chain; 115 struct pci_devinst *pdi; 116 int idx; 117 enum pcibar_type type; 118 uint64_t size; 119 }; 120 121 static TAILQ_HEAD(pci_bar_list, pci_bar_allocation) pci_bars = 122 TAILQ_HEAD_INITIALIZER(pci_bars); 123 124 struct boot_device { 125 TAILQ_ENTRY(boot_device) boot_device_chain; 126 struct pci_devinst *pdi; 127 int bootindex; 128 }; 129 static TAILQ_HEAD(boot_list, boot_device) boot_devices = TAILQ_HEAD_INITIALIZER( 130 boot_devices); 131 132 #define PCI_EMUL_IOBASE 0x2000 133 #define PCI_EMUL_IOLIMIT 0x10000 134 135 #define PCI_EMUL_ROMSIZE 0x10000000 136 137 #define PCI_EMUL_ECFG_BASE 0xE0000000 /* 3.5GB */ 138 #define PCI_EMUL_ECFG_SIZE (MAXBUSES * 1024 * 1024) /* 1MB per bus */ 139 SYSRES_MEM(PCI_EMUL_ECFG_BASE, PCI_EMUL_ECFG_SIZE); 140 141 /* 142 * OVMF always uses 0xC0000000 as base address for 32 bit PCI MMIO. Don't 143 * change this address without changing it in OVMF. 144 */ 145 #define PCI_EMUL_MEMBASE32 0xC0000000 146 #define PCI_EMUL_MEMLIMIT32 PCI_EMUL_ECFG_BASE 147 #define PCI_EMUL_MEMSIZE64 (32*GB) 148 149 #ifdef __amd64__ 150 static void pci_lintr_route(struct pci_devinst *pi); 151 static void pci_lintr_update(struct pci_devinst *pi); 152 #endif 153 154 static struct pci_devemu *pci_emul_finddev(const char *name); 155 static void pci_cfgrw(int in, int bus, int slot, int func, int coff, 156 int bytes, uint32_t *val); 157 158 static __inline void 159 CFGWRITE(struct pci_devinst *pi, int coff, uint32_t val, int bytes) 160 { 161 162 if (bytes == 1) 163 pci_set_cfgdata8(pi, coff, val); 164 else if (bytes == 2) 165 pci_set_cfgdata16(pi, coff, val); 166 else 167 pci_set_cfgdata32(pi, coff, val); 168 } 169 170 static __inline uint32_t 171 CFGREAD(struct pci_devinst *pi, int coff, int bytes) 172 { 173 174 if (bytes == 1) 175 return (pci_get_cfgdata8(pi, coff)); 176 else if (bytes == 2) 177 return (pci_get_cfgdata16(pi, coff)); 178 else 179 return (pci_get_cfgdata32(pi, coff)); 180 } 181 182 static int 183 is_pcir_bar(int coff) 184 { 185 return (coff >= PCIR_BAR(0) && coff < PCIR_BAR(PCI_BARMAX + 1)); 186 } 187 188 static int 189 is_pcir_bios(int coff) 190 { 191 return (coff >= PCIR_BIOS && coff < PCIR_BIOS + 4); 192 } 193 194 /* 195 * I/O access 196 */ 197 198 /* 199 * Slot options are in the form: 200 * 201 * <bus>:<slot>:<func>,<emul>[,<config>] 202 * <slot>[:<func>],<emul>[,<config>] 203 * 204 * slot is 0..31 205 * func is 0..7 206 * emul is a string describing the type of PCI device e.g. virtio-net 207 * config is an optional string, depending on the device, that can be 208 * used for configuration. 209 * Examples are: 210 * 1,virtio-net,tap0 211 * 3:0,dummy 212 */ 213 static void 214 pci_parse_slot_usage(char *aopt) 215 { 216 217 EPRINTLN("Invalid PCI slot info field \"%s\"", aopt); 218 } 219 220 /* 221 * Helper function to parse a list of comma-separated options where 222 * each option is formatted as "name[=value]". If no value is 223 * provided, the option is treated as a boolean and is given a value 224 * of true. 225 */ 226 int 227 pci_parse_legacy_config(nvlist_t *nvl, const char *opt) 228 { 229 char *config, *name, *tofree, *value; 230 231 if (opt == NULL) 232 return (0); 233 234 config = tofree = strdup(opt); 235 while ((name = strsep(&config, ",")) != NULL) { 236 value = strchr(name, '='); 237 if (value != NULL) { 238 *value = '\0'; 239 value++; 240 set_config_value_node(nvl, name, value); 241 } else 242 set_config_bool_node(nvl, name, true); 243 } 244 free(tofree); 245 return (0); 246 } 247 248 /* 249 * PCI device configuration is stored in MIBs that encode the device's 250 * location: 251 * 252 * pci.<bus>.<slot>.<func> 253 * 254 * Where "bus", "slot", and "func" are all decimal values without 255 * leading zeroes. Each valid device must have a "device" node which 256 * identifies the driver model of the device. 257 * 258 * Device backends can provide a parser for the "config" string. If 259 * a custom parser is not provided, pci_parse_legacy_config() is used 260 * to parse the string. 261 */ 262 int 263 pci_parse_slot(char *opt) 264 { 265 char node_name[sizeof("pci.XXX.XX.X")]; 266 struct pci_devemu *pde; 267 char *emul, *config, *str, *cp; 268 int error, bnum, snum, fnum; 269 nvlist_t *nvl; 270 271 error = -1; 272 str = strdup(opt); 273 274 emul = config = NULL; 275 if ((cp = strchr(str, ',')) != NULL) { 276 *cp = '\0'; 277 emul = cp + 1; 278 if ((cp = strchr(emul, ',')) != NULL) { 279 *cp = '\0'; 280 config = cp + 1; 281 } 282 } else { 283 pci_parse_slot_usage(opt); 284 goto done; 285 } 286 287 /* <bus>:<slot>:<func> */ 288 if (sscanf(str, "%d:%d:%d", &bnum, &snum, &fnum) != 3) { 289 bnum = 0; 290 /* <slot>:<func> */ 291 if (sscanf(str, "%d:%d", &snum, &fnum) != 2) { 292 fnum = 0; 293 /* <slot> */ 294 if (sscanf(str, "%d", &snum) != 1) { 295 snum = -1; 296 } 297 } 298 } 299 300 if (bnum < 0 || bnum >= MAXBUSES || snum < 0 || snum >= MAXSLOTS || 301 fnum < 0 || fnum >= MAXFUNCS) { 302 pci_parse_slot_usage(opt); 303 goto done; 304 } 305 306 pde = pci_emul_finddev(emul); 307 if (pde == NULL) { 308 EPRINTLN("pci slot %d:%d:%d: unknown device \"%s\"", bnum, snum, 309 fnum, emul); 310 goto done; 311 } 312 313 snprintf(node_name, sizeof(node_name), "pci.%d.%d.%d", bnum, snum, 314 fnum); 315 nvl = find_config_node(node_name); 316 if (nvl != NULL) { 317 EPRINTLN("pci slot %d:%d:%d already occupied!", bnum, snum, 318 fnum); 319 goto done; 320 } 321 nvl = create_config_node(node_name); 322 if (pde->pe_alias != NULL) 323 set_config_value_node(nvl, "device", pde->pe_alias); 324 else 325 set_config_value_node(nvl, "device", pde->pe_emu); 326 327 if (pde->pe_legacy_config != NULL) 328 error = pde->pe_legacy_config(nvl, config); 329 else 330 error = pci_parse_legacy_config(nvl, config); 331 done: 332 free(str); 333 return (error); 334 } 335 336 void 337 pci_print_supported_devices(void) 338 { 339 struct pci_devemu **pdpp, *pdp; 340 341 SET_FOREACH(pdpp, pci_devemu_set) { 342 pdp = *pdpp; 343 printf("%s\n", pdp->pe_emu); 344 } 345 } 346 347 uint32_t 348 pci_config_read_reg(const struct pcisel *const host_sel, nvlist_t *nvl, 349 const uint32_t reg, const uint8_t size, const uint32_t def) 350 { 351 const char *config; 352 const nvlist_t *pci_regs; 353 354 assert(size == 1 || size == 2 || size == 4); 355 356 pci_regs = find_relative_config_node(nvl, "pcireg"); 357 if (pci_regs == NULL) { 358 return def; 359 } 360 361 switch (reg) { 362 case PCIR_DEVICE: 363 config = get_config_value_node(pci_regs, "device"); 364 break; 365 case PCIR_VENDOR: 366 config = get_config_value_node(pci_regs, "vendor"); 367 break; 368 case PCIR_REVID: 369 config = get_config_value_node(pci_regs, "revid"); 370 break; 371 case PCIR_SUBVEND_0: 372 config = get_config_value_node(pci_regs, "subvendor"); 373 break; 374 case PCIR_SUBDEV_0: 375 config = get_config_value_node(pci_regs, "subdevice"); 376 break; 377 default: 378 return (-1); 379 } 380 381 if (config == NULL) { 382 return def; 383 } else if (host_sel != NULL && strcmp(config, "host") == 0) { 384 return pci_host_read_config(host_sel, reg, size); 385 } else { 386 return strtol(config, NULL, 16); 387 } 388 } 389 390 static int 391 pci_valid_pba_offset(struct pci_devinst *pi, uint64_t offset) 392 { 393 394 if (offset < pi->pi_msix.pba_offset) 395 return (0); 396 397 if (offset >= pi->pi_msix.pba_offset + pi->pi_msix.pba_size) { 398 return (0); 399 } 400 401 return (1); 402 } 403 404 int 405 pci_emul_msix_twrite(struct pci_devinst *pi, uint64_t offset, int size, 406 uint64_t value) 407 { 408 int msix_entry_offset; 409 int tab_index; 410 char *dest; 411 412 /* support only 4 or 8 byte writes */ 413 if (size != 4 && size != 8) 414 return (-1); 415 416 /* 417 * Return if table index is beyond what device supports 418 */ 419 tab_index = offset / MSIX_TABLE_ENTRY_SIZE; 420 if (tab_index >= pi->pi_msix.table_count) 421 return (-1); 422 423 msix_entry_offset = offset % MSIX_TABLE_ENTRY_SIZE; 424 425 /* support only aligned writes */ 426 if ((msix_entry_offset % size) != 0) 427 return (-1); 428 429 dest = (char *)(pi->pi_msix.table + tab_index); 430 dest += msix_entry_offset; 431 432 if (size == 4) 433 *((uint32_t *)dest) = value; 434 else 435 *((uint64_t *)dest) = value; 436 437 return (0); 438 } 439 440 uint64_t 441 pci_emul_msix_tread(struct pci_devinst *pi, uint64_t offset, int size) 442 { 443 char *dest; 444 int msix_entry_offset; 445 int tab_index; 446 uint64_t retval = ~0; 447 448 /* 449 * The PCI standard only allows 4 and 8 byte accesses to the MSI-X 450 * table but we also allow 1 byte access to accommodate reads from 451 * ddb. 452 */ 453 if (size != 1 && size != 4 && size != 8) 454 return (retval); 455 456 msix_entry_offset = offset % MSIX_TABLE_ENTRY_SIZE; 457 458 /* support only aligned reads */ 459 if ((msix_entry_offset % size) != 0) { 460 return (retval); 461 } 462 463 tab_index = offset / MSIX_TABLE_ENTRY_SIZE; 464 465 if (tab_index < pi->pi_msix.table_count) { 466 /* valid MSI-X Table access */ 467 dest = (char *)(pi->pi_msix.table + tab_index); 468 dest += msix_entry_offset; 469 470 if (size == 1) 471 retval = *((uint8_t *)dest); 472 else if (size == 4) 473 retval = *((uint32_t *)dest); 474 else 475 retval = *((uint64_t *)dest); 476 } else if (pci_valid_pba_offset(pi, offset)) { 477 /* return 0 for PBA access */ 478 retval = 0; 479 } 480 481 return (retval); 482 } 483 484 int 485 pci_msix_table_bar(struct pci_devinst *pi) 486 { 487 488 if (pi->pi_msix.table != NULL) 489 return (pi->pi_msix.table_bar); 490 else 491 return (-1); 492 } 493 494 int 495 pci_msix_pba_bar(struct pci_devinst *pi) 496 { 497 498 if (pi->pi_msix.table != NULL) 499 return (pi->pi_msix.pba_bar); 500 else 501 return (-1); 502 } 503 504 #ifdef __amd64__ 505 static int 506 pci_emul_io_handler(struct vmctx *ctx __unused, int in, int port, 507 int bytes, uint32_t *eax, void *arg) 508 { 509 struct pci_devinst *pdi = arg; 510 struct pci_devemu *pe = pdi->pi_d; 511 uint64_t offset; 512 int i; 513 514 assert(port >= 0); 515 516 for (i = 0; i <= PCI_BARMAX; i++) { 517 if (pdi->pi_bar[i].type == PCIBAR_IO && 518 (uint64_t)port >= pdi->pi_bar[i].addr && 519 (uint64_t)port + bytes <= 520 pdi->pi_bar[i].addr + pdi->pi_bar[i].size) { 521 offset = port - pdi->pi_bar[i].addr; 522 if (in) 523 *eax = (*pe->pe_barread)(pdi, i, 524 offset, bytes); 525 else 526 (*pe->pe_barwrite)(pdi, i, offset, 527 bytes, *eax); 528 return (0); 529 } 530 } 531 return (-1); 532 } 533 #else 534 static int 535 pci_emul_iomem_handler(struct vcpu *vcpu __unused, int dir, 536 uint64_t addr, int size, uint64_t *val, void *arg1, long arg2) 537 { 538 struct pci_devinst *pdi = arg1; 539 struct pci_devemu *pe = pdi->pi_d; 540 uint64_t offset; 541 int bidx = (int)arg2; 542 543 assert(bidx <= PCI_BARMAX); 544 assert(pdi->pi_bar[bidx].type == PCIBAR_IO); 545 assert(addr >= pdi->pi_bar[bidx].addr && 546 addr + size <= pdi->pi_bar[bidx].addr + pdi->pi_bar[bidx].size); 547 assert(size == 1 || size == 2 || size == 4); 548 549 offset = addr - pdi->pi_bar[bidx].addr; 550 if (dir == MEM_F_READ) 551 *val = (*pe->pe_barread)(pdi, bidx, offset, size); 552 else 553 (*pe->pe_barwrite)(pdi, bidx, offset, size, *val); 554 555 return (0); 556 } 557 #endif /* !__amd64__ */ 558 559 static int 560 pci_emul_mem_handler(struct vcpu *vcpu __unused, int dir, 561 uint64_t addr, int size, uint64_t *val, void *arg1, long arg2) 562 { 563 struct pci_devinst *pdi = arg1; 564 struct pci_devemu *pe = pdi->pi_d; 565 uint64_t offset; 566 int bidx = (int)arg2; 567 568 assert(bidx <= PCI_BARMAX); 569 assert(pdi->pi_bar[bidx].type == PCIBAR_MEM32 || 570 pdi->pi_bar[bidx].type == PCIBAR_MEM64); 571 assert(addr >= pdi->pi_bar[bidx].addr && 572 addr + size <= pdi->pi_bar[bidx].addr + pdi->pi_bar[bidx].size); 573 574 offset = addr - pdi->pi_bar[bidx].addr; 575 576 if (dir == MEM_F_WRITE) { 577 if (size == 8) { 578 (*pe->pe_barwrite)(pdi, bidx, offset, 579 4, *val & 0xffffffff); 580 (*pe->pe_barwrite)(pdi, bidx, offset + 4, 581 4, *val >> 32); 582 } else { 583 (*pe->pe_barwrite)(pdi, bidx, offset, 584 size, *val); 585 } 586 } else { 587 if (size == 8) { 588 *val = (*pe->pe_barread)(pdi, bidx, 589 offset, 4); 590 *val |= (*pe->pe_barread)(pdi, bidx, 591 offset + 4, 4) << 32; 592 } else { 593 *val = (*pe->pe_barread)(pdi, bidx, 594 offset, size); 595 } 596 } 597 598 return (0); 599 } 600 601 602 static int 603 pci_emul_alloc_resource(uint64_t *baseptr, uint64_t limit, uint64_t size, 604 uint64_t *addr) 605 { 606 uint64_t base; 607 608 assert((size & (size - 1)) == 0); /* must be a power of 2 */ 609 610 base = roundup2(*baseptr, size); 611 612 if (base + size <= limit) { 613 *addr = base; 614 *baseptr = base + size; 615 return (0); 616 } else 617 return (-1); 618 } 619 620 /* 621 * Register (or unregister) the MMIO or I/O region associated with the BAR 622 * register 'idx' of an emulated pci device. 623 */ 624 static void 625 modify_bar_registration(struct pci_devinst *pi, int idx, int registration) 626 { 627 struct pci_devemu *pe; 628 int error; 629 enum pcibar_type type; 630 631 pe = pi->pi_d; 632 type = pi->pi_bar[idx].type; 633 switch (type) { 634 case PCIBAR_IO: 635 { 636 #ifdef __amd64__ 637 struct inout_port iop; 638 639 bzero(&iop, sizeof(struct inout_port)); 640 iop.name = pi->pi_name; 641 iop.port = pi->pi_bar[idx].addr; 642 iop.size = pi->pi_bar[idx].size; 643 if (registration) { 644 iop.flags = IOPORT_F_INOUT; 645 iop.handler = pci_emul_io_handler; 646 iop.arg = pi; 647 error = register_inout(&iop); 648 } else 649 error = unregister_inout(&iop); 650 #else 651 struct mem_range mr; 652 653 bzero(&mr, sizeof(struct mem_range)); 654 mr.name = pi->pi_name; 655 mr.base = pi->pi_bar[idx].addr; 656 mr.size = pi->pi_bar[idx].size; 657 if (registration) { 658 mr.flags = MEM_F_RW; 659 mr.handler = pci_emul_iomem_handler; 660 mr.arg1 = pi; 661 mr.arg2 = idx; 662 error = register_mem(&mr); 663 } else 664 error = unregister_mem(&mr); 665 #endif 666 break; 667 } 668 case PCIBAR_MEM32: 669 case PCIBAR_MEM64: 670 { 671 struct mem_range mr; 672 673 bzero(&mr, sizeof(struct mem_range)); 674 mr.name = pi->pi_name; 675 mr.base = pi->pi_bar[idx].addr; 676 mr.size = pi->pi_bar[idx].size; 677 if (registration) { 678 mr.flags = MEM_F_RW; 679 mr.handler = pci_emul_mem_handler; 680 mr.arg1 = pi; 681 mr.arg2 = idx; 682 error = register_mem(&mr); 683 } else 684 error = unregister_mem(&mr); 685 break; 686 } 687 case PCIBAR_ROM: 688 error = 0; 689 break; 690 default: 691 error = EINVAL; 692 break; 693 } 694 assert(error == 0); 695 696 if (pe->pe_baraddr != NULL) 697 (*pe->pe_baraddr)(pi, idx, registration, pi->pi_bar[idx].addr); 698 } 699 700 static void 701 unregister_bar(struct pci_devinst *pi, int idx) 702 { 703 704 modify_bar_registration(pi, idx, 0); 705 } 706 707 static void 708 register_bar(struct pci_devinst *pi, int idx) 709 { 710 711 modify_bar_registration(pi, idx, 1); 712 } 713 714 /* Is the ROM enabled for the emulated pci device? */ 715 static int 716 romen(struct pci_devinst *pi) 717 { 718 return (pi->pi_bar[PCI_ROM_IDX].lobits & PCIM_BIOS_ENABLE) == 719 PCIM_BIOS_ENABLE; 720 } 721 722 /* Are we decoding i/o port accesses for the emulated pci device? */ 723 static int 724 porten(struct pci_devinst *pi) 725 { 726 uint16_t cmd; 727 728 cmd = pci_get_cfgdata16(pi, PCIR_COMMAND); 729 730 return (cmd & PCIM_CMD_PORTEN); 731 } 732 733 /* Are we decoding memory accesses for the emulated pci device? */ 734 static int 735 memen(struct pci_devinst *pi) 736 { 737 uint16_t cmd; 738 739 cmd = pci_get_cfgdata16(pi, PCIR_COMMAND); 740 741 return (cmd & PCIM_CMD_MEMEN); 742 } 743 744 /* 745 * Update the MMIO or I/O address that is decoded by the BAR register. 746 * 747 * If the pci device has enabled the address space decoding then intercept 748 * the address range decoded by the BAR register. 749 */ 750 static void 751 update_bar_address(struct pci_devinst *pi, uint64_t addr, int idx, int type) 752 { 753 int decode; 754 755 if (pi->pi_bar[idx].type == PCIBAR_IO) 756 decode = porten(pi); 757 else 758 decode = memen(pi); 759 760 if (decode) 761 unregister_bar(pi, idx); 762 763 switch (type) { 764 case PCIBAR_IO: 765 case PCIBAR_MEM32: 766 pi->pi_bar[idx].addr = addr; 767 break; 768 case PCIBAR_MEM64: 769 pi->pi_bar[idx].addr &= ~0xffffffffUL; 770 pi->pi_bar[idx].addr |= addr; 771 break; 772 case PCIBAR_MEMHI64: 773 pi->pi_bar[idx].addr &= 0xffffffff; 774 pi->pi_bar[idx].addr |= addr; 775 break; 776 default: 777 assert(0); 778 } 779 780 if (decode) 781 register_bar(pi, idx); 782 } 783 784 int 785 pci_emul_alloc_bar(struct pci_devinst *pdi, int idx, enum pcibar_type type, 786 uint64_t size) 787 { 788 assert((type == PCIBAR_ROM) || (idx >= 0 && idx <= PCI_BARMAX)); 789 assert((type != PCIBAR_ROM) || (idx == PCI_ROM_IDX)); 790 791 if ((size & (size - 1)) != 0) 792 size = 1UL << flsl(size); /* round up to a power of 2 */ 793 794 /* Enforce minimum BAR sizes required by the PCI standard */ 795 if (type == PCIBAR_IO) { 796 if (size < 4) 797 size = 4; 798 } else if (type == PCIBAR_ROM) { 799 if (size < ~PCIM_BIOS_ADDR_MASK + 1) 800 size = ~PCIM_BIOS_ADDR_MASK + 1; 801 } else { 802 if (size < 16) 803 size = 16; 804 } 805 806 /* 807 * To reduce fragmentation of the MMIO space, we allocate the BARs by 808 * size. Therefore, don't allocate the BAR yet. We create a list of all 809 * BAR allocation which is sorted by BAR size. When all PCI devices are 810 * initialized, we will assign an address to the BARs. 811 */ 812 813 /* create a new list entry */ 814 struct pci_bar_allocation *const new_bar = malloc(sizeof(*new_bar)); 815 memset(new_bar, 0, sizeof(*new_bar)); 816 new_bar->pdi = pdi; 817 new_bar->idx = idx; 818 new_bar->type = type; 819 new_bar->size = size; 820 821 /* 822 * Search for a BAR which size is lower than the size of our newly 823 * allocated BAR. 824 */ 825 struct pci_bar_allocation *bar = NULL; 826 TAILQ_FOREACH(bar, &pci_bars, chain) { 827 if (bar->size < size) { 828 break; 829 } 830 } 831 832 if (bar == NULL) { 833 /* 834 * Either the list is empty or new BAR is the smallest BAR of 835 * the list. Append it to the end of our list. 836 */ 837 TAILQ_INSERT_TAIL(&pci_bars, new_bar, chain); 838 } else { 839 /* 840 * The found BAR is smaller than our new BAR. For that reason, 841 * insert our new BAR before the found BAR. 842 */ 843 TAILQ_INSERT_BEFORE(bar, new_bar, chain); 844 } 845 846 /* 847 * pci_passthru devices synchronize their physical and virtual command 848 * register on init. For that reason, the virtual cmd reg should be 849 * updated as early as possible. 850 */ 851 uint16_t enbit = 0; 852 switch (type) { 853 case PCIBAR_IO: 854 enbit = PCIM_CMD_PORTEN; 855 break; 856 case PCIBAR_MEM64: 857 case PCIBAR_MEM32: 858 enbit = PCIM_CMD_MEMEN; 859 break; 860 default: 861 enbit = 0; 862 break; 863 } 864 865 const uint16_t cmd = pci_get_cfgdata16(pdi, PCIR_COMMAND); 866 pci_set_cfgdata16(pdi, PCIR_COMMAND, cmd | enbit); 867 868 return (0); 869 } 870 871 static int 872 pci_emul_assign_bar(struct pci_devinst *const pdi, const int idx, 873 const enum pcibar_type type, const uint64_t size) 874 { 875 int error; 876 uint64_t *baseptr, limit, addr, mask, lobits, bar; 877 878 switch (type) { 879 case PCIBAR_NONE: 880 baseptr = NULL; 881 addr = mask = lobits = 0; 882 break; 883 case PCIBAR_IO: 884 baseptr = &pci_emul_iobase; 885 limit = PCI_EMUL_IOLIMIT; 886 mask = PCIM_BAR_IO_BASE; 887 lobits = PCIM_BAR_IO_SPACE; 888 break; 889 case PCIBAR_MEM64: 890 /* 891 * XXX 892 * Some drivers do not work well if the 64-bit BAR is allocated 893 * above 4GB. Allow for this by allocating small requests under 894 * 4GB unless then allocation size is larger than some arbitrary 895 * number (128MB currently). 896 */ 897 if (size > 128 * 1024 * 1024) { 898 baseptr = &pci_emul_membase64; 899 limit = pci_emul_memlim64; 900 mask = PCIM_BAR_MEM_BASE; 901 lobits = PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_64 | 902 PCIM_BAR_MEM_PREFETCH; 903 } else { 904 baseptr = &pci_emul_membase32; 905 limit = PCI_EMUL_MEMLIMIT32; 906 mask = PCIM_BAR_MEM_BASE; 907 lobits = PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_64; 908 } 909 break; 910 case PCIBAR_MEM32: 911 baseptr = &pci_emul_membase32; 912 limit = PCI_EMUL_MEMLIMIT32; 913 mask = PCIM_BAR_MEM_BASE; 914 lobits = PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_32; 915 break; 916 case PCIBAR_ROM: 917 /* do not claim memory for ROM. OVMF will do it for us. */ 918 baseptr = NULL; 919 limit = 0; 920 mask = PCIM_BIOS_ADDR_MASK; 921 lobits = 0; 922 break; 923 default: 924 printf("pci_emul_alloc_base: invalid bar type %d\n", type); 925 assert(0); 926 } 927 928 if (baseptr != NULL) { 929 error = pci_emul_alloc_resource(baseptr, limit, size, &addr); 930 if (error != 0) 931 return (error); 932 } else { 933 addr = 0; 934 } 935 936 pdi->pi_bar[idx].type = type; 937 pdi->pi_bar[idx].addr = addr; 938 pdi->pi_bar[idx].size = size; 939 /* 940 * passthru devices are using same lobits as physical device they set 941 * this property 942 */ 943 if (pdi->pi_bar[idx].lobits != 0) { 944 lobits = pdi->pi_bar[idx].lobits; 945 } else { 946 pdi->pi_bar[idx].lobits = lobits; 947 } 948 949 /* Initialize the BAR register in config space */ 950 bar = (addr & mask) | lobits; 951 pci_set_cfgdata32(pdi, PCIR_BAR(idx), bar); 952 953 if (type == PCIBAR_MEM64) { 954 assert(idx + 1 <= PCI_BARMAX); 955 pdi->pi_bar[idx + 1].type = PCIBAR_MEMHI64; 956 pci_set_cfgdata32(pdi, PCIR_BAR(idx + 1), bar >> 32); 957 } 958 959 if (type != PCIBAR_ROM) { 960 register_bar(pdi, idx); 961 } 962 963 return (0); 964 } 965 966 int 967 pci_emul_alloc_rom(struct pci_devinst *const pdi, const uint64_t size, 968 void **const addr) 969 { 970 /* allocate ROM space once on first call */ 971 if (pci_emul_rombase == 0) { 972 pci_emul_rombase = vm_create_devmem(pdi->pi_vmctx, VM_PCIROM, 973 "pcirom", PCI_EMUL_ROMSIZE); 974 if (pci_emul_rombase == MAP_FAILED) { 975 warnx("%s: failed to create rom segment", __func__); 976 return (-1); 977 } 978 pci_emul_romlim = pci_emul_rombase + PCI_EMUL_ROMSIZE; 979 pci_emul_romoffset = 0; 980 } 981 982 /* ROM size should be a power of 2 and greater than 2 KB */ 983 const uint64_t rom_size = MAX(1UL << flsl(size), 984 ~PCIM_BIOS_ADDR_MASK + 1); 985 986 /* check if ROM fits into ROM space */ 987 if (pci_emul_romoffset + rom_size > PCI_EMUL_ROMSIZE) { 988 warnx("%s: no space left in rom segment:", __func__); 989 warnx("%16lu bytes left", 990 PCI_EMUL_ROMSIZE - pci_emul_romoffset); 991 warnx("%16lu bytes required by %d/%d/%d", rom_size, pdi->pi_bus, 992 pdi->pi_slot, pdi->pi_func); 993 return (-1); 994 } 995 996 /* allocate ROM BAR */ 997 const int error = pci_emul_alloc_bar(pdi, PCI_ROM_IDX, PCIBAR_ROM, 998 rom_size); 999 if (error) 1000 return error; 1001 1002 /* return address */ 1003 *addr = pci_emul_rombase + pci_emul_romoffset; 1004 1005 /* save offset into ROM Space */ 1006 pdi->pi_romoffset = pci_emul_romoffset; 1007 1008 /* increase offset for next ROM */ 1009 pci_emul_romoffset += rom_size; 1010 1011 return (0); 1012 } 1013 1014 int 1015 pci_emul_add_boot_device(struct pci_devinst *pi, int bootindex) 1016 { 1017 struct boot_device *new_device, *device; 1018 1019 /* don't permit a negative bootindex */ 1020 if (bootindex < 0) { 1021 errx(4, "Invalid bootindex %d for %s", bootindex, pi->pi_name); 1022 } 1023 1024 /* alloc new boot device */ 1025 new_device = calloc(1, sizeof(struct boot_device)); 1026 if (new_device == NULL) { 1027 return (ENOMEM); 1028 } 1029 new_device->pdi = pi; 1030 new_device->bootindex = bootindex; 1031 1032 /* search for boot device with higher boot index */ 1033 TAILQ_FOREACH(device, &boot_devices, boot_device_chain) { 1034 if (device->bootindex == bootindex) { 1035 errx(4, 1036 "Could not set bootindex %d for %s. Bootindex already occupied by %s", 1037 bootindex, pi->pi_name, device->pdi->pi_name); 1038 } else if (device->bootindex > bootindex) { 1039 break; 1040 } 1041 } 1042 1043 /* add boot device to queue */ 1044 if (device == NULL) { 1045 TAILQ_INSERT_TAIL(&boot_devices, new_device, boot_device_chain); 1046 } else { 1047 TAILQ_INSERT_BEFORE(device, new_device, boot_device_chain); 1048 } 1049 1050 return (0); 1051 } 1052 1053 #define CAP_START_OFFSET 0x40 1054 static int 1055 pci_emul_add_capability(struct pci_devinst *pi, u_char *capdata, int caplen) 1056 { 1057 int i, capoff, reallen; 1058 uint16_t sts; 1059 1060 assert(caplen > 0); 1061 1062 reallen = roundup2(caplen, 4); /* dword aligned */ 1063 1064 sts = pci_get_cfgdata16(pi, PCIR_STATUS); 1065 if ((sts & PCIM_STATUS_CAPPRESENT) == 0) 1066 capoff = CAP_START_OFFSET; 1067 else 1068 capoff = pi->pi_capend + 1; 1069 1070 /* Check if we have enough space */ 1071 if (capoff + reallen > PCI_REGMAX + 1) 1072 return (-1); 1073 1074 /* Set the previous capability pointer */ 1075 if ((sts & PCIM_STATUS_CAPPRESENT) == 0) { 1076 pci_set_cfgdata8(pi, PCIR_CAP_PTR, capoff); 1077 pci_set_cfgdata16(pi, PCIR_STATUS, sts|PCIM_STATUS_CAPPRESENT); 1078 } else 1079 pci_set_cfgdata8(pi, pi->pi_prevcap + 1, capoff); 1080 1081 /* Copy the capability */ 1082 for (i = 0; i < caplen; i++) 1083 pci_set_cfgdata8(pi, capoff + i, capdata[i]); 1084 1085 /* Set the next capability pointer */ 1086 pci_set_cfgdata8(pi, capoff + 1, 0); 1087 1088 pi->pi_prevcap = capoff; 1089 pi->pi_capend = capoff + reallen - 1; 1090 return (0); 1091 } 1092 1093 static struct pci_devemu * 1094 pci_emul_finddev(const char *name) 1095 { 1096 struct pci_devemu **pdpp, *pdp; 1097 1098 SET_FOREACH(pdpp, pci_devemu_set) { 1099 pdp = *pdpp; 1100 if (!strcmp(pdp->pe_emu, name)) { 1101 return (pdp); 1102 } 1103 } 1104 1105 return (NULL); 1106 } 1107 1108 static int 1109 pci_emul_init(struct vmctx *ctx, struct pci_devemu *pde, int bus, int slot, 1110 int func, struct funcinfo *fi) 1111 { 1112 struct pci_devinst *pdi; 1113 int err; 1114 1115 pdi = calloc(1, sizeof(struct pci_devinst)); 1116 1117 pdi->pi_vmctx = ctx; 1118 pdi->pi_bus = bus; 1119 pdi->pi_slot = slot; 1120 pdi->pi_func = func; 1121 #ifdef __amd64__ 1122 pthread_mutex_init(&pdi->pi_lintr.lock, NULL); 1123 pdi->pi_lintr.pin = 0; 1124 pdi->pi_lintr.state = IDLE; 1125 pdi->pi_lintr.pirq_pin = 0; 1126 pdi->pi_lintr.ioapic_irq = 0; 1127 #endif 1128 pdi->pi_d = pde; 1129 snprintf(pdi->pi_name, PI_NAMESZ, "%s@pci.%d.%d.%d", pde->pe_emu, bus, 1130 slot, func); 1131 1132 /* Disable legacy interrupts */ 1133 pci_set_cfgdata8(pdi, PCIR_INTLINE, 255); 1134 pci_set_cfgdata8(pdi, PCIR_INTPIN, 0); 1135 1136 pci_set_cfgdata8(pdi, PCIR_COMMAND, PCIM_CMD_BUSMASTEREN); 1137 1138 err = (*pde->pe_init)(pdi, fi->fi_config); 1139 if (err == 0) 1140 fi->fi_devi = pdi; 1141 else 1142 free(pdi); 1143 1144 return (err); 1145 } 1146 1147 void 1148 pci_populate_msicap(struct msicap *msicap, int msgnum, int nextptr) 1149 { 1150 int mmc; 1151 1152 /* Number of msi messages must be a power of 2 between 1 and 32 */ 1153 assert((msgnum & (msgnum - 1)) == 0 && msgnum >= 1 && msgnum <= 32); 1154 mmc = ffs(msgnum) - 1; 1155 1156 bzero(msicap, sizeof(struct msicap)); 1157 msicap->capid = PCIY_MSI; 1158 msicap->nextptr = nextptr; 1159 msicap->msgctrl = PCIM_MSICTRL_64BIT | (mmc << 1); 1160 } 1161 1162 int 1163 pci_emul_add_msicap(struct pci_devinst *pi, int msgnum) 1164 { 1165 struct msicap msicap; 1166 1167 pci_populate_msicap(&msicap, msgnum, 0); 1168 1169 return (pci_emul_add_capability(pi, (u_char *)&msicap, sizeof(msicap))); 1170 } 1171 1172 static void 1173 pci_populate_msixcap(struct msixcap *msixcap, int msgnum, int barnum, 1174 uint32_t msix_tab_size) 1175 { 1176 1177 assert(msix_tab_size % 4096 == 0); 1178 1179 bzero(msixcap, sizeof(struct msixcap)); 1180 msixcap->capid = PCIY_MSIX; 1181 1182 /* 1183 * Message Control Register, all fields set to 1184 * zero except for the Table Size. 1185 * Note: Table size N is encoded as N-1 1186 */ 1187 msixcap->msgctrl = msgnum - 1; 1188 1189 /* 1190 * MSI-X BAR setup: 1191 * - MSI-X table start at offset 0 1192 * - PBA table starts at a 4K aligned offset after the MSI-X table 1193 */ 1194 msixcap->table_info = barnum & PCIM_MSIX_BIR_MASK; 1195 msixcap->pba_info = msix_tab_size | (barnum & PCIM_MSIX_BIR_MASK); 1196 } 1197 1198 static void 1199 pci_msix_table_init(struct pci_devinst *pi, int table_entries) 1200 { 1201 int i, table_size; 1202 1203 assert(table_entries > 0); 1204 assert(table_entries <= MAX_MSIX_TABLE_ENTRIES); 1205 1206 table_size = table_entries * MSIX_TABLE_ENTRY_SIZE; 1207 pi->pi_msix.table = calloc(1, table_size); 1208 1209 /* set mask bit of vector control register */ 1210 for (i = 0; i < table_entries; i++) 1211 pi->pi_msix.table[i].vector_control |= PCIM_MSIX_VCTRL_MASK; 1212 } 1213 1214 int 1215 pci_emul_add_msixcap(struct pci_devinst *pi, int msgnum, int barnum) 1216 { 1217 uint32_t tab_size; 1218 struct msixcap msixcap; 1219 1220 assert(msgnum >= 1 && msgnum <= MAX_MSIX_TABLE_ENTRIES); 1221 assert(barnum >= 0 && barnum <= PCIR_MAX_BAR_0); 1222 1223 tab_size = msgnum * MSIX_TABLE_ENTRY_SIZE; 1224 1225 /* Align table size to nearest 4K */ 1226 tab_size = roundup2(tab_size, 4096); 1227 1228 pi->pi_msix.table_bar = barnum; 1229 pi->pi_msix.pba_bar = barnum; 1230 pi->pi_msix.table_offset = 0; 1231 pi->pi_msix.table_count = msgnum; 1232 pi->pi_msix.pba_offset = tab_size; 1233 pi->pi_msix.pba_size = PBA_SIZE(msgnum); 1234 1235 pci_msix_table_init(pi, msgnum); 1236 1237 pci_populate_msixcap(&msixcap, msgnum, barnum, tab_size); 1238 1239 /* allocate memory for MSI-X Table and PBA */ 1240 pci_emul_alloc_bar(pi, barnum, PCIBAR_MEM32, 1241 tab_size + pi->pi_msix.pba_size); 1242 1243 return (pci_emul_add_capability(pi, (u_char *)&msixcap, 1244 sizeof(msixcap))); 1245 } 1246 1247 static void 1248 msixcap_cfgwrite(struct pci_devinst *pi, int capoff, int offset, 1249 int bytes, uint32_t val) 1250 { 1251 uint16_t msgctrl, rwmask; 1252 int off; 1253 1254 off = offset - capoff; 1255 /* Message Control Register */ 1256 if (off == 2 && bytes == 2) { 1257 rwmask = PCIM_MSIXCTRL_MSIX_ENABLE | PCIM_MSIXCTRL_FUNCTION_MASK; 1258 msgctrl = pci_get_cfgdata16(pi, offset); 1259 msgctrl &= ~rwmask; 1260 msgctrl |= val & rwmask; 1261 val = msgctrl; 1262 1263 pi->pi_msix.enabled = val & PCIM_MSIXCTRL_MSIX_ENABLE; 1264 pi->pi_msix.function_mask = val & PCIM_MSIXCTRL_FUNCTION_MASK; 1265 #ifdef __amd64__ 1266 pci_lintr_update(pi); 1267 #endif 1268 } 1269 1270 CFGWRITE(pi, offset, val, bytes); 1271 } 1272 1273 static void 1274 msicap_cfgwrite(struct pci_devinst *pi, int capoff, int offset, 1275 int bytes, uint32_t val) 1276 { 1277 uint16_t msgctrl, rwmask, msgdata, mme; 1278 uint32_t addrlo; 1279 1280 /* 1281 * If guest is writing to the message control register make sure 1282 * we do not overwrite read-only fields. 1283 */ 1284 if ((offset - capoff) == 2 && bytes == 2) { 1285 rwmask = PCIM_MSICTRL_MME_MASK | PCIM_MSICTRL_MSI_ENABLE; 1286 msgctrl = pci_get_cfgdata16(pi, offset); 1287 msgctrl &= ~rwmask; 1288 msgctrl |= val & rwmask; 1289 val = msgctrl; 1290 } 1291 CFGWRITE(pi, offset, val, bytes); 1292 1293 msgctrl = pci_get_cfgdata16(pi, capoff + 2); 1294 addrlo = pci_get_cfgdata32(pi, capoff + 4); 1295 if (msgctrl & PCIM_MSICTRL_64BIT) 1296 msgdata = pci_get_cfgdata16(pi, capoff + 12); 1297 else 1298 msgdata = pci_get_cfgdata16(pi, capoff + 8); 1299 1300 mme = msgctrl & PCIM_MSICTRL_MME_MASK; 1301 pi->pi_msi.enabled = msgctrl & PCIM_MSICTRL_MSI_ENABLE ? 1 : 0; 1302 if (pi->pi_msi.enabled) { 1303 pi->pi_msi.addr = addrlo; 1304 pi->pi_msi.msg_data = msgdata; 1305 pi->pi_msi.maxmsgnum = 1 << (mme >> 4); 1306 } else { 1307 pi->pi_msi.maxmsgnum = 0; 1308 } 1309 #ifdef __amd64__ 1310 pci_lintr_update(pi); 1311 #endif 1312 } 1313 1314 static void 1315 pciecap_cfgwrite(struct pci_devinst *pi, int capoff __unused, int offset, 1316 int bytes, uint32_t val) 1317 { 1318 1319 /* XXX don't write to the readonly parts */ 1320 CFGWRITE(pi, offset, val, bytes); 1321 } 1322 1323 #define PCIECAP_VERSION 0x2 1324 int 1325 pci_emul_add_pciecap(struct pci_devinst *pi, int type) 1326 { 1327 int err; 1328 struct pciecap pciecap; 1329 1330 bzero(&pciecap, sizeof(pciecap)); 1331 1332 /* 1333 * Use the integrated endpoint type for endpoints on a root complex bus. 1334 * 1335 * NB: bhyve currently only supports a single PCI bus that is the root 1336 * complex bus, so all endpoints are integrated. 1337 */ 1338 if ((type == PCIEM_TYPE_ENDPOINT) && (pi->pi_bus == 0)) 1339 type = PCIEM_TYPE_ROOT_INT_EP; 1340 1341 pciecap.capid = PCIY_EXPRESS; 1342 pciecap.pcie_capabilities = PCIECAP_VERSION | type; 1343 if (type != PCIEM_TYPE_ROOT_INT_EP) { 1344 pciecap.link_capabilities = 0x411; /* gen1, x1 */ 1345 pciecap.link_status = 0x11; /* gen1, x1 */ 1346 } 1347 1348 err = pci_emul_add_capability(pi, (u_char *)&pciecap, sizeof(pciecap)); 1349 return (err); 1350 } 1351 1352 /* 1353 * This function assumes that 'coff' is in the capabilities region of the 1354 * config space. A capoff parameter of zero will force a search for the 1355 * offset and type. 1356 */ 1357 void 1358 pci_emul_capwrite(struct pci_devinst *pi, int offset, int bytes, uint32_t val, 1359 uint8_t capoff, int capid) 1360 { 1361 uint8_t nextoff; 1362 1363 /* Do not allow un-aligned writes */ 1364 if ((offset & (bytes - 1)) != 0) 1365 return; 1366 1367 if (capoff == 0) { 1368 /* Find the capability that we want to update */ 1369 capoff = CAP_START_OFFSET; 1370 while (1) { 1371 nextoff = pci_get_cfgdata8(pi, capoff + 1); 1372 if (nextoff == 0) 1373 break; 1374 if (offset >= capoff && offset < nextoff) 1375 break; 1376 1377 capoff = nextoff; 1378 } 1379 assert(offset >= capoff); 1380 capid = pci_get_cfgdata8(pi, capoff); 1381 } 1382 1383 /* 1384 * Capability ID and Next Capability Pointer are readonly. 1385 * However, some o/s's do 4-byte writes that include these. 1386 * For this case, trim the write back to 2 bytes and adjust 1387 * the data. 1388 */ 1389 if (offset == capoff || offset == capoff + 1) { 1390 if (offset == capoff && bytes == 4) { 1391 bytes = 2; 1392 offset += 2; 1393 val >>= 16; 1394 } else 1395 return; 1396 } 1397 1398 switch (capid) { 1399 case PCIY_MSI: 1400 msicap_cfgwrite(pi, capoff, offset, bytes, val); 1401 break; 1402 case PCIY_MSIX: 1403 msixcap_cfgwrite(pi, capoff, offset, bytes, val); 1404 break; 1405 case PCIY_EXPRESS: 1406 pciecap_cfgwrite(pi, capoff, offset, bytes, val); 1407 break; 1408 default: 1409 break; 1410 } 1411 } 1412 1413 static int 1414 pci_emul_iscap(struct pci_devinst *pi, int offset) 1415 { 1416 uint16_t sts; 1417 1418 sts = pci_get_cfgdata16(pi, PCIR_STATUS); 1419 if ((sts & PCIM_STATUS_CAPPRESENT) != 0) { 1420 if (offset >= CAP_START_OFFSET && offset <= pi->pi_capend) 1421 return (1); 1422 } 1423 return (0); 1424 } 1425 1426 static int 1427 pci_emul_fallback_handler(struct vcpu *vcpu __unused, int dir, 1428 uint64_t addr __unused, int size __unused, uint64_t *val, 1429 void *arg1 __unused, long arg2 __unused) 1430 { 1431 /* 1432 * Ignore writes; return 0xff's for reads. The mem read code 1433 * will take care of truncating to the correct size. 1434 */ 1435 if (dir == MEM_F_READ) { 1436 *val = 0xffffffffffffffff; 1437 } 1438 1439 return (0); 1440 } 1441 1442 static int 1443 pci_emul_ecfg_handler(struct vcpu *vcpu __unused, int dir, uint64_t addr, 1444 int bytes, uint64_t *val, void *arg1 __unused, long arg2 __unused) 1445 { 1446 int bus, slot, func, coff, in; 1447 1448 coff = addr & 0xfff; 1449 func = (addr >> 12) & 0x7; 1450 slot = (addr >> 15) & 0x1f; 1451 bus = (addr >> 20) & 0xff; 1452 in = (dir == MEM_F_READ); 1453 if (in) 1454 *val = ~0UL; 1455 pci_cfgrw(in, bus, slot, func, coff, bytes, (uint32_t *)val); 1456 return (0); 1457 } 1458 1459 uint64_t 1460 pci_ecfg_base(void) 1461 { 1462 1463 return (PCI_EMUL_ECFG_BASE); 1464 } 1465 1466 static int 1467 init_bootorder(void) 1468 { 1469 struct boot_device *device; 1470 FILE *fp; 1471 char *bootorder; 1472 size_t bootorder_len; 1473 1474 if (TAILQ_EMPTY(&boot_devices)) 1475 return (0); 1476 1477 fp = open_memstream(&bootorder, &bootorder_len); 1478 TAILQ_FOREACH(device, &boot_devices, boot_device_chain) { 1479 fprintf(fp, "/pci@i0cf8/pci@%d,%d\n", 1480 device->pdi->pi_slot, device->pdi->pi_func); 1481 } 1482 fclose(fp); 1483 1484 return (qemu_fwcfg_add_file("bootorder", bootorder_len, bootorder)); 1485 } 1486 1487 #define BUSIO_ROUNDUP 32 1488 #define BUSMEM32_ROUNDUP (1024 * 1024) 1489 #define BUSMEM64_ROUNDUP (512 * 1024 * 1024) 1490 1491 int 1492 init_pci(struct vmctx *ctx) 1493 { 1494 char node_name[sizeof("pci.XXX.XX.X")]; 1495 struct mem_range mr; 1496 struct pci_devemu *pde; 1497 struct businfo *bi; 1498 struct slotinfo *si; 1499 struct funcinfo *fi; 1500 nvlist_t *nvl; 1501 const char *emul; 1502 size_t lowmem; 1503 int bus, slot, func; 1504 int error; 1505 1506 if (vm_get_lowmem_limit(ctx) > PCI_EMUL_MEMBASE32) 1507 errx(EX_OSERR, "Invalid lowmem limit"); 1508 1509 pci_emul_iobase = PCI_EMUL_IOBASE; 1510 pci_emul_membase32 = PCI_EMUL_MEMBASE32; 1511 1512 pci_emul_membase64 = 4*GB + vm_get_highmem_size(ctx); 1513 pci_emul_membase64 = roundup2(pci_emul_membase64, PCI_EMUL_MEMSIZE64); 1514 pci_emul_memlim64 = pci_emul_membase64 + PCI_EMUL_MEMSIZE64; 1515 1516 TAILQ_INIT(&boot_devices); 1517 1518 for (bus = 0; bus < MAXBUSES; bus++) { 1519 snprintf(node_name, sizeof(node_name), "pci.%d", bus); 1520 nvl = find_config_node(node_name); 1521 if (nvl == NULL) 1522 continue; 1523 pci_businfo[bus] = calloc(1, sizeof(struct businfo)); 1524 bi = pci_businfo[bus]; 1525 1526 /* 1527 * Keep track of the i/o and memory resources allocated to 1528 * this bus. 1529 */ 1530 bi->iobase = pci_emul_iobase; 1531 bi->membase32 = pci_emul_membase32; 1532 bi->membase64 = pci_emul_membase64; 1533 1534 /* first run: init devices */ 1535 for (slot = 0; slot < MAXSLOTS; slot++) { 1536 si = &bi->slotinfo[slot]; 1537 for (func = 0; func < MAXFUNCS; func++) { 1538 fi = &si->si_funcs[func]; 1539 snprintf(node_name, sizeof(node_name), 1540 "pci.%d.%d.%d", bus, slot, func); 1541 nvl = find_config_node(node_name); 1542 if (nvl == NULL) 1543 continue; 1544 1545 fi->fi_config = nvl; 1546 emul = get_config_value_node(nvl, "device"); 1547 if (emul == NULL) { 1548 EPRINTLN("pci slot %d:%d:%d: missing " 1549 "\"device\" value", bus, slot, func); 1550 return (EINVAL); 1551 } 1552 pde = pci_emul_finddev(emul); 1553 if (pde == NULL) { 1554 EPRINTLN("pci slot %d:%d:%d: unknown " 1555 "device \"%s\"", bus, slot, func, 1556 emul); 1557 return (EINVAL); 1558 } 1559 if (pde->pe_alias != NULL) { 1560 EPRINTLN("pci slot %d:%d:%d: legacy " 1561 "device \"%s\", use \"%s\" instead", 1562 bus, slot, func, emul, 1563 pde->pe_alias); 1564 return (EINVAL); 1565 } 1566 fi->fi_pde = pde; 1567 error = pci_emul_init(ctx, pde, bus, slot, 1568 func, fi); 1569 if (error) 1570 return (error); 1571 } 1572 } 1573 1574 /* second run: assign BARs and free list */ 1575 struct pci_bar_allocation *bar; 1576 struct pci_bar_allocation *bar_tmp; 1577 TAILQ_FOREACH_SAFE(bar, &pci_bars, chain, bar_tmp) { 1578 pci_emul_assign_bar(bar->pdi, bar->idx, bar->type, 1579 bar->size); 1580 free(bar); 1581 } 1582 TAILQ_INIT(&pci_bars); 1583 1584 /* 1585 * Add some slop to the I/O and memory resources decoded by 1586 * this bus to give a guest some flexibility if it wants to 1587 * reprogram the BARs. 1588 */ 1589 pci_emul_iobase += BUSIO_ROUNDUP; 1590 pci_emul_iobase = roundup2(pci_emul_iobase, BUSIO_ROUNDUP); 1591 bi->iolimit = pci_emul_iobase; 1592 1593 pci_emul_membase32 += BUSMEM32_ROUNDUP; 1594 pci_emul_membase32 = roundup2(pci_emul_membase32, 1595 BUSMEM32_ROUNDUP); 1596 bi->memlimit32 = pci_emul_membase32; 1597 1598 pci_emul_membase64 += BUSMEM64_ROUNDUP; 1599 pci_emul_membase64 = roundup2(pci_emul_membase64, 1600 BUSMEM64_ROUNDUP); 1601 bi->memlimit64 = pci_emul_membase64; 1602 } 1603 1604 #ifdef __amd64__ 1605 /* 1606 * PCI backends are initialized before routing INTx interrupts 1607 * so that LPC devices are able to reserve ISA IRQs before 1608 * routing PIRQ pins. 1609 */ 1610 for (bus = 0; bus < MAXBUSES; bus++) { 1611 if ((bi = pci_businfo[bus]) == NULL) 1612 continue; 1613 1614 for (slot = 0; slot < MAXSLOTS; slot++) { 1615 si = &bi->slotinfo[slot]; 1616 for (func = 0; func < MAXFUNCS; func++) { 1617 fi = &si->si_funcs[func]; 1618 if (fi->fi_devi == NULL) 1619 continue; 1620 pci_lintr_route(fi->fi_devi); 1621 } 1622 } 1623 } 1624 lpc_pirq_routed(); 1625 #endif 1626 1627 if ((error = init_bootorder()) != 0) { 1628 warnx("%s: Unable to init bootorder", __func__); 1629 return (error); 1630 } 1631 1632 /* 1633 * The guest physical memory map looks like the following: 1634 * [0, lowmem) guest system memory 1635 * [lowmem, 0xC0000000) memory hole (may be absent) 1636 * [0xC0000000, 0xE0000000) PCI hole (32-bit BAR allocation) 1637 * [0xE0000000, 0xF0000000) PCI extended config window 1638 * [0xF0000000, 4GB) LAPIC, IOAPIC, HPET, firmware 1639 * [4GB, 4GB + highmem) 1640 */ 1641 1642 /* 1643 * Accesses to memory addresses that are not allocated to system 1644 * memory or PCI devices return 0xff's. 1645 */ 1646 lowmem = vm_get_lowmem_size(ctx); 1647 bzero(&mr, sizeof(struct mem_range)); 1648 mr.name = "PCI hole"; 1649 mr.flags = MEM_F_RW | MEM_F_IMMUTABLE; 1650 mr.base = lowmem; 1651 mr.size = (4ULL * 1024 * 1024 * 1024) - lowmem; 1652 mr.handler = pci_emul_fallback_handler; 1653 error = register_mem_fallback(&mr); 1654 assert(error == 0); 1655 1656 /* PCI extended config space */ 1657 bzero(&mr, sizeof(struct mem_range)); 1658 mr.name = "PCI ECFG"; 1659 mr.flags = MEM_F_RW | MEM_F_IMMUTABLE; 1660 mr.base = PCI_EMUL_ECFG_BASE; 1661 mr.size = PCI_EMUL_ECFG_SIZE; 1662 mr.handler = pci_emul_ecfg_handler; 1663 error = register_mem(&mr); 1664 assert(error == 0); 1665 1666 return (0); 1667 } 1668 1669 #ifdef __amd64__ 1670 static void 1671 pci_apic_prt_entry(int bus __unused, int slot, int pin, int pirq_pin __unused, 1672 int ioapic_irq, void *arg __unused) 1673 { 1674 1675 dsdt_line(" Package ()"); 1676 dsdt_line(" {"); 1677 dsdt_line(" 0x%X,", slot << 16 | 0xffff); 1678 dsdt_line(" 0x%02X,", pin - 1); 1679 dsdt_line(" Zero,"); 1680 dsdt_line(" 0x%X", ioapic_irq); 1681 dsdt_line(" },"); 1682 } 1683 1684 static void 1685 pci_pirq_prt_entry(int bus __unused, int slot, int pin, int pirq_pin, 1686 int ioapic_irq __unused, void *arg __unused) 1687 { 1688 char *name; 1689 1690 name = lpc_pirq_name(pirq_pin); 1691 if (name == NULL) 1692 return; 1693 dsdt_line(" Package ()"); 1694 dsdt_line(" {"); 1695 dsdt_line(" 0x%X,", slot << 16 | 0xffff); 1696 dsdt_line(" 0x%02X,", pin - 1); 1697 dsdt_line(" %s,", name); 1698 dsdt_line(" 0x00"); 1699 dsdt_line(" },"); 1700 free(name); 1701 } 1702 #endif 1703 1704 /* 1705 * A bhyve virtual machine has a flat PCI hierarchy with a root port 1706 * corresponding to each PCI bus. 1707 */ 1708 static void 1709 pci_bus_write_dsdt(int bus) 1710 { 1711 struct businfo *bi; 1712 struct slotinfo *si; 1713 struct pci_devinst *pi; 1714 int func, slot; 1715 1716 /* 1717 * If there are no devices on this 'bus' then just return. 1718 */ 1719 if ((bi = pci_businfo[bus]) == NULL) { 1720 /* 1721 * Bus 0 is special because it decodes the I/O ports used 1722 * for PCI config space access even if there are no devices 1723 * on it. 1724 */ 1725 if (bus != 0) 1726 return; 1727 } 1728 1729 dsdt_line(" Device (PC%02X)", bus); 1730 dsdt_line(" {"); 1731 dsdt_line(" Name (_HID, EisaId (\"PNP0A03\"))"); 1732 1733 dsdt_line(" Method (_BBN, 0, NotSerialized)"); 1734 dsdt_line(" {"); 1735 dsdt_line(" Return (0x%08X)", bus); 1736 dsdt_line(" }"); 1737 dsdt_line(" Name (_CRS, ResourceTemplate ()"); 1738 dsdt_line(" {"); 1739 dsdt_line(" WordBusNumber (ResourceProducer, MinFixed, " 1740 "MaxFixed, PosDecode,"); 1741 dsdt_line(" 0x0000, // Granularity"); 1742 dsdt_line(" 0x%04X, // Range Minimum", bus); 1743 dsdt_line(" 0x%04X, // Range Maximum", bus); 1744 dsdt_line(" 0x0000, // Translation Offset"); 1745 dsdt_line(" 0x0001, // Length"); 1746 dsdt_line(" ,, )"); 1747 1748 if (bus == 0) { 1749 dsdt_indent(3); 1750 dsdt_fixed_ioport(0xCF8, 8); 1751 dsdt_unindent(3); 1752 1753 dsdt_line(" WordIO (ResourceProducer, MinFixed, MaxFixed, " 1754 "PosDecode, EntireRange,"); 1755 dsdt_line(" 0x0000, // Granularity"); 1756 dsdt_line(" 0x0000, // Range Minimum"); 1757 dsdt_line(" 0x0CF7, // Range Maximum"); 1758 dsdt_line(" 0x0000, // Translation Offset"); 1759 dsdt_line(" 0x0CF8, // Length"); 1760 dsdt_line(" ,, , TypeStatic)"); 1761 1762 dsdt_line(" WordIO (ResourceProducer, MinFixed, MaxFixed, " 1763 "PosDecode, EntireRange,"); 1764 dsdt_line(" 0x0000, // Granularity"); 1765 dsdt_line(" 0x0D00, // Range Minimum"); 1766 dsdt_line(" 0x%04X, // Range Maximum", 1767 PCI_EMUL_IOBASE - 1); 1768 dsdt_line(" 0x0000, // Translation Offset"); 1769 dsdt_line(" 0x%04X, // Length", 1770 PCI_EMUL_IOBASE - 0x0D00); 1771 dsdt_line(" ,, , TypeStatic)"); 1772 1773 if (bi == NULL) { 1774 dsdt_line(" })"); 1775 goto done; 1776 } 1777 } 1778 assert(bi != NULL); 1779 1780 /* i/o window */ 1781 dsdt_line(" WordIO (ResourceProducer, MinFixed, MaxFixed, " 1782 "PosDecode, EntireRange,"); 1783 dsdt_line(" 0x0000, // Granularity"); 1784 dsdt_line(" 0x%04X, // Range Minimum", bi->iobase); 1785 dsdt_line(" 0x%04X, // Range Maximum", 1786 bi->iolimit - 1); 1787 dsdt_line(" 0x0000, // Translation Offset"); 1788 dsdt_line(" 0x%04X, // Length", 1789 bi->iolimit - bi->iobase); 1790 dsdt_line(" ,, , TypeStatic)"); 1791 1792 /* mmio window (32-bit) */ 1793 dsdt_line(" DWordMemory (ResourceProducer, PosDecode, " 1794 "MinFixed, MaxFixed, NonCacheable, ReadWrite,"); 1795 dsdt_line(" 0x00000000, // Granularity"); 1796 dsdt_line(" 0x%08X, // Range Minimum\n", bi->membase32); 1797 dsdt_line(" 0x%08X, // Range Maximum\n", 1798 bi->memlimit32 - 1); 1799 dsdt_line(" 0x00000000, // Translation Offset"); 1800 dsdt_line(" 0x%08X, // Length\n", 1801 bi->memlimit32 - bi->membase32); 1802 dsdt_line(" ,, , AddressRangeMemory, TypeStatic)"); 1803 1804 /* mmio window (64-bit) */ 1805 dsdt_line(" QWordMemory (ResourceProducer, PosDecode, " 1806 "MinFixed, MaxFixed, NonCacheable, ReadWrite,"); 1807 dsdt_line(" 0x0000000000000000, // Granularity"); 1808 dsdt_line(" 0x%016lX, // Range Minimum\n", bi->membase64); 1809 dsdt_line(" 0x%016lX, // Range Maximum\n", 1810 bi->memlimit64 - 1); 1811 dsdt_line(" 0x0000000000000000, // Translation Offset"); 1812 dsdt_line(" 0x%016lX, // Length\n", 1813 bi->memlimit64 - bi->membase64); 1814 dsdt_line(" ,, , AddressRangeMemory, TypeStatic)"); 1815 dsdt_line(" })"); 1816 1817 #ifdef __amd64__ 1818 if (pci_count_lintr(bus) != 0) { 1819 dsdt_indent(2); 1820 dsdt_line("Name (PPRT, Package ()"); 1821 dsdt_line("{"); 1822 pci_walk_lintr(bus, pci_pirq_prt_entry, NULL); 1823 dsdt_line("})"); 1824 dsdt_line("Name (APRT, Package ()"); 1825 dsdt_line("{"); 1826 pci_walk_lintr(bus, pci_apic_prt_entry, NULL); 1827 dsdt_line("})"); 1828 dsdt_line("Method (_PRT, 0, NotSerialized)"); 1829 dsdt_line("{"); 1830 dsdt_line(" If (PICM)"); 1831 dsdt_line(" {"); 1832 dsdt_line(" Return (APRT)"); 1833 dsdt_line(" }"); 1834 dsdt_line(" Else"); 1835 dsdt_line(" {"); 1836 dsdt_line(" Return (PPRT)"); 1837 dsdt_line(" }"); 1838 dsdt_line("}"); 1839 dsdt_unindent(2); 1840 } 1841 #endif 1842 1843 dsdt_indent(2); 1844 for (slot = 0; slot < MAXSLOTS; slot++) { 1845 si = &bi->slotinfo[slot]; 1846 for (func = 0; func < MAXFUNCS; func++) { 1847 pi = si->si_funcs[func].fi_devi; 1848 if (pi != NULL && pi->pi_d->pe_write_dsdt != NULL) 1849 pi->pi_d->pe_write_dsdt(pi); 1850 } 1851 } 1852 dsdt_unindent(2); 1853 done: 1854 dsdt_line(" }"); 1855 } 1856 1857 void 1858 pci_write_dsdt(void) 1859 { 1860 int bus; 1861 1862 dsdt_indent(1); 1863 dsdt_line("Name (PICM, 0x00)"); 1864 dsdt_line("Method (_PIC, 1, NotSerialized)"); 1865 dsdt_line("{"); 1866 dsdt_line(" Store (Arg0, PICM)"); 1867 dsdt_line("}"); 1868 dsdt_line(""); 1869 dsdt_line("Scope (_SB)"); 1870 dsdt_line("{"); 1871 for (bus = 0; bus < MAXBUSES; bus++) 1872 pci_bus_write_dsdt(bus); 1873 dsdt_line("}"); 1874 dsdt_unindent(1); 1875 } 1876 1877 int 1878 pci_bus_configured(int bus) 1879 { 1880 assert(bus >= 0 && bus < MAXBUSES); 1881 return (pci_businfo[bus] != NULL); 1882 } 1883 1884 int 1885 pci_msi_enabled(struct pci_devinst *pi) 1886 { 1887 return (pi->pi_msi.enabled); 1888 } 1889 1890 int 1891 pci_msi_maxmsgnum(struct pci_devinst *pi) 1892 { 1893 if (pi->pi_msi.enabled) 1894 return (pi->pi_msi.maxmsgnum); 1895 else 1896 return (0); 1897 } 1898 1899 int 1900 pci_msix_enabled(struct pci_devinst *pi) 1901 { 1902 1903 return (pi->pi_msix.enabled && !pi->pi_msi.enabled); 1904 } 1905 1906 void 1907 pci_generate_msix(struct pci_devinst *pi, int index) 1908 { 1909 struct msix_table_entry *mte; 1910 1911 if (!pci_msix_enabled(pi)) 1912 return; 1913 1914 if (pi->pi_msix.function_mask) 1915 return; 1916 1917 if (index >= pi->pi_msix.table_count) 1918 return; 1919 1920 mte = &pi->pi_msix.table[index]; 1921 if ((mte->vector_control & PCIM_MSIX_VCTRL_MASK) == 0) { 1922 /* XXX Set PBA bit if interrupt is disabled */ 1923 vm_lapic_msi(pi->pi_vmctx, mte->addr, mte->msg_data); 1924 } 1925 } 1926 1927 void 1928 pci_generate_msi(struct pci_devinst *pi, int index) 1929 { 1930 1931 if (pci_msi_enabled(pi) && index < pci_msi_maxmsgnum(pi)) { 1932 vm_lapic_msi(pi->pi_vmctx, pi->pi_msi.addr, 1933 pi->pi_msi.msg_data + index); 1934 } 1935 } 1936 1937 #ifdef __amd64__ 1938 static bool 1939 pci_lintr_permitted(struct pci_devinst *pi) 1940 { 1941 uint16_t cmd; 1942 1943 cmd = pci_get_cfgdata16(pi, PCIR_COMMAND); 1944 return (!(pi->pi_msi.enabled || pi->pi_msix.enabled || 1945 (cmd & PCIM_CMD_INTxDIS))); 1946 } 1947 1948 void 1949 pci_lintr_request(struct pci_devinst *pi) 1950 { 1951 struct businfo *bi; 1952 struct slotinfo *si; 1953 int bestpin, bestcount, pin; 1954 1955 bi = pci_businfo[pi->pi_bus]; 1956 assert(bi != NULL); 1957 1958 /* 1959 * Just allocate a pin from our slot. The pin will be 1960 * assigned IRQs later when interrupts are routed. 1961 */ 1962 si = &bi->slotinfo[pi->pi_slot]; 1963 bestpin = 0; 1964 bestcount = si->si_intpins[0].ii_count; 1965 for (pin = 1; pin < 4; pin++) { 1966 if (si->si_intpins[pin].ii_count < bestcount) { 1967 bestpin = pin; 1968 bestcount = si->si_intpins[pin].ii_count; 1969 } 1970 } 1971 1972 si->si_intpins[bestpin].ii_count++; 1973 pi->pi_lintr.pin = bestpin + 1; 1974 pci_set_cfgdata8(pi, PCIR_INTPIN, bestpin + 1); 1975 } 1976 1977 static void 1978 pci_lintr_route(struct pci_devinst *pi) 1979 { 1980 struct businfo *bi; 1981 struct intxinfo *ii; 1982 1983 if (pi->pi_lintr.pin == 0) 1984 return; 1985 1986 bi = pci_businfo[pi->pi_bus]; 1987 assert(bi != NULL); 1988 ii = &bi->slotinfo[pi->pi_slot].si_intpins[pi->pi_lintr.pin - 1]; 1989 1990 /* 1991 * Attempt to allocate an I/O APIC pin for this intpin if one 1992 * is not yet assigned. 1993 */ 1994 if (ii->ii_ioapic_irq == 0) 1995 ii->ii_ioapic_irq = ioapic_pci_alloc_irq(pi); 1996 assert(ii->ii_ioapic_irq > 0); 1997 1998 /* 1999 * Attempt to allocate a PIRQ pin for this intpin if one is 2000 * not yet assigned. 2001 */ 2002 if (ii->ii_pirq_pin == 0) 2003 ii->ii_pirq_pin = pirq_alloc_pin(pi); 2004 assert(ii->ii_pirq_pin > 0); 2005 2006 pi->pi_lintr.ioapic_irq = ii->ii_ioapic_irq; 2007 pi->pi_lintr.pirq_pin = ii->ii_pirq_pin; 2008 pci_set_cfgdata8(pi, PCIR_INTLINE, pirq_irq(ii->ii_pirq_pin)); 2009 } 2010 2011 void 2012 pci_lintr_assert(struct pci_devinst *pi) 2013 { 2014 2015 assert(pi->pi_lintr.pin > 0); 2016 2017 pthread_mutex_lock(&pi->pi_lintr.lock); 2018 if (pi->pi_lintr.state == IDLE) { 2019 if (pci_lintr_permitted(pi)) { 2020 pi->pi_lintr.state = ASSERTED; 2021 pci_irq_assert(pi); 2022 } else 2023 pi->pi_lintr.state = PENDING; 2024 } 2025 pthread_mutex_unlock(&pi->pi_lintr.lock); 2026 } 2027 2028 void 2029 pci_lintr_deassert(struct pci_devinst *pi) 2030 { 2031 2032 assert(pi->pi_lintr.pin > 0); 2033 2034 pthread_mutex_lock(&pi->pi_lintr.lock); 2035 if (pi->pi_lintr.state == ASSERTED) { 2036 pi->pi_lintr.state = IDLE; 2037 pci_irq_deassert(pi); 2038 } else if (pi->pi_lintr.state == PENDING) 2039 pi->pi_lintr.state = IDLE; 2040 pthread_mutex_unlock(&pi->pi_lintr.lock); 2041 } 2042 2043 static void 2044 pci_lintr_update(struct pci_devinst *pi) 2045 { 2046 2047 pthread_mutex_lock(&pi->pi_lintr.lock); 2048 if (pi->pi_lintr.state == ASSERTED && !pci_lintr_permitted(pi)) { 2049 pci_irq_deassert(pi); 2050 pi->pi_lintr.state = PENDING; 2051 } else if (pi->pi_lintr.state == PENDING && pci_lintr_permitted(pi)) { 2052 pi->pi_lintr.state = ASSERTED; 2053 pci_irq_assert(pi); 2054 } 2055 pthread_mutex_unlock(&pi->pi_lintr.lock); 2056 } 2057 2058 int 2059 pci_count_lintr(int bus) 2060 { 2061 int count, slot, pin; 2062 struct slotinfo *slotinfo; 2063 2064 count = 0; 2065 if (pci_businfo[bus] != NULL) { 2066 for (slot = 0; slot < MAXSLOTS; slot++) { 2067 slotinfo = &pci_businfo[bus]->slotinfo[slot]; 2068 for (pin = 0; pin < 4; pin++) { 2069 if (slotinfo->si_intpins[pin].ii_count != 0) 2070 count++; 2071 } 2072 } 2073 } 2074 return (count); 2075 } 2076 2077 void 2078 pci_walk_lintr(int bus, pci_lintr_cb cb, void *arg) 2079 { 2080 struct businfo *bi; 2081 struct slotinfo *si; 2082 struct intxinfo *ii; 2083 int slot, pin; 2084 2085 if ((bi = pci_businfo[bus]) == NULL) 2086 return; 2087 2088 for (slot = 0; slot < MAXSLOTS; slot++) { 2089 si = &bi->slotinfo[slot]; 2090 for (pin = 0; pin < 4; pin++) { 2091 ii = &si->si_intpins[pin]; 2092 if (ii->ii_count != 0) 2093 cb(bus, slot, pin + 1, ii->ii_pirq_pin, 2094 ii->ii_ioapic_irq, arg); 2095 } 2096 } 2097 } 2098 #endif /* __amd64__ */ 2099 2100 /* 2101 * Return 1 if the emulated device in 'slot' is a multi-function device. 2102 * Return 0 otherwise. 2103 */ 2104 static int 2105 pci_emul_is_mfdev(int bus, int slot) 2106 { 2107 struct businfo *bi; 2108 struct slotinfo *si; 2109 int f, numfuncs; 2110 2111 numfuncs = 0; 2112 if ((bi = pci_businfo[bus]) != NULL) { 2113 si = &bi->slotinfo[slot]; 2114 for (f = 0; f < MAXFUNCS; f++) { 2115 if (si->si_funcs[f].fi_devi != NULL) { 2116 numfuncs++; 2117 } 2118 } 2119 } 2120 return (numfuncs > 1); 2121 } 2122 2123 /* 2124 * Ensure that the PCIM_MFDEV bit is properly set (or unset) depending on 2125 * whether or not is a multi-function being emulated in the pci 'slot'. 2126 */ 2127 static void 2128 pci_emul_hdrtype_fixup(int bus, int slot, int off, int bytes, uint32_t *rv) 2129 { 2130 int mfdev; 2131 2132 if (off <= PCIR_HDRTYPE && off + bytes > PCIR_HDRTYPE) { 2133 mfdev = pci_emul_is_mfdev(bus, slot); 2134 switch (bytes) { 2135 case 1: 2136 case 2: 2137 *rv &= ~PCIM_MFDEV; 2138 if (mfdev) { 2139 *rv |= PCIM_MFDEV; 2140 } 2141 break; 2142 case 4: 2143 *rv &= ~(PCIM_MFDEV << 16); 2144 if (mfdev) { 2145 *rv |= (PCIM_MFDEV << 16); 2146 } 2147 break; 2148 } 2149 } 2150 } 2151 2152 /* 2153 * Update device state in response to changes to the PCI command 2154 * register. 2155 */ 2156 void 2157 pci_emul_cmd_changed(struct pci_devinst *pi, uint16_t old) 2158 { 2159 int i; 2160 uint16_t changed, new; 2161 2162 new = pci_get_cfgdata16(pi, PCIR_COMMAND); 2163 changed = old ^ new; 2164 2165 /* 2166 * If the MMIO or I/O address space decoding has changed then 2167 * register/unregister all BARs that decode that address space. 2168 */ 2169 for (i = 0; i <= PCI_BARMAX_WITH_ROM; i++) { 2170 switch (pi->pi_bar[i].type) { 2171 case PCIBAR_NONE: 2172 case PCIBAR_MEMHI64: 2173 break; 2174 case PCIBAR_IO: 2175 /* I/O address space decoding changed? */ 2176 if (changed & PCIM_CMD_PORTEN) { 2177 if (new & PCIM_CMD_PORTEN) 2178 register_bar(pi, i); 2179 else 2180 unregister_bar(pi, i); 2181 } 2182 break; 2183 case PCIBAR_ROM: 2184 /* skip (un-)register of ROM if it disabled */ 2185 if (!romen(pi)) 2186 break; 2187 /* fallthrough */ 2188 case PCIBAR_MEM32: 2189 case PCIBAR_MEM64: 2190 /* MMIO address space decoding changed? */ 2191 if (changed & PCIM_CMD_MEMEN) { 2192 if (new & PCIM_CMD_MEMEN) 2193 register_bar(pi, i); 2194 else 2195 unregister_bar(pi, i); 2196 } 2197 break; 2198 default: 2199 assert(0); 2200 } 2201 } 2202 2203 #ifdef __amd64__ 2204 /* 2205 * If INTx has been unmasked and is pending, assert the 2206 * interrupt. 2207 */ 2208 pci_lintr_update(pi); 2209 #endif 2210 } 2211 2212 static void 2213 pci_emul_cmdsts_write(struct pci_devinst *pi, int coff, uint32_t new, int bytes) 2214 { 2215 int rshift; 2216 uint32_t cmd, old, readonly; 2217 2218 cmd = pci_get_cfgdata16(pi, PCIR_COMMAND); /* stash old value */ 2219 2220 /* 2221 * From PCI Local Bus Specification 3.0 sections 6.2.2 and 6.2.3. 2222 * 2223 * XXX Bits 8, 11, 12, 13, 14 and 15 in the status register are 2224 * 'write 1 to clear'. However these bits are not set to '1' by 2225 * any device emulation so it is simpler to treat them as readonly. 2226 */ 2227 rshift = (coff & 0x3) * 8; 2228 readonly = 0xFFFFF880 >> rshift; 2229 2230 old = CFGREAD(pi, coff, bytes); 2231 new &= ~readonly; 2232 new |= (old & readonly); 2233 CFGWRITE(pi, coff, new, bytes); /* update config */ 2234 2235 pci_emul_cmd_changed(pi, cmd); 2236 } 2237 2238 static void 2239 pci_cfgrw(int in, int bus, int slot, int func, int coff, int bytes, 2240 uint32_t *valp) 2241 { 2242 struct businfo *bi; 2243 struct slotinfo *si; 2244 struct pci_devinst *pi; 2245 struct pci_devemu *pe; 2246 int idx, needcfg; 2247 uint64_t addr, bar, mask; 2248 2249 if ((bi = pci_businfo[bus]) != NULL) { 2250 si = &bi->slotinfo[slot]; 2251 pi = si->si_funcs[func].fi_devi; 2252 } else 2253 pi = NULL; 2254 2255 /* 2256 * Just return if there is no device at this slot:func or if the 2257 * the guest is doing an un-aligned access. 2258 */ 2259 if (pi == NULL || (bytes != 1 && bytes != 2 && bytes != 4) || 2260 (coff & (bytes - 1)) != 0) { 2261 if (in) 2262 *valp = 0xffffffff; 2263 return; 2264 } 2265 2266 /* 2267 * Ignore all writes beyond the standard config space and return all 2268 * ones on reads. 2269 */ 2270 if (coff >= PCI_REGMAX + 1) { 2271 if (in) { 2272 *valp = 0xffffffff; 2273 /* 2274 * Extended capabilities begin at offset 256 in config 2275 * space. Absence of extended capabilities is signaled 2276 * with all 0s in the extended capability header at 2277 * offset 256. 2278 */ 2279 if (coff <= PCI_REGMAX + 4) 2280 *valp = 0x00000000; 2281 } 2282 return; 2283 } 2284 2285 pe = pi->pi_d; 2286 2287 /* 2288 * Config read 2289 */ 2290 if (in) { 2291 /* Let the device emulation override the default handler */ 2292 if (pe->pe_cfgread != NULL) { 2293 needcfg = pe->pe_cfgread(pi, coff, bytes, valp); 2294 } else { 2295 needcfg = 1; 2296 } 2297 2298 if (needcfg) 2299 *valp = CFGREAD(pi, coff, bytes); 2300 2301 pci_emul_hdrtype_fixup(bus, slot, coff, bytes, valp); 2302 } else { 2303 /* Let the device emulation override the default handler */ 2304 if (pe->pe_cfgwrite != NULL && 2305 (*pe->pe_cfgwrite)(pi, coff, bytes, *valp) == 0) 2306 return; 2307 2308 /* 2309 * Special handling for write to BAR and ROM registers 2310 */ 2311 if (is_pcir_bar(coff) || is_pcir_bios(coff)) { 2312 /* 2313 * Ignore writes to BAR registers that are not 2314 * 4-byte aligned. 2315 */ 2316 if (bytes != 4 || (coff & 0x3) != 0) 2317 return; 2318 2319 if (is_pcir_bar(coff)) { 2320 idx = (coff - PCIR_BAR(0)) / 4; 2321 } else if (is_pcir_bios(coff)) { 2322 idx = PCI_ROM_IDX; 2323 } else { 2324 errx(4, "%s: invalid BAR offset %d", __func__, 2325 coff); 2326 } 2327 2328 mask = ~(pi->pi_bar[idx].size - 1); 2329 switch (pi->pi_bar[idx].type) { 2330 case PCIBAR_NONE: 2331 pi->pi_bar[idx].addr = bar = 0; 2332 break; 2333 case PCIBAR_IO: 2334 addr = *valp & mask; 2335 addr &= 0xffff; 2336 bar = addr | pi->pi_bar[idx].lobits; 2337 /* 2338 * Register the new BAR value for interception 2339 */ 2340 if (addr != pi->pi_bar[idx].addr) { 2341 update_bar_address(pi, addr, idx, 2342 PCIBAR_IO); 2343 } 2344 break; 2345 case PCIBAR_MEM32: 2346 addr = bar = *valp & mask; 2347 bar |= pi->pi_bar[idx].lobits; 2348 if (addr != pi->pi_bar[idx].addr) { 2349 update_bar_address(pi, addr, idx, 2350 PCIBAR_MEM32); 2351 } 2352 break; 2353 case PCIBAR_MEM64: 2354 addr = bar = *valp & mask; 2355 bar |= pi->pi_bar[idx].lobits; 2356 if (addr != (uint32_t)pi->pi_bar[idx].addr) { 2357 update_bar_address(pi, addr, idx, 2358 PCIBAR_MEM64); 2359 } 2360 break; 2361 case PCIBAR_MEMHI64: 2362 mask = ~(pi->pi_bar[idx - 1].size - 1); 2363 addr = ((uint64_t)*valp << 32) & mask; 2364 bar = addr >> 32; 2365 if (bar != pi->pi_bar[idx - 1].addr >> 32) { 2366 update_bar_address(pi, addr, idx - 1, 2367 PCIBAR_MEMHI64); 2368 } 2369 break; 2370 case PCIBAR_ROM: 2371 addr = bar = *valp & mask; 2372 if (memen(pi) && romen(pi)) { 2373 unregister_bar(pi, idx); 2374 } 2375 pi->pi_bar[idx].addr = addr; 2376 pi->pi_bar[idx].lobits = *valp & 2377 PCIM_BIOS_ENABLE; 2378 /* romen could have changed it value */ 2379 if (memen(pi) && romen(pi)) { 2380 register_bar(pi, idx); 2381 } 2382 bar |= pi->pi_bar[idx].lobits; 2383 break; 2384 default: 2385 assert(0); 2386 } 2387 pci_set_cfgdata32(pi, coff, bar); 2388 2389 } else if (pci_emul_iscap(pi, coff)) { 2390 pci_emul_capwrite(pi, coff, bytes, *valp, 0, 0); 2391 } else if (coff >= PCIR_COMMAND && coff < PCIR_REVID) { 2392 pci_emul_cmdsts_write(pi, coff, *valp, bytes); 2393 } else { 2394 CFGWRITE(pi, coff, *valp, bytes); 2395 } 2396 } 2397 } 2398 2399 #ifdef __amd64__ 2400 static int cfgenable, cfgbus, cfgslot, cfgfunc, cfgoff; 2401 2402 static int 2403 pci_emul_cfgaddr(struct vmctx *ctx __unused, int in, 2404 int port __unused, int bytes, uint32_t *eax, void *arg __unused) 2405 { 2406 uint32_t x; 2407 2408 if (bytes != 4) { 2409 if (in) 2410 *eax = (bytes == 2) ? 0xffff : 0xff; 2411 return (0); 2412 } 2413 2414 if (in) { 2415 x = (cfgbus << 16) | (cfgslot << 11) | (cfgfunc << 8) | cfgoff; 2416 if (cfgenable) 2417 x |= CONF1_ENABLE; 2418 *eax = x; 2419 } else { 2420 x = *eax; 2421 cfgenable = (x & CONF1_ENABLE) == CONF1_ENABLE; 2422 cfgoff = (x & PCI_REGMAX) & ~0x03; 2423 cfgfunc = (x >> 8) & PCI_FUNCMAX; 2424 cfgslot = (x >> 11) & PCI_SLOTMAX; 2425 cfgbus = (x >> 16) & PCI_BUSMAX; 2426 } 2427 2428 return (0); 2429 } 2430 INOUT_PORT(pci_cfgaddr, CONF1_ADDR_PORT, IOPORT_F_INOUT, pci_emul_cfgaddr); 2431 2432 static int 2433 pci_emul_cfgdata(struct vmctx *ctx __unused, int in, int port, 2434 int bytes, uint32_t *eax, void *arg __unused) 2435 { 2436 int coff; 2437 2438 assert(bytes == 1 || bytes == 2 || bytes == 4); 2439 2440 coff = cfgoff + (port - CONF1_DATA_PORT); 2441 if (cfgenable) { 2442 pci_cfgrw(in, cfgbus, cfgslot, cfgfunc, coff, bytes, eax); 2443 } else { 2444 /* Ignore accesses to cfgdata if not enabled by cfgaddr */ 2445 if (in) 2446 *eax = 0xffffffff; 2447 } 2448 return (0); 2449 } 2450 2451 INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+0, IOPORT_F_INOUT, pci_emul_cfgdata); 2452 INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+1, IOPORT_F_INOUT, pci_emul_cfgdata); 2453 INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+2, IOPORT_F_INOUT, pci_emul_cfgdata); 2454 INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+3, IOPORT_F_INOUT, pci_emul_cfgdata); 2455 #endif 2456 2457 #ifdef BHYVE_SNAPSHOT 2458 /* 2459 * Saves/restores PCI device emulated state. Returns 0 on success. 2460 */ 2461 static int 2462 pci_snapshot_pci_dev(struct vm_snapshot_meta *meta) 2463 { 2464 struct pci_devinst *pi; 2465 int i; 2466 int ret; 2467 2468 pi = meta->dev_data; 2469 2470 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msi.enabled, meta, ret, done); 2471 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msi.addr, meta, ret, done); 2472 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msi.msg_data, meta, ret, done); 2473 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msi.maxmsgnum, meta, ret, done); 2474 2475 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.enabled, meta, ret, done); 2476 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.table_bar, meta, ret, done); 2477 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.pba_bar, meta, ret, done); 2478 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.table_offset, meta, ret, done); 2479 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.table_count, meta, ret, done); 2480 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.pba_offset, meta, ret, done); 2481 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.pba_size, meta, ret, done); 2482 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.function_mask, meta, ret, done); 2483 2484 SNAPSHOT_BUF_OR_LEAVE(pi->pi_cfgdata, sizeof(pi->pi_cfgdata), 2485 meta, ret, done); 2486 2487 for (i = 0; i < (int)nitems(pi->pi_bar); i++) { 2488 SNAPSHOT_VAR_OR_LEAVE(pi->pi_bar[i].type, meta, ret, done); 2489 SNAPSHOT_VAR_OR_LEAVE(pi->pi_bar[i].size, meta, ret, done); 2490 SNAPSHOT_VAR_OR_LEAVE(pi->pi_bar[i].addr, meta, ret, done); 2491 } 2492 2493 /* Restore MSI-X table. */ 2494 for (i = 0; i < pi->pi_msix.table_count; i++) { 2495 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.table[i].addr, 2496 meta, ret, done); 2497 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.table[i].msg_data, 2498 meta, ret, done); 2499 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.table[i].vector_control, 2500 meta, ret, done); 2501 } 2502 2503 done: 2504 return (ret); 2505 } 2506 2507 int 2508 pci_snapshot(struct vm_snapshot_meta *meta) 2509 { 2510 struct pci_devemu *pde; 2511 struct pci_devinst *pdi; 2512 int ret; 2513 2514 assert(meta->dev_name != NULL); 2515 2516 pdi = meta->dev_data; 2517 pde = pdi->pi_d; 2518 2519 if (pde->pe_snapshot == NULL) 2520 return (ENOTSUP); 2521 2522 ret = pci_snapshot_pci_dev(meta); 2523 if (ret == 0) 2524 ret = (*pde->pe_snapshot)(meta); 2525 2526 return (ret); 2527 } 2528 2529 int 2530 pci_pause(struct pci_devinst *pdi) 2531 { 2532 struct pci_devemu *pde = pdi->pi_d; 2533 2534 if (pde->pe_pause == NULL) { 2535 /* The pause/resume functionality is optional. */ 2536 return (0); 2537 } 2538 2539 return (*pde->pe_pause)(pdi); 2540 } 2541 2542 int 2543 pci_resume(struct pci_devinst *pdi) 2544 { 2545 struct pci_devemu *pde = pdi->pi_d; 2546 2547 if (pde->pe_resume == NULL) { 2548 /* The pause/resume functionality is optional. */ 2549 return (0); 2550 } 2551 2552 return (*pde->pe_resume)(pdi); 2553 } 2554 #endif 2555 2556 #define PCI_EMUL_TEST 2557 #ifdef PCI_EMUL_TEST 2558 /* 2559 * Define a dummy test device 2560 */ 2561 #define DIOSZ 8 2562 #define DMEMSZ 4096 2563 struct pci_emul_dsoftc { 2564 uint8_t ioregs[DIOSZ]; 2565 uint8_t memregs[2][DMEMSZ]; 2566 }; 2567 2568 #define PCI_EMUL_MSI_MSGS 4 2569 #define PCI_EMUL_MSIX_MSGS 16 2570 2571 static int 2572 pci_emul_dinit(struct pci_devinst *pi, nvlist_t *nvl __unused) 2573 { 2574 int error; 2575 struct pci_emul_dsoftc *sc; 2576 2577 sc = calloc(1, sizeof(struct pci_emul_dsoftc)); 2578 2579 pi->pi_arg = sc; 2580 2581 pci_set_cfgdata16(pi, PCIR_DEVICE, 0x0001); 2582 pci_set_cfgdata16(pi, PCIR_VENDOR, 0x10DD); 2583 pci_set_cfgdata8(pi, PCIR_CLASS, 0x02); 2584 2585 error = pci_emul_add_msicap(pi, PCI_EMUL_MSI_MSGS); 2586 assert(error == 0); 2587 2588 error = pci_emul_alloc_bar(pi, 0, PCIBAR_IO, DIOSZ); 2589 assert(error == 0); 2590 2591 error = pci_emul_alloc_bar(pi, 1, PCIBAR_MEM32, DMEMSZ); 2592 assert(error == 0); 2593 2594 error = pci_emul_alloc_bar(pi, 2, PCIBAR_MEM32, DMEMSZ); 2595 assert(error == 0); 2596 2597 return (0); 2598 } 2599 2600 static void 2601 pci_emul_diow(struct pci_devinst *pi, int baridx, uint64_t offset, int size, 2602 uint64_t value) 2603 { 2604 int i; 2605 struct pci_emul_dsoftc *sc = pi->pi_arg; 2606 2607 if (baridx == 0) { 2608 if (offset + size > DIOSZ) { 2609 printf("diow: iow too large, offset %ld size %d\n", 2610 offset, size); 2611 return; 2612 } 2613 2614 if (size == 1) { 2615 sc->ioregs[offset] = value & 0xff; 2616 } else if (size == 2) { 2617 *(uint16_t *)&sc->ioregs[offset] = value & 0xffff; 2618 } else if (size == 4) { 2619 *(uint32_t *)&sc->ioregs[offset] = value; 2620 } else { 2621 printf("diow: iow unknown size %d\n", size); 2622 } 2623 2624 /* 2625 * Special magic value to generate an interrupt 2626 */ 2627 if (offset == 4 && size == 4 && pci_msi_enabled(pi)) 2628 pci_generate_msi(pi, value % pci_msi_maxmsgnum(pi)); 2629 2630 if (value == 0xabcdef) { 2631 for (i = 0; i < pci_msi_maxmsgnum(pi); i++) 2632 pci_generate_msi(pi, i); 2633 } 2634 } 2635 2636 if (baridx == 1 || baridx == 2) { 2637 if (offset + size > DMEMSZ) { 2638 printf("diow: memw too large, offset %ld size %d\n", 2639 offset, size); 2640 return; 2641 } 2642 2643 i = baridx - 1; /* 'memregs' index */ 2644 2645 if (size == 1) { 2646 sc->memregs[i][offset] = value; 2647 } else if (size == 2) { 2648 *(uint16_t *)&sc->memregs[i][offset] = value; 2649 } else if (size == 4) { 2650 *(uint32_t *)&sc->memregs[i][offset] = value; 2651 } else if (size == 8) { 2652 *(uint64_t *)&sc->memregs[i][offset] = value; 2653 } else { 2654 printf("diow: memw unknown size %d\n", size); 2655 } 2656 2657 /* 2658 * magic interrupt ?? 2659 */ 2660 } 2661 2662 if (baridx > 2 || baridx < 0) { 2663 printf("diow: unknown bar idx %d\n", baridx); 2664 } 2665 } 2666 2667 static uint64_t 2668 pci_emul_dior(struct pci_devinst *pi, int baridx, uint64_t offset, int size) 2669 { 2670 struct pci_emul_dsoftc *sc = pi->pi_arg; 2671 uint32_t value; 2672 int i; 2673 2674 if (baridx == 0) { 2675 if (offset + size > DIOSZ) { 2676 printf("dior: ior too large, offset %ld size %d\n", 2677 offset, size); 2678 return (0); 2679 } 2680 2681 value = 0; 2682 if (size == 1) { 2683 value = sc->ioregs[offset]; 2684 } else if (size == 2) { 2685 value = *(uint16_t *) &sc->ioregs[offset]; 2686 } else if (size == 4) { 2687 value = *(uint32_t *) &sc->ioregs[offset]; 2688 } else { 2689 printf("dior: ior unknown size %d\n", size); 2690 } 2691 } 2692 2693 if (baridx == 1 || baridx == 2) { 2694 if (offset + size > DMEMSZ) { 2695 printf("dior: memr too large, offset %ld size %d\n", 2696 offset, size); 2697 return (0); 2698 } 2699 2700 i = baridx - 1; /* 'memregs' index */ 2701 2702 if (size == 1) { 2703 value = sc->memregs[i][offset]; 2704 } else if (size == 2) { 2705 value = *(uint16_t *) &sc->memregs[i][offset]; 2706 } else if (size == 4) { 2707 value = *(uint32_t *) &sc->memregs[i][offset]; 2708 } else if (size == 8) { 2709 value = *(uint64_t *) &sc->memregs[i][offset]; 2710 } else { 2711 printf("dior: ior unknown size %d\n", size); 2712 } 2713 } 2714 2715 2716 if (baridx > 2 || baridx < 0) { 2717 printf("dior: unknown bar idx %d\n", baridx); 2718 return (0); 2719 } 2720 2721 return (value); 2722 } 2723 2724 #ifdef BHYVE_SNAPSHOT 2725 struct pci_devinst * 2726 pci_next(const struct pci_devinst *cursor) 2727 { 2728 unsigned bus = 0, slot = 0, func = 0; 2729 struct businfo *bi; 2730 struct slotinfo *si; 2731 struct funcinfo *fi; 2732 2733 bus = cursor ? cursor->pi_bus : 0; 2734 slot = cursor ? cursor->pi_slot : 0; 2735 func = cursor ? (cursor->pi_func + 1) : 0; 2736 2737 for (; bus < MAXBUSES; bus++) { 2738 if ((bi = pci_businfo[bus]) == NULL) 2739 continue; 2740 2741 if (slot >= MAXSLOTS) 2742 slot = 0; 2743 2744 for (; slot < MAXSLOTS; slot++) { 2745 si = &bi->slotinfo[slot]; 2746 if (func >= MAXFUNCS) 2747 func = 0; 2748 for (; func < MAXFUNCS; func++) { 2749 fi = &si->si_funcs[func]; 2750 if (fi->fi_devi == NULL) 2751 continue; 2752 2753 return (fi->fi_devi); 2754 } 2755 } 2756 } 2757 2758 return (NULL); 2759 } 2760 2761 static int 2762 pci_emul_snapshot(struct vm_snapshot_meta *meta __unused) 2763 { 2764 return (0); 2765 } 2766 #endif 2767 2768 static const struct pci_devemu pci_dummy = { 2769 .pe_emu = "dummy", 2770 .pe_init = pci_emul_dinit, 2771 .pe_barwrite = pci_emul_diow, 2772 .pe_barread = pci_emul_dior, 2773 #ifdef BHYVE_SNAPSHOT 2774 .pe_snapshot = pci_emul_snapshot, 2775 #endif 2776 }; 2777 PCI_EMUL_SET(pci_dummy); 2778 2779 #endif /* PCI_EMUL_TEST */ 2780