1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2011 NetApp, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 */ 30 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD$"); 33 34 #include <sys/param.h> 35 #include <sys/linker_set.h> 36 37 #include <ctype.h> 38 #include <errno.h> 39 #include <pthread.h> 40 #include <stdio.h> 41 #include <stdlib.h> 42 #include <string.h> 43 #include <strings.h> 44 #include <assert.h> 45 #include <stdbool.h> 46 47 #include <machine/vmm.h> 48 #include <vmmapi.h> 49 50 #include "acpi.h" 51 #include "bhyverun.h" 52 #include "inout.h" 53 #include "ioapic.h" 54 #include "mem.h" 55 #include "pci_emul.h" 56 #include "pci_irq.h" 57 #include "pci_lpc.h" 58 59 #define CONF1_ADDR_PORT 0x0cf8 60 #define CONF1_DATA_PORT 0x0cfc 61 62 #define CONF1_ENABLE 0x80000000ul 63 64 #define MAXBUSES (PCI_BUSMAX + 1) 65 #define MAXSLOTS (PCI_SLOTMAX + 1) 66 #define MAXFUNCS (PCI_FUNCMAX + 1) 67 68 struct funcinfo { 69 char *fi_name; 70 char *fi_param; 71 struct pci_devinst *fi_devi; 72 }; 73 74 struct intxinfo { 75 int ii_count; 76 int ii_pirq_pin; 77 int ii_ioapic_irq; 78 }; 79 80 struct slotinfo { 81 struct intxinfo si_intpins[4]; 82 struct funcinfo si_funcs[MAXFUNCS]; 83 }; 84 85 struct businfo { 86 uint16_t iobase, iolimit; /* I/O window */ 87 uint32_t membase32, memlimit32; /* mmio window below 4GB */ 88 uint64_t membase64, memlimit64; /* mmio window above 4GB */ 89 struct slotinfo slotinfo[MAXSLOTS]; 90 }; 91 92 static struct businfo *pci_businfo[MAXBUSES]; 93 94 SET_DECLARE(pci_devemu_set, struct pci_devemu); 95 96 static uint64_t pci_emul_iobase; 97 static uint64_t pci_emul_membase32; 98 static uint64_t pci_emul_membase64; 99 100 #define PCI_EMUL_IOBASE 0x2000 101 #define PCI_EMUL_IOLIMIT 0x10000 102 103 #define PCI_EMUL_ECFG_BASE 0xE0000000 /* 3.5GB */ 104 #define PCI_EMUL_ECFG_SIZE (MAXBUSES * 1024 * 1024) /* 1MB per bus */ 105 SYSRES_MEM(PCI_EMUL_ECFG_BASE, PCI_EMUL_ECFG_SIZE); 106 107 #define PCI_EMUL_MEMLIMIT32 PCI_EMUL_ECFG_BASE 108 109 #define PCI_EMUL_MEMBASE64 0xD000000000UL 110 #define PCI_EMUL_MEMLIMIT64 0xFD00000000UL 111 112 static struct pci_devemu *pci_emul_finddev(char *name); 113 static void pci_lintr_route(struct pci_devinst *pi); 114 static void pci_lintr_update(struct pci_devinst *pi); 115 static void pci_cfgrw(struct vmctx *ctx, int vcpu, int in, int bus, int slot, 116 int func, int coff, int bytes, uint32_t *val); 117 118 static __inline void 119 CFGWRITE(struct pci_devinst *pi, int coff, uint32_t val, int bytes) 120 { 121 122 if (bytes == 1) 123 pci_set_cfgdata8(pi, coff, val); 124 else if (bytes == 2) 125 pci_set_cfgdata16(pi, coff, val); 126 else 127 pci_set_cfgdata32(pi, coff, val); 128 } 129 130 static __inline uint32_t 131 CFGREAD(struct pci_devinst *pi, int coff, int bytes) 132 { 133 134 if (bytes == 1) 135 return (pci_get_cfgdata8(pi, coff)); 136 else if (bytes == 2) 137 return (pci_get_cfgdata16(pi, coff)); 138 else 139 return (pci_get_cfgdata32(pi, coff)); 140 } 141 142 /* 143 * I/O access 144 */ 145 146 /* 147 * Slot options are in the form: 148 * 149 * <bus>:<slot>:<func>,<emul>[,<config>] 150 * <slot>[:<func>],<emul>[,<config>] 151 * 152 * slot is 0..31 153 * func is 0..7 154 * emul is a string describing the type of PCI device e.g. virtio-net 155 * config is an optional string, depending on the device, that can be 156 * used for configuration. 157 * Examples are: 158 * 1,virtio-net,tap0 159 * 3:0,dummy 160 */ 161 static void 162 pci_parse_slot_usage(char *aopt) 163 { 164 165 fprintf(stderr, "Invalid PCI slot info field \"%s\"\n", aopt); 166 } 167 168 int 169 pci_parse_slot(char *opt) 170 { 171 struct businfo *bi; 172 struct slotinfo *si; 173 char *emul, *config, *str, *cp; 174 int error, bnum, snum, fnum; 175 176 error = -1; 177 str = strdup(opt); 178 179 emul = config = NULL; 180 if ((cp = strchr(str, ',')) != NULL) { 181 *cp = '\0'; 182 emul = cp + 1; 183 if ((cp = strchr(emul, ',')) != NULL) { 184 *cp = '\0'; 185 config = cp + 1; 186 } 187 } else { 188 pci_parse_slot_usage(opt); 189 goto done; 190 } 191 192 /* <bus>:<slot>:<func> */ 193 if (sscanf(str, "%d:%d:%d", &bnum, &snum, &fnum) != 3) { 194 bnum = 0; 195 /* <slot>:<func> */ 196 if (sscanf(str, "%d:%d", &snum, &fnum) != 2) { 197 fnum = 0; 198 /* <slot> */ 199 if (sscanf(str, "%d", &snum) != 1) { 200 snum = -1; 201 } 202 } 203 } 204 205 if (bnum < 0 || bnum >= MAXBUSES || snum < 0 || snum >= MAXSLOTS || 206 fnum < 0 || fnum >= MAXFUNCS) { 207 pci_parse_slot_usage(opt); 208 goto done; 209 } 210 211 if (pci_businfo[bnum] == NULL) 212 pci_businfo[bnum] = calloc(1, sizeof(struct businfo)); 213 214 bi = pci_businfo[bnum]; 215 si = &bi->slotinfo[snum]; 216 217 if (si->si_funcs[fnum].fi_name != NULL) { 218 fprintf(stderr, "pci slot %d:%d already occupied!\n", 219 snum, fnum); 220 goto done; 221 } 222 223 if (pci_emul_finddev(emul) == NULL) { 224 fprintf(stderr, "pci slot %d:%d: unknown device \"%s\"\n", 225 snum, fnum, emul); 226 goto done; 227 } 228 229 error = 0; 230 si->si_funcs[fnum].fi_name = emul; 231 si->si_funcs[fnum].fi_param = config; 232 233 done: 234 if (error) 235 free(str); 236 237 return (error); 238 } 239 240 static int 241 pci_valid_pba_offset(struct pci_devinst *pi, uint64_t offset) 242 { 243 244 if (offset < pi->pi_msix.pba_offset) 245 return (0); 246 247 if (offset >= pi->pi_msix.pba_offset + pi->pi_msix.pba_size) { 248 return (0); 249 } 250 251 return (1); 252 } 253 254 int 255 pci_emul_msix_twrite(struct pci_devinst *pi, uint64_t offset, int size, 256 uint64_t value) 257 { 258 int msix_entry_offset; 259 int tab_index; 260 char *dest; 261 262 /* support only 4 or 8 byte writes */ 263 if (size != 4 && size != 8) 264 return (-1); 265 266 /* 267 * Return if table index is beyond what device supports 268 */ 269 tab_index = offset / MSIX_TABLE_ENTRY_SIZE; 270 if (tab_index >= pi->pi_msix.table_count) 271 return (-1); 272 273 msix_entry_offset = offset % MSIX_TABLE_ENTRY_SIZE; 274 275 /* support only aligned writes */ 276 if ((msix_entry_offset % size) != 0) 277 return (-1); 278 279 dest = (char *)(pi->pi_msix.table + tab_index); 280 dest += msix_entry_offset; 281 282 if (size == 4) 283 *((uint32_t *)dest) = value; 284 else 285 *((uint64_t *)dest) = value; 286 287 return (0); 288 } 289 290 uint64_t 291 pci_emul_msix_tread(struct pci_devinst *pi, uint64_t offset, int size) 292 { 293 char *dest; 294 int msix_entry_offset; 295 int tab_index; 296 uint64_t retval = ~0; 297 298 /* 299 * The PCI standard only allows 4 and 8 byte accesses to the MSI-X 300 * table but we also allow 1 byte access to accommodate reads from 301 * ddb. 302 */ 303 if (size != 1 && size != 4 && size != 8) 304 return (retval); 305 306 msix_entry_offset = offset % MSIX_TABLE_ENTRY_SIZE; 307 308 /* support only aligned reads */ 309 if ((msix_entry_offset % size) != 0) { 310 return (retval); 311 } 312 313 tab_index = offset / MSIX_TABLE_ENTRY_SIZE; 314 315 if (tab_index < pi->pi_msix.table_count) { 316 /* valid MSI-X Table access */ 317 dest = (char *)(pi->pi_msix.table + tab_index); 318 dest += msix_entry_offset; 319 320 if (size == 1) 321 retval = *((uint8_t *)dest); 322 else if (size == 4) 323 retval = *((uint32_t *)dest); 324 else 325 retval = *((uint64_t *)dest); 326 } else if (pci_valid_pba_offset(pi, offset)) { 327 /* return 0 for PBA access */ 328 retval = 0; 329 } 330 331 return (retval); 332 } 333 334 int 335 pci_msix_table_bar(struct pci_devinst *pi) 336 { 337 338 if (pi->pi_msix.table != NULL) 339 return (pi->pi_msix.table_bar); 340 else 341 return (-1); 342 } 343 344 int 345 pci_msix_pba_bar(struct pci_devinst *pi) 346 { 347 348 if (pi->pi_msix.table != NULL) 349 return (pi->pi_msix.pba_bar); 350 else 351 return (-1); 352 } 353 354 static int 355 pci_emul_io_handler(struct vmctx *ctx, int vcpu, int in, int port, int bytes, 356 uint32_t *eax, void *arg) 357 { 358 struct pci_devinst *pdi = arg; 359 struct pci_devemu *pe = pdi->pi_d; 360 uint64_t offset; 361 int i; 362 363 for (i = 0; i <= PCI_BARMAX; i++) { 364 if (pdi->pi_bar[i].type == PCIBAR_IO && 365 port >= pdi->pi_bar[i].addr && 366 port + bytes <= pdi->pi_bar[i].addr + pdi->pi_bar[i].size) { 367 offset = port - pdi->pi_bar[i].addr; 368 if (in) 369 *eax = (*pe->pe_barread)(ctx, vcpu, pdi, i, 370 offset, bytes); 371 else 372 (*pe->pe_barwrite)(ctx, vcpu, pdi, i, offset, 373 bytes, *eax); 374 return (0); 375 } 376 } 377 return (-1); 378 } 379 380 static int 381 pci_emul_mem_handler(struct vmctx *ctx, int vcpu, int dir, uint64_t addr, 382 int size, uint64_t *val, void *arg1, long arg2) 383 { 384 struct pci_devinst *pdi = arg1; 385 struct pci_devemu *pe = pdi->pi_d; 386 uint64_t offset; 387 int bidx = (int) arg2; 388 389 assert(bidx <= PCI_BARMAX); 390 assert(pdi->pi_bar[bidx].type == PCIBAR_MEM32 || 391 pdi->pi_bar[bidx].type == PCIBAR_MEM64); 392 assert(addr >= pdi->pi_bar[bidx].addr && 393 addr + size <= pdi->pi_bar[bidx].addr + pdi->pi_bar[bidx].size); 394 395 offset = addr - pdi->pi_bar[bidx].addr; 396 397 if (dir == MEM_F_WRITE) { 398 if (size == 8) { 399 (*pe->pe_barwrite)(ctx, vcpu, pdi, bidx, offset, 400 4, *val & 0xffffffff); 401 (*pe->pe_barwrite)(ctx, vcpu, pdi, bidx, offset + 4, 402 4, *val >> 32); 403 } else { 404 (*pe->pe_barwrite)(ctx, vcpu, pdi, bidx, offset, 405 size, *val); 406 } 407 } else { 408 if (size == 8) { 409 *val = (*pe->pe_barread)(ctx, vcpu, pdi, bidx, 410 offset, 4); 411 *val |= (*pe->pe_barread)(ctx, vcpu, pdi, bidx, 412 offset + 4, 4) << 32; 413 } else { 414 *val = (*pe->pe_barread)(ctx, vcpu, pdi, bidx, 415 offset, size); 416 } 417 } 418 419 return (0); 420 } 421 422 423 static int 424 pci_emul_alloc_resource(uint64_t *baseptr, uint64_t limit, uint64_t size, 425 uint64_t *addr) 426 { 427 uint64_t base; 428 429 assert((size & (size - 1)) == 0); /* must be a power of 2 */ 430 431 base = roundup2(*baseptr, size); 432 433 if (base + size <= limit) { 434 *addr = base; 435 *baseptr = base + size; 436 return (0); 437 } else 438 return (-1); 439 } 440 441 int 442 pci_emul_alloc_bar(struct pci_devinst *pdi, int idx, enum pcibar_type type, 443 uint64_t size) 444 { 445 446 return (pci_emul_alloc_pbar(pdi, idx, 0, type, size)); 447 } 448 449 /* 450 * Register (or unregister) the MMIO or I/O region associated with the BAR 451 * register 'idx' of an emulated pci device. 452 */ 453 static void 454 modify_bar_registration(struct pci_devinst *pi, int idx, int registration) 455 { 456 int error; 457 struct inout_port iop; 458 struct mem_range mr; 459 460 switch (pi->pi_bar[idx].type) { 461 case PCIBAR_IO: 462 bzero(&iop, sizeof(struct inout_port)); 463 iop.name = pi->pi_name; 464 iop.port = pi->pi_bar[idx].addr; 465 iop.size = pi->pi_bar[idx].size; 466 if (registration) { 467 iop.flags = IOPORT_F_INOUT; 468 iop.handler = pci_emul_io_handler; 469 iop.arg = pi; 470 error = register_inout(&iop); 471 } else 472 error = unregister_inout(&iop); 473 break; 474 case PCIBAR_MEM32: 475 case PCIBAR_MEM64: 476 bzero(&mr, sizeof(struct mem_range)); 477 mr.name = pi->pi_name; 478 mr.base = pi->pi_bar[idx].addr; 479 mr.size = pi->pi_bar[idx].size; 480 if (registration) { 481 mr.flags = MEM_F_RW; 482 mr.handler = pci_emul_mem_handler; 483 mr.arg1 = pi; 484 mr.arg2 = idx; 485 error = register_mem(&mr); 486 } else 487 error = unregister_mem(&mr); 488 break; 489 default: 490 error = EINVAL; 491 break; 492 } 493 assert(error == 0); 494 } 495 496 static void 497 unregister_bar(struct pci_devinst *pi, int idx) 498 { 499 500 modify_bar_registration(pi, idx, 0); 501 } 502 503 static void 504 register_bar(struct pci_devinst *pi, int idx) 505 { 506 507 modify_bar_registration(pi, idx, 1); 508 } 509 510 /* Are we decoding i/o port accesses for the emulated pci device? */ 511 static int 512 porten(struct pci_devinst *pi) 513 { 514 uint16_t cmd; 515 516 cmd = pci_get_cfgdata16(pi, PCIR_COMMAND); 517 518 return (cmd & PCIM_CMD_PORTEN); 519 } 520 521 /* Are we decoding memory accesses for the emulated pci device? */ 522 static int 523 memen(struct pci_devinst *pi) 524 { 525 uint16_t cmd; 526 527 cmd = pci_get_cfgdata16(pi, PCIR_COMMAND); 528 529 return (cmd & PCIM_CMD_MEMEN); 530 } 531 532 /* 533 * Update the MMIO or I/O address that is decoded by the BAR register. 534 * 535 * If the pci device has enabled the address space decoding then intercept 536 * the address range decoded by the BAR register. 537 */ 538 static void 539 update_bar_address(struct pci_devinst *pi, uint64_t addr, int idx, int type) 540 { 541 int decode; 542 543 if (pi->pi_bar[idx].type == PCIBAR_IO) 544 decode = porten(pi); 545 else 546 decode = memen(pi); 547 548 if (decode) 549 unregister_bar(pi, idx); 550 551 switch (type) { 552 case PCIBAR_IO: 553 case PCIBAR_MEM32: 554 pi->pi_bar[idx].addr = addr; 555 break; 556 case PCIBAR_MEM64: 557 pi->pi_bar[idx].addr &= ~0xffffffffUL; 558 pi->pi_bar[idx].addr |= addr; 559 break; 560 case PCIBAR_MEMHI64: 561 pi->pi_bar[idx].addr &= 0xffffffff; 562 pi->pi_bar[idx].addr |= addr; 563 break; 564 default: 565 assert(0); 566 } 567 568 if (decode) 569 register_bar(pi, idx); 570 } 571 572 int 573 pci_emul_alloc_pbar(struct pci_devinst *pdi, int idx, uint64_t hostbase, 574 enum pcibar_type type, uint64_t size) 575 { 576 int error; 577 uint64_t *baseptr, limit, addr, mask, lobits, bar; 578 579 assert(idx >= 0 && idx <= PCI_BARMAX); 580 581 if ((size & (size - 1)) != 0) 582 size = 1UL << flsl(size); /* round up to a power of 2 */ 583 584 /* Enforce minimum BAR sizes required by the PCI standard */ 585 if (type == PCIBAR_IO) { 586 if (size < 4) 587 size = 4; 588 } else { 589 if (size < 16) 590 size = 16; 591 } 592 593 switch (type) { 594 case PCIBAR_NONE: 595 baseptr = NULL; 596 addr = mask = lobits = 0; 597 break; 598 case PCIBAR_IO: 599 baseptr = &pci_emul_iobase; 600 limit = PCI_EMUL_IOLIMIT; 601 mask = PCIM_BAR_IO_BASE; 602 lobits = PCIM_BAR_IO_SPACE; 603 break; 604 case PCIBAR_MEM64: 605 /* 606 * XXX 607 * Some drivers do not work well if the 64-bit BAR is allocated 608 * above 4GB. Allow for this by allocating small requests under 609 * 4GB unless then allocation size is larger than some arbitrary 610 * number (32MB currently). 611 */ 612 if (size > 32 * 1024 * 1024) { 613 /* 614 * XXX special case for device requiring peer-peer DMA 615 */ 616 if (size == 0x100000000UL) 617 baseptr = &hostbase; 618 else 619 baseptr = &pci_emul_membase64; 620 limit = PCI_EMUL_MEMLIMIT64; 621 mask = PCIM_BAR_MEM_BASE; 622 lobits = PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_64 | 623 PCIM_BAR_MEM_PREFETCH; 624 break; 625 } else { 626 baseptr = &pci_emul_membase32; 627 limit = PCI_EMUL_MEMLIMIT32; 628 mask = PCIM_BAR_MEM_BASE; 629 lobits = PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_64; 630 } 631 break; 632 case PCIBAR_MEM32: 633 baseptr = &pci_emul_membase32; 634 limit = PCI_EMUL_MEMLIMIT32; 635 mask = PCIM_BAR_MEM_BASE; 636 lobits = PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_32; 637 break; 638 default: 639 printf("pci_emul_alloc_base: invalid bar type %d\n", type); 640 assert(0); 641 } 642 643 if (baseptr != NULL) { 644 error = pci_emul_alloc_resource(baseptr, limit, size, &addr); 645 if (error != 0) 646 return (error); 647 } 648 649 pdi->pi_bar[idx].type = type; 650 pdi->pi_bar[idx].addr = addr; 651 pdi->pi_bar[idx].size = size; 652 653 /* Initialize the BAR register in config space */ 654 bar = (addr & mask) | lobits; 655 pci_set_cfgdata32(pdi, PCIR_BAR(idx), bar); 656 657 if (type == PCIBAR_MEM64) { 658 assert(idx + 1 <= PCI_BARMAX); 659 pdi->pi_bar[idx + 1].type = PCIBAR_MEMHI64; 660 pci_set_cfgdata32(pdi, PCIR_BAR(idx + 1), bar >> 32); 661 } 662 663 register_bar(pdi, idx); 664 665 return (0); 666 } 667 668 #define CAP_START_OFFSET 0x40 669 static int 670 pci_emul_add_capability(struct pci_devinst *pi, u_char *capdata, int caplen) 671 { 672 int i, capoff, reallen; 673 uint16_t sts; 674 675 assert(caplen > 0); 676 677 reallen = roundup2(caplen, 4); /* dword aligned */ 678 679 sts = pci_get_cfgdata16(pi, PCIR_STATUS); 680 if ((sts & PCIM_STATUS_CAPPRESENT) == 0) 681 capoff = CAP_START_OFFSET; 682 else 683 capoff = pi->pi_capend + 1; 684 685 /* Check if we have enough space */ 686 if (capoff + reallen > PCI_REGMAX + 1) 687 return (-1); 688 689 /* Set the previous capability pointer */ 690 if ((sts & PCIM_STATUS_CAPPRESENT) == 0) { 691 pci_set_cfgdata8(pi, PCIR_CAP_PTR, capoff); 692 pci_set_cfgdata16(pi, PCIR_STATUS, sts|PCIM_STATUS_CAPPRESENT); 693 } else 694 pci_set_cfgdata8(pi, pi->pi_prevcap + 1, capoff); 695 696 /* Copy the capability */ 697 for (i = 0; i < caplen; i++) 698 pci_set_cfgdata8(pi, capoff + i, capdata[i]); 699 700 /* Set the next capability pointer */ 701 pci_set_cfgdata8(pi, capoff + 1, 0); 702 703 pi->pi_prevcap = capoff; 704 pi->pi_capend = capoff + reallen - 1; 705 return (0); 706 } 707 708 static struct pci_devemu * 709 pci_emul_finddev(char *name) 710 { 711 struct pci_devemu **pdpp, *pdp; 712 713 SET_FOREACH(pdpp, pci_devemu_set) { 714 pdp = *pdpp; 715 if (!strcmp(pdp->pe_emu, name)) { 716 return (pdp); 717 } 718 } 719 720 return (NULL); 721 } 722 723 static int 724 pci_emul_init(struct vmctx *ctx, struct pci_devemu *pde, int bus, int slot, 725 int func, struct funcinfo *fi) 726 { 727 struct pci_devinst *pdi; 728 int err; 729 730 pdi = calloc(1, sizeof(struct pci_devinst)); 731 732 pdi->pi_vmctx = ctx; 733 pdi->pi_bus = bus; 734 pdi->pi_slot = slot; 735 pdi->pi_func = func; 736 pthread_mutex_init(&pdi->pi_lintr.lock, NULL); 737 pdi->pi_lintr.pin = 0; 738 pdi->pi_lintr.state = IDLE; 739 pdi->pi_lintr.pirq_pin = 0; 740 pdi->pi_lintr.ioapic_irq = 0; 741 pdi->pi_d = pde; 742 snprintf(pdi->pi_name, PI_NAMESZ, "%s-pci-%d", pde->pe_emu, slot); 743 744 /* Disable legacy interrupts */ 745 pci_set_cfgdata8(pdi, PCIR_INTLINE, 255); 746 pci_set_cfgdata8(pdi, PCIR_INTPIN, 0); 747 748 pci_set_cfgdata8(pdi, PCIR_COMMAND, 749 PCIM_CMD_PORTEN | PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN); 750 751 err = (*pde->pe_init)(ctx, pdi, fi->fi_param); 752 if (err == 0) 753 fi->fi_devi = pdi; 754 else 755 free(pdi); 756 757 return (err); 758 } 759 760 void 761 pci_populate_msicap(struct msicap *msicap, int msgnum, int nextptr) 762 { 763 int mmc; 764 765 /* Number of msi messages must be a power of 2 between 1 and 32 */ 766 assert((msgnum & (msgnum - 1)) == 0 && msgnum >= 1 && msgnum <= 32); 767 mmc = ffs(msgnum) - 1; 768 769 bzero(msicap, sizeof(struct msicap)); 770 msicap->capid = PCIY_MSI; 771 msicap->nextptr = nextptr; 772 msicap->msgctrl = PCIM_MSICTRL_64BIT | (mmc << 1); 773 } 774 775 int 776 pci_emul_add_msicap(struct pci_devinst *pi, int msgnum) 777 { 778 struct msicap msicap; 779 780 pci_populate_msicap(&msicap, msgnum, 0); 781 782 return (pci_emul_add_capability(pi, (u_char *)&msicap, sizeof(msicap))); 783 } 784 785 static void 786 pci_populate_msixcap(struct msixcap *msixcap, int msgnum, int barnum, 787 uint32_t msix_tab_size) 788 { 789 790 assert(msix_tab_size % 4096 == 0); 791 792 bzero(msixcap, sizeof(struct msixcap)); 793 msixcap->capid = PCIY_MSIX; 794 795 /* 796 * Message Control Register, all fields set to 797 * zero except for the Table Size. 798 * Note: Table size N is encoded as N-1 799 */ 800 msixcap->msgctrl = msgnum - 1; 801 802 /* 803 * MSI-X BAR setup: 804 * - MSI-X table start at offset 0 805 * - PBA table starts at a 4K aligned offset after the MSI-X table 806 */ 807 msixcap->table_info = barnum & PCIM_MSIX_BIR_MASK; 808 msixcap->pba_info = msix_tab_size | (barnum & PCIM_MSIX_BIR_MASK); 809 } 810 811 static void 812 pci_msix_table_init(struct pci_devinst *pi, int table_entries) 813 { 814 int i, table_size; 815 816 assert(table_entries > 0); 817 assert(table_entries <= MAX_MSIX_TABLE_ENTRIES); 818 819 table_size = table_entries * MSIX_TABLE_ENTRY_SIZE; 820 pi->pi_msix.table = calloc(1, table_size); 821 822 /* set mask bit of vector control register */ 823 for (i = 0; i < table_entries; i++) 824 pi->pi_msix.table[i].vector_control |= PCIM_MSIX_VCTRL_MASK; 825 } 826 827 int 828 pci_emul_add_msixcap(struct pci_devinst *pi, int msgnum, int barnum) 829 { 830 uint32_t tab_size; 831 struct msixcap msixcap; 832 833 assert(msgnum >= 1 && msgnum <= MAX_MSIX_TABLE_ENTRIES); 834 assert(barnum >= 0 && barnum <= PCIR_MAX_BAR_0); 835 836 tab_size = msgnum * MSIX_TABLE_ENTRY_SIZE; 837 838 /* Align table size to nearest 4K */ 839 tab_size = roundup2(tab_size, 4096); 840 841 pi->pi_msix.table_bar = barnum; 842 pi->pi_msix.pba_bar = barnum; 843 pi->pi_msix.table_offset = 0; 844 pi->pi_msix.table_count = msgnum; 845 pi->pi_msix.pba_offset = tab_size; 846 pi->pi_msix.pba_size = PBA_SIZE(msgnum); 847 848 pci_msix_table_init(pi, msgnum); 849 850 pci_populate_msixcap(&msixcap, msgnum, barnum, tab_size); 851 852 /* allocate memory for MSI-X Table and PBA */ 853 pci_emul_alloc_bar(pi, barnum, PCIBAR_MEM32, 854 tab_size + pi->pi_msix.pba_size); 855 856 return (pci_emul_add_capability(pi, (u_char *)&msixcap, 857 sizeof(msixcap))); 858 } 859 860 void 861 msixcap_cfgwrite(struct pci_devinst *pi, int capoff, int offset, 862 int bytes, uint32_t val) 863 { 864 uint16_t msgctrl, rwmask; 865 int off; 866 867 off = offset - capoff; 868 /* Message Control Register */ 869 if (off == 2 && bytes == 2) { 870 rwmask = PCIM_MSIXCTRL_MSIX_ENABLE | PCIM_MSIXCTRL_FUNCTION_MASK; 871 msgctrl = pci_get_cfgdata16(pi, offset); 872 msgctrl &= ~rwmask; 873 msgctrl |= val & rwmask; 874 val = msgctrl; 875 876 pi->pi_msix.enabled = val & PCIM_MSIXCTRL_MSIX_ENABLE; 877 pi->pi_msix.function_mask = val & PCIM_MSIXCTRL_FUNCTION_MASK; 878 pci_lintr_update(pi); 879 } 880 881 CFGWRITE(pi, offset, val, bytes); 882 } 883 884 void 885 msicap_cfgwrite(struct pci_devinst *pi, int capoff, int offset, 886 int bytes, uint32_t val) 887 { 888 uint16_t msgctrl, rwmask, msgdata, mme; 889 uint32_t addrlo; 890 891 /* 892 * If guest is writing to the message control register make sure 893 * we do not overwrite read-only fields. 894 */ 895 if ((offset - capoff) == 2 && bytes == 2) { 896 rwmask = PCIM_MSICTRL_MME_MASK | PCIM_MSICTRL_MSI_ENABLE; 897 msgctrl = pci_get_cfgdata16(pi, offset); 898 msgctrl &= ~rwmask; 899 msgctrl |= val & rwmask; 900 val = msgctrl; 901 902 addrlo = pci_get_cfgdata32(pi, capoff + 4); 903 if (msgctrl & PCIM_MSICTRL_64BIT) 904 msgdata = pci_get_cfgdata16(pi, capoff + 12); 905 else 906 msgdata = pci_get_cfgdata16(pi, capoff + 8); 907 908 mme = msgctrl & PCIM_MSICTRL_MME_MASK; 909 pi->pi_msi.enabled = msgctrl & PCIM_MSICTRL_MSI_ENABLE ? 1 : 0; 910 if (pi->pi_msi.enabled) { 911 pi->pi_msi.addr = addrlo; 912 pi->pi_msi.msg_data = msgdata; 913 pi->pi_msi.maxmsgnum = 1 << (mme >> 4); 914 } else { 915 pi->pi_msi.maxmsgnum = 0; 916 } 917 pci_lintr_update(pi); 918 } 919 920 CFGWRITE(pi, offset, val, bytes); 921 } 922 923 void 924 pciecap_cfgwrite(struct pci_devinst *pi, int capoff, int offset, 925 int bytes, uint32_t val) 926 { 927 928 /* XXX don't write to the readonly parts */ 929 CFGWRITE(pi, offset, val, bytes); 930 } 931 932 #define PCIECAP_VERSION 0x2 933 int 934 pci_emul_add_pciecap(struct pci_devinst *pi, int type) 935 { 936 int err; 937 struct pciecap pciecap; 938 939 if (type != PCIEM_TYPE_ROOT_PORT) 940 return (-1); 941 942 bzero(&pciecap, sizeof(pciecap)); 943 944 pciecap.capid = PCIY_EXPRESS; 945 pciecap.pcie_capabilities = PCIECAP_VERSION | PCIEM_TYPE_ROOT_PORT; 946 pciecap.link_capabilities = 0x411; /* gen1, x1 */ 947 pciecap.link_status = 0x11; /* gen1, x1 */ 948 949 err = pci_emul_add_capability(pi, (u_char *)&pciecap, sizeof(pciecap)); 950 return (err); 951 } 952 953 /* 954 * This function assumes that 'coff' is in the capabilities region of the 955 * config space. 956 */ 957 static void 958 pci_emul_capwrite(struct pci_devinst *pi, int offset, int bytes, uint32_t val) 959 { 960 int capid; 961 uint8_t capoff, nextoff; 962 963 /* Do not allow un-aligned writes */ 964 if ((offset & (bytes - 1)) != 0) 965 return; 966 967 /* Find the capability that we want to update */ 968 capoff = CAP_START_OFFSET; 969 while (1) { 970 nextoff = pci_get_cfgdata8(pi, capoff + 1); 971 if (nextoff == 0) 972 break; 973 if (offset >= capoff && offset < nextoff) 974 break; 975 976 capoff = nextoff; 977 } 978 assert(offset >= capoff); 979 980 /* 981 * Capability ID and Next Capability Pointer are readonly. 982 * However, some o/s's do 4-byte writes that include these. 983 * For this case, trim the write back to 2 bytes and adjust 984 * the data. 985 */ 986 if (offset == capoff || offset == capoff + 1) { 987 if (offset == capoff && bytes == 4) { 988 bytes = 2; 989 offset += 2; 990 val >>= 16; 991 } else 992 return; 993 } 994 995 capid = pci_get_cfgdata8(pi, capoff); 996 switch (capid) { 997 case PCIY_MSI: 998 msicap_cfgwrite(pi, capoff, offset, bytes, val); 999 break; 1000 case PCIY_MSIX: 1001 msixcap_cfgwrite(pi, capoff, offset, bytes, val); 1002 break; 1003 case PCIY_EXPRESS: 1004 pciecap_cfgwrite(pi, capoff, offset, bytes, val); 1005 break; 1006 default: 1007 break; 1008 } 1009 } 1010 1011 static int 1012 pci_emul_iscap(struct pci_devinst *pi, int offset) 1013 { 1014 uint16_t sts; 1015 1016 sts = pci_get_cfgdata16(pi, PCIR_STATUS); 1017 if ((sts & PCIM_STATUS_CAPPRESENT) != 0) { 1018 if (offset >= CAP_START_OFFSET && offset <= pi->pi_capend) 1019 return (1); 1020 } 1021 return (0); 1022 } 1023 1024 static int 1025 pci_emul_fallback_handler(struct vmctx *ctx, int vcpu, int dir, uint64_t addr, 1026 int size, uint64_t *val, void *arg1, long arg2) 1027 { 1028 /* 1029 * Ignore writes; return 0xff's for reads. The mem read code 1030 * will take care of truncating to the correct size. 1031 */ 1032 if (dir == MEM_F_READ) { 1033 *val = 0xffffffffffffffff; 1034 } 1035 1036 return (0); 1037 } 1038 1039 static int 1040 pci_emul_ecfg_handler(struct vmctx *ctx, int vcpu, int dir, uint64_t addr, 1041 int bytes, uint64_t *val, void *arg1, long arg2) 1042 { 1043 int bus, slot, func, coff, in; 1044 1045 coff = addr & 0xfff; 1046 func = (addr >> 12) & 0x7; 1047 slot = (addr >> 15) & 0x1f; 1048 bus = (addr >> 20) & 0xff; 1049 in = (dir == MEM_F_READ); 1050 if (in) 1051 *val = ~0UL; 1052 pci_cfgrw(ctx, vcpu, in, bus, slot, func, coff, bytes, (uint32_t *)val); 1053 return (0); 1054 } 1055 1056 uint64_t 1057 pci_ecfg_base(void) 1058 { 1059 1060 return (PCI_EMUL_ECFG_BASE); 1061 } 1062 1063 #define BUSIO_ROUNDUP 32 1064 #define BUSMEM_ROUNDUP (1024 * 1024) 1065 1066 int 1067 init_pci(struct vmctx *ctx) 1068 { 1069 struct mem_range mr; 1070 struct pci_devemu *pde; 1071 struct businfo *bi; 1072 struct slotinfo *si; 1073 struct funcinfo *fi; 1074 size_t lowmem; 1075 int bus, slot, func; 1076 int error; 1077 1078 pci_emul_iobase = PCI_EMUL_IOBASE; 1079 pci_emul_membase32 = vm_get_lowmem_limit(ctx); 1080 pci_emul_membase64 = PCI_EMUL_MEMBASE64; 1081 1082 for (bus = 0; bus < MAXBUSES; bus++) { 1083 if ((bi = pci_businfo[bus]) == NULL) 1084 continue; 1085 /* 1086 * Keep track of the i/o and memory resources allocated to 1087 * this bus. 1088 */ 1089 bi->iobase = pci_emul_iobase; 1090 bi->membase32 = pci_emul_membase32; 1091 bi->membase64 = pci_emul_membase64; 1092 1093 for (slot = 0; slot < MAXSLOTS; slot++) { 1094 si = &bi->slotinfo[slot]; 1095 for (func = 0; func < MAXFUNCS; func++) { 1096 fi = &si->si_funcs[func]; 1097 if (fi->fi_name == NULL) 1098 continue; 1099 pde = pci_emul_finddev(fi->fi_name); 1100 assert(pde != NULL); 1101 error = pci_emul_init(ctx, pde, bus, slot, 1102 func, fi); 1103 if (error) 1104 return (error); 1105 } 1106 } 1107 1108 /* 1109 * Add some slop to the I/O and memory resources decoded by 1110 * this bus to give a guest some flexibility if it wants to 1111 * reprogram the BARs. 1112 */ 1113 pci_emul_iobase += BUSIO_ROUNDUP; 1114 pci_emul_iobase = roundup2(pci_emul_iobase, BUSIO_ROUNDUP); 1115 bi->iolimit = pci_emul_iobase; 1116 1117 pci_emul_membase32 += BUSMEM_ROUNDUP; 1118 pci_emul_membase32 = roundup2(pci_emul_membase32, 1119 BUSMEM_ROUNDUP); 1120 bi->memlimit32 = pci_emul_membase32; 1121 1122 pci_emul_membase64 += BUSMEM_ROUNDUP; 1123 pci_emul_membase64 = roundup2(pci_emul_membase64, 1124 BUSMEM_ROUNDUP); 1125 bi->memlimit64 = pci_emul_membase64; 1126 } 1127 1128 /* 1129 * PCI backends are initialized before routing INTx interrupts 1130 * so that LPC devices are able to reserve ISA IRQs before 1131 * routing PIRQ pins. 1132 */ 1133 for (bus = 0; bus < MAXBUSES; bus++) { 1134 if ((bi = pci_businfo[bus]) == NULL) 1135 continue; 1136 1137 for (slot = 0; slot < MAXSLOTS; slot++) { 1138 si = &bi->slotinfo[slot]; 1139 for (func = 0; func < MAXFUNCS; func++) { 1140 fi = &si->si_funcs[func]; 1141 if (fi->fi_devi == NULL) 1142 continue; 1143 pci_lintr_route(fi->fi_devi); 1144 } 1145 } 1146 } 1147 lpc_pirq_routed(); 1148 1149 /* 1150 * The guest physical memory map looks like the following: 1151 * [0, lowmem) guest system memory 1152 * [lowmem, lowmem_limit) memory hole (may be absent) 1153 * [lowmem_limit, 0xE0000000) PCI hole (32-bit BAR allocation) 1154 * [0xE0000000, 0xF0000000) PCI extended config window 1155 * [0xF0000000, 4GB) LAPIC, IOAPIC, HPET, firmware 1156 * [4GB, 4GB + highmem) 1157 */ 1158 1159 /* 1160 * Accesses to memory addresses that are not allocated to system 1161 * memory or PCI devices return 0xff's. 1162 */ 1163 lowmem = vm_get_lowmem_size(ctx); 1164 bzero(&mr, sizeof(struct mem_range)); 1165 mr.name = "PCI hole"; 1166 mr.flags = MEM_F_RW | MEM_F_IMMUTABLE; 1167 mr.base = lowmem; 1168 mr.size = (4ULL * 1024 * 1024 * 1024) - lowmem; 1169 mr.handler = pci_emul_fallback_handler; 1170 error = register_mem_fallback(&mr); 1171 assert(error == 0); 1172 1173 /* PCI extended config space */ 1174 bzero(&mr, sizeof(struct mem_range)); 1175 mr.name = "PCI ECFG"; 1176 mr.flags = MEM_F_RW | MEM_F_IMMUTABLE; 1177 mr.base = PCI_EMUL_ECFG_BASE; 1178 mr.size = PCI_EMUL_ECFG_SIZE; 1179 mr.handler = pci_emul_ecfg_handler; 1180 error = register_mem(&mr); 1181 assert(error == 0); 1182 1183 return (0); 1184 } 1185 1186 static void 1187 pci_apic_prt_entry(int bus, int slot, int pin, int pirq_pin, int ioapic_irq, 1188 void *arg) 1189 { 1190 1191 dsdt_line(" Package ()"); 1192 dsdt_line(" {"); 1193 dsdt_line(" 0x%X,", slot << 16 | 0xffff); 1194 dsdt_line(" 0x%02X,", pin - 1); 1195 dsdt_line(" Zero,"); 1196 dsdt_line(" 0x%X", ioapic_irq); 1197 dsdt_line(" },"); 1198 } 1199 1200 static void 1201 pci_pirq_prt_entry(int bus, int slot, int pin, int pirq_pin, int ioapic_irq, 1202 void *arg) 1203 { 1204 char *name; 1205 1206 name = lpc_pirq_name(pirq_pin); 1207 if (name == NULL) 1208 return; 1209 dsdt_line(" Package ()"); 1210 dsdt_line(" {"); 1211 dsdt_line(" 0x%X,", slot << 16 | 0xffff); 1212 dsdt_line(" 0x%02X,", pin - 1); 1213 dsdt_line(" %s,", name); 1214 dsdt_line(" 0x00"); 1215 dsdt_line(" },"); 1216 free(name); 1217 } 1218 1219 /* 1220 * A bhyve virtual machine has a flat PCI hierarchy with a root port 1221 * corresponding to each PCI bus. 1222 */ 1223 static void 1224 pci_bus_write_dsdt(int bus) 1225 { 1226 struct businfo *bi; 1227 struct slotinfo *si; 1228 struct pci_devinst *pi; 1229 int count, func, slot; 1230 1231 /* 1232 * If there are no devices on this 'bus' then just return. 1233 */ 1234 if ((bi = pci_businfo[bus]) == NULL) { 1235 /* 1236 * Bus 0 is special because it decodes the I/O ports used 1237 * for PCI config space access even if there are no devices 1238 * on it. 1239 */ 1240 if (bus != 0) 1241 return; 1242 } 1243 1244 dsdt_line(" Device (PC%02X)", bus); 1245 dsdt_line(" {"); 1246 dsdt_line(" Name (_HID, EisaId (\"PNP0A03\"))"); 1247 dsdt_line(" Name (_ADR, Zero)"); 1248 1249 dsdt_line(" Method (_BBN, 0, NotSerialized)"); 1250 dsdt_line(" {"); 1251 dsdt_line(" Return (0x%08X)", bus); 1252 dsdt_line(" }"); 1253 dsdt_line(" Name (_CRS, ResourceTemplate ()"); 1254 dsdt_line(" {"); 1255 dsdt_line(" WordBusNumber (ResourceProducer, MinFixed, " 1256 "MaxFixed, PosDecode,"); 1257 dsdt_line(" 0x0000, // Granularity"); 1258 dsdt_line(" 0x%04X, // Range Minimum", bus); 1259 dsdt_line(" 0x%04X, // Range Maximum", bus); 1260 dsdt_line(" 0x0000, // Translation Offset"); 1261 dsdt_line(" 0x0001, // Length"); 1262 dsdt_line(" ,, )"); 1263 1264 if (bus == 0) { 1265 dsdt_indent(3); 1266 dsdt_fixed_ioport(0xCF8, 8); 1267 dsdt_unindent(3); 1268 1269 dsdt_line(" WordIO (ResourceProducer, MinFixed, MaxFixed, " 1270 "PosDecode, EntireRange,"); 1271 dsdt_line(" 0x0000, // Granularity"); 1272 dsdt_line(" 0x0000, // Range Minimum"); 1273 dsdt_line(" 0x0CF7, // Range Maximum"); 1274 dsdt_line(" 0x0000, // Translation Offset"); 1275 dsdt_line(" 0x0CF8, // Length"); 1276 dsdt_line(" ,, , TypeStatic)"); 1277 1278 dsdt_line(" WordIO (ResourceProducer, MinFixed, MaxFixed, " 1279 "PosDecode, EntireRange,"); 1280 dsdt_line(" 0x0000, // Granularity"); 1281 dsdt_line(" 0x0D00, // Range Minimum"); 1282 dsdt_line(" 0x%04X, // Range Maximum", 1283 PCI_EMUL_IOBASE - 1); 1284 dsdt_line(" 0x0000, // Translation Offset"); 1285 dsdt_line(" 0x%04X, // Length", 1286 PCI_EMUL_IOBASE - 0x0D00); 1287 dsdt_line(" ,, , TypeStatic)"); 1288 1289 if (bi == NULL) { 1290 dsdt_line(" })"); 1291 goto done; 1292 } 1293 } 1294 assert(bi != NULL); 1295 1296 /* i/o window */ 1297 dsdt_line(" WordIO (ResourceProducer, MinFixed, MaxFixed, " 1298 "PosDecode, EntireRange,"); 1299 dsdt_line(" 0x0000, // Granularity"); 1300 dsdt_line(" 0x%04X, // Range Minimum", bi->iobase); 1301 dsdt_line(" 0x%04X, // Range Maximum", 1302 bi->iolimit - 1); 1303 dsdt_line(" 0x0000, // Translation Offset"); 1304 dsdt_line(" 0x%04X, // Length", 1305 bi->iolimit - bi->iobase); 1306 dsdt_line(" ,, , TypeStatic)"); 1307 1308 /* mmio window (32-bit) */ 1309 dsdt_line(" DWordMemory (ResourceProducer, PosDecode, " 1310 "MinFixed, MaxFixed, NonCacheable, ReadWrite,"); 1311 dsdt_line(" 0x00000000, // Granularity"); 1312 dsdt_line(" 0x%08X, // Range Minimum\n", bi->membase32); 1313 dsdt_line(" 0x%08X, // Range Maximum\n", 1314 bi->memlimit32 - 1); 1315 dsdt_line(" 0x00000000, // Translation Offset"); 1316 dsdt_line(" 0x%08X, // Length\n", 1317 bi->memlimit32 - bi->membase32); 1318 dsdt_line(" ,, , AddressRangeMemory, TypeStatic)"); 1319 1320 /* mmio window (64-bit) */ 1321 dsdt_line(" QWordMemory (ResourceProducer, PosDecode, " 1322 "MinFixed, MaxFixed, NonCacheable, ReadWrite,"); 1323 dsdt_line(" 0x0000000000000000, // Granularity"); 1324 dsdt_line(" 0x%016lX, // Range Minimum\n", bi->membase64); 1325 dsdt_line(" 0x%016lX, // Range Maximum\n", 1326 bi->memlimit64 - 1); 1327 dsdt_line(" 0x0000000000000000, // Translation Offset"); 1328 dsdt_line(" 0x%016lX, // Length\n", 1329 bi->memlimit64 - bi->membase64); 1330 dsdt_line(" ,, , AddressRangeMemory, TypeStatic)"); 1331 dsdt_line(" })"); 1332 1333 count = pci_count_lintr(bus); 1334 if (count != 0) { 1335 dsdt_indent(2); 1336 dsdt_line("Name (PPRT, Package ()"); 1337 dsdt_line("{"); 1338 pci_walk_lintr(bus, pci_pirq_prt_entry, NULL); 1339 dsdt_line("})"); 1340 dsdt_line("Name (APRT, Package ()"); 1341 dsdt_line("{"); 1342 pci_walk_lintr(bus, pci_apic_prt_entry, NULL); 1343 dsdt_line("})"); 1344 dsdt_line("Method (_PRT, 0, NotSerialized)"); 1345 dsdt_line("{"); 1346 dsdt_line(" If (PICM)"); 1347 dsdt_line(" {"); 1348 dsdt_line(" Return (APRT)"); 1349 dsdt_line(" }"); 1350 dsdt_line(" Else"); 1351 dsdt_line(" {"); 1352 dsdt_line(" Return (PPRT)"); 1353 dsdt_line(" }"); 1354 dsdt_line("}"); 1355 dsdt_unindent(2); 1356 } 1357 1358 dsdt_indent(2); 1359 for (slot = 0; slot < MAXSLOTS; slot++) { 1360 si = &bi->slotinfo[slot]; 1361 for (func = 0; func < MAXFUNCS; func++) { 1362 pi = si->si_funcs[func].fi_devi; 1363 if (pi != NULL && pi->pi_d->pe_write_dsdt != NULL) 1364 pi->pi_d->pe_write_dsdt(pi); 1365 } 1366 } 1367 dsdt_unindent(2); 1368 done: 1369 dsdt_line(" }"); 1370 } 1371 1372 void 1373 pci_write_dsdt(void) 1374 { 1375 int bus; 1376 1377 dsdt_indent(1); 1378 dsdt_line("Name (PICM, 0x00)"); 1379 dsdt_line("Method (_PIC, 1, NotSerialized)"); 1380 dsdt_line("{"); 1381 dsdt_line(" Store (Arg0, PICM)"); 1382 dsdt_line("}"); 1383 dsdt_line(""); 1384 dsdt_line("Scope (_SB)"); 1385 dsdt_line("{"); 1386 for (bus = 0; bus < MAXBUSES; bus++) 1387 pci_bus_write_dsdt(bus); 1388 dsdt_line("}"); 1389 dsdt_unindent(1); 1390 } 1391 1392 int 1393 pci_bus_configured(int bus) 1394 { 1395 assert(bus >= 0 && bus < MAXBUSES); 1396 return (pci_businfo[bus] != NULL); 1397 } 1398 1399 int 1400 pci_msi_enabled(struct pci_devinst *pi) 1401 { 1402 return (pi->pi_msi.enabled); 1403 } 1404 1405 int 1406 pci_msi_maxmsgnum(struct pci_devinst *pi) 1407 { 1408 if (pi->pi_msi.enabled) 1409 return (pi->pi_msi.maxmsgnum); 1410 else 1411 return (0); 1412 } 1413 1414 int 1415 pci_msix_enabled(struct pci_devinst *pi) 1416 { 1417 1418 return (pi->pi_msix.enabled && !pi->pi_msi.enabled); 1419 } 1420 1421 void 1422 pci_generate_msix(struct pci_devinst *pi, int index) 1423 { 1424 struct msix_table_entry *mte; 1425 1426 if (!pci_msix_enabled(pi)) 1427 return; 1428 1429 if (pi->pi_msix.function_mask) 1430 return; 1431 1432 if (index >= pi->pi_msix.table_count) 1433 return; 1434 1435 mte = &pi->pi_msix.table[index]; 1436 if ((mte->vector_control & PCIM_MSIX_VCTRL_MASK) == 0) { 1437 /* XXX Set PBA bit if interrupt is disabled */ 1438 vm_lapic_msi(pi->pi_vmctx, mte->addr, mte->msg_data); 1439 } 1440 } 1441 1442 void 1443 pci_generate_msi(struct pci_devinst *pi, int index) 1444 { 1445 1446 if (pci_msi_enabled(pi) && index < pci_msi_maxmsgnum(pi)) { 1447 vm_lapic_msi(pi->pi_vmctx, pi->pi_msi.addr, 1448 pi->pi_msi.msg_data + index); 1449 } 1450 } 1451 1452 static bool 1453 pci_lintr_permitted(struct pci_devinst *pi) 1454 { 1455 uint16_t cmd; 1456 1457 cmd = pci_get_cfgdata16(pi, PCIR_COMMAND); 1458 return (!(pi->pi_msi.enabled || pi->pi_msix.enabled || 1459 (cmd & PCIM_CMD_INTxDIS))); 1460 } 1461 1462 void 1463 pci_lintr_request(struct pci_devinst *pi) 1464 { 1465 struct businfo *bi; 1466 struct slotinfo *si; 1467 int bestpin, bestcount, pin; 1468 1469 bi = pci_businfo[pi->pi_bus]; 1470 assert(bi != NULL); 1471 1472 /* 1473 * Just allocate a pin from our slot. The pin will be 1474 * assigned IRQs later when interrupts are routed. 1475 */ 1476 si = &bi->slotinfo[pi->pi_slot]; 1477 bestpin = 0; 1478 bestcount = si->si_intpins[0].ii_count; 1479 for (pin = 1; pin < 4; pin++) { 1480 if (si->si_intpins[pin].ii_count < bestcount) { 1481 bestpin = pin; 1482 bestcount = si->si_intpins[pin].ii_count; 1483 } 1484 } 1485 1486 si->si_intpins[bestpin].ii_count++; 1487 pi->pi_lintr.pin = bestpin + 1; 1488 pci_set_cfgdata8(pi, PCIR_INTPIN, bestpin + 1); 1489 } 1490 1491 static void 1492 pci_lintr_route(struct pci_devinst *pi) 1493 { 1494 struct businfo *bi; 1495 struct intxinfo *ii; 1496 1497 if (pi->pi_lintr.pin == 0) 1498 return; 1499 1500 bi = pci_businfo[pi->pi_bus]; 1501 assert(bi != NULL); 1502 ii = &bi->slotinfo[pi->pi_slot].si_intpins[pi->pi_lintr.pin - 1]; 1503 1504 /* 1505 * Attempt to allocate an I/O APIC pin for this intpin if one 1506 * is not yet assigned. 1507 */ 1508 if (ii->ii_ioapic_irq == 0) 1509 ii->ii_ioapic_irq = ioapic_pci_alloc_irq(pi); 1510 assert(ii->ii_ioapic_irq > 0); 1511 1512 /* 1513 * Attempt to allocate a PIRQ pin for this intpin if one is 1514 * not yet assigned. 1515 */ 1516 if (ii->ii_pirq_pin == 0) 1517 ii->ii_pirq_pin = pirq_alloc_pin(pi); 1518 assert(ii->ii_pirq_pin > 0); 1519 1520 pi->pi_lintr.ioapic_irq = ii->ii_ioapic_irq; 1521 pi->pi_lintr.pirq_pin = ii->ii_pirq_pin; 1522 pci_set_cfgdata8(pi, PCIR_INTLINE, pirq_irq(ii->ii_pirq_pin)); 1523 } 1524 1525 void 1526 pci_lintr_assert(struct pci_devinst *pi) 1527 { 1528 1529 assert(pi->pi_lintr.pin > 0); 1530 1531 pthread_mutex_lock(&pi->pi_lintr.lock); 1532 if (pi->pi_lintr.state == IDLE) { 1533 if (pci_lintr_permitted(pi)) { 1534 pi->pi_lintr.state = ASSERTED; 1535 pci_irq_assert(pi); 1536 } else 1537 pi->pi_lintr.state = PENDING; 1538 } 1539 pthread_mutex_unlock(&pi->pi_lintr.lock); 1540 } 1541 1542 void 1543 pci_lintr_deassert(struct pci_devinst *pi) 1544 { 1545 1546 assert(pi->pi_lintr.pin > 0); 1547 1548 pthread_mutex_lock(&pi->pi_lintr.lock); 1549 if (pi->pi_lintr.state == ASSERTED) { 1550 pi->pi_lintr.state = IDLE; 1551 pci_irq_deassert(pi); 1552 } else if (pi->pi_lintr.state == PENDING) 1553 pi->pi_lintr.state = IDLE; 1554 pthread_mutex_unlock(&pi->pi_lintr.lock); 1555 } 1556 1557 static void 1558 pci_lintr_update(struct pci_devinst *pi) 1559 { 1560 1561 pthread_mutex_lock(&pi->pi_lintr.lock); 1562 if (pi->pi_lintr.state == ASSERTED && !pci_lintr_permitted(pi)) { 1563 pci_irq_deassert(pi); 1564 pi->pi_lintr.state = PENDING; 1565 } else if (pi->pi_lintr.state == PENDING && pci_lintr_permitted(pi)) { 1566 pi->pi_lintr.state = ASSERTED; 1567 pci_irq_assert(pi); 1568 } 1569 pthread_mutex_unlock(&pi->pi_lintr.lock); 1570 } 1571 1572 int 1573 pci_count_lintr(int bus) 1574 { 1575 int count, slot, pin; 1576 struct slotinfo *slotinfo; 1577 1578 count = 0; 1579 if (pci_businfo[bus] != NULL) { 1580 for (slot = 0; slot < MAXSLOTS; slot++) { 1581 slotinfo = &pci_businfo[bus]->slotinfo[slot]; 1582 for (pin = 0; pin < 4; pin++) { 1583 if (slotinfo->si_intpins[pin].ii_count != 0) 1584 count++; 1585 } 1586 } 1587 } 1588 return (count); 1589 } 1590 1591 void 1592 pci_walk_lintr(int bus, pci_lintr_cb cb, void *arg) 1593 { 1594 struct businfo *bi; 1595 struct slotinfo *si; 1596 struct intxinfo *ii; 1597 int slot, pin; 1598 1599 if ((bi = pci_businfo[bus]) == NULL) 1600 return; 1601 1602 for (slot = 0; slot < MAXSLOTS; slot++) { 1603 si = &bi->slotinfo[slot]; 1604 for (pin = 0; pin < 4; pin++) { 1605 ii = &si->si_intpins[pin]; 1606 if (ii->ii_count != 0) 1607 cb(bus, slot, pin + 1, ii->ii_pirq_pin, 1608 ii->ii_ioapic_irq, arg); 1609 } 1610 } 1611 } 1612 1613 /* 1614 * Return 1 if the emulated device in 'slot' is a multi-function device. 1615 * Return 0 otherwise. 1616 */ 1617 static int 1618 pci_emul_is_mfdev(int bus, int slot) 1619 { 1620 struct businfo *bi; 1621 struct slotinfo *si; 1622 int f, numfuncs; 1623 1624 numfuncs = 0; 1625 if ((bi = pci_businfo[bus]) != NULL) { 1626 si = &bi->slotinfo[slot]; 1627 for (f = 0; f < MAXFUNCS; f++) { 1628 if (si->si_funcs[f].fi_devi != NULL) { 1629 numfuncs++; 1630 } 1631 } 1632 } 1633 return (numfuncs > 1); 1634 } 1635 1636 /* 1637 * Ensure that the PCIM_MFDEV bit is properly set (or unset) depending on 1638 * whether or not is a multi-function being emulated in the pci 'slot'. 1639 */ 1640 static void 1641 pci_emul_hdrtype_fixup(int bus, int slot, int off, int bytes, uint32_t *rv) 1642 { 1643 int mfdev; 1644 1645 if (off <= PCIR_HDRTYPE && off + bytes > PCIR_HDRTYPE) { 1646 mfdev = pci_emul_is_mfdev(bus, slot); 1647 switch (bytes) { 1648 case 1: 1649 case 2: 1650 *rv &= ~PCIM_MFDEV; 1651 if (mfdev) { 1652 *rv |= PCIM_MFDEV; 1653 } 1654 break; 1655 case 4: 1656 *rv &= ~(PCIM_MFDEV << 16); 1657 if (mfdev) { 1658 *rv |= (PCIM_MFDEV << 16); 1659 } 1660 break; 1661 } 1662 } 1663 } 1664 1665 static void 1666 pci_emul_cmdsts_write(struct pci_devinst *pi, int coff, uint32_t new, int bytes) 1667 { 1668 int i, rshift; 1669 uint32_t cmd, cmd2, changed, old, readonly; 1670 1671 cmd = pci_get_cfgdata16(pi, PCIR_COMMAND); /* stash old value */ 1672 1673 /* 1674 * From PCI Local Bus Specification 3.0 sections 6.2.2 and 6.2.3. 1675 * 1676 * XXX Bits 8, 11, 12, 13, 14 and 15 in the status register are 1677 * 'write 1 to clear'. However these bits are not set to '1' by 1678 * any device emulation so it is simpler to treat them as readonly. 1679 */ 1680 rshift = (coff & 0x3) * 8; 1681 readonly = 0xFFFFF880 >> rshift; 1682 1683 old = CFGREAD(pi, coff, bytes); 1684 new &= ~readonly; 1685 new |= (old & readonly); 1686 CFGWRITE(pi, coff, new, bytes); /* update config */ 1687 1688 cmd2 = pci_get_cfgdata16(pi, PCIR_COMMAND); /* get updated value */ 1689 changed = cmd ^ cmd2; 1690 1691 /* 1692 * If the MMIO or I/O address space decoding has changed then 1693 * register/unregister all BARs that decode that address space. 1694 */ 1695 for (i = 0; i <= PCI_BARMAX; i++) { 1696 switch (pi->pi_bar[i].type) { 1697 case PCIBAR_NONE: 1698 case PCIBAR_MEMHI64: 1699 break; 1700 case PCIBAR_IO: 1701 /* I/O address space decoding changed? */ 1702 if (changed & PCIM_CMD_PORTEN) { 1703 if (porten(pi)) 1704 register_bar(pi, i); 1705 else 1706 unregister_bar(pi, i); 1707 } 1708 break; 1709 case PCIBAR_MEM32: 1710 case PCIBAR_MEM64: 1711 /* MMIO address space decoding changed? */ 1712 if (changed & PCIM_CMD_MEMEN) { 1713 if (memen(pi)) 1714 register_bar(pi, i); 1715 else 1716 unregister_bar(pi, i); 1717 } 1718 break; 1719 default: 1720 assert(0); 1721 } 1722 } 1723 1724 /* 1725 * If INTx has been unmasked and is pending, assert the 1726 * interrupt. 1727 */ 1728 pci_lintr_update(pi); 1729 } 1730 1731 static void 1732 pci_cfgrw(struct vmctx *ctx, int vcpu, int in, int bus, int slot, int func, 1733 int coff, int bytes, uint32_t *eax) 1734 { 1735 struct businfo *bi; 1736 struct slotinfo *si; 1737 struct pci_devinst *pi; 1738 struct pci_devemu *pe; 1739 int idx, needcfg; 1740 uint64_t addr, bar, mask; 1741 1742 if ((bi = pci_businfo[bus]) != NULL) { 1743 si = &bi->slotinfo[slot]; 1744 pi = si->si_funcs[func].fi_devi; 1745 } else 1746 pi = NULL; 1747 1748 /* 1749 * Just return if there is no device at this slot:func or if the 1750 * the guest is doing an un-aligned access. 1751 */ 1752 if (pi == NULL || (bytes != 1 && bytes != 2 && bytes != 4) || 1753 (coff & (bytes - 1)) != 0) { 1754 if (in) 1755 *eax = 0xffffffff; 1756 return; 1757 } 1758 1759 /* 1760 * Ignore all writes beyond the standard config space and return all 1761 * ones on reads. 1762 */ 1763 if (coff >= PCI_REGMAX + 1) { 1764 if (in) { 1765 *eax = 0xffffffff; 1766 /* 1767 * Extended capabilities begin at offset 256 in config 1768 * space. Absence of extended capabilities is signaled 1769 * with all 0s in the extended capability header at 1770 * offset 256. 1771 */ 1772 if (coff <= PCI_REGMAX + 4) 1773 *eax = 0x00000000; 1774 } 1775 return; 1776 } 1777 1778 pe = pi->pi_d; 1779 1780 /* 1781 * Config read 1782 */ 1783 if (in) { 1784 /* Let the device emulation override the default handler */ 1785 if (pe->pe_cfgread != NULL) { 1786 needcfg = pe->pe_cfgread(ctx, vcpu, pi, coff, bytes, 1787 eax); 1788 } else { 1789 needcfg = 1; 1790 } 1791 1792 if (needcfg) 1793 *eax = CFGREAD(pi, coff, bytes); 1794 1795 pci_emul_hdrtype_fixup(bus, slot, coff, bytes, eax); 1796 } else { 1797 /* Let the device emulation override the default handler */ 1798 if (pe->pe_cfgwrite != NULL && 1799 (*pe->pe_cfgwrite)(ctx, vcpu, pi, coff, bytes, *eax) == 0) 1800 return; 1801 1802 /* 1803 * Special handling for write to BAR registers 1804 */ 1805 if (coff >= PCIR_BAR(0) && coff < PCIR_BAR(PCI_BARMAX + 1)) { 1806 /* 1807 * Ignore writes to BAR registers that are not 1808 * 4-byte aligned. 1809 */ 1810 if (bytes != 4 || (coff & 0x3) != 0) 1811 return; 1812 idx = (coff - PCIR_BAR(0)) / 4; 1813 mask = ~(pi->pi_bar[idx].size - 1); 1814 switch (pi->pi_bar[idx].type) { 1815 case PCIBAR_NONE: 1816 pi->pi_bar[idx].addr = bar = 0; 1817 break; 1818 case PCIBAR_IO: 1819 addr = *eax & mask; 1820 addr &= 0xffff; 1821 bar = addr | PCIM_BAR_IO_SPACE; 1822 /* 1823 * Register the new BAR value for interception 1824 */ 1825 if (addr != pi->pi_bar[idx].addr) { 1826 update_bar_address(pi, addr, idx, 1827 PCIBAR_IO); 1828 } 1829 break; 1830 case PCIBAR_MEM32: 1831 addr = bar = *eax & mask; 1832 bar |= PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_32; 1833 if (addr != pi->pi_bar[idx].addr) { 1834 update_bar_address(pi, addr, idx, 1835 PCIBAR_MEM32); 1836 } 1837 break; 1838 case PCIBAR_MEM64: 1839 addr = bar = *eax & mask; 1840 bar |= PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_64 | 1841 PCIM_BAR_MEM_PREFETCH; 1842 if (addr != (uint32_t)pi->pi_bar[idx].addr) { 1843 update_bar_address(pi, addr, idx, 1844 PCIBAR_MEM64); 1845 } 1846 break; 1847 case PCIBAR_MEMHI64: 1848 mask = ~(pi->pi_bar[idx - 1].size - 1); 1849 addr = ((uint64_t)*eax << 32) & mask; 1850 bar = addr >> 32; 1851 if (bar != pi->pi_bar[idx - 1].addr >> 32) { 1852 update_bar_address(pi, addr, idx - 1, 1853 PCIBAR_MEMHI64); 1854 } 1855 break; 1856 default: 1857 assert(0); 1858 } 1859 pci_set_cfgdata32(pi, coff, bar); 1860 1861 } else if (pci_emul_iscap(pi, coff)) { 1862 pci_emul_capwrite(pi, coff, bytes, *eax); 1863 } else if (coff >= PCIR_COMMAND && coff < PCIR_REVID) { 1864 pci_emul_cmdsts_write(pi, coff, *eax, bytes); 1865 } else { 1866 CFGWRITE(pi, coff, *eax, bytes); 1867 } 1868 } 1869 } 1870 1871 static int cfgenable, cfgbus, cfgslot, cfgfunc, cfgoff; 1872 1873 static int 1874 pci_emul_cfgaddr(struct vmctx *ctx, int vcpu, int in, int port, int bytes, 1875 uint32_t *eax, void *arg) 1876 { 1877 uint32_t x; 1878 1879 if (bytes != 4) { 1880 if (in) 1881 *eax = (bytes == 2) ? 0xffff : 0xff; 1882 return (0); 1883 } 1884 1885 if (in) { 1886 x = (cfgbus << 16) | (cfgslot << 11) | (cfgfunc << 8) | cfgoff; 1887 if (cfgenable) 1888 x |= CONF1_ENABLE; 1889 *eax = x; 1890 } else { 1891 x = *eax; 1892 cfgenable = (x & CONF1_ENABLE) == CONF1_ENABLE; 1893 cfgoff = x & PCI_REGMAX; 1894 cfgfunc = (x >> 8) & PCI_FUNCMAX; 1895 cfgslot = (x >> 11) & PCI_SLOTMAX; 1896 cfgbus = (x >> 16) & PCI_BUSMAX; 1897 } 1898 1899 return (0); 1900 } 1901 INOUT_PORT(pci_cfgaddr, CONF1_ADDR_PORT, IOPORT_F_INOUT, pci_emul_cfgaddr); 1902 1903 static int 1904 pci_emul_cfgdata(struct vmctx *ctx, int vcpu, int in, int port, int bytes, 1905 uint32_t *eax, void *arg) 1906 { 1907 int coff; 1908 1909 assert(bytes == 1 || bytes == 2 || bytes == 4); 1910 1911 coff = cfgoff + (port - CONF1_DATA_PORT); 1912 if (cfgenable) { 1913 pci_cfgrw(ctx, vcpu, in, cfgbus, cfgslot, cfgfunc, coff, bytes, 1914 eax); 1915 } else { 1916 /* Ignore accesses to cfgdata if not enabled by cfgaddr */ 1917 if (in) 1918 *eax = 0xffffffff; 1919 } 1920 return (0); 1921 } 1922 1923 INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+0, IOPORT_F_INOUT, pci_emul_cfgdata); 1924 INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+1, IOPORT_F_INOUT, pci_emul_cfgdata); 1925 INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+2, IOPORT_F_INOUT, pci_emul_cfgdata); 1926 INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+3, IOPORT_F_INOUT, pci_emul_cfgdata); 1927 1928 #define PCI_EMUL_TEST 1929 #ifdef PCI_EMUL_TEST 1930 /* 1931 * Define a dummy test device 1932 */ 1933 #define DIOSZ 8 1934 #define DMEMSZ 4096 1935 struct pci_emul_dsoftc { 1936 uint8_t ioregs[DIOSZ]; 1937 uint8_t memregs[2][DMEMSZ]; 1938 }; 1939 1940 #define PCI_EMUL_MSI_MSGS 4 1941 #define PCI_EMUL_MSIX_MSGS 16 1942 1943 static int 1944 pci_emul_dinit(struct vmctx *ctx, struct pci_devinst *pi, char *opts) 1945 { 1946 int error; 1947 struct pci_emul_dsoftc *sc; 1948 1949 sc = calloc(1, sizeof(struct pci_emul_dsoftc)); 1950 1951 pi->pi_arg = sc; 1952 1953 pci_set_cfgdata16(pi, PCIR_DEVICE, 0x0001); 1954 pci_set_cfgdata16(pi, PCIR_VENDOR, 0x10DD); 1955 pci_set_cfgdata8(pi, PCIR_CLASS, 0x02); 1956 1957 error = pci_emul_add_msicap(pi, PCI_EMUL_MSI_MSGS); 1958 assert(error == 0); 1959 1960 error = pci_emul_alloc_bar(pi, 0, PCIBAR_IO, DIOSZ); 1961 assert(error == 0); 1962 1963 error = pci_emul_alloc_bar(pi, 1, PCIBAR_MEM32, DMEMSZ); 1964 assert(error == 0); 1965 1966 error = pci_emul_alloc_bar(pi, 2, PCIBAR_MEM32, DMEMSZ); 1967 assert(error == 0); 1968 1969 return (0); 1970 } 1971 1972 static void 1973 pci_emul_diow(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, int baridx, 1974 uint64_t offset, int size, uint64_t value) 1975 { 1976 int i; 1977 struct pci_emul_dsoftc *sc = pi->pi_arg; 1978 1979 if (baridx == 0) { 1980 if (offset + size > DIOSZ) { 1981 printf("diow: iow too large, offset %ld size %d\n", 1982 offset, size); 1983 return; 1984 } 1985 1986 if (size == 1) { 1987 sc->ioregs[offset] = value & 0xff; 1988 } else if (size == 2) { 1989 *(uint16_t *)&sc->ioregs[offset] = value & 0xffff; 1990 } else if (size == 4) { 1991 *(uint32_t *)&sc->ioregs[offset] = value; 1992 } else { 1993 printf("diow: iow unknown size %d\n", size); 1994 } 1995 1996 /* 1997 * Special magic value to generate an interrupt 1998 */ 1999 if (offset == 4 && size == 4 && pci_msi_enabled(pi)) 2000 pci_generate_msi(pi, value % pci_msi_maxmsgnum(pi)); 2001 2002 if (value == 0xabcdef) { 2003 for (i = 0; i < pci_msi_maxmsgnum(pi); i++) 2004 pci_generate_msi(pi, i); 2005 } 2006 } 2007 2008 if (baridx == 1 || baridx == 2) { 2009 if (offset + size > DMEMSZ) { 2010 printf("diow: memw too large, offset %ld size %d\n", 2011 offset, size); 2012 return; 2013 } 2014 2015 i = baridx - 1; /* 'memregs' index */ 2016 2017 if (size == 1) { 2018 sc->memregs[i][offset] = value; 2019 } else if (size == 2) { 2020 *(uint16_t *)&sc->memregs[i][offset] = value; 2021 } else if (size == 4) { 2022 *(uint32_t *)&sc->memregs[i][offset] = value; 2023 } else if (size == 8) { 2024 *(uint64_t *)&sc->memregs[i][offset] = value; 2025 } else { 2026 printf("diow: memw unknown size %d\n", size); 2027 } 2028 2029 /* 2030 * magic interrupt ?? 2031 */ 2032 } 2033 2034 if (baridx > 2 || baridx < 0) { 2035 printf("diow: unknown bar idx %d\n", baridx); 2036 } 2037 } 2038 2039 static uint64_t 2040 pci_emul_dior(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, int baridx, 2041 uint64_t offset, int size) 2042 { 2043 struct pci_emul_dsoftc *sc = pi->pi_arg; 2044 uint32_t value; 2045 int i; 2046 2047 if (baridx == 0) { 2048 if (offset + size > DIOSZ) { 2049 printf("dior: ior too large, offset %ld size %d\n", 2050 offset, size); 2051 return (0); 2052 } 2053 2054 value = 0; 2055 if (size == 1) { 2056 value = sc->ioregs[offset]; 2057 } else if (size == 2) { 2058 value = *(uint16_t *) &sc->ioregs[offset]; 2059 } else if (size == 4) { 2060 value = *(uint32_t *) &sc->ioregs[offset]; 2061 } else { 2062 printf("dior: ior unknown size %d\n", size); 2063 } 2064 } 2065 2066 if (baridx == 1 || baridx == 2) { 2067 if (offset + size > DMEMSZ) { 2068 printf("dior: memr too large, offset %ld size %d\n", 2069 offset, size); 2070 return (0); 2071 } 2072 2073 i = baridx - 1; /* 'memregs' index */ 2074 2075 if (size == 1) { 2076 value = sc->memregs[i][offset]; 2077 } else if (size == 2) { 2078 value = *(uint16_t *) &sc->memregs[i][offset]; 2079 } else if (size == 4) { 2080 value = *(uint32_t *) &sc->memregs[i][offset]; 2081 } else if (size == 8) { 2082 value = *(uint64_t *) &sc->memregs[i][offset]; 2083 } else { 2084 printf("dior: ior unknown size %d\n", size); 2085 } 2086 } 2087 2088 2089 if (baridx > 2 || baridx < 0) { 2090 printf("dior: unknown bar idx %d\n", baridx); 2091 return (0); 2092 } 2093 2094 return (value); 2095 } 2096 2097 struct pci_devemu pci_dummy = { 2098 .pe_emu = "dummy", 2099 .pe_init = pci_emul_dinit, 2100 .pe_barwrite = pci_emul_diow, 2101 .pe_barread = pci_emul_dior 2102 }; 2103 PCI_EMUL_SET(pci_dummy); 2104 2105 #endif /* PCI_EMUL_TEST */ 2106