1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2011 NetApp, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/param.h> 30 #include <sys/linker_set.h> 31 #include <sys/mman.h> 32 33 #include <ctype.h> 34 #include <err.h> 35 #include <errno.h> 36 #include <pthread.h> 37 #include <stdio.h> 38 #include <stdlib.h> 39 #include <string.h> 40 #include <strings.h> 41 #include <assert.h> 42 #include <stdbool.h> 43 #include <sysexits.h> 44 45 #include <machine/vmm.h> 46 #include <machine/vmm_snapshot.h> 47 #include <vmmapi.h> 48 49 #include "acpi.h" 50 #include "bhyverun.h" 51 #include "config.h" 52 #include "debug.h" 53 #ifdef __amd64__ 54 #include "amd64/inout.h" 55 #include "amd64/ioapic.h" 56 #endif 57 #include "mem.h" 58 #include "pci_emul.h" 59 #ifdef __amd64__ 60 #include "amd64/pci_irq.h" 61 #include "amd64/pci_lpc.h" 62 #include "pci_passthru.h" 63 #endif 64 #include "qemu_fwcfg.h" 65 66 #define CONF1_ADDR_PORT 0x0cf8 67 #define CONF1_DATA_PORT 0x0cfc 68 69 #define CONF1_ENABLE 0x80000000ul 70 71 #define MAXBUSES (PCI_BUSMAX + 1) 72 #define MAXSLOTS (PCI_SLOTMAX + 1) 73 #define MAXFUNCS (PCI_FUNCMAX + 1) 74 75 #define GB (1024 * 1024 * 1024UL) 76 77 struct funcinfo { 78 nvlist_t *fi_config; 79 struct pci_devemu *fi_pde; 80 struct pci_devinst *fi_devi; 81 }; 82 83 struct intxinfo { 84 int ii_count; 85 int ii_pirq_pin; 86 int ii_ioapic_irq; 87 }; 88 89 struct slotinfo { 90 struct intxinfo si_intpins[4]; 91 struct funcinfo si_funcs[MAXFUNCS]; 92 }; 93 94 struct businfo { 95 uint16_t iobase, iolimit; /* I/O window */ 96 uint32_t membase32, memlimit32; /* mmio window below 4GB */ 97 uint64_t membase64, memlimit64; /* mmio window above 4GB */ 98 struct slotinfo slotinfo[MAXSLOTS]; 99 }; 100 101 static struct businfo *pci_businfo[MAXBUSES]; 102 103 SET_DECLARE(pci_devemu_set, struct pci_devemu); 104 105 static uint64_t pci_emul_iobase; 106 static uint8_t *pci_emul_rombase; 107 static uint64_t pci_emul_romoffset; 108 static uint8_t *pci_emul_romlim; 109 static uint64_t pci_emul_membase32; 110 static uint64_t pci_emul_membase64; 111 static uint64_t pci_emul_memlim64; 112 113 struct pci_bar_allocation { 114 TAILQ_ENTRY(pci_bar_allocation) chain; 115 struct pci_devinst *pdi; 116 int idx; 117 enum pcibar_type type; 118 uint64_t size; 119 }; 120 121 static TAILQ_HEAD(pci_bar_list, pci_bar_allocation) pci_bars = 122 TAILQ_HEAD_INITIALIZER(pci_bars); 123 124 struct boot_device { 125 TAILQ_ENTRY(boot_device) boot_device_chain; 126 struct pci_devinst *pdi; 127 int bootindex; 128 }; 129 static TAILQ_HEAD(boot_list, boot_device) boot_devices = TAILQ_HEAD_INITIALIZER( 130 boot_devices); 131 132 #if defined(__amd64__) 133 #define PCI_EMUL_IOBASE 0x2000 134 #define PCI_EMUL_IOLIMIT 0x10000 135 #define PCI_EMUL_IOMASK 0xffff 136 /* 137 * OVMF always uses 0xc0000000 as base address for 32 bit PCI MMIO. Don't 138 * change this address without changing it in OVMF. 139 */ 140 #define PCI_EMUL_MEMBASE32 0xc0000000 141 #elif defined(__aarch64__) 142 #define PCI_EMUL_IOBASE 0x00df00000UL 143 #define PCI_EMUL_IOLIMIT 0x00e000000UL 144 #define PCI_EMUL_MEMBASE32 0x0a0000000UL 145 #else 146 #error Unsupported platform 147 #endif 148 149 #define PCI_EMUL_ROMSIZE 0x10000000 150 151 #define PCI_EMUL_ECFG_BASE 0xE0000000 /* 3.5GB */ 152 #define PCI_EMUL_ECFG_SIZE (MAXBUSES * 1024 * 1024) /* 1MB per bus */ 153 #ifdef __amd64__ 154 SYSRES_MEM(PCI_EMUL_ECFG_BASE, PCI_EMUL_ECFG_SIZE); 155 #endif 156 157 #define PCI_EMUL_MEMLIMIT32 PCI_EMUL_ECFG_BASE 158 #define PCI_EMUL_MEMSIZE64 (32*GB) 159 160 #ifdef __amd64__ 161 static void pci_lintr_route(struct pci_devinst *pi); 162 static void pci_lintr_update(struct pci_devinst *pi); 163 #endif 164 165 static struct pci_devemu *pci_emul_finddev(const char *name); 166 static void pci_cfgrw(int in, int bus, int slot, int func, int coff, 167 int bytes, uint32_t *val); 168 169 static __inline void 170 CFGWRITE(struct pci_devinst *pi, int coff, uint32_t val, int bytes) 171 { 172 173 if (bytes == 1) 174 pci_set_cfgdata8(pi, coff, val); 175 else if (bytes == 2) 176 pci_set_cfgdata16(pi, coff, val); 177 else 178 pci_set_cfgdata32(pi, coff, val); 179 } 180 181 static __inline uint32_t 182 CFGREAD(struct pci_devinst *pi, int coff, int bytes) 183 { 184 185 if (bytes == 1) 186 return (pci_get_cfgdata8(pi, coff)); 187 else if (bytes == 2) 188 return (pci_get_cfgdata16(pi, coff)); 189 else 190 return (pci_get_cfgdata32(pi, coff)); 191 } 192 193 static int 194 is_pcir_bar(int coff) 195 { 196 return (coff >= PCIR_BAR(0) && coff < PCIR_BAR(PCI_BARMAX + 1)); 197 } 198 199 static int 200 is_pcir_bios(int coff) 201 { 202 return (coff >= PCIR_BIOS && coff < PCIR_BIOS + 4); 203 } 204 205 /* 206 * I/O access 207 */ 208 209 /* 210 * Slot options are in the form: 211 * 212 * <bus>:<slot>:<func>,<emul>[,<config>] 213 * <slot>[:<func>],<emul>[,<config>] 214 * 215 * slot is 0..31 216 * func is 0..7 217 * emul is a string describing the type of PCI device e.g. virtio-net 218 * config is an optional string, depending on the device, that can be 219 * used for configuration. 220 * Examples are: 221 * 1,virtio-net,tap0 222 * 3:0,dummy 223 */ 224 static void 225 pci_parse_slot_usage(char *aopt) 226 { 227 228 EPRINTLN("Invalid PCI slot info field \"%s\"", aopt); 229 } 230 231 /* 232 * Helper function to parse a list of comma-separated options where 233 * each option is formatted as "name[=value]". If no value is 234 * provided, the option is treated as a boolean and is given a value 235 * of true. 236 */ 237 int 238 pci_parse_legacy_config(nvlist_t *nvl, const char *opt) 239 { 240 char *config, *name, *tofree, *value; 241 242 if (opt == NULL) 243 return (0); 244 245 config = tofree = strdup(opt); 246 while ((name = strsep(&config, ",")) != NULL) { 247 value = strchr(name, '='); 248 if (value != NULL) { 249 *value = '\0'; 250 value++; 251 set_config_value_node(nvl, name, value); 252 } else 253 set_config_bool_node(nvl, name, true); 254 } 255 free(tofree); 256 return (0); 257 } 258 259 /* 260 * PCI device configuration is stored in MIBs that encode the device's 261 * location: 262 * 263 * pci.<bus>.<slot>.<func> 264 * 265 * Where "bus", "slot", and "func" are all decimal values without 266 * leading zeroes. Each valid device must have a "device" node which 267 * identifies the driver model of the device. 268 * 269 * Device backends can provide a parser for the "config" string. If 270 * a custom parser is not provided, pci_parse_legacy_config() is used 271 * to parse the string. 272 */ 273 int 274 pci_parse_slot(char *opt) 275 { 276 char node_name[sizeof("pci.XXX.XX.X")]; 277 struct pci_devemu *pde; 278 char *emul, *config, *str, *cp; 279 int error, bnum, snum, fnum; 280 nvlist_t *nvl; 281 282 error = -1; 283 str = strdup(opt); 284 285 emul = config = NULL; 286 if ((cp = strchr(str, ',')) != NULL) { 287 *cp = '\0'; 288 emul = cp + 1; 289 if ((cp = strchr(emul, ',')) != NULL) { 290 *cp = '\0'; 291 config = cp + 1; 292 } 293 } else { 294 pci_parse_slot_usage(opt); 295 goto done; 296 } 297 298 /* <bus>:<slot>:<func> */ 299 if (sscanf(str, "%d:%d:%d", &bnum, &snum, &fnum) != 3) { 300 bnum = 0; 301 /* <slot>:<func> */ 302 if (sscanf(str, "%d:%d", &snum, &fnum) != 2) { 303 fnum = 0; 304 /* <slot> */ 305 if (sscanf(str, "%d", &snum) != 1) { 306 snum = -1; 307 } 308 } 309 } 310 311 if (bnum < 0 || bnum >= MAXBUSES || snum < 0 || snum >= MAXSLOTS || 312 fnum < 0 || fnum >= MAXFUNCS) { 313 pci_parse_slot_usage(opt); 314 goto done; 315 } 316 317 pde = pci_emul_finddev(emul); 318 if (pde == NULL) { 319 EPRINTLN("pci slot %d:%d:%d: unknown device \"%s\"", bnum, snum, 320 fnum, emul); 321 goto done; 322 } 323 324 snprintf(node_name, sizeof(node_name), "pci.%d.%d.%d", bnum, snum, 325 fnum); 326 nvl = find_config_node(node_name); 327 if (nvl != NULL) { 328 EPRINTLN("pci slot %d:%d:%d already occupied!", bnum, snum, 329 fnum); 330 goto done; 331 } 332 nvl = create_config_node(node_name); 333 if (pde->pe_alias != NULL) 334 set_config_value_node(nvl, "device", pde->pe_alias); 335 else 336 set_config_value_node(nvl, "device", pde->pe_emu); 337 338 if (pde->pe_legacy_config != NULL) 339 error = pde->pe_legacy_config(nvl, config); 340 else 341 error = pci_parse_legacy_config(nvl, config); 342 done: 343 free(str); 344 return (error); 345 } 346 347 void 348 pci_print_supported_devices(void) 349 { 350 struct pci_devemu **pdpp, *pdp; 351 352 SET_FOREACH(pdpp, pci_devemu_set) { 353 pdp = *pdpp; 354 printf("%s\n", pdp->pe_emu); 355 } 356 } 357 358 uint32_t 359 pci_config_read_reg(const struct pcisel *const host_sel, nvlist_t *nvl, 360 const uint32_t reg, const uint8_t size, const uint32_t def) 361 { 362 const char *config; 363 const nvlist_t *pci_regs; 364 365 assert(size == 1 || size == 2 || size == 4); 366 367 pci_regs = find_relative_config_node(nvl, "pcireg"); 368 if (pci_regs == NULL) { 369 return def; 370 } 371 372 switch (reg) { 373 case PCIR_DEVICE: 374 config = get_config_value_node(pci_regs, "device"); 375 break; 376 case PCIR_VENDOR: 377 config = get_config_value_node(pci_regs, "vendor"); 378 break; 379 case PCIR_REVID: 380 config = get_config_value_node(pci_regs, "revid"); 381 break; 382 case PCIR_SUBVEND_0: 383 config = get_config_value_node(pci_regs, "subvendor"); 384 break; 385 case PCIR_SUBDEV_0: 386 config = get_config_value_node(pci_regs, "subdevice"); 387 break; 388 default: 389 return (-1); 390 } 391 392 if (config == NULL) { 393 return def; 394 } else if (host_sel != NULL && strcmp(config, "host") == 0) { 395 #ifdef __amd64__ 396 return pci_host_read_config(host_sel, reg, size); 397 #else 398 errx(1, "cannot fetch host PCI configuration"); 399 #endif 400 } else { 401 return strtol(config, NULL, 16); 402 } 403 } 404 405 static int 406 pci_valid_pba_offset(struct pci_devinst *pi, uint64_t offset) 407 { 408 409 if (offset < pi->pi_msix.pba_offset) 410 return (0); 411 412 if (offset >= pi->pi_msix.pba_offset + pi->pi_msix.pba_size) { 413 return (0); 414 } 415 416 return (1); 417 } 418 419 int 420 pci_emul_msix_twrite(struct pci_devinst *pi, uint64_t offset, int size, 421 uint64_t value) 422 { 423 int msix_entry_offset; 424 int tab_index; 425 char *dest; 426 427 /* support only 4 or 8 byte writes */ 428 if (size != 4 && size != 8) 429 return (-1); 430 431 /* 432 * Return if table index is beyond what device supports 433 */ 434 tab_index = offset / MSIX_TABLE_ENTRY_SIZE; 435 if (tab_index >= pi->pi_msix.table_count) 436 return (-1); 437 438 msix_entry_offset = offset % MSIX_TABLE_ENTRY_SIZE; 439 440 /* support only aligned writes */ 441 if ((msix_entry_offset % size) != 0) 442 return (-1); 443 444 dest = (char *)(pi->pi_msix.table + tab_index); 445 dest += msix_entry_offset; 446 447 if (size == 4) 448 *((uint32_t *)dest) = value; 449 else 450 *((uint64_t *)dest) = value; 451 452 return (0); 453 } 454 455 uint64_t 456 pci_emul_msix_tread(struct pci_devinst *pi, uint64_t offset, int size) 457 { 458 char *dest; 459 int msix_entry_offset; 460 int tab_index; 461 uint64_t retval = ~0; 462 463 /* 464 * The PCI standard only allows 4 and 8 byte accesses to the MSI-X 465 * table but we also allow 1 byte access to accommodate reads from 466 * ddb. 467 */ 468 if (size != 1 && size != 4 && size != 8) 469 return (retval); 470 471 msix_entry_offset = offset % MSIX_TABLE_ENTRY_SIZE; 472 473 /* support only aligned reads */ 474 if ((msix_entry_offset % size) != 0) { 475 return (retval); 476 } 477 478 tab_index = offset / MSIX_TABLE_ENTRY_SIZE; 479 480 if (tab_index < pi->pi_msix.table_count) { 481 /* valid MSI-X Table access */ 482 dest = (char *)(pi->pi_msix.table + tab_index); 483 dest += msix_entry_offset; 484 485 if (size == 1) 486 retval = *((uint8_t *)dest); 487 else if (size == 4) 488 retval = *((uint32_t *)dest); 489 else 490 retval = *((uint64_t *)dest); 491 } else if (pci_valid_pba_offset(pi, offset)) { 492 /* return 0 for PBA access */ 493 retval = 0; 494 } 495 496 return (retval); 497 } 498 499 int 500 pci_msix_table_bar(struct pci_devinst *pi) 501 { 502 503 if (pi->pi_msix.table != NULL) 504 return (pi->pi_msix.table_bar); 505 else 506 return (-1); 507 } 508 509 int 510 pci_msix_pba_bar(struct pci_devinst *pi) 511 { 512 513 if (pi->pi_msix.table != NULL) 514 return (pi->pi_msix.pba_bar); 515 else 516 return (-1); 517 } 518 519 #ifdef __amd64__ 520 static int 521 pci_emul_io_handler(struct vmctx *ctx __unused, int in, int port, 522 int bytes, uint32_t *eax, void *arg) 523 { 524 struct pci_devinst *pdi = arg; 525 struct pci_devemu *pe = pdi->pi_d; 526 uint64_t offset; 527 int i; 528 529 assert(port >= 0); 530 531 for (i = 0; i <= PCI_BARMAX; i++) { 532 if (pdi->pi_bar[i].type == PCIBAR_IO && 533 (uint64_t)port >= pdi->pi_bar[i].addr && 534 (uint64_t)port + bytes <= 535 pdi->pi_bar[i].addr + pdi->pi_bar[i].size) { 536 offset = port - pdi->pi_bar[i].addr; 537 if (in) 538 *eax = (*pe->pe_barread)(pdi, i, 539 offset, bytes); 540 else 541 (*pe->pe_barwrite)(pdi, i, offset, 542 bytes, *eax); 543 return (0); 544 } 545 } 546 return (-1); 547 } 548 #else 549 static int 550 pci_emul_iomem_handler(struct vcpu *vcpu __unused, int dir, 551 uint64_t addr, int size, uint64_t *val, void *arg1, long arg2) 552 { 553 struct pci_devinst *pdi = arg1; 554 struct pci_devemu *pe = pdi->pi_d; 555 uint64_t offset; 556 int bidx = (int)arg2; 557 558 assert(bidx <= PCI_BARMAX); 559 assert(pdi->pi_bar[bidx].type == PCIBAR_IO); 560 assert(addr >= pdi->pi_bar[bidx].addr && 561 addr + size <= pdi->pi_bar[bidx].addr + pdi->pi_bar[bidx].size); 562 assert(size == 1 || size == 2 || size == 4); 563 564 offset = addr - pdi->pi_bar[bidx].addr; 565 if (dir == MEM_F_READ) 566 *val = (*pe->pe_barread)(pdi, bidx, offset, size); 567 else 568 (*pe->pe_barwrite)(pdi, bidx, offset, size, *val); 569 570 return (0); 571 } 572 #endif /* !__amd64__ */ 573 574 static int 575 pci_emul_mem_handler(struct vcpu *vcpu __unused, int dir, 576 uint64_t addr, int size, uint64_t *val, void *arg1, long arg2) 577 { 578 struct pci_devinst *pdi = arg1; 579 struct pci_devemu *pe = pdi->pi_d; 580 uint64_t offset; 581 int bidx = (int)arg2; 582 583 assert(bidx <= PCI_BARMAX); 584 assert(pdi->pi_bar[bidx].type == PCIBAR_MEM32 || 585 pdi->pi_bar[bidx].type == PCIBAR_MEM64); 586 assert(addr >= pdi->pi_bar[bidx].addr && 587 addr + size <= pdi->pi_bar[bidx].addr + pdi->pi_bar[bidx].size); 588 589 offset = addr - pdi->pi_bar[bidx].addr; 590 591 if (dir == MEM_F_WRITE) { 592 if (size == 8) { 593 (*pe->pe_barwrite)(pdi, bidx, offset, 594 4, *val & 0xffffffff); 595 (*pe->pe_barwrite)(pdi, bidx, offset + 4, 596 4, *val >> 32); 597 } else { 598 (*pe->pe_barwrite)(pdi, bidx, offset, 599 size, *val); 600 } 601 } else { 602 if (size == 8) { 603 *val = (*pe->pe_barread)(pdi, bidx, 604 offset, 4); 605 *val |= (*pe->pe_barread)(pdi, bidx, 606 offset + 4, 4) << 32; 607 } else { 608 *val = (*pe->pe_barread)(pdi, bidx, 609 offset, size); 610 } 611 } 612 613 return (0); 614 } 615 616 617 static int 618 pci_emul_alloc_resource(uint64_t *baseptr, uint64_t limit, uint64_t size, 619 uint64_t *addr) 620 { 621 uint64_t base; 622 623 assert((size & (size - 1)) == 0); /* must be a power of 2 */ 624 625 base = roundup2(*baseptr, size); 626 627 if (base + size <= limit) { 628 *addr = base; 629 *baseptr = base + size; 630 return (0); 631 } else 632 return (-1); 633 } 634 635 /* 636 * Register (or unregister) the MMIO or I/O region associated with the BAR 637 * register 'idx' of an emulated pci device. 638 */ 639 static void 640 modify_bar_registration(struct pci_devinst *pi, int idx, int registration) 641 { 642 struct pci_devemu *pe; 643 int error; 644 enum pcibar_type type; 645 646 pe = pi->pi_d; 647 type = pi->pi_bar[idx].type; 648 switch (type) { 649 case PCIBAR_IO: 650 { 651 #ifdef __amd64__ 652 struct inout_port iop; 653 654 bzero(&iop, sizeof(struct inout_port)); 655 iop.name = pi->pi_name; 656 iop.port = pi->pi_bar[idx].addr; 657 iop.size = pi->pi_bar[idx].size; 658 if (registration) { 659 iop.flags = IOPORT_F_INOUT; 660 iop.handler = pci_emul_io_handler; 661 iop.arg = pi; 662 error = register_inout(&iop); 663 } else 664 error = unregister_inout(&iop); 665 #else 666 struct mem_range mr; 667 668 bzero(&mr, sizeof(struct mem_range)); 669 mr.name = pi->pi_name; 670 mr.base = pi->pi_bar[idx].addr; 671 mr.size = pi->pi_bar[idx].size; 672 if (registration) { 673 mr.flags = MEM_F_RW; 674 mr.handler = pci_emul_iomem_handler; 675 mr.arg1 = pi; 676 mr.arg2 = idx; 677 error = register_mem(&mr); 678 } else 679 error = unregister_mem(&mr); 680 #endif 681 break; 682 } 683 case PCIBAR_MEM32: 684 case PCIBAR_MEM64: 685 { 686 struct mem_range mr; 687 688 bzero(&mr, sizeof(struct mem_range)); 689 mr.name = pi->pi_name; 690 mr.base = pi->pi_bar[idx].addr; 691 mr.size = pi->pi_bar[idx].size; 692 if (registration) { 693 mr.flags = MEM_F_RW; 694 mr.handler = pci_emul_mem_handler; 695 mr.arg1 = pi; 696 mr.arg2 = idx; 697 error = register_mem(&mr); 698 } else 699 error = unregister_mem(&mr); 700 break; 701 } 702 case PCIBAR_ROM: 703 error = 0; 704 break; 705 default: 706 error = EINVAL; 707 break; 708 } 709 assert(error == 0); 710 711 if (pe->pe_baraddr != NULL) 712 (*pe->pe_baraddr)(pi, idx, registration, pi->pi_bar[idx].addr); 713 } 714 715 static void 716 unregister_bar(struct pci_devinst *pi, int idx) 717 { 718 719 modify_bar_registration(pi, idx, 0); 720 } 721 722 static void 723 register_bar(struct pci_devinst *pi, int idx) 724 { 725 726 modify_bar_registration(pi, idx, 1); 727 } 728 729 /* Is the ROM enabled for the emulated pci device? */ 730 static int 731 romen(struct pci_devinst *pi) 732 { 733 return (pi->pi_bar[PCI_ROM_IDX].lobits & PCIM_BIOS_ENABLE) == 734 PCIM_BIOS_ENABLE; 735 } 736 737 /* Are we decoding i/o port accesses for the emulated pci device? */ 738 static int 739 porten(struct pci_devinst *pi) 740 { 741 uint16_t cmd; 742 743 cmd = pci_get_cfgdata16(pi, PCIR_COMMAND); 744 745 return (cmd & PCIM_CMD_PORTEN); 746 } 747 748 /* Are we decoding memory accesses for the emulated pci device? */ 749 static int 750 memen(struct pci_devinst *pi) 751 { 752 uint16_t cmd; 753 754 cmd = pci_get_cfgdata16(pi, PCIR_COMMAND); 755 756 return (cmd & PCIM_CMD_MEMEN); 757 } 758 759 /* 760 * Update the MMIO or I/O address that is decoded by the BAR register. 761 * 762 * If the pci device has enabled the address space decoding then intercept 763 * the address range decoded by the BAR register. 764 */ 765 static void 766 update_bar_address(struct pci_devinst *pi, uint64_t addr, int idx, int type) 767 { 768 int decode; 769 770 if (pi->pi_bar[idx].type == PCIBAR_IO) 771 decode = porten(pi); 772 else 773 decode = memen(pi); 774 775 if (decode) 776 unregister_bar(pi, idx); 777 778 switch (type) { 779 case PCIBAR_IO: 780 case PCIBAR_MEM32: 781 pi->pi_bar[idx].addr = addr; 782 break; 783 case PCIBAR_MEM64: 784 pi->pi_bar[idx].addr &= ~0xffffffffUL; 785 pi->pi_bar[idx].addr |= addr; 786 break; 787 case PCIBAR_MEMHI64: 788 pi->pi_bar[idx].addr &= 0xffffffff; 789 pi->pi_bar[idx].addr |= addr; 790 break; 791 default: 792 assert(0); 793 } 794 795 if (decode) 796 register_bar(pi, idx); 797 } 798 799 int 800 pci_emul_alloc_bar(struct pci_devinst *pdi, int idx, enum pcibar_type type, 801 uint64_t size) 802 { 803 assert((type == PCIBAR_ROM) || (idx >= 0 && idx <= PCI_BARMAX)); 804 assert((type != PCIBAR_ROM) || (idx == PCI_ROM_IDX)); 805 806 if ((size & (size - 1)) != 0) 807 size = 1UL << flsl(size); /* round up to a power of 2 */ 808 809 /* Enforce minimum BAR sizes required by the PCI standard */ 810 if (type == PCIBAR_IO) { 811 if (size < 4) 812 size = 4; 813 } else if (type == PCIBAR_ROM) { 814 if (size < ~PCIM_BIOS_ADDR_MASK + 1) 815 size = ~PCIM_BIOS_ADDR_MASK + 1; 816 } else { 817 if (size < 16) 818 size = 16; 819 } 820 821 /* 822 * To reduce fragmentation of the MMIO space, we allocate the BARs by 823 * size. Therefore, don't allocate the BAR yet. We create a list of all 824 * BAR allocation which is sorted by BAR size. When all PCI devices are 825 * initialized, we will assign an address to the BARs. 826 */ 827 828 /* create a new list entry */ 829 struct pci_bar_allocation *const new_bar = malloc(sizeof(*new_bar)); 830 memset(new_bar, 0, sizeof(*new_bar)); 831 new_bar->pdi = pdi; 832 new_bar->idx = idx; 833 new_bar->type = type; 834 new_bar->size = size; 835 836 /* 837 * Search for a BAR which size is lower than the size of our newly 838 * allocated BAR. 839 */ 840 struct pci_bar_allocation *bar = NULL; 841 TAILQ_FOREACH(bar, &pci_bars, chain) { 842 if (bar->size < size) { 843 break; 844 } 845 } 846 847 if (bar == NULL) { 848 /* 849 * Either the list is empty or new BAR is the smallest BAR of 850 * the list. Append it to the end of our list. 851 */ 852 TAILQ_INSERT_TAIL(&pci_bars, new_bar, chain); 853 } else { 854 /* 855 * The found BAR is smaller than our new BAR. For that reason, 856 * insert our new BAR before the found BAR. 857 */ 858 TAILQ_INSERT_BEFORE(bar, new_bar, chain); 859 } 860 861 /* 862 * pci_passthru devices synchronize their physical and virtual command 863 * register on init. For that reason, the virtual cmd reg should be 864 * updated as early as possible. 865 */ 866 uint16_t enbit = 0; 867 switch (type) { 868 case PCIBAR_IO: 869 enbit = PCIM_CMD_PORTEN; 870 break; 871 case PCIBAR_MEM64: 872 case PCIBAR_MEM32: 873 enbit = PCIM_CMD_MEMEN; 874 break; 875 default: 876 enbit = 0; 877 break; 878 } 879 880 const uint16_t cmd = pci_get_cfgdata16(pdi, PCIR_COMMAND); 881 pci_set_cfgdata16(pdi, PCIR_COMMAND, cmd | enbit); 882 883 return (0); 884 } 885 886 static int 887 pci_emul_assign_bar(struct pci_devinst *const pdi, const int idx, 888 const enum pcibar_type type, const uint64_t size) 889 { 890 int error; 891 uint64_t *baseptr, limit, addr, mask, lobits, bar; 892 893 switch (type) { 894 case PCIBAR_NONE: 895 baseptr = NULL; 896 addr = mask = lobits = 0; 897 break; 898 case PCIBAR_IO: 899 baseptr = &pci_emul_iobase; 900 limit = PCI_EMUL_IOLIMIT; 901 mask = PCIM_BAR_IO_BASE; 902 lobits = PCIM_BAR_IO_SPACE; 903 break; 904 case PCIBAR_MEM64: 905 /* 906 * XXX 907 * Some drivers do not work well if the 64-bit BAR is allocated 908 * above 4GB. Allow for this by allocating small requests under 909 * 4GB unless then allocation size is larger than some arbitrary 910 * number (128MB currently). 911 */ 912 if (size > 128 * 1024 * 1024) { 913 baseptr = &pci_emul_membase64; 914 limit = pci_emul_memlim64; 915 mask = PCIM_BAR_MEM_BASE; 916 lobits = PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_64 | 917 PCIM_BAR_MEM_PREFETCH; 918 } else { 919 baseptr = &pci_emul_membase32; 920 limit = PCI_EMUL_MEMLIMIT32; 921 mask = PCIM_BAR_MEM_BASE; 922 lobits = PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_64; 923 } 924 break; 925 case PCIBAR_MEM32: 926 baseptr = &pci_emul_membase32; 927 limit = PCI_EMUL_MEMLIMIT32; 928 mask = PCIM_BAR_MEM_BASE; 929 lobits = PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_32; 930 break; 931 case PCIBAR_ROM: 932 /* do not claim memory for ROM. OVMF will do it for us. */ 933 baseptr = NULL; 934 limit = 0; 935 mask = PCIM_BIOS_ADDR_MASK; 936 lobits = 0; 937 break; 938 default: 939 printf("pci_emul_alloc_base: invalid bar type %d\n", type); 940 assert(0); 941 } 942 943 if (baseptr != NULL) { 944 error = pci_emul_alloc_resource(baseptr, limit, size, &addr); 945 if (error != 0) 946 return (error); 947 } else { 948 addr = 0; 949 } 950 951 pdi->pi_bar[idx].type = type; 952 pdi->pi_bar[idx].addr = addr; 953 pdi->pi_bar[idx].size = size; 954 /* 955 * passthru devices are using same lobits as physical device they set 956 * this property 957 */ 958 if (pdi->pi_bar[idx].lobits != 0) { 959 lobits = pdi->pi_bar[idx].lobits; 960 } else { 961 pdi->pi_bar[idx].lobits = lobits; 962 } 963 964 /* Initialize the BAR register in config space */ 965 bar = (addr & mask) | lobits; 966 pci_set_cfgdata32(pdi, PCIR_BAR(idx), bar); 967 968 if (type == PCIBAR_MEM64) { 969 assert(idx + 1 <= PCI_BARMAX); 970 pdi->pi_bar[idx + 1].type = PCIBAR_MEMHI64; 971 pci_set_cfgdata32(pdi, PCIR_BAR(idx + 1), bar >> 32); 972 } 973 974 if (type != PCIBAR_ROM) { 975 register_bar(pdi, idx); 976 } 977 978 return (0); 979 } 980 981 int 982 pci_emul_alloc_rom(struct pci_devinst *const pdi, const uint64_t size, 983 void **const addr) 984 { 985 /* allocate ROM space once on first call */ 986 if (pci_emul_rombase == 0) { 987 pci_emul_rombase = vm_create_devmem(pdi->pi_vmctx, VM_PCIROM, 988 "pcirom", PCI_EMUL_ROMSIZE); 989 if (pci_emul_rombase == MAP_FAILED) { 990 warnx("%s: failed to create rom segment", __func__); 991 return (-1); 992 } 993 pci_emul_romlim = pci_emul_rombase + PCI_EMUL_ROMSIZE; 994 pci_emul_romoffset = 0; 995 } 996 997 /* ROM size should be a power of 2 and greater than 2 KB */ 998 const uint64_t rom_size = MAX(1UL << flsl(size), 999 ~PCIM_BIOS_ADDR_MASK + 1); 1000 1001 /* check if ROM fits into ROM space */ 1002 if (pci_emul_romoffset + rom_size > PCI_EMUL_ROMSIZE) { 1003 warnx("%s: no space left in rom segment:", __func__); 1004 warnx("%16lu bytes left", 1005 PCI_EMUL_ROMSIZE - pci_emul_romoffset); 1006 warnx("%16lu bytes required by %d/%d/%d", rom_size, pdi->pi_bus, 1007 pdi->pi_slot, pdi->pi_func); 1008 return (-1); 1009 } 1010 1011 /* allocate ROM BAR */ 1012 const int error = pci_emul_alloc_bar(pdi, PCI_ROM_IDX, PCIBAR_ROM, 1013 rom_size); 1014 if (error) 1015 return error; 1016 1017 /* return address */ 1018 *addr = pci_emul_rombase + pci_emul_romoffset; 1019 1020 /* save offset into ROM Space */ 1021 pdi->pi_romoffset = pci_emul_romoffset; 1022 1023 /* increase offset for next ROM */ 1024 pci_emul_romoffset += rom_size; 1025 1026 return (0); 1027 } 1028 1029 int 1030 pci_emul_add_boot_device(struct pci_devinst *pi, int bootindex) 1031 { 1032 struct boot_device *new_device, *device; 1033 1034 /* don't permit a negative bootindex */ 1035 if (bootindex < 0) { 1036 errx(4, "Invalid bootindex %d for %s", bootindex, pi->pi_name); 1037 } 1038 1039 /* alloc new boot device */ 1040 new_device = calloc(1, sizeof(struct boot_device)); 1041 if (new_device == NULL) { 1042 return (ENOMEM); 1043 } 1044 new_device->pdi = pi; 1045 new_device->bootindex = bootindex; 1046 1047 /* search for boot device with higher boot index */ 1048 TAILQ_FOREACH(device, &boot_devices, boot_device_chain) { 1049 if (device->bootindex == bootindex) { 1050 errx(4, 1051 "Could not set bootindex %d for %s. Bootindex already occupied by %s", 1052 bootindex, pi->pi_name, device->pdi->pi_name); 1053 } else if (device->bootindex > bootindex) { 1054 break; 1055 } 1056 } 1057 1058 /* add boot device to queue */ 1059 if (device == NULL) { 1060 TAILQ_INSERT_TAIL(&boot_devices, new_device, boot_device_chain); 1061 } else { 1062 TAILQ_INSERT_BEFORE(device, new_device, boot_device_chain); 1063 } 1064 1065 return (0); 1066 } 1067 1068 #define CAP_START_OFFSET 0x40 1069 static int 1070 pci_emul_add_capability(struct pci_devinst *pi, u_char *capdata, int caplen) 1071 { 1072 int i, capoff, reallen; 1073 uint16_t sts; 1074 1075 assert(caplen > 0); 1076 1077 reallen = roundup2(caplen, 4); /* dword aligned */ 1078 1079 sts = pci_get_cfgdata16(pi, PCIR_STATUS); 1080 if ((sts & PCIM_STATUS_CAPPRESENT) == 0) 1081 capoff = CAP_START_OFFSET; 1082 else 1083 capoff = pi->pi_capend + 1; 1084 1085 /* Check if we have enough space */ 1086 if (capoff + reallen > PCI_REGMAX + 1) 1087 return (-1); 1088 1089 /* Set the previous capability pointer */ 1090 if ((sts & PCIM_STATUS_CAPPRESENT) == 0) { 1091 pci_set_cfgdata8(pi, PCIR_CAP_PTR, capoff); 1092 pci_set_cfgdata16(pi, PCIR_STATUS, sts|PCIM_STATUS_CAPPRESENT); 1093 } else 1094 pci_set_cfgdata8(pi, pi->pi_prevcap + 1, capoff); 1095 1096 /* Copy the capability */ 1097 for (i = 0; i < caplen; i++) 1098 pci_set_cfgdata8(pi, capoff + i, capdata[i]); 1099 1100 /* Set the next capability pointer */ 1101 pci_set_cfgdata8(pi, capoff + 1, 0); 1102 1103 pi->pi_prevcap = capoff; 1104 pi->pi_capend = capoff + reallen - 1; 1105 return (0); 1106 } 1107 1108 static struct pci_devemu * 1109 pci_emul_finddev(const char *name) 1110 { 1111 struct pci_devemu **pdpp, *pdp; 1112 1113 SET_FOREACH(pdpp, pci_devemu_set) { 1114 pdp = *pdpp; 1115 if (!strcmp(pdp->pe_emu, name)) { 1116 return (pdp); 1117 } 1118 } 1119 1120 return (NULL); 1121 } 1122 1123 static int 1124 pci_emul_init(struct vmctx *ctx, struct pci_devemu *pde, int bus, int slot, 1125 int func, struct funcinfo *fi) 1126 { 1127 struct pci_devinst *pdi; 1128 int err; 1129 1130 pdi = calloc(1, sizeof(struct pci_devinst)); 1131 1132 pdi->pi_vmctx = ctx; 1133 pdi->pi_bus = bus; 1134 pdi->pi_slot = slot; 1135 pdi->pi_func = func; 1136 #ifdef __amd64__ 1137 pthread_mutex_init(&pdi->pi_lintr.lock, NULL); 1138 pdi->pi_lintr.pin = 0; 1139 pdi->pi_lintr.state = IDLE; 1140 pdi->pi_lintr.pirq_pin = 0; 1141 pdi->pi_lintr.ioapic_irq = 0; 1142 #endif 1143 pdi->pi_d = pde; 1144 snprintf(pdi->pi_name, PI_NAMESZ, "%s@pci.%d.%d.%d", pde->pe_emu, bus, 1145 slot, func); 1146 1147 /* Disable legacy interrupts */ 1148 pci_set_cfgdata8(pdi, PCIR_INTLINE, 255); 1149 pci_set_cfgdata8(pdi, PCIR_INTPIN, 0); 1150 1151 pci_set_cfgdata8(pdi, PCIR_COMMAND, PCIM_CMD_BUSMASTEREN); 1152 1153 err = (*pde->pe_init)(pdi, fi->fi_config); 1154 if (err == 0) 1155 fi->fi_devi = pdi; 1156 else 1157 free(pdi); 1158 1159 return (err); 1160 } 1161 1162 void 1163 pci_populate_msicap(struct msicap *msicap, int msgnum, int nextptr) 1164 { 1165 int mmc; 1166 1167 /* Number of msi messages must be a power of 2 between 1 and 32 */ 1168 assert((msgnum & (msgnum - 1)) == 0 && msgnum >= 1 && msgnum <= 32); 1169 mmc = ffs(msgnum) - 1; 1170 1171 bzero(msicap, sizeof(struct msicap)); 1172 msicap->capid = PCIY_MSI; 1173 msicap->nextptr = nextptr; 1174 msicap->msgctrl = PCIM_MSICTRL_64BIT | (mmc << 1); 1175 } 1176 1177 int 1178 pci_emul_add_msicap(struct pci_devinst *pi, int msgnum) 1179 { 1180 struct msicap msicap; 1181 1182 pci_populate_msicap(&msicap, msgnum, 0); 1183 1184 return (pci_emul_add_capability(pi, (u_char *)&msicap, sizeof(msicap))); 1185 } 1186 1187 static void 1188 pci_populate_msixcap(struct msixcap *msixcap, int msgnum, int barnum, 1189 uint32_t msix_tab_size) 1190 { 1191 1192 assert(msix_tab_size % 4096 == 0); 1193 1194 bzero(msixcap, sizeof(struct msixcap)); 1195 msixcap->capid = PCIY_MSIX; 1196 1197 /* 1198 * Message Control Register, all fields set to 1199 * zero except for the Table Size. 1200 * Note: Table size N is encoded as N-1 1201 */ 1202 msixcap->msgctrl = msgnum - 1; 1203 1204 /* 1205 * MSI-X BAR setup: 1206 * - MSI-X table start at offset 0 1207 * - PBA table starts at a 4K aligned offset after the MSI-X table 1208 */ 1209 msixcap->table_info = barnum & PCIM_MSIX_BIR_MASK; 1210 msixcap->pba_info = msix_tab_size | (barnum & PCIM_MSIX_BIR_MASK); 1211 } 1212 1213 static void 1214 pci_msix_table_init(struct pci_devinst *pi, int table_entries) 1215 { 1216 int i, table_size; 1217 1218 assert(table_entries > 0); 1219 assert(table_entries <= MAX_MSIX_TABLE_ENTRIES); 1220 1221 table_size = table_entries * MSIX_TABLE_ENTRY_SIZE; 1222 pi->pi_msix.table = calloc(1, table_size); 1223 1224 /* set mask bit of vector control register */ 1225 for (i = 0; i < table_entries; i++) 1226 pi->pi_msix.table[i].vector_control |= PCIM_MSIX_VCTRL_MASK; 1227 } 1228 1229 int 1230 pci_emul_add_msixcap(struct pci_devinst *pi, int msgnum, int barnum) 1231 { 1232 uint32_t tab_size; 1233 struct msixcap msixcap; 1234 1235 assert(msgnum >= 1 && msgnum <= MAX_MSIX_TABLE_ENTRIES); 1236 assert(barnum >= 0 && barnum <= PCIR_MAX_BAR_0); 1237 1238 tab_size = msgnum * MSIX_TABLE_ENTRY_SIZE; 1239 1240 /* Align table size to nearest 4K */ 1241 tab_size = roundup2(tab_size, 4096); 1242 1243 pi->pi_msix.table_bar = barnum; 1244 pi->pi_msix.pba_bar = barnum; 1245 pi->pi_msix.table_offset = 0; 1246 pi->pi_msix.table_count = msgnum; 1247 pi->pi_msix.pba_offset = tab_size; 1248 pi->pi_msix.pba_size = PBA_SIZE(msgnum); 1249 1250 pci_msix_table_init(pi, msgnum); 1251 1252 pci_populate_msixcap(&msixcap, msgnum, barnum, tab_size); 1253 1254 /* allocate memory for MSI-X Table and PBA */ 1255 pci_emul_alloc_bar(pi, barnum, PCIBAR_MEM32, 1256 tab_size + pi->pi_msix.pba_size); 1257 1258 return (pci_emul_add_capability(pi, (u_char *)&msixcap, 1259 sizeof(msixcap))); 1260 } 1261 1262 static void 1263 msixcap_cfgwrite(struct pci_devinst *pi, int capoff, int offset, 1264 int bytes, uint32_t val) 1265 { 1266 uint16_t msgctrl, rwmask; 1267 int off; 1268 1269 off = offset - capoff; 1270 /* Message Control Register */ 1271 if (off == 2 && bytes == 2) { 1272 rwmask = PCIM_MSIXCTRL_MSIX_ENABLE | PCIM_MSIXCTRL_FUNCTION_MASK; 1273 msgctrl = pci_get_cfgdata16(pi, offset); 1274 msgctrl &= ~rwmask; 1275 msgctrl |= val & rwmask; 1276 val = msgctrl; 1277 1278 pi->pi_msix.enabled = val & PCIM_MSIXCTRL_MSIX_ENABLE; 1279 pi->pi_msix.function_mask = val & PCIM_MSIXCTRL_FUNCTION_MASK; 1280 #ifdef __amd64__ 1281 pci_lintr_update(pi); 1282 #endif 1283 } 1284 1285 CFGWRITE(pi, offset, val, bytes); 1286 } 1287 1288 static void 1289 msicap_cfgwrite(struct pci_devinst *pi, int capoff, int offset, 1290 int bytes, uint32_t val) 1291 { 1292 uint16_t msgctrl, rwmask, msgdata, mme; 1293 uint32_t addrlo; 1294 1295 /* 1296 * If guest is writing to the message control register make sure 1297 * we do not overwrite read-only fields. 1298 */ 1299 if ((offset - capoff) == 2 && bytes == 2) { 1300 rwmask = PCIM_MSICTRL_MME_MASK | PCIM_MSICTRL_MSI_ENABLE; 1301 msgctrl = pci_get_cfgdata16(pi, offset); 1302 msgctrl &= ~rwmask; 1303 msgctrl |= val & rwmask; 1304 val = msgctrl; 1305 } 1306 CFGWRITE(pi, offset, val, bytes); 1307 1308 msgctrl = pci_get_cfgdata16(pi, capoff + 2); 1309 addrlo = pci_get_cfgdata32(pi, capoff + 4); 1310 if (msgctrl & PCIM_MSICTRL_64BIT) 1311 msgdata = pci_get_cfgdata16(pi, capoff + 12); 1312 else 1313 msgdata = pci_get_cfgdata16(pi, capoff + 8); 1314 1315 mme = msgctrl & PCIM_MSICTRL_MME_MASK; 1316 pi->pi_msi.enabled = msgctrl & PCIM_MSICTRL_MSI_ENABLE ? 1 : 0; 1317 if (pi->pi_msi.enabled) { 1318 pi->pi_msi.addr = addrlo; 1319 pi->pi_msi.msg_data = msgdata; 1320 pi->pi_msi.maxmsgnum = 1 << (mme >> 4); 1321 } else { 1322 pi->pi_msi.maxmsgnum = 0; 1323 } 1324 #ifdef __amd64__ 1325 pci_lintr_update(pi); 1326 #endif 1327 } 1328 1329 static void 1330 pciecap_cfgwrite(struct pci_devinst *pi, int capoff __unused, int offset, 1331 int bytes, uint32_t val) 1332 { 1333 1334 /* XXX don't write to the readonly parts */ 1335 CFGWRITE(pi, offset, val, bytes); 1336 } 1337 1338 #define PCIECAP_VERSION 0x2 1339 int 1340 pci_emul_add_pciecap(struct pci_devinst *pi, int type) 1341 { 1342 int err; 1343 struct pciecap pciecap; 1344 1345 bzero(&pciecap, sizeof(pciecap)); 1346 1347 /* 1348 * Use the integrated endpoint type for endpoints on a root complex bus. 1349 * 1350 * NB: bhyve currently only supports a single PCI bus that is the root 1351 * complex bus, so all endpoints are integrated. 1352 */ 1353 if ((type == PCIEM_TYPE_ENDPOINT) && (pi->pi_bus == 0)) 1354 type = PCIEM_TYPE_ROOT_INT_EP; 1355 1356 pciecap.capid = PCIY_EXPRESS; 1357 pciecap.pcie_capabilities = PCIECAP_VERSION | type; 1358 if (type != PCIEM_TYPE_ROOT_INT_EP) { 1359 pciecap.link_capabilities = 0x411; /* gen1, x1 */ 1360 pciecap.link_status = 0x11; /* gen1, x1 */ 1361 } 1362 1363 err = pci_emul_add_capability(pi, (u_char *)&pciecap, sizeof(pciecap)); 1364 return (err); 1365 } 1366 1367 /* 1368 * This function assumes that 'coff' is in the capabilities region of the 1369 * config space. A capoff parameter of zero will force a search for the 1370 * offset and type. 1371 */ 1372 void 1373 pci_emul_capwrite(struct pci_devinst *pi, int offset, int bytes, uint32_t val, 1374 uint8_t capoff, int capid) 1375 { 1376 uint8_t nextoff; 1377 1378 /* Do not allow un-aligned writes */ 1379 if ((offset & (bytes - 1)) != 0) 1380 return; 1381 1382 if (capoff == 0) { 1383 /* Find the capability that we want to update */ 1384 capoff = CAP_START_OFFSET; 1385 while (1) { 1386 nextoff = pci_get_cfgdata8(pi, capoff + 1); 1387 if (nextoff == 0) 1388 break; 1389 if (offset >= capoff && offset < nextoff) 1390 break; 1391 1392 capoff = nextoff; 1393 } 1394 assert(offset >= capoff); 1395 capid = pci_get_cfgdata8(pi, capoff); 1396 } 1397 1398 /* 1399 * Capability ID and Next Capability Pointer are readonly. 1400 * However, some o/s's do 4-byte writes that include these. 1401 * For this case, trim the write back to 2 bytes and adjust 1402 * the data. 1403 */ 1404 if (offset == capoff || offset == capoff + 1) { 1405 if (offset == capoff && bytes == 4) { 1406 bytes = 2; 1407 offset += 2; 1408 val >>= 16; 1409 } else 1410 return; 1411 } 1412 1413 switch (capid) { 1414 case PCIY_MSI: 1415 msicap_cfgwrite(pi, capoff, offset, bytes, val); 1416 break; 1417 case PCIY_MSIX: 1418 msixcap_cfgwrite(pi, capoff, offset, bytes, val); 1419 break; 1420 case PCIY_EXPRESS: 1421 pciecap_cfgwrite(pi, capoff, offset, bytes, val); 1422 break; 1423 default: 1424 break; 1425 } 1426 } 1427 1428 static int 1429 pci_emul_iscap(struct pci_devinst *pi, int offset) 1430 { 1431 uint16_t sts; 1432 1433 sts = pci_get_cfgdata16(pi, PCIR_STATUS); 1434 if ((sts & PCIM_STATUS_CAPPRESENT) != 0) { 1435 if (offset >= CAP_START_OFFSET && offset <= pi->pi_capend) 1436 return (1); 1437 } 1438 return (0); 1439 } 1440 1441 static int 1442 pci_emul_fallback_handler(struct vcpu *vcpu __unused, int dir, 1443 uint64_t addr __unused, int size __unused, uint64_t *val, 1444 void *arg1 __unused, long arg2 __unused) 1445 { 1446 /* 1447 * Ignore writes; return 0xff's for reads. The mem read code 1448 * will take care of truncating to the correct size. 1449 */ 1450 if (dir == MEM_F_READ) { 1451 *val = 0xffffffffffffffff; 1452 } 1453 1454 return (0); 1455 } 1456 1457 static int 1458 pci_emul_ecfg_handler(struct vcpu *vcpu __unused, int dir, uint64_t addr, 1459 int bytes, uint64_t *val, void *arg1 __unused, long arg2 __unused) 1460 { 1461 int bus, slot, func, coff, in; 1462 1463 coff = addr & 0xfff; 1464 func = (addr >> 12) & 0x7; 1465 slot = (addr >> 15) & 0x1f; 1466 bus = (addr >> 20) & 0xff; 1467 in = (dir == MEM_F_READ); 1468 if (in) 1469 *val = ~0UL; 1470 pci_cfgrw(in, bus, slot, func, coff, bytes, (uint32_t *)val); 1471 return (0); 1472 } 1473 1474 uint64_t 1475 pci_ecfg_base(void) 1476 { 1477 1478 return (PCI_EMUL_ECFG_BASE); 1479 } 1480 1481 static int 1482 init_bootorder(void) 1483 { 1484 struct boot_device *device; 1485 FILE *fp; 1486 char *bootorder; 1487 size_t bootorder_len; 1488 1489 if (TAILQ_EMPTY(&boot_devices)) 1490 return (0); 1491 1492 fp = open_memstream(&bootorder, &bootorder_len); 1493 TAILQ_FOREACH(device, &boot_devices, boot_device_chain) { 1494 fprintf(fp, "/pci@i0cf8/pci@%d,%d\n", 1495 device->pdi->pi_slot, device->pdi->pi_func); 1496 } 1497 fclose(fp); 1498 1499 return (qemu_fwcfg_add_file("bootorder", bootorder_len, bootorder)); 1500 } 1501 1502 #define BUSIO_ROUNDUP 32 1503 #define BUSMEM32_ROUNDUP (1024 * 1024) 1504 #define BUSMEM64_ROUNDUP (512 * 1024 * 1024) 1505 1506 int 1507 init_pci(struct vmctx *ctx) 1508 { 1509 char node_name[sizeof("pci.XXX.XX.X")]; 1510 struct mem_range mr; 1511 struct pci_devemu *pde; 1512 struct businfo *bi; 1513 struct slotinfo *si; 1514 struct funcinfo *fi; 1515 nvlist_t *nvl; 1516 const char *emul; 1517 size_t lowmem; 1518 int bus, slot, func; 1519 int error; 1520 1521 if (vm_get_lowmem_limit(ctx) > PCI_EMUL_MEMBASE32) 1522 errx(EX_OSERR, "Invalid lowmem limit"); 1523 1524 pci_emul_iobase = PCI_EMUL_IOBASE; 1525 pci_emul_membase32 = PCI_EMUL_MEMBASE32; 1526 1527 pci_emul_membase64 = vm_get_highmem_base(ctx) + 1528 vm_get_highmem_size(ctx); 1529 pci_emul_membase64 = roundup2(pci_emul_membase64, PCI_EMUL_MEMSIZE64); 1530 pci_emul_memlim64 = pci_emul_membase64 + PCI_EMUL_MEMSIZE64; 1531 1532 TAILQ_INIT(&boot_devices); 1533 1534 for (bus = 0; bus < MAXBUSES; bus++) { 1535 snprintf(node_name, sizeof(node_name), "pci.%d", bus); 1536 nvl = find_config_node(node_name); 1537 if (nvl == NULL) 1538 continue; 1539 pci_businfo[bus] = calloc(1, sizeof(struct businfo)); 1540 bi = pci_businfo[bus]; 1541 1542 /* 1543 * Keep track of the i/o and memory resources allocated to 1544 * this bus. 1545 */ 1546 bi->iobase = pci_emul_iobase; 1547 bi->membase32 = pci_emul_membase32; 1548 bi->membase64 = pci_emul_membase64; 1549 1550 /* first run: init devices */ 1551 for (slot = 0; slot < MAXSLOTS; slot++) { 1552 si = &bi->slotinfo[slot]; 1553 for (func = 0; func < MAXFUNCS; func++) { 1554 fi = &si->si_funcs[func]; 1555 snprintf(node_name, sizeof(node_name), 1556 "pci.%d.%d.%d", bus, slot, func); 1557 nvl = find_config_node(node_name); 1558 if (nvl == NULL) 1559 continue; 1560 1561 fi->fi_config = nvl; 1562 emul = get_config_value_node(nvl, "device"); 1563 if (emul == NULL) { 1564 EPRINTLN("pci slot %d:%d:%d: missing " 1565 "\"device\" value", bus, slot, func); 1566 return (EINVAL); 1567 } 1568 pde = pci_emul_finddev(emul); 1569 if (pde == NULL) { 1570 EPRINTLN("pci slot %d:%d:%d: unknown " 1571 "device \"%s\"", bus, slot, func, 1572 emul); 1573 return (EINVAL); 1574 } 1575 if (pde->pe_alias != NULL) { 1576 EPRINTLN("pci slot %d:%d:%d: legacy " 1577 "device \"%s\", use \"%s\" instead", 1578 bus, slot, func, emul, 1579 pde->pe_alias); 1580 return (EINVAL); 1581 } 1582 fi->fi_pde = pde; 1583 error = pci_emul_init(ctx, pde, bus, slot, 1584 func, fi); 1585 if (error) 1586 return (error); 1587 } 1588 } 1589 1590 /* second run: assign BARs and free list */ 1591 struct pci_bar_allocation *bar; 1592 struct pci_bar_allocation *bar_tmp; 1593 TAILQ_FOREACH_SAFE(bar, &pci_bars, chain, bar_tmp) { 1594 pci_emul_assign_bar(bar->pdi, bar->idx, bar->type, 1595 bar->size); 1596 free(bar); 1597 } 1598 TAILQ_INIT(&pci_bars); 1599 1600 /* 1601 * Add some slop to the I/O and memory resources decoded by 1602 * this bus to give a guest some flexibility if it wants to 1603 * reprogram the BARs. 1604 */ 1605 pci_emul_iobase += BUSIO_ROUNDUP; 1606 pci_emul_iobase = roundup2(pci_emul_iobase, BUSIO_ROUNDUP); 1607 bi->iolimit = pci_emul_iobase; 1608 1609 pci_emul_membase32 += BUSMEM32_ROUNDUP; 1610 pci_emul_membase32 = roundup2(pci_emul_membase32, 1611 BUSMEM32_ROUNDUP); 1612 bi->memlimit32 = pci_emul_membase32; 1613 1614 pci_emul_membase64 += BUSMEM64_ROUNDUP; 1615 pci_emul_membase64 = roundup2(pci_emul_membase64, 1616 BUSMEM64_ROUNDUP); 1617 bi->memlimit64 = pci_emul_membase64; 1618 } 1619 1620 #ifdef __amd64__ 1621 /* 1622 * PCI backends are initialized before routing INTx interrupts 1623 * so that LPC devices are able to reserve ISA IRQs before 1624 * routing PIRQ pins. 1625 */ 1626 for (bus = 0; bus < MAXBUSES; bus++) { 1627 if ((bi = pci_businfo[bus]) == NULL) 1628 continue; 1629 1630 for (slot = 0; slot < MAXSLOTS; slot++) { 1631 si = &bi->slotinfo[slot]; 1632 for (func = 0; func < MAXFUNCS; func++) { 1633 fi = &si->si_funcs[func]; 1634 if (fi->fi_devi == NULL) 1635 continue; 1636 pci_lintr_route(fi->fi_devi); 1637 } 1638 } 1639 } 1640 lpc_pirq_routed(); 1641 #endif 1642 1643 if ((error = init_bootorder()) != 0) { 1644 warnx("%s: Unable to init bootorder", __func__); 1645 return (error); 1646 } 1647 1648 /* 1649 * The guest physical memory map looks like the following on amd64: 1650 * [0, lowmem) guest system memory 1651 * [lowmem, 0xC0000000) memory hole (may be absent) 1652 * [0xC0000000, 0xE0000000) PCI hole (32-bit BAR allocation) 1653 * [0xE0000000, 0xF0000000) PCI extended config window 1654 * [0xF0000000, 4GB) LAPIC, IOAPIC, HPET, firmware 1655 * [4GB, 4GB + highmem) guest system memory 1656 * [roundup(4GB + highmem, 32GB), ...) PCI 64-bit BAR allocation 1657 * 1658 * On arm64 the guest physical memory map looks like this: 1659 * [0x0DF00000, 0x10000000) PCI I/O memory 1660 * [0xA0000000, 0xE0000000) PCI 32-bit BAR allocation 1661 * [0xE0000000, 0xF0000000) PCI extended config window 1662 * [4GB, 4GB + highmem) guest system memory 1663 * [roundup(4GB + highmem, 32GB), ...) PCI 64-bit BAR allocation 1664 * 1665 * "lowmem" is guest memory below 0xC0000000. amd64 guests provisioned 1666 * with less than 3GB of RAM will have no memory above the 4GB boundary. 1667 * System memory for arm64 guests is all above the 4GB boundary. 1668 */ 1669 1670 /* 1671 * Accesses to memory addresses that are not allocated to system 1672 * memory or PCI devices return 0xff's. 1673 */ 1674 lowmem = vm_get_lowmem_size(ctx); 1675 bzero(&mr, sizeof(struct mem_range)); 1676 mr.name = "PCI hole"; 1677 mr.flags = MEM_F_RW | MEM_F_IMMUTABLE; 1678 mr.base = lowmem; 1679 mr.size = (4ULL * 1024 * 1024 * 1024) - lowmem; 1680 mr.handler = pci_emul_fallback_handler; 1681 error = register_mem_fallback(&mr); 1682 assert(error == 0); 1683 1684 /* PCI extended config space */ 1685 bzero(&mr, sizeof(struct mem_range)); 1686 mr.name = "PCI ECFG"; 1687 mr.flags = MEM_F_RW | MEM_F_IMMUTABLE; 1688 mr.base = PCI_EMUL_ECFG_BASE; 1689 mr.size = PCI_EMUL_ECFG_SIZE; 1690 mr.handler = pci_emul_ecfg_handler; 1691 error = register_mem(&mr); 1692 assert(error == 0); 1693 1694 return (0); 1695 } 1696 1697 #ifdef __amd64__ 1698 static void 1699 pci_apic_prt_entry(int bus __unused, int slot, int pin, int pirq_pin __unused, 1700 int ioapic_irq, void *arg __unused) 1701 { 1702 1703 dsdt_line(" Package ()"); 1704 dsdt_line(" {"); 1705 dsdt_line(" 0x%X,", slot << 16 | 0xffff); 1706 dsdt_line(" 0x%02X,", pin - 1); 1707 dsdt_line(" Zero,"); 1708 dsdt_line(" 0x%X", ioapic_irq); 1709 dsdt_line(" },"); 1710 } 1711 1712 static void 1713 pci_pirq_prt_entry(int bus __unused, int slot, int pin, int pirq_pin, 1714 int ioapic_irq __unused, void *arg __unused) 1715 { 1716 char *name; 1717 1718 name = lpc_pirq_name(pirq_pin); 1719 if (name == NULL) 1720 return; 1721 dsdt_line(" Package ()"); 1722 dsdt_line(" {"); 1723 dsdt_line(" 0x%X,", slot << 16 | 0xffff); 1724 dsdt_line(" 0x%02X,", pin - 1); 1725 dsdt_line(" %s,", name); 1726 dsdt_line(" 0x00"); 1727 dsdt_line(" },"); 1728 free(name); 1729 } 1730 #endif 1731 1732 /* 1733 * A bhyve virtual machine has a flat PCI hierarchy with a root port 1734 * corresponding to each PCI bus. 1735 */ 1736 static void 1737 pci_bus_write_dsdt(int bus) 1738 { 1739 struct businfo *bi; 1740 struct slotinfo *si; 1741 struct pci_devinst *pi; 1742 int func, slot; 1743 1744 /* 1745 * If there are no devices on this 'bus' then just return. 1746 */ 1747 if ((bi = pci_businfo[bus]) == NULL) { 1748 /* 1749 * Bus 0 is special because it decodes the I/O ports used 1750 * for PCI config space access even if there are no devices 1751 * on it. 1752 */ 1753 if (bus != 0) 1754 return; 1755 } 1756 1757 dsdt_line(" Device (PC%02X)", bus); 1758 dsdt_line(" {"); 1759 dsdt_line(" Name (_HID, EisaId (\"PNP0A03\"))"); 1760 1761 dsdt_line(" Method (_BBN, 0, NotSerialized)"); 1762 dsdt_line(" {"); 1763 dsdt_line(" Return (0x%08X)", bus); 1764 dsdt_line(" }"); 1765 dsdt_line(" Name (_CRS, ResourceTemplate ()"); 1766 dsdt_line(" {"); 1767 dsdt_line(" WordBusNumber (ResourceProducer, MinFixed, " 1768 "MaxFixed, PosDecode,"); 1769 dsdt_line(" 0x0000, // Granularity"); 1770 dsdt_line(" 0x%04X, // Range Minimum", bus); 1771 dsdt_line(" 0x%04X, // Range Maximum", bus); 1772 dsdt_line(" 0x0000, // Translation Offset"); 1773 dsdt_line(" 0x0001, // Length"); 1774 dsdt_line(" ,, )"); 1775 1776 #ifdef __amd64__ 1777 if (bus == 0) { 1778 dsdt_indent(3); 1779 dsdt_fixed_ioport(0xCF8, 8); 1780 dsdt_unindent(3); 1781 1782 dsdt_line(" WordIO (ResourceProducer, MinFixed, MaxFixed, " 1783 "PosDecode, EntireRange,"); 1784 dsdt_line(" 0x0000, // Granularity"); 1785 dsdt_line(" 0x0000, // Range Minimum"); 1786 dsdt_line(" 0x0CF7, // Range Maximum"); 1787 dsdt_line(" 0x0000, // Translation Offset"); 1788 dsdt_line(" 0x0CF8, // Length"); 1789 dsdt_line(" ,, , TypeStatic)"); 1790 1791 dsdt_line(" WordIO (ResourceProducer, MinFixed, MaxFixed, " 1792 "PosDecode, EntireRange,"); 1793 dsdt_line(" 0x0000, // Granularity"); 1794 dsdt_line(" 0x0D00, // Range Minimum"); 1795 dsdt_line(" 0x%04X, // Range Maximum", 1796 PCI_EMUL_IOBASE - 1); 1797 dsdt_line(" 0x0000, // Translation Offset"); 1798 dsdt_line(" 0x%04X, // Length", 1799 PCI_EMUL_IOBASE - 0x0D00); 1800 dsdt_line(" ,, , TypeStatic)"); 1801 1802 if (bi == NULL) { 1803 dsdt_line(" })"); 1804 goto done; 1805 } 1806 } 1807 #endif 1808 assert(bi != NULL); 1809 1810 /* i/o window */ 1811 dsdt_line(" WordIO (ResourceProducer, MinFixed, MaxFixed, " 1812 "PosDecode, EntireRange,"); 1813 dsdt_line(" 0x0000, // Granularity"); 1814 dsdt_line(" 0x%04X, // Range Minimum", bi->iobase); 1815 dsdt_line(" 0x%04X, // Range Maximum", 1816 bi->iolimit - 1); 1817 dsdt_line(" 0x0000, // Translation Offset"); 1818 dsdt_line(" 0x%04X, // Length", 1819 bi->iolimit - bi->iobase); 1820 dsdt_line(" ,, , TypeStatic)"); 1821 1822 /* mmio window (32-bit) */ 1823 dsdt_line(" DWordMemory (ResourceProducer, PosDecode, " 1824 "MinFixed, MaxFixed, NonCacheable, ReadWrite,"); 1825 dsdt_line(" 0x00000000, // Granularity"); 1826 dsdt_line(" 0x%08X, // Range Minimum\n", bi->membase32); 1827 dsdt_line(" 0x%08X, // Range Maximum\n", 1828 bi->memlimit32 - 1); 1829 dsdt_line(" 0x00000000, // Translation Offset"); 1830 dsdt_line(" 0x%08X, // Length\n", 1831 bi->memlimit32 - bi->membase32); 1832 dsdt_line(" ,, , AddressRangeMemory, TypeStatic)"); 1833 1834 /* mmio window (64-bit) */ 1835 dsdt_line(" QWordMemory (ResourceProducer, PosDecode, " 1836 "MinFixed, MaxFixed, NonCacheable, ReadWrite,"); 1837 dsdt_line(" 0x0000000000000000, // Granularity"); 1838 dsdt_line(" 0x%016lX, // Range Minimum\n", bi->membase64); 1839 dsdt_line(" 0x%016lX, // Range Maximum\n", 1840 bi->memlimit64 - 1); 1841 dsdt_line(" 0x0000000000000000, // Translation Offset"); 1842 dsdt_line(" 0x%016lX, // Length\n", 1843 bi->memlimit64 - bi->membase64); 1844 dsdt_line(" ,, , AddressRangeMemory, TypeStatic)"); 1845 dsdt_line(" })"); 1846 1847 #ifdef __amd64__ 1848 if (pci_count_lintr(bus) != 0) { 1849 dsdt_indent(2); 1850 dsdt_line("Name (PPRT, Package ()"); 1851 dsdt_line("{"); 1852 pci_walk_lintr(bus, pci_pirq_prt_entry, NULL); 1853 dsdt_line("})"); 1854 dsdt_line("Name (APRT, Package ()"); 1855 dsdt_line("{"); 1856 pci_walk_lintr(bus, pci_apic_prt_entry, NULL); 1857 dsdt_line("})"); 1858 dsdt_line("Method (_PRT, 0, NotSerialized)"); 1859 dsdt_line("{"); 1860 dsdt_line(" If (PICM)"); 1861 dsdt_line(" {"); 1862 dsdt_line(" Return (APRT)"); 1863 dsdt_line(" }"); 1864 dsdt_line(" Else"); 1865 dsdt_line(" {"); 1866 dsdt_line(" Return (PPRT)"); 1867 dsdt_line(" }"); 1868 dsdt_line("}"); 1869 dsdt_unindent(2); 1870 } 1871 #endif 1872 1873 dsdt_indent(2); 1874 for (slot = 0; slot < MAXSLOTS; slot++) { 1875 si = &bi->slotinfo[slot]; 1876 for (func = 0; func < MAXFUNCS; func++) { 1877 pi = si->si_funcs[func].fi_devi; 1878 if (pi != NULL && pi->pi_d->pe_write_dsdt != NULL) 1879 pi->pi_d->pe_write_dsdt(pi); 1880 } 1881 } 1882 dsdt_unindent(2); 1883 #ifdef __amd64__ 1884 done: 1885 #endif 1886 dsdt_line(" }"); 1887 } 1888 1889 void 1890 pci_write_dsdt(void) 1891 { 1892 int bus; 1893 1894 dsdt_indent(1); 1895 dsdt_line("Name (PICM, 0x00)"); 1896 dsdt_line("Method (_PIC, 1, NotSerialized)"); 1897 dsdt_line("{"); 1898 dsdt_line(" Store (Arg0, PICM)"); 1899 dsdt_line("}"); 1900 dsdt_line(""); 1901 dsdt_line("Scope (_SB)"); 1902 dsdt_line("{"); 1903 for (bus = 0; bus < MAXBUSES; bus++) 1904 pci_bus_write_dsdt(bus); 1905 dsdt_line("}"); 1906 dsdt_unindent(1); 1907 } 1908 1909 int 1910 pci_bus_configured(int bus) 1911 { 1912 assert(bus >= 0 && bus < MAXBUSES); 1913 return (pci_businfo[bus] != NULL); 1914 } 1915 1916 int 1917 pci_msi_enabled(struct pci_devinst *pi) 1918 { 1919 return (pi->pi_msi.enabled); 1920 } 1921 1922 int 1923 pci_msi_maxmsgnum(struct pci_devinst *pi) 1924 { 1925 if (pi->pi_msi.enabled) 1926 return (pi->pi_msi.maxmsgnum); 1927 else 1928 return (0); 1929 } 1930 1931 int 1932 pci_msix_enabled(struct pci_devinst *pi) 1933 { 1934 1935 return (pi->pi_msix.enabled && !pi->pi_msi.enabled); 1936 } 1937 1938 void 1939 pci_generate_msix(struct pci_devinst *pi, int index) 1940 { 1941 struct msix_table_entry *mte; 1942 1943 if (!pci_msix_enabled(pi)) 1944 return; 1945 1946 if (pi->pi_msix.function_mask) 1947 return; 1948 1949 if (index >= pi->pi_msix.table_count) 1950 return; 1951 1952 mte = &pi->pi_msix.table[index]; 1953 if ((mte->vector_control & PCIM_MSIX_VCTRL_MASK) == 0) { 1954 /* XXX Set PBA bit if interrupt is disabled */ 1955 vm_lapic_msi(pi->pi_vmctx, mte->addr, mte->msg_data); 1956 } 1957 } 1958 1959 void 1960 pci_generate_msi(struct pci_devinst *pi, int index) 1961 { 1962 1963 if (pci_msi_enabled(pi) && index < pci_msi_maxmsgnum(pi)) { 1964 vm_lapic_msi(pi->pi_vmctx, pi->pi_msi.addr, 1965 pi->pi_msi.msg_data + index); 1966 } 1967 } 1968 1969 #ifdef __amd64__ 1970 static bool 1971 pci_lintr_permitted(struct pci_devinst *pi) 1972 { 1973 uint16_t cmd; 1974 1975 cmd = pci_get_cfgdata16(pi, PCIR_COMMAND); 1976 return (!(pi->pi_msi.enabled || pi->pi_msix.enabled || 1977 (cmd & PCIM_CMD_INTxDIS))); 1978 } 1979 1980 void 1981 pci_lintr_request(struct pci_devinst *pi) 1982 { 1983 struct businfo *bi; 1984 struct slotinfo *si; 1985 int bestpin, bestcount, pin; 1986 1987 bi = pci_businfo[pi->pi_bus]; 1988 assert(bi != NULL); 1989 1990 /* 1991 * Just allocate a pin from our slot. The pin will be 1992 * assigned IRQs later when interrupts are routed. 1993 */ 1994 si = &bi->slotinfo[pi->pi_slot]; 1995 bestpin = 0; 1996 bestcount = si->si_intpins[0].ii_count; 1997 for (pin = 1; pin < 4; pin++) { 1998 if (si->si_intpins[pin].ii_count < bestcount) { 1999 bestpin = pin; 2000 bestcount = si->si_intpins[pin].ii_count; 2001 } 2002 } 2003 2004 si->si_intpins[bestpin].ii_count++; 2005 pi->pi_lintr.pin = bestpin + 1; 2006 pci_set_cfgdata8(pi, PCIR_INTPIN, bestpin + 1); 2007 } 2008 2009 static void 2010 pci_lintr_route(struct pci_devinst *pi) 2011 { 2012 struct businfo *bi; 2013 struct intxinfo *ii; 2014 2015 if (pi->pi_lintr.pin == 0) 2016 return; 2017 2018 bi = pci_businfo[pi->pi_bus]; 2019 assert(bi != NULL); 2020 ii = &bi->slotinfo[pi->pi_slot].si_intpins[pi->pi_lintr.pin - 1]; 2021 2022 /* 2023 * Attempt to allocate an I/O APIC pin for this intpin if one 2024 * is not yet assigned. 2025 */ 2026 if (ii->ii_ioapic_irq == 0) 2027 ii->ii_ioapic_irq = ioapic_pci_alloc_irq(pi); 2028 assert(ii->ii_ioapic_irq > 0); 2029 2030 /* 2031 * Attempt to allocate a PIRQ pin for this intpin if one is 2032 * not yet assigned. 2033 */ 2034 if (ii->ii_pirq_pin == 0) 2035 ii->ii_pirq_pin = pirq_alloc_pin(pi); 2036 assert(ii->ii_pirq_pin > 0); 2037 2038 pi->pi_lintr.ioapic_irq = ii->ii_ioapic_irq; 2039 pi->pi_lintr.pirq_pin = ii->ii_pirq_pin; 2040 pci_set_cfgdata8(pi, PCIR_INTLINE, pirq_irq(ii->ii_pirq_pin)); 2041 } 2042 2043 void 2044 pci_lintr_assert(struct pci_devinst *pi) 2045 { 2046 2047 assert(pi->pi_lintr.pin > 0); 2048 2049 pthread_mutex_lock(&pi->pi_lintr.lock); 2050 if (pi->pi_lintr.state == IDLE) { 2051 if (pci_lintr_permitted(pi)) { 2052 pi->pi_lintr.state = ASSERTED; 2053 pci_irq_assert(pi); 2054 } else 2055 pi->pi_lintr.state = PENDING; 2056 } 2057 pthread_mutex_unlock(&pi->pi_lintr.lock); 2058 } 2059 2060 void 2061 pci_lintr_deassert(struct pci_devinst *pi) 2062 { 2063 2064 assert(pi->pi_lintr.pin > 0); 2065 2066 pthread_mutex_lock(&pi->pi_lintr.lock); 2067 if (pi->pi_lintr.state == ASSERTED) { 2068 pi->pi_lintr.state = IDLE; 2069 pci_irq_deassert(pi); 2070 } else if (pi->pi_lintr.state == PENDING) 2071 pi->pi_lintr.state = IDLE; 2072 pthread_mutex_unlock(&pi->pi_lintr.lock); 2073 } 2074 2075 static void 2076 pci_lintr_update(struct pci_devinst *pi) 2077 { 2078 2079 pthread_mutex_lock(&pi->pi_lintr.lock); 2080 if (pi->pi_lintr.state == ASSERTED && !pci_lintr_permitted(pi)) { 2081 pci_irq_deassert(pi); 2082 pi->pi_lintr.state = PENDING; 2083 } else if (pi->pi_lintr.state == PENDING && pci_lintr_permitted(pi)) { 2084 pi->pi_lintr.state = ASSERTED; 2085 pci_irq_assert(pi); 2086 } 2087 pthread_mutex_unlock(&pi->pi_lintr.lock); 2088 } 2089 2090 int 2091 pci_count_lintr(int bus) 2092 { 2093 int count, slot, pin; 2094 struct slotinfo *slotinfo; 2095 2096 count = 0; 2097 if (pci_businfo[bus] != NULL) { 2098 for (slot = 0; slot < MAXSLOTS; slot++) { 2099 slotinfo = &pci_businfo[bus]->slotinfo[slot]; 2100 for (pin = 0; pin < 4; pin++) { 2101 if (slotinfo->si_intpins[pin].ii_count != 0) 2102 count++; 2103 } 2104 } 2105 } 2106 return (count); 2107 } 2108 2109 void 2110 pci_walk_lintr(int bus, pci_lintr_cb cb, void *arg) 2111 { 2112 struct businfo *bi; 2113 struct slotinfo *si; 2114 struct intxinfo *ii; 2115 int slot, pin; 2116 2117 if ((bi = pci_businfo[bus]) == NULL) 2118 return; 2119 2120 for (slot = 0; slot < MAXSLOTS; slot++) { 2121 si = &bi->slotinfo[slot]; 2122 for (pin = 0; pin < 4; pin++) { 2123 ii = &si->si_intpins[pin]; 2124 if (ii->ii_count != 0) 2125 cb(bus, slot, pin + 1, ii->ii_pirq_pin, 2126 ii->ii_ioapic_irq, arg); 2127 } 2128 } 2129 } 2130 #endif /* __amd64__ */ 2131 2132 /* 2133 * Return 1 if the emulated device in 'slot' is a multi-function device. 2134 * Return 0 otherwise. 2135 */ 2136 static int 2137 pci_emul_is_mfdev(int bus, int slot) 2138 { 2139 struct businfo *bi; 2140 struct slotinfo *si; 2141 int f, numfuncs; 2142 2143 numfuncs = 0; 2144 if ((bi = pci_businfo[bus]) != NULL) { 2145 si = &bi->slotinfo[slot]; 2146 for (f = 0; f < MAXFUNCS; f++) { 2147 if (si->si_funcs[f].fi_devi != NULL) { 2148 numfuncs++; 2149 } 2150 } 2151 } 2152 return (numfuncs > 1); 2153 } 2154 2155 /* 2156 * Ensure that the PCIM_MFDEV bit is properly set (or unset) depending on 2157 * whether or not is a multi-function being emulated in the pci 'slot'. 2158 */ 2159 static void 2160 pci_emul_hdrtype_fixup(int bus, int slot, int off, int bytes, uint32_t *rv) 2161 { 2162 int mfdev; 2163 2164 if (off <= PCIR_HDRTYPE && off + bytes > PCIR_HDRTYPE) { 2165 mfdev = pci_emul_is_mfdev(bus, slot); 2166 switch (bytes) { 2167 case 1: 2168 case 2: 2169 *rv &= ~PCIM_MFDEV; 2170 if (mfdev) { 2171 *rv |= PCIM_MFDEV; 2172 } 2173 break; 2174 case 4: 2175 *rv &= ~(PCIM_MFDEV << 16); 2176 if (mfdev) { 2177 *rv |= (PCIM_MFDEV << 16); 2178 } 2179 break; 2180 } 2181 } 2182 } 2183 2184 /* 2185 * Update device state in response to changes to the PCI command 2186 * register. 2187 */ 2188 void 2189 pci_emul_cmd_changed(struct pci_devinst *pi, uint16_t old) 2190 { 2191 int i; 2192 uint16_t changed, new; 2193 2194 new = pci_get_cfgdata16(pi, PCIR_COMMAND); 2195 changed = old ^ new; 2196 2197 /* 2198 * If the MMIO or I/O address space decoding has changed then 2199 * register/unregister all BARs that decode that address space. 2200 */ 2201 for (i = 0; i <= PCI_BARMAX_WITH_ROM; i++) { 2202 switch (pi->pi_bar[i].type) { 2203 case PCIBAR_NONE: 2204 case PCIBAR_MEMHI64: 2205 break; 2206 case PCIBAR_IO: 2207 /* I/O address space decoding changed? */ 2208 if (changed & PCIM_CMD_PORTEN) { 2209 if (new & PCIM_CMD_PORTEN) 2210 register_bar(pi, i); 2211 else 2212 unregister_bar(pi, i); 2213 } 2214 break; 2215 case PCIBAR_ROM: 2216 /* skip (un-)register of ROM if it disabled */ 2217 if (!romen(pi)) 2218 break; 2219 /* fallthrough */ 2220 case PCIBAR_MEM32: 2221 case PCIBAR_MEM64: 2222 /* MMIO address space decoding changed? */ 2223 if (changed & PCIM_CMD_MEMEN) { 2224 if (new & PCIM_CMD_MEMEN) 2225 register_bar(pi, i); 2226 else 2227 unregister_bar(pi, i); 2228 } 2229 break; 2230 default: 2231 assert(0); 2232 } 2233 } 2234 2235 #ifdef __amd64__ 2236 /* 2237 * If INTx has been unmasked and is pending, assert the 2238 * interrupt. 2239 */ 2240 pci_lintr_update(pi); 2241 #endif 2242 } 2243 2244 static void 2245 pci_emul_cmdsts_write(struct pci_devinst *pi, int coff, uint32_t new, int bytes) 2246 { 2247 int rshift; 2248 uint32_t cmd, old, readonly; 2249 2250 cmd = pci_get_cfgdata16(pi, PCIR_COMMAND); /* stash old value */ 2251 2252 /* 2253 * From PCI Local Bus Specification 3.0 sections 6.2.2 and 6.2.3. 2254 * 2255 * XXX Bits 8, 11, 12, 13, 14 and 15 in the status register are 2256 * 'write 1 to clear'. However these bits are not set to '1' by 2257 * any device emulation so it is simpler to treat them as readonly. 2258 */ 2259 rshift = (coff & 0x3) * 8; 2260 readonly = 0xFFFFF880 >> rshift; 2261 2262 old = CFGREAD(pi, coff, bytes); 2263 new &= ~readonly; 2264 new |= (old & readonly); 2265 CFGWRITE(pi, coff, new, bytes); /* update config */ 2266 2267 pci_emul_cmd_changed(pi, cmd); 2268 } 2269 2270 static void 2271 pci_cfgrw(int in, int bus, int slot, int func, int coff, int bytes, 2272 uint32_t *valp) 2273 { 2274 struct businfo *bi; 2275 struct slotinfo *si; 2276 struct pci_devinst *pi; 2277 struct pci_devemu *pe; 2278 int idx, needcfg; 2279 uint64_t addr, bar, mask; 2280 2281 if ((bi = pci_businfo[bus]) != NULL) { 2282 si = &bi->slotinfo[slot]; 2283 pi = si->si_funcs[func].fi_devi; 2284 } else 2285 pi = NULL; 2286 2287 /* 2288 * Just return if there is no device at this slot:func or if the 2289 * the guest is doing an un-aligned access. 2290 */ 2291 if (pi == NULL || (bytes != 1 && bytes != 2 && bytes != 4) || 2292 (coff & (bytes - 1)) != 0) { 2293 if (in) 2294 *valp = 0xffffffff; 2295 return; 2296 } 2297 2298 /* 2299 * Ignore all writes beyond the standard config space and return all 2300 * ones on reads. 2301 */ 2302 if (coff >= PCI_REGMAX + 1) { 2303 if (in) { 2304 *valp = 0xffffffff; 2305 /* 2306 * Extended capabilities begin at offset 256 in config 2307 * space. Absence of extended capabilities is signaled 2308 * with all 0s in the extended capability header at 2309 * offset 256. 2310 */ 2311 if (coff <= PCI_REGMAX + 4) 2312 *valp = 0x00000000; 2313 } 2314 return; 2315 } 2316 2317 pe = pi->pi_d; 2318 2319 /* 2320 * Config read 2321 */ 2322 if (in) { 2323 /* Let the device emulation override the default handler */ 2324 if (pe->pe_cfgread != NULL) { 2325 needcfg = pe->pe_cfgread(pi, coff, bytes, valp); 2326 } else { 2327 needcfg = 1; 2328 } 2329 2330 if (needcfg) 2331 *valp = CFGREAD(pi, coff, bytes); 2332 2333 pci_emul_hdrtype_fixup(bus, slot, coff, bytes, valp); 2334 } else { 2335 /* Let the device emulation override the default handler */ 2336 if (pe->pe_cfgwrite != NULL && 2337 (*pe->pe_cfgwrite)(pi, coff, bytes, *valp) == 0) 2338 return; 2339 2340 /* 2341 * Special handling for write to BAR and ROM registers 2342 */ 2343 if (is_pcir_bar(coff) || is_pcir_bios(coff)) { 2344 /* 2345 * Ignore writes to BAR registers that are not 2346 * 4-byte aligned. 2347 */ 2348 if (bytes != 4 || (coff & 0x3) != 0) 2349 return; 2350 2351 if (is_pcir_bar(coff)) { 2352 idx = (coff - PCIR_BAR(0)) / 4; 2353 } else if (is_pcir_bios(coff)) { 2354 idx = PCI_ROM_IDX; 2355 } else { 2356 errx(4, "%s: invalid BAR offset %d", __func__, 2357 coff); 2358 } 2359 2360 mask = ~(pi->pi_bar[idx].size - 1); 2361 switch (pi->pi_bar[idx].type) { 2362 case PCIBAR_NONE: 2363 pi->pi_bar[idx].addr = bar = 0; 2364 break; 2365 case PCIBAR_IO: 2366 addr = *valp & mask; 2367 #if defined(PCI_EMUL_IOMASK) 2368 addr &= PCI_EMUL_IOMASK; 2369 #endif 2370 bar = addr | pi->pi_bar[idx].lobits; 2371 /* 2372 * Register the new BAR value for interception 2373 */ 2374 if (addr != pi->pi_bar[idx].addr) { 2375 update_bar_address(pi, addr, idx, 2376 PCIBAR_IO); 2377 } 2378 break; 2379 case PCIBAR_MEM32: 2380 addr = bar = *valp & mask; 2381 bar |= pi->pi_bar[idx].lobits; 2382 if (addr != pi->pi_bar[idx].addr) { 2383 update_bar_address(pi, addr, idx, 2384 PCIBAR_MEM32); 2385 } 2386 break; 2387 case PCIBAR_MEM64: 2388 addr = bar = *valp & mask; 2389 bar |= pi->pi_bar[idx].lobits; 2390 if (addr != (uint32_t)pi->pi_bar[idx].addr) { 2391 update_bar_address(pi, addr, idx, 2392 PCIBAR_MEM64); 2393 } 2394 break; 2395 case PCIBAR_MEMHI64: 2396 mask = ~(pi->pi_bar[idx - 1].size - 1); 2397 addr = ((uint64_t)*valp << 32) & mask; 2398 bar = addr >> 32; 2399 if (bar != pi->pi_bar[idx - 1].addr >> 32) { 2400 update_bar_address(pi, addr, idx - 1, 2401 PCIBAR_MEMHI64); 2402 } 2403 break; 2404 case PCIBAR_ROM: 2405 addr = bar = *valp & mask; 2406 if (memen(pi) && romen(pi)) { 2407 unregister_bar(pi, idx); 2408 } 2409 pi->pi_bar[idx].addr = addr; 2410 pi->pi_bar[idx].lobits = *valp & 2411 PCIM_BIOS_ENABLE; 2412 /* romen could have changed it value */ 2413 if (memen(pi) && romen(pi)) { 2414 register_bar(pi, idx); 2415 } 2416 bar |= pi->pi_bar[idx].lobits; 2417 break; 2418 default: 2419 assert(0); 2420 } 2421 pci_set_cfgdata32(pi, coff, bar); 2422 2423 } else if (pci_emul_iscap(pi, coff)) { 2424 pci_emul_capwrite(pi, coff, bytes, *valp, 0, 0); 2425 } else if (coff >= PCIR_COMMAND && coff < PCIR_REVID) { 2426 pci_emul_cmdsts_write(pi, coff, *valp, bytes); 2427 } else { 2428 CFGWRITE(pi, coff, *valp, bytes); 2429 } 2430 } 2431 } 2432 2433 #ifdef __amd64__ 2434 static int cfgenable, cfgbus, cfgslot, cfgfunc, cfgoff; 2435 2436 static int 2437 pci_emul_cfgaddr(struct vmctx *ctx __unused, int in, 2438 int port __unused, int bytes, uint32_t *eax, void *arg __unused) 2439 { 2440 uint32_t x; 2441 2442 if (bytes != 4) { 2443 if (in) 2444 *eax = (bytes == 2) ? 0xffff : 0xff; 2445 return (0); 2446 } 2447 2448 if (in) { 2449 x = (cfgbus << 16) | (cfgslot << 11) | (cfgfunc << 8) | cfgoff; 2450 if (cfgenable) 2451 x |= CONF1_ENABLE; 2452 *eax = x; 2453 } else { 2454 x = *eax; 2455 cfgenable = (x & CONF1_ENABLE) == CONF1_ENABLE; 2456 cfgoff = (x & PCI_REGMAX) & ~0x03; 2457 cfgfunc = (x >> 8) & PCI_FUNCMAX; 2458 cfgslot = (x >> 11) & PCI_SLOTMAX; 2459 cfgbus = (x >> 16) & PCI_BUSMAX; 2460 } 2461 2462 return (0); 2463 } 2464 INOUT_PORT(pci_cfgaddr, CONF1_ADDR_PORT, IOPORT_F_INOUT, pci_emul_cfgaddr); 2465 2466 static int 2467 pci_emul_cfgdata(struct vmctx *ctx __unused, int in, int port, 2468 int bytes, uint32_t *eax, void *arg __unused) 2469 { 2470 int coff; 2471 2472 assert(bytes == 1 || bytes == 2 || bytes == 4); 2473 2474 coff = cfgoff + (port - CONF1_DATA_PORT); 2475 if (cfgenable) { 2476 pci_cfgrw(in, cfgbus, cfgslot, cfgfunc, coff, bytes, eax); 2477 } else { 2478 /* Ignore accesses to cfgdata if not enabled by cfgaddr */ 2479 if (in) 2480 *eax = 0xffffffff; 2481 } 2482 return (0); 2483 } 2484 2485 INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+0, IOPORT_F_INOUT, pci_emul_cfgdata); 2486 INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+1, IOPORT_F_INOUT, pci_emul_cfgdata); 2487 INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+2, IOPORT_F_INOUT, pci_emul_cfgdata); 2488 INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+3, IOPORT_F_INOUT, pci_emul_cfgdata); 2489 #endif 2490 2491 #ifdef BHYVE_SNAPSHOT 2492 /* 2493 * Saves/restores PCI device emulated state. Returns 0 on success. 2494 */ 2495 static int 2496 pci_snapshot_pci_dev(struct vm_snapshot_meta *meta) 2497 { 2498 struct pci_devinst *pi; 2499 int i; 2500 int ret; 2501 2502 pi = meta->dev_data; 2503 2504 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msi.enabled, meta, ret, done); 2505 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msi.addr, meta, ret, done); 2506 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msi.msg_data, meta, ret, done); 2507 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msi.maxmsgnum, meta, ret, done); 2508 2509 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.enabled, meta, ret, done); 2510 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.table_bar, meta, ret, done); 2511 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.pba_bar, meta, ret, done); 2512 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.table_offset, meta, ret, done); 2513 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.table_count, meta, ret, done); 2514 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.pba_offset, meta, ret, done); 2515 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.pba_size, meta, ret, done); 2516 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.function_mask, meta, ret, done); 2517 2518 SNAPSHOT_BUF_OR_LEAVE(pi->pi_cfgdata, sizeof(pi->pi_cfgdata), 2519 meta, ret, done); 2520 2521 for (i = 0; i < (int)nitems(pi->pi_bar); i++) { 2522 SNAPSHOT_VAR_OR_LEAVE(pi->pi_bar[i].type, meta, ret, done); 2523 SNAPSHOT_VAR_OR_LEAVE(pi->pi_bar[i].size, meta, ret, done); 2524 SNAPSHOT_VAR_OR_LEAVE(pi->pi_bar[i].addr, meta, ret, done); 2525 } 2526 2527 /* Restore MSI-X table. */ 2528 for (i = 0; i < pi->pi_msix.table_count; i++) { 2529 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.table[i].addr, 2530 meta, ret, done); 2531 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.table[i].msg_data, 2532 meta, ret, done); 2533 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.table[i].vector_control, 2534 meta, ret, done); 2535 } 2536 2537 done: 2538 return (ret); 2539 } 2540 2541 int 2542 pci_snapshot(struct vm_snapshot_meta *meta) 2543 { 2544 struct pci_devemu *pde; 2545 struct pci_devinst *pdi; 2546 int ret; 2547 2548 assert(meta->dev_name != NULL); 2549 2550 pdi = meta->dev_data; 2551 pde = pdi->pi_d; 2552 2553 if (pde->pe_snapshot == NULL) 2554 return (ENOTSUP); 2555 2556 ret = pci_snapshot_pci_dev(meta); 2557 if (ret == 0) 2558 ret = (*pde->pe_snapshot)(meta); 2559 2560 return (ret); 2561 } 2562 2563 int 2564 pci_pause(struct pci_devinst *pdi) 2565 { 2566 struct pci_devemu *pde = pdi->pi_d; 2567 2568 if (pde->pe_pause == NULL) { 2569 /* The pause/resume functionality is optional. */ 2570 return (0); 2571 } 2572 2573 return (*pde->pe_pause)(pdi); 2574 } 2575 2576 int 2577 pci_resume(struct pci_devinst *pdi) 2578 { 2579 struct pci_devemu *pde = pdi->pi_d; 2580 2581 if (pde->pe_resume == NULL) { 2582 /* The pause/resume functionality is optional. */ 2583 return (0); 2584 } 2585 2586 return (*pde->pe_resume)(pdi); 2587 } 2588 #endif 2589 2590 #define PCI_EMUL_TEST 2591 #ifdef PCI_EMUL_TEST 2592 /* 2593 * Define a dummy test device 2594 */ 2595 #define DIOSZ 8 2596 #define DMEMSZ 4096 2597 struct pci_emul_dsoftc { 2598 uint8_t ioregs[DIOSZ]; 2599 uint8_t memregs[2][DMEMSZ]; 2600 }; 2601 2602 #define PCI_EMUL_MSI_MSGS 4 2603 #define PCI_EMUL_MSIX_MSGS 16 2604 2605 static int 2606 pci_emul_dinit(struct pci_devinst *pi, nvlist_t *nvl __unused) 2607 { 2608 int error; 2609 struct pci_emul_dsoftc *sc; 2610 2611 sc = calloc(1, sizeof(struct pci_emul_dsoftc)); 2612 2613 pi->pi_arg = sc; 2614 2615 pci_set_cfgdata16(pi, PCIR_DEVICE, 0x0001); 2616 pci_set_cfgdata16(pi, PCIR_VENDOR, 0x10DD); 2617 pci_set_cfgdata8(pi, PCIR_CLASS, 0x02); 2618 2619 error = pci_emul_add_msicap(pi, PCI_EMUL_MSI_MSGS); 2620 assert(error == 0); 2621 2622 error = pci_emul_alloc_bar(pi, 0, PCIBAR_IO, DIOSZ); 2623 assert(error == 0); 2624 2625 error = pci_emul_alloc_bar(pi, 1, PCIBAR_MEM32, DMEMSZ); 2626 assert(error == 0); 2627 2628 error = pci_emul_alloc_bar(pi, 2, PCIBAR_MEM32, DMEMSZ); 2629 assert(error == 0); 2630 2631 return (0); 2632 } 2633 2634 static void 2635 pci_emul_diow(struct pci_devinst *pi, int baridx, uint64_t offset, int size, 2636 uint64_t value) 2637 { 2638 int i; 2639 struct pci_emul_dsoftc *sc = pi->pi_arg; 2640 2641 if (baridx == 0) { 2642 if (offset + size > DIOSZ) { 2643 printf("diow: iow too large, offset %ld size %d\n", 2644 offset, size); 2645 return; 2646 } 2647 2648 if (size == 1) { 2649 sc->ioregs[offset] = value & 0xff; 2650 } else if (size == 2) { 2651 *(uint16_t *)&sc->ioregs[offset] = value & 0xffff; 2652 } else if (size == 4) { 2653 *(uint32_t *)&sc->ioregs[offset] = value; 2654 } else { 2655 printf("diow: iow unknown size %d\n", size); 2656 } 2657 2658 /* 2659 * Special magic value to generate an interrupt 2660 */ 2661 if (offset == 4 && size == 4 && pci_msi_enabled(pi)) 2662 pci_generate_msi(pi, value % pci_msi_maxmsgnum(pi)); 2663 2664 if (value == 0xabcdef) { 2665 for (i = 0; i < pci_msi_maxmsgnum(pi); i++) 2666 pci_generate_msi(pi, i); 2667 } 2668 } 2669 2670 if (baridx == 1 || baridx == 2) { 2671 if (offset + size > DMEMSZ) { 2672 printf("diow: memw too large, offset %ld size %d\n", 2673 offset, size); 2674 return; 2675 } 2676 2677 i = baridx - 1; /* 'memregs' index */ 2678 2679 if (size == 1) { 2680 sc->memregs[i][offset] = value; 2681 } else if (size == 2) { 2682 *(uint16_t *)&sc->memregs[i][offset] = value; 2683 } else if (size == 4) { 2684 *(uint32_t *)&sc->memregs[i][offset] = value; 2685 } else if (size == 8) { 2686 *(uint64_t *)&sc->memregs[i][offset] = value; 2687 } else { 2688 printf("diow: memw unknown size %d\n", size); 2689 } 2690 2691 /* 2692 * magic interrupt ?? 2693 */ 2694 } 2695 2696 if (baridx > 2 || baridx < 0) { 2697 printf("diow: unknown bar idx %d\n", baridx); 2698 } 2699 } 2700 2701 static uint64_t 2702 pci_emul_dior(struct pci_devinst *pi, int baridx, uint64_t offset, int size) 2703 { 2704 struct pci_emul_dsoftc *sc = pi->pi_arg; 2705 uint32_t value; 2706 int i; 2707 2708 if (baridx == 0) { 2709 if (offset + size > DIOSZ) { 2710 printf("dior: ior too large, offset %ld size %d\n", 2711 offset, size); 2712 return (0); 2713 } 2714 2715 value = 0; 2716 if (size == 1) { 2717 value = sc->ioregs[offset]; 2718 } else if (size == 2) { 2719 value = *(uint16_t *) &sc->ioregs[offset]; 2720 } else if (size == 4) { 2721 value = *(uint32_t *) &sc->ioregs[offset]; 2722 } else { 2723 printf("dior: ior unknown size %d\n", size); 2724 } 2725 } 2726 2727 if (baridx == 1 || baridx == 2) { 2728 if (offset + size > DMEMSZ) { 2729 printf("dior: memr too large, offset %ld size %d\n", 2730 offset, size); 2731 return (0); 2732 } 2733 2734 i = baridx - 1; /* 'memregs' index */ 2735 2736 if (size == 1) { 2737 value = sc->memregs[i][offset]; 2738 } else if (size == 2) { 2739 value = *(uint16_t *) &sc->memregs[i][offset]; 2740 } else if (size == 4) { 2741 value = *(uint32_t *) &sc->memregs[i][offset]; 2742 } else if (size == 8) { 2743 value = *(uint64_t *) &sc->memregs[i][offset]; 2744 } else { 2745 printf("dior: ior unknown size %d\n", size); 2746 } 2747 } 2748 2749 2750 if (baridx > 2 || baridx < 0) { 2751 printf("dior: unknown bar idx %d\n", baridx); 2752 return (0); 2753 } 2754 2755 return (value); 2756 } 2757 2758 #ifdef BHYVE_SNAPSHOT 2759 struct pci_devinst * 2760 pci_next(const struct pci_devinst *cursor) 2761 { 2762 unsigned bus = 0, slot = 0, func = 0; 2763 struct businfo *bi; 2764 struct slotinfo *si; 2765 struct funcinfo *fi; 2766 2767 bus = cursor ? cursor->pi_bus : 0; 2768 slot = cursor ? cursor->pi_slot : 0; 2769 func = cursor ? (cursor->pi_func + 1) : 0; 2770 2771 for (; bus < MAXBUSES; bus++) { 2772 if ((bi = pci_businfo[bus]) == NULL) 2773 continue; 2774 2775 if (slot >= MAXSLOTS) 2776 slot = 0; 2777 2778 for (; slot < MAXSLOTS; slot++) { 2779 si = &bi->slotinfo[slot]; 2780 if (func >= MAXFUNCS) 2781 func = 0; 2782 for (; func < MAXFUNCS; func++) { 2783 fi = &si->si_funcs[func]; 2784 if (fi->fi_devi == NULL) 2785 continue; 2786 2787 return (fi->fi_devi); 2788 } 2789 } 2790 } 2791 2792 return (NULL); 2793 } 2794 2795 static int 2796 pci_emul_snapshot(struct vm_snapshot_meta *meta __unused) 2797 { 2798 return (0); 2799 } 2800 #endif 2801 2802 static const struct pci_devemu pci_dummy = { 2803 .pe_emu = "dummy", 2804 .pe_init = pci_emul_dinit, 2805 .pe_barwrite = pci_emul_diow, 2806 .pe_barread = pci_emul_dior, 2807 #ifdef BHYVE_SNAPSHOT 2808 .pe_snapshot = pci_emul_snapshot, 2809 #endif 2810 }; 2811 PCI_EMUL_SET(pci_dummy); 2812 2813 #endif /* PCI_EMUL_TEST */ 2814