1 /*- 2 * Copyright (c) 2011 NetApp, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 #include <sys/param.h> 33 #include <sys/linker_set.h> 34 #include <sys/errno.h> 35 36 #include <ctype.h> 37 #include <stdio.h> 38 #include <stdlib.h> 39 #include <string.h> 40 #include <strings.h> 41 #include <assert.h> 42 #include <stdbool.h> 43 44 #include <machine/vmm.h> 45 #include <vmmapi.h> 46 47 #include "bhyverun.h" 48 #include "inout.h" 49 #include "legacy_irq.h" 50 #include "mem.h" 51 #include "pci_emul.h" 52 53 #define CONF1_ADDR_PORT 0x0cf8 54 #define CONF1_DATA_PORT 0x0cfc 55 56 #define CONF1_ENABLE 0x80000000ul 57 58 #define CFGWRITE(pi,off,val,b) \ 59 do { \ 60 if ((b) == 1) { \ 61 pci_set_cfgdata8((pi),(off),(val)); \ 62 } else if ((b) == 2) { \ 63 pci_set_cfgdata16((pi),(off),(val)); \ 64 } else { \ 65 pci_set_cfgdata32((pi),(off),(val)); \ 66 } \ 67 } while (0) 68 69 #define MAXSLOTS (PCI_SLOTMAX + 1) 70 #define MAXFUNCS (PCI_FUNCMAX + 1) 71 72 static struct slotinfo { 73 char *si_name; 74 char *si_param; 75 struct pci_devinst *si_devi; 76 int si_legacy; 77 } pci_slotinfo[MAXSLOTS][MAXFUNCS]; 78 79 SET_DECLARE(pci_devemu_set, struct pci_devemu); 80 81 static uint64_t pci_emul_iobase; 82 static uint64_t pci_emul_membase32; 83 static uint64_t pci_emul_membase64; 84 85 #define PCI_EMUL_IOBASE 0x2000 86 #define PCI_EMUL_IOLIMIT 0x10000 87 88 #define PCI_EMUL_MEMLIMIT32 0xE0000000 /* 3.5GB */ 89 90 #define PCI_EMUL_MEMBASE64 0xD000000000UL 91 #define PCI_EMUL_MEMLIMIT64 0xFD00000000UL 92 93 static struct pci_devemu *pci_emul_finddev(char *name); 94 95 static int pci_emul_devices; 96 97 /* 98 * I/O access 99 */ 100 101 /* 102 * Slot options are in the form: 103 * 104 * <slot>[:<func>],<emul>[,<config>] 105 * 106 * slot is 0..31 107 * func is 0..7 108 * emul is a string describing the type of PCI device e.g. virtio-net 109 * config is an optional string, depending on the device, that can be 110 * used for configuration. 111 * Examples are: 112 * 1,virtio-net,tap0 113 * 3:0,dummy 114 */ 115 static void 116 pci_parse_slot_usage(char *aopt) 117 { 118 119 fprintf(stderr, "Invalid PCI slot info field \"%s\"\n", aopt); 120 } 121 122 int 123 pci_parse_slot(char *opt, int legacy) 124 { 125 char *slot, *func, *emul, *config; 126 char *str, *cpy; 127 int error, snum, fnum; 128 129 error = -1; 130 str = cpy = strdup(opt); 131 132 slot = strsep(&str, ","); 133 func = NULL; 134 if (strchr(slot, ':') != NULL) { 135 func = cpy; 136 (void) strsep(&func, ":"); 137 } 138 139 emul = strsep(&str, ","); 140 config = str; 141 142 if (emul == NULL) { 143 pci_parse_slot_usage(opt); 144 goto done; 145 } 146 147 snum = atoi(slot); 148 fnum = func ? atoi(func) : 0; 149 150 if (snum < 0 || snum >= MAXSLOTS || fnum < 0 || fnum >= MAXFUNCS) { 151 pci_parse_slot_usage(opt); 152 goto done; 153 } 154 155 if (pci_slotinfo[snum][fnum].si_name != NULL) { 156 fprintf(stderr, "pci slot %d:%d already occupied!\n", 157 snum, fnum); 158 goto done; 159 } 160 161 if (pci_emul_finddev(emul) == NULL) { 162 fprintf(stderr, "pci slot %d:%d: unknown device \"%s\"\n", 163 snum, fnum, emul); 164 goto done; 165 } 166 167 error = 0; 168 pci_slotinfo[snum][fnum].si_name = emul; 169 pci_slotinfo[snum][fnum].si_param = config; 170 pci_slotinfo[snum][fnum].si_legacy = legacy; 171 172 done: 173 if (error) 174 free(cpy); 175 176 return (error); 177 } 178 179 static int 180 pci_valid_pba_offset(struct pci_devinst *pi, uint64_t offset) 181 { 182 183 if (offset < pi->pi_msix.pba_offset) 184 return (0); 185 186 if (offset >= pi->pi_msix.pba_offset + pi->pi_msix.pba_size) { 187 return (0); 188 } 189 190 return (1); 191 } 192 193 int 194 pci_emul_msix_twrite(struct pci_devinst *pi, uint64_t offset, int size, 195 uint64_t value) 196 { 197 int msix_entry_offset; 198 int tab_index; 199 char *dest; 200 201 /* support only 4 or 8 byte writes */ 202 if (size != 4 && size != 8) 203 return (-1); 204 205 /* 206 * Return if table index is beyond what device supports 207 */ 208 tab_index = offset / MSIX_TABLE_ENTRY_SIZE; 209 if (tab_index >= pi->pi_msix.table_count) 210 return (-1); 211 212 msix_entry_offset = offset % MSIX_TABLE_ENTRY_SIZE; 213 214 /* support only aligned writes */ 215 if ((msix_entry_offset % size) != 0) 216 return (-1); 217 218 dest = (char *)(pi->pi_msix.table + tab_index); 219 dest += msix_entry_offset; 220 221 if (size == 4) 222 *((uint32_t *)dest) = value; 223 else 224 *((uint64_t *)dest) = value; 225 226 return (0); 227 } 228 229 uint64_t 230 pci_emul_msix_tread(struct pci_devinst *pi, uint64_t offset, int size) 231 { 232 char *dest; 233 int msix_entry_offset; 234 int tab_index; 235 uint64_t retval = ~0; 236 237 /* 238 * The PCI standard only allows 4 and 8 byte accesses to the MSI-X 239 * table but we also allow 1 byte access to accomodate reads from 240 * ddb. 241 */ 242 if (size != 1 && size != 4 && size != 8) 243 return (retval); 244 245 msix_entry_offset = offset % MSIX_TABLE_ENTRY_SIZE; 246 247 /* support only aligned reads */ 248 if ((msix_entry_offset % size) != 0) { 249 return (retval); 250 } 251 252 tab_index = offset / MSIX_TABLE_ENTRY_SIZE; 253 254 if (tab_index < pi->pi_msix.table_count) { 255 /* valid MSI-X Table access */ 256 dest = (char *)(pi->pi_msix.table + tab_index); 257 dest += msix_entry_offset; 258 259 if (size == 1) 260 retval = *((uint8_t *)dest); 261 else if (size == 4) 262 retval = *((uint32_t *)dest); 263 else 264 retval = *((uint64_t *)dest); 265 } else if (pci_valid_pba_offset(pi, offset)) { 266 /* return 0 for PBA access */ 267 retval = 0; 268 } 269 270 return (retval); 271 } 272 273 int 274 pci_msix_table_bar(struct pci_devinst *pi) 275 { 276 277 if (pi->pi_msix.table != NULL) 278 return (pi->pi_msix.table_bar); 279 else 280 return (-1); 281 } 282 283 int 284 pci_msix_pba_bar(struct pci_devinst *pi) 285 { 286 287 if (pi->pi_msix.table != NULL) 288 return (pi->pi_msix.pba_bar); 289 else 290 return (-1); 291 } 292 293 static int 294 pci_emul_io_handler(struct vmctx *ctx, int vcpu, int in, int port, int bytes, 295 uint32_t *eax, void *arg) 296 { 297 struct pci_devinst *pdi = arg; 298 struct pci_devemu *pe = pdi->pi_d; 299 uint64_t offset; 300 int i; 301 302 for (i = 0; i <= PCI_BARMAX; i++) { 303 if (pdi->pi_bar[i].type == PCIBAR_IO && 304 port >= pdi->pi_bar[i].addr && 305 port + bytes <= pdi->pi_bar[i].addr + pdi->pi_bar[i].size) { 306 offset = port - pdi->pi_bar[i].addr; 307 if (in) 308 *eax = (*pe->pe_barread)(ctx, vcpu, pdi, i, 309 offset, bytes); 310 else 311 (*pe->pe_barwrite)(ctx, vcpu, pdi, i, offset, 312 bytes, *eax); 313 return (0); 314 } 315 } 316 return (-1); 317 } 318 319 static int 320 pci_emul_mem_handler(struct vmctx *ctx, int vcpu, int dir, uint64_t addr, 321 int size, uint64_t *val, void *arg1, long arg2) 322 { 323 struct pci_devinst *pdi = arg1; 324 struct pci_devemu *pe = pdi->pi_d; 325 uint64_t offset; 326 int bidx = (int) arg2; 327 328 assert(bidx <= PCI_BARMAX); 329 assert(pdi->pi_bar[bidx].type == PCIBAR_MEM32 || 330 pdi->pi_bar[bidx].type == PCIBAR_MEM64); 331 assert(addr >= pdi->pi_bar[bidx].addr && 332 addr + size <= pdi->pi_bar[bidx].addr + pdi->pi_bar[bidx].size); 333 334 offset = addr - pdi->pi_bar[bidx].addr; 335 336 if (dir == MEM_F_WRITE) 337 (*pe->pe_barwrite)(ctx, vcpu, pdi, bidx, offset, size, *val); 338 else 339 *val = (*pe->pe_barread)(ctx, vcpu, pdi, bidx, offset, size); 340 341 return (0); 342 } 343 344 345 static int 346 pci_emul_alloc_resource(uint64_t *baseptr, uint64_t limit, uint64_t size, 347 uint64_t *addr) 348 { 349 uint64_t base; 350 351 assert((size & (size - 1)) == 0); /* must be a power of 2 */ 352 353 base = roundup2(*baseptr, size); 354 355 if (base + size <= limit) { 356 *addr = base; 357 *baseptr = base + size; 358 return (0); 359 } else 360 return (-1); 361 } 362 363 int 364 pci_emul_alloc_bar(struct pci_devinst *pdi, int idx, enum pcibar_type type, 365 uint64_t size) 366 { 367 368 return (pci_emul_alloc_pbar(pdi, idx, 0, type, size)); 369 } 370 371 /* 372 * Register (or unregister) the MMIO or I/O region associated with the BAR 373 * register 'idx' of an emulated pci device. 374 */ 375 static void 376 modify_bar_registration(struct pci_devinst *pi, int idx, int registration) 377 { 378 int error; 379 struct inout_port iop; 380 struct mem_range mr; 381 382 switch (pi->pi_bar[idx].type) { 383 case PCIBAR_IO: 384 bzero(&iop, sizeof(struct inout_port)); 385 iop.name = pi->pi_name; 386 iop.port = pi->pi_bar[idx].addr; 387 iop.size = pi->pi_bar[idx].size; 388 if (registration) { 389 iop.flags = IOPORT_F_INOUT; 390 iop.handler = pci_emul_io_handler; 391 iop.arg = pi; 392 error = register_inout(&iop); 393 } else 394 error = unregister_inout(&iop); 395 break; 396 case PCIBAR_MEM32: 397 case PCIBAR_MEM64: 398 bzero(&mr, sizeof(struct mem_range)); 399 mr.name = pi->pi_name; 400 mr.base = pi->pi_bar[idx].addr; 401 mr.size = pi->pi_bar[idx].size; 402 if (registration) { 403 mr.flags = MEM_F_RW; 404 mr.handler = pci_emul_mem_handler; 405 mr.arg1 = pi; 406 mr.arg2 = idx; 407 error = register_mem(&mr); 408 } else 409 error = unregister_mem(&mr); 410 break; 411 default: 412 error = EINVAL; 413 break; 414 } 415 assert(error == 0); 416 } 417 418 static void 419 unregister_bar(struct pci_devinst *pi, int idx) 420 { 421 422 modify_bar_registration(pi, idx, 0); 423 } 424 425 static void 426 register_bar(struct pci_devinst *pi, int idx) 427 { 428 429 modify_bar_registration(pi, idx, 1); 430 } 431 432 /* Are we decoding i/o port accesses for the emulated pci device? */ 433 static int 434 porten(struct pci_devinst *pi) 435 { 436 uint16_t cmd; 437 438 cmd = pci_get_cfgdata16(pi, PCIR_COMMAND); 439 440 return (cmd & PCIM_CMD_PORTEN); 441 } 442 443 /* Are we decoding memory accesses for the emulated pci device? */ 444 static int 445 memen(struct pci_devinst *pi) 446 { 447 uint16_t cmd; 448 449 cmd = pci_get_cfgdata16(pi, PCIR_COMMAND); 450 451 return (cmd & PCIM_CMD_MEMEN); 452 } 453 454 /* 455 * Update the MMIO or I/O address that is decoded by the BAR register. 456 * 457 * If the pci device has enabled the address space decoding then intercept 458 * the address range decoded by the BAR register. 459 */ 460 static void 461 update_bar_address(struct pci_devinst *pi, uint64_t addr, int idx, int type) 462 { 463 int decode; 464 465 if (pi->pi_bar[idx].type == PCIBAR_IO) 466 decode = porten(pi); 467 else 468 decode = memen(pi); 469 470 if (decode) 471 unregister_bar(pi, idx); 472 473 switch (type) { 474 case PCIBAR_IO: 475 case PCIBAR_MEM32: 476 pi->pi_bar[idx].addr = addr; 477 break; 478 case PCIBAR_MEM64: 479 pi->pi_bar[idx].addr &= ~0xffffffffUL; 480 pi->pi_bar[idx].addr |= addr; 481 break; 482 case PCIBAR_MEMHI64: 483 pi->pi_bar[idx].addr &= 0xffffffff; 484 pi->pi_bar[idx].addr |= addr; 485 break; 486 default: 487 assert(0); 488 } 489 490 if (decode) 491 register_bar(pi, idx); 492 } 493 494 int 495 pci_emul_alloc_pbar(struct pci_devinst *pdi, int idx, uint64_t hostbase, 496 enum pcibar_type type, uint64_t size) 497 { 498 int error; 499 uint64_t *baseptr, limit, addr, mask, lobits, bar; 500 501 assert(idx >= 0 && idx <= PCI_BARMAX); 502 503 if ((size & (size - 1)) != 0) 504 size = 1UL << flsl(size); /* round up to a power of 2 */ 505 506 /* Enforce minimum BAR sizes required by the PCI standard */ 507 if (type == PCIBAR_IO) { 508 if (size < 4) 509 size = 4; 510 } else { 511 if (size < 16) 512 size = 16; 513 } 514 515 switch (type) { 516 case PCIBAR_NONE: 517 baseptr = NULL; 518 addr = mask = lobits = 0; 519 break; 520 case PCIBAR_IO: 521 if (hostbase && 522 pci_slotinfo[pdi->pi_slot][pdi->pi_func].si_legacy) { 523 assert(hostbase < PCI_EMUL_IOBASE); 524 baseptr = &hostbase; 525 } else { 526 baseptr = &pci_emul_iobase; 527 } 528 limit = PCI_EMUL_IOLIMIT; 529 mask = PCIM_BAR_IO_BASE; 530 lobits = PCIM_BAR_IO_SPACE; 531 break; 532 case PCIBAR_MEM64: 533 /* 534 * XXX 535 * Some drivers do not work well if the 64-bit BAR is allocated 536 * above 4GB. Allow for this by allocating small requests under 537 * 4GB unless then allocation size is larger than some arbitrary 538 * number (32MB currently). 539 */ 540 if (size > 32 * 1024 * 1024) { 541 /* 542 * XXX special case for device requiring peer-peer DMA 543 */ 544 if (size == 0x100000000UL) 545 baseptr = &hostbase; 546 else 547 baseptr = &pci_emul_membase64; 548 limit = PCI_EMUL_MEMLIMIT64; 549 mask = PCIM_BAR_MEM_BASE; 550 lobits = PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_64 | 551 PCIM_BAR_MEM_PREFETCH; 552 break; 553 } else { 554 baseptr = &pci_emul_membase32; 555 limit = PCI_EMUL_MEMLIMIT32; 556 mask = PCIM_BAR_MEM_BASE; 557 lobits = PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_64; 558 } 559 break; 560 case PCIBAR_MEM32: 561 baseptr = &pci_emul_membase32; 562 limit = PCI_EMUL_MEMLIMIT32; 563 mask = PCIM_BAR_MEM_BASE; 564 lobits = PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_32; 565 break; 566 default: 567 printf("pci_emul_alloc_base: invalid bar type %d\n", type); 568 assert(0); 569 } 570 571 if (baseptr != NULL) { 572 error = pci_emul_alloc_resource(baseptr, limit, size, &addr); 573 if (error != 0) 574 return (error); 575 } 576 577 pdi->pi_bar[idx].type = type; 578 pdi->pi_bar[idx].addr = addr; 579 pdi->pi_bar[idx].size = size; 580 581 /* Initialize the BAR register in config space */ 582 bar = (addr & mask) | lobits; 583 pci_set_cfgdata32(pdi, PCIR_BAR(idx), bar); 584 585 if (type == PCIBAR_MEM64) { 586 assert(idx + 1 <= PCI_BARMAX); 587 pdi->pi_bar[idx + 1].type = PCIBAR_MEMHI64; 588 pci_set_cfgdata32(pdi, PCIR_BAR(idx + 1), bar >> 32); 589 } 590 591 register_bar(pdi, idx); 592 593 return (0); 594 } 595 596 #define CAP_START_OFFSET 0x40 597 static int 598 pci_emul_add_capability(struct pci_devinst *pi, u_char *capdata, int caplen) 599 { 600 int i, capoff, capid, reallen; 601 uint16_t sts; 602 603 static u_char endofcap[4] = { 604 PCIY_RESERVED, 0, 0, 0 605 }; 606 607 assert(caplen > 0 && capdata[0] != PCIY_RESERVED); 608 609 reallen = roundup2(caplen, 4); /* dword aligned */ 610 611 sts = pci_get_cfgdata16(pi, PCIR_STATUS); 612 if ((sts & PCIM_STATUS_CAPPRESENT) == 0) { 613 capoff = CAP_START_OFFSET; 614 pci_set_cfgdata8(pi, PCIR_CAP_PTR, capoff); 615 pci_set_cfgdata16(pi, PCIR_STATUS, sts|PCIM_STATUS_CAPPRESENT); 616 } else { 617 capoff = pci_get_cfgdata8(pi, PCIR_CAP_PTR); 618 while (1) { 619 assert((capoff & 0x3) == 0); 620 capid = pci_get_cfgdata8(pi, capoff); 621 if (capid == PCIY_RESERVED) 622 break; 623 capoff = pci_get_cfgdata8(pi, capoff + 1); 624 } 625 } 626 627 /* Check if we have enough space */ 628 if (capoff + reallen + sizeof(endofcap) > PCI_REGMAX + 1) 629 return (-1); 630 631 /* Copy the capability */ 632 for (i = 0; i < caplen; i++) 633 pci_set_cfgdata8(pi, capoff + i, capdata[i]); 634 635 /* Set the next capability pointer */ 636 pci_set_cfgdata8(pi, capoff + 1, capoff + reallen); 637 638 /* Copy of the reserved capability which serves as the end marker */ 639 for (i = 0; i < sizeof(endofcap); i++) 640 pci_set_cfgdata8(pi, capoff + reallen + i, endofcap[i]); 641 642 return (0); 643 } 644 645 static struct pci_devemu * 646 pci_emul_finddev(char *name) 647 { 648 struct pci_devemu **pdpp, *pdp; 649 650 SET_FOREACH(pdpp, pci_devemu_set) { 651 pdp = *pdpp; 652 if (!strcmp(pdp->pe_emu, name)) { 653 return (pdp); 654 } 655 } 656 657 return (NULL); 658 } 659 660 static int 661 pci_emul_init(struct vmctx *ctx, struct pci_devemu *pde, int slot, int func, 662 char *params) 663 { 664 struct pci_devinst *pdi; 665 int err; 666 667 pdi = malloc(sizeof(struct pci_devinst)); 668 bzero(pdi, sizeof(*pdi)); 669 670 pdi->pi_vmctx = ctx; 671 pdi->pi_bus = 0; 672 pdi->pi_slot = slot; 673 pdi->pi_func = func; 674 pdi->pi_lintr_pin = -1; 675 pdi->pi_d = pde; 676 snprintf(pdi->pi_name, PI_NAMESZ, "%s-pci-%d", pde->pe_emu, slot); 677 678 /* Disable legacy interrupts */ 679 pci_set_cfgdata8(pdi, PCIR_INTLINE, 255); 680 pci_set_cfgdata8(pdi, PCIR_INTPIN, 0); 681 682 pci_set_cfgdata8(pdi, PCIR_COMMAND, 683 PCIM_CMD_PORTEN | PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN); 684 685 err = (*pde->pe_init)(ctx, pdi, params); 686 if (err != 0) { 687 free(pdi); 688 } else { 689 pci_emul_devices++; 690 pci_slotinfo[slot][func].si_devi = pdi; 691 } 692 693 return (err); 694 } 695 696 void 697 pci_populate_msicap(struct msicap *msicap, int msgnum, int nextptr) 698 { 699 int mmc; 700 701 CTASSERT(sizeof(struct msicap) == 14); 702 703 /* Number of msi messages must be a power of 2 between 1 and 32 */ 704 assert((msgnum & (msgnum - 1)) == 0 && msgnum >= 1 && msgnum <= 32); 705 mmc = ffs(msgnum) - 1; 706 707 bzero(msicap, sizeof(struct msicap)); 708 msicap->capid = PCIY_MSI; 709 msicap->nextptr = nextptr; 710 msicap->msgctrl = PCIM_MSICTRL_64BIT | (mmc << 1); 711 } 712 713 int 714 pci_emul_add_msicap(struct pci_devinst *pi, int msgnum) 715 { 716 struct msicap msicap; 717 718 pci_populate_msicap(&msicap, msgnum, 0); 719 720 return (pci_emul_add_capability(pi, (u_char *)&msicap, sizeof(msicap))); 721 } 722 723 static void 724 pci_populate_msixcap(struct msixcap *msixcap, int msgnum, int barnum, 725 uint32_t msix_tab_size, int nextptr) 726 { 727 CTASSERT(sizeof(struct msixcap) == 12); 728 729 assert(msix_tab_size % 4096 == 0); 730 731 bzero(msixcap, sizeof(struct msixcap)); 732 msixcap->capid = PCIY_MSIX; 733 msixcap->nextptr = nextptr; 734 735 /* 736 * Message Control Register, all fields set to 737 * zero except for the Table Size. 738 * Note: Table size N is encoded as N-1 739 */ 740 msixcap->msgctrl = msgnum - 1; 741 742 /* 743 * MSI-X BAR setup: 744 * - MSI-X table start at offset 0 745 * - PBA table starts at a 4K aligned offset after the MSI-X table 746 */ 747 msixcap->table_info = barnum & PCIM_MSIX_BIR_MASK; 748 msixcap->pba_info = msix_tab_size | (barnum & PCIM_MSIX_BIR_MASK); 749 } 750 751 static void 752 pci_msix_table_init(struct pci_devinst *pi, int table_entries) 753 { 754 int i, table_size; 755 756 assert(table_entries > 0); 757 assert(table_entries <= MAX_MSIX_TABLE_ENTRIES); 758 759 table_size = table_entries * MSIX_TABLE_ENTRY_SIZE; 760 pi->pi_msix.table = malloc(table_size); 761 bzero(pi->pi_msix.table, table_size); 762 763 /* set mask bit of vector control register */ 764 for (i = 0; i < table_entries; i++) 765 pi->pi_msix.table[i].vector_control |= PCIM_MSIX_VCTRL_MASK; 766 } 767 768 int 769 pci_emul_add_msixcap(struct pci_devinst *pi, int msgnum, int barnum) 770 { 771 uint16_t pba_index; 772 uint32_t tab_size; 773 struct msixcap msixcap; 774 775 assert(msgnum >= 1 && msgnum <= MAX_MSIX_TABLE_ENTRIES); 776 assert(barnum >= 0 && barnum <= PCIR_MAX_BAR_0); 777 778 tab_size = msgnum * MSIX_TABLE_ENTRY_SIZE; 779 780 /* Align table size to nearest 4K */ 781 tab_size = roundup2(tab_size, 4096); 782 783 pi->pi_msix.table_bar = barnum; 784 pi->pi_msix.pba_bar = barnum; 785 pi->pi_msix.table_offset = 0; 786 pi->pi_msix.table_count = msgnum; 787 pi->pi_msix.pba_offset = tab_size; 788 789 /* calculate the MMIO size required for MSI-X PBA */ 790 pba_index = (msgnum - 1) / (PBA_TABLE_ENTRY_SIZE * 8); 791 pi->pi_msix.pba_size = (pba_index + 1) * PBA_TABLE_ENTRY_SIZE; 792 793 pci_msix_table_init(pi, msgnum); 794 795 pci_populate_msixcap(&msixcap, msgnum, barnum, tab_size, 0); 796 797 /* allocate memory for MSI-X Table and PBA */ 798 pci_emul_alloc_bar(pi, barnum, PCIBAR_MEM32, 799 tab_size + pi->pi_msix.pba_size); 800 801 return (pci_emul_add_capability(pi, (u_char *)&msixcap, 802 sizeof(msixcap))); 803 } 804 805 void 806 msixcap_cfgwrite(struct pci_devinst *pi, int capoff, int offset, 807 int bytes, uint32_t val) 808 { 809 uint16_t msgctrl, rwmask; 810 int off, table_bar; 811 812 off = offset - capoff; 813 table_bar = pi->pi_msix.table_bar; 814 /* Message Control Register */ 815 if (off == 2 && bytes == 2) { 816 rwmask = PCIM_MSIXCTRL_MSIX_ENABLE | PCIM_MSIXCTRL_FUNCTION_MASK; 817 msgctrl = pci_get_cfgdata16(pi, offset); 818 msgctrl &= ~rwmask; 819 msgctrl |= val & rwmask; 820 val = msgctrl; 821 822 pi->pi_msix.enabled = val & PCIM_MSIXCTRL_MSIX_ENABLE; 823 pi->pi_msix.function_mask = val & PCIM_MSIXCTRL_FUNCTION_MASK; 824 } 825 826 CFGWRITE(pi, offset, val, bytes); 827 } 828 829 void 830 msicap_cfgwrite(struct pci_devinst *pi, int capoff, int offset, 831 int bytes, uint32_t val) 832 { 833 uint16_t msgctrl, rwmask, msgdata, mme; 834 uint32_t addrlo; 835 836 /* 837 * If guest is writing to the message control register make sure 838 * we do not overwrite read-only fields. 839 */ 840 if ((offset - capoff) == 2 && bytes == 2) { 841 rwmask = PCIM_MSICTRL_MME_MASK | PCIM_MSICTRL_MSI_ENABLE; 842 msgctrl = pci_get_cfgdata16(pi, offset); 843 msgctrl &= ~rwmask; 844 msgctrl |= val & rwmask; 845 val = msgctrl; 846 847 addrlo = pci_get_cfgdata32(pi, capoff + 4); 848 if (msgctrl & PCIM_MSICTRL_64BIT) 849 msgdata = pci_get_cfgdata16(pi, capoff + 12); 850 else 851 msgdata = pci_get_cfgdata16(pi, capoff + 8); 852 853 /* 854 * XXX check delivery mode, destination mode etc 855 */ 856 mme = msgctrl & PCIM_MSICTRL_MME_MASK; 857 pi->pi_msi.enabled = msgctrl & PCIM_MSICTRL_MSI_ENABLE ? 1 : 0; 858 if (pi->pi_msi.enabled) { 859 pi->pi_msi.cpu = (addrlo >> 12) & 0xff; 860 pi->pi_msi.vector = msgdata & 0xff; 861 pi->pi_msi.msgnum = 1 << (mme >> 4); 862 } else { 863 pi->pi_msi.cpu = 0; 864 pi->pi_msi.vector = 0; 865 pi->pi_msi.msgnum = 0; 866 } 867 } 868 869 CFGWRITE(pi, offset, val, bytes); 870 } 871 872 void 873 pciecap_cfgwrite(struct pci_devinst *pi, int capoff, int offset, 874 int bytes, uint32_t val) 875 { 876 877 /* XXX don't write to the readonly parts */ 878 CFGWRITE(pi, offset, val, bytes); 879 } 880 881 #define PCIECAP_VERSION 0x2 882 int 883 pci_emul_add_pciecap(struct pci_devinst *pi, int type) 884 { 885 int err; 886 struct pciecap pciecap; 887 888 CTASSERT(sizeof(struct pciecap) == 60); 889 890 if (type != PCIEM_TYPE_ROOT_PORT) 891 return (-1); 892 893 bzero(&pciecap, sizeof(pciecap)); 894 895 pciecap.capid = PCIY_EXPRESS; 896 pciecap.pcie_capabilities = PCIECAP_VERSION | PCIEM_TYPE_ROOT_PORT; 897 pciecap.link_capabilities = 0x411; /* gen1, x1 */ 898 pciecap.link_status = 0x11; /* gen1, x1 */ 899 900 err = pci_emul_add_capability(pi, (u_char *)&pciecap, sizeof(pciecap)); 901 return (err); 902 } 903 904 /* 905 * This function assumes that 'coff' is in the capabilities region of the 906 * config space. 907 */ 908 static void 909 pci_emul_capwrite(struct pci_devinst *pi, int offset, int bytes, uint32_t val) 910 { 911 int capid; 912 uint8_t capoff, nextoff; 913 914 /* Do not allow un-aligned writes */ 915 if ((offset & (bytes - 1)) != 0) 916 return; 917 918 /* Find the capability that we want to update */ 919 capoff = CAP_START_OFFSET; 920 while (1) { 921 capid = pci_get_cfgdata8(pi, capoff); 922 if (capid == PCIY_RESERVED) 923 break; 924 925 nextoff = pci_get_cfgdata8(pi, capoff + 1); 926 if (offset >= capoff && offset < nextoff) 927 break; 928 929 capoff = nextoff; 930 } 931 assert(offset >= capoff); 932 933 /* 934 * Capability ID and Next Capability Pointer are readonly. 935 * However, some o/s's do 4-byte writes that include these. 936 * For this case, trim the write back to 2 bytes and adjust 937 * the data. 938 */ 939 if (offset == capoff || offset == capoff + 1) { 940 if (offset == capoff && bytes == 4) { 941 bytes = 2; 942 offset += 2; 943 val >>= 16; 944 } else 945 return; 946 } 947 948 switch (capid) { 949 case PCIY_MSI: 950 msicap_cfgwrite(pi, capoff, offset, bytes, val); 951 break; 952 case PCIY_MSIX: 953 msixcap_cfgwrite(pi, capoff, offset, bytes, val); 954 break; 955 case PCIY_EXPRESS: 956 pciecap_cfgwrite(pi, capoff, offset, bytes, val); 957 break; 958 default: 959 break; 960 } 961 } 962 963 static int 964 pci_emul_iscap(struct pci_devinst *pi, int offset) 965 { 966 int found; 967 uint16_t sts; 968 uint8_t capid, lastoff; 969 970 found = 0; 971 sts = pci_get_cfgdata16(pi, PCIR_STATUS); 972 if ((sts & PCIM_STATUS_CAPPRESENT) != 0) { 973 lastoff = pci_get_cfgdata8(pi, PCIR_CAP_PTR); 974 while (1) { 975 assert((lastoff & 0x3) == 0); 976 capid = pci_get_cfgdata8(pi, lastoff); 977 if (capid == PCIY_RESERVED) 978 break; 979 lastoff = pci_get_cfgdata8(pi, lastoff + 1); 980 } 981 if (offset >= CAP_START_OFFSET && offset <= lastoff) 982 found = 1; 983 } 984 return (found); 985 } 986 987 static int 988 pci_emul_fallback_handler(struct vmctx *ctx, int vcpu, int dir, uint64_t addr, 989 int size, uint64_t *val, void *arg1, long arg2) 990 { 991 /* 992 * Ignore writes; return 0xff's for reads. The mem read code 993 * will take care of truncating to the correct size. 994 */ 995 if (dir == MEM_F_READ) { 996 *val = 0xffffffffffffffff; 997 } 998 999 return (0); 1000 } 1001 1002 int 1003 init_pci(struct vmctx *ctx) 1004 { 1005 struct mem_range memp; 1006 struct pci_devemu *pde; 1007 struct slotinfo *si; 1008 size_t lowmem; 1009 int slot, func; 1010 int error; 1011 1012 pci_emul_iobase = PCI_EMUL_IOBASE; 1013 pci_emul_membase32 = vm_get_lowmem_limit(ctx); 1014 pci_emul_membase64 = PCI_EMUL_MEMBASE64; 1015 1016 for (slot = 0; slot < MAXSLOTS; slot++) { 1017 for (func = 0; func < MAXFUNCS; func++) { 1018 si = &pci_slotinfo[slot][func]; 1019 if (si->si_name != NULL) { 1020 pde = pci_emul_finddev(si->si_name); 1021 assert(pde != NULL); 1022 error = pci_emul_init(ctx, pde, slot, func, 1023 si->si_param); 1024 if (error) 1025 return (error); 1026 } 1027 } 1028 } 1029 1030 /* 1031 * The guest physical memory map looks like the following: 1032 * [0, lowmem) guest system memory 1033 * [lowmem, lowmem_limit) memory hole (may be absent) 1034 * [lowmem_limit, 4GB) PCI hole (32-bit BAR allocation) 1035 * [4GB, 4GB + highmem) 1036 * 1037 * Accesses to memory addresses that are not allocated to system 1038 * memory or PCI devices return 0xff's. 1039 */ 1040 error = vm_get_memory_seg(ctx, 0, &lowmem, NULL); 1041 assert(error == 0); 1042 1043 memset(&memp, 0, sizeof(struct mem_range)); 1044 memp.name = "PCI hole"; 1045 memp.flags = MEM_F_RW; 1046 memp.base = lowmem; 1047 memp.size = (4ULL * 1024 * 1024 * 1024) - lowmem; 1048 memp.handler = pci_emul_fallback_handler; 1049 1050 error = register_mem_fallback(&memp); 1051 assert(error == 0); 1052 1053 return (0); 1054 } 1055 1056 int 1057 pci_msi_enabled(struct pci_devinst *pi) 1058 { 1059 return (pi->pi_msi.enabled); 1060 } 1061 1062 int 1063 pci_msi_msgnum(struct pci_devinst *pi) 1064 { 1065 if (pi->pi_msi.enabled) 1066 return (pi->pi_msi.msgnum); 1067 else 1068 return (0); 1069 } 1070 1071 int 1072 pci_msix_enabled(struct pci_devinst *pi) 1073 { 1074 1075 return (pi->pi_msix.enabled && !pi->pi_msi.enabled); 1076 } 1077 1078 void 1079 pci_generate_msix(struct pci_devinst *pi, int index) 1080 { 1081 struct msix_table_entry *mte; 1082 1083 if (!pci_msix_enabled(pi)) 1084 return; 1085 1086 if (pi->pi_msix.function_mask) 1087 return; 1088 1089 if (index >= pi->pi_msix.table_count) 1090 return; 1091 1092 mte = &pi->pi_msix.table[index]; 1093 if ((mte->vector_control & PCIM_MSIX_VCTRL_MASK) == 0) { 1094 /* XXX Set PBA bit if interrupt is disabled */ 1095 vm_lapic_irq(pi->pi_vmctx, 1096 (mte->addr >> 12) & 0xff, mte->msg_data & 0xff); 1097 } 1098 } 1099 1100 void 1101 pci_generate_msi(struct pci_devinst *pi, int msg) 1102 { 1103 1104 if (pci_msi_enabled(pi) && msg < pci_msi_msgnum(pi)) { 1105 vm_lapic_irq(pi->pi_vmctx, 1106 pi->pi_msi.cpu, 1107 pi->pi_msi.vector + msg); 1108 } 1109 } 1110 1111 int 1112 pci_is_legacy(struct pci_devinst *pi) 1113 { 1114 1115 return (pci_slotinfo[pi->pi_slot][pi->pi_func].si_legacy); 1116 } 1117 1118 int 1119 pci_lintr_request(struct pci_devinst *pi, int req) 1120 { 1121 int irq; 1122 1123 irq = legacy_irq_alloc(req); 1124 if (irq < 0) 1125 return (-1); 1126 1127 pi->pi_lintr_pin = irq; 1128 pci_set_cfgdata8(pi, PCIR_INTLINE, irq); 1129 pci_set_cfgdata8(pi, PCIR_INTPIN, 1); 1130 return (0); 1131 } 1132 1133 void 1134 pci_lintr_assert(struct pci_devinst *pi) 1135 { 1136 1137 assert(pi->pi_lintr_pin >= 0); 1138 1139 if (pi->pi_lintr_state == 0) { 1140 pi->pi_lintr_state = 1; 1141 vm_ioapic_assert_irq(pi->pi_vmctx, pi->pi_lintr_pin); 1142 } 1143 } 1144 1145 void 1146 pci_lintr_deassert(struct pci_devinst *pi) 1147 { 1148 1149 assert(pi->pi_lintr_pin >= 0); 1150 1151 if (pi->pi_lintr_state == 1) { 1152 pi->pi_lintr_state = 0; 1153 vm_ioapic_deassert_irq(pi->pi_vmctx, pi->pi_lintr_pin); 1154 } 1155 } 1156 1157 /* 1158 * Return 1 if the emulated device in 'slot' is a multi-function device. 1159 * Return 0 otherwise. 1160 */ 1161 static int 1162 pci_emul_is_mfdev(int slot) 1163 { 1164 int f, numfuncs; 1165 1166 numfuncs = 0; 1167 for (f = 0; f < MAXFUNCS; f++) { 1168 if (pci_slotinfo[slot][f].si_devi != NULL) { 1169 numfuncs++; 1170 } 1171 } 1172 return (numfuncs > 1); 1173 } 1174 1175 /* 1176 * Ensure that the PCIM_MFDEV bit is properly set (or unset) depending on 1177 * whether or not is a multi-function being emulated in the pci 'slot'. 1178 */ 1179 static void 1180 pci_emul_hdrtype_fixup(int slot, int off, int bytes, uint32_t *rv) 1181 { 1182 int mfdev; 1183 1184 if (off <= PCIR_HDRTYPE && off + bytes > PCIR_HDRTYPE) { 1185 mfdev = pci_emul_is_mfdev(slot); 1186 switch (bytes) { 1187 case 1: 1188 case 2: 1189 *rv &= ~PCIM_MFDEV; 1190 if (mfdev) { 1191 *rv |= PCIM_MFDEV; 1192 } 1193 break; 1194 case 4: 1195 *rv &= ~(PCIM_MFDEV << 16); 1196 if (mfdev) { 1197 *rv |= (PCIM_MFDEV << 16); 1198 } 1199 break; 1200 } 1201 } 1202 } 1203 1204 static int cfgbus, cfgslot, cfgfunc, cfgoff; 1205 1206 static int 1207 pci_emul_cfgaddr(struct vmctx *ctx, int vcpu, int in, int port, int bytes, 1208 uint32_t *eax, void *arg) 1209 { 1210 uint32_t x; 1211 1212 if (bytes != 4) { 1213 if (in) 1214 *eax = (bytes == 2) ? 0xffff : 0xff; 1215 return (0); 1216 } 1217 1218 if (in) { 1219 x = (cfgbus << 16) | 1220 (cfgslot << 11) | 1221 (cfgfunc << 8) | 1222 cfgoff; 1223 *eax = x | CONF1_ENABLE; 1224 } else { 1225 x = *eax; 1226 cfgoff = x & PCI_REGMAX; 1227 cfgfunc = (x >> 8) & PCI_FUNCMAX; 1228 cfgslot = (x >> 11) & PCI_SLOTMAX; 1229 cfgbus = (x >> 16) & PCI_BUSMAX; 1230 } 1231 1232 return (0); 1233 } 1234 INOUT_PORT(pci_cfgaddr, CONF1_ADDR_PORT, IOPORT_F_INOUT, pci_emul_cfgaddr); 1235 1236 static uint32_t 1237 bits_changed(uint32_t old, uint32_t new, uint32_t mask) 1238 { 1239 1240 return ((old ^ new) & mask); 1241 } 1242 1243 static void 1244 pci_emul_cmdwrite(struct pci_devinst *pi, uint32_t new, int bytes) 1245 { 1246 int i; 1247 uint16_t old; 1248 1249 /* 1250 * The command register is at an offset of 4 bytes and thus the 1251 * guest could write 1, 2 or 4 bytes starting at this offset. 1252 */ 1253 1254 old = pci_get_cfgdata16(pi, PCIR_COMMAND); /* stash old value */ 1255 CFGWRITE(pi, PCIR_COMMAND, new, bytes); /* update config */ 1256 new = pci_get_cfgdata16(pi, PCIR_COMMAND); /* get updated value */ 1257 1258 /* 1259 * If the MMIO or I/O address space decoding has changed then 1260 * register/unregister all BARs that decode that address space. 1261 */ 1262 for (i = 0; i <= PCI_BARMAX; i++) { 1263 switch (pi->pi_bar[i].type) { 1264 case PCIBAR_NONE: 1265 case PCIBAR_MEMHI64: 1266 break; 1267 case PCIBAR_IO: 1268 /* I/O address space decoding changed? */ 1269 if (bits_changed(old, new, PCIM_CMD_PORTEN)) { 1270 if (porten(pi)) 1271 register_bar(pi, i); 1272 else 1273 unregister_bar(pi, i); 1274 } 1275 break; 1276 case PCIBAR_MEM32: 1277 case PCIBAR_MEM64: 1278 /* MMIO address space decoding changed? */ 1279 if (bits_changed(old, new, PCIM_CMD_MEMEN)) { 1280 if (memen(pi)) 1281 register_bar(pi, i); 1282 else 1283 unregister_bar(pi, i); 1284 } 1285 break; 1286 default: 1287 assert(0); 1288 } 1289 } 1290 } 1291 1292 static int 1293 pci_emul_cfgdata(struct vmctx *ctx, int vcpu, int in, int port, int bytes, 1294 uint32_t *eax, void *arg) 1295 { 1296 struct pci_devinst *pi; 1297 struct pci_devemu *pe; 1298 int coff, idx, needcfg; 1299 uint64_t addr, bar, mask; 1300 1301 assert(bytes == 1 || bytes == 2 || bytes == 4); 1302 1303 if (cfgbus == 0) 1304 pi = pci_slotinfo[cfgslot][cfgfunc].si_devi; 1305 else 1306 pi = NULL; 1307 1308 coff = cfgoff + (port - CONF1_DATA_PORT); 1309 1310 #if 0 1311 printf("pcicfg-%s from 0x%0x of %d bytes (%d/%d/%d)\n\r", 1312 in ? "read" : "write", coff, bytes, cfgbus, cfgslot, cfgfunc); 1313 #endif 1314 1315 /* 1316 * Just return if there is no device at this cfgslot:cfgfunc or 1317 * if the guest is doing an un-aligned access 1318 */ 1319 if (pi == NULL || (coff & (bytes - 1)) != 0) { 1320 if (in) 1321 *eax = 0xffffffff; 1322 return (0); 1323 } 1324 1325 pe = pi->pi_d; 1326 1327 /* 1328 * Config read 1329 */ 1330 if (in) { 1331 /* Let the device emulation override the default handler */ 1332 if (pe->pe_cfgread != NULL) { 1333 needcfg = pe->pe_cfgread(ctx, vcpu, pi, 1334 coff, bytes, eax); 1335 } else { 1336 needcfg = 1; 1337 } 1338 1339 if (needcfg) { 1340 if (bytes == 1) 1341 *eax = pci_get_cfgdata8(pi, coff); 1342 else if (bytes == 2) 1343 *eax = pci_get_cfgdata16(pi, coff); 1344 else 1345 *eax = pci_get_cfgdata32(pi, coff); 1346 } 1347 1348 pci_emul_hdrtype_fixup(cfgslot, coff, bytes, eax); 1349 } else { 1350 /* Let the device emulation override the default handler */ 1351 if (pe->pe_cfgwrite != NULL && 1352 (*pe->pe_cfgwrite)(ctx, vcpu, pi, coff, bytes, *eax) == 0) 1353 return (0); 1354 1355 /* 1356 * Special handling for write to BAR registers 1357 */ 1358 if (coff >= PCIR_BAR(0) && coff < PCIR_BAR(PCI_BARMAX + 1)) { 1359 /* 1360 * Ignore writes to BAR registers that are not 1361 * 4-byte aligned. 1362 */ 1363 if (bytes != 4 || (coff & 0x3) != 0) 1364 return (0); 1365 idx = (coff - PCIR_BAR(0)) / 4; 1366 mask = ~(pi->pi_bar[idx].size - 1); 1367 switch (pi->pi_bar[idx].type) { 1368 case PCIBAR_NONE: 1369 pi->pi_bar[idx].addr = bar = 0; 1370 break; 1371 case PCIBAR_IO: 1372 addr = *eax & mask; 1373 addr &= 0xffff; 1374 bar = addr | PCIM_BAR_IO_SPACE; 1375 /* 1376 * Register the new BAR value for interception 1377 */ 1378 if (addr != pi->pi_bar[idx].addr) { 1379 update_bar_address(pi, addr, idx, 1380 PCIBAR_IO); 1381 } 1382 break; 1383 case PCIBAR_MEM32: 1384 addr = bar = *eax & mask; 1385 bar |= PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_32; 1386 if (addr != pi->pi_bar[idx].addr) { 1387 update_bar_address(pi, addr, idx, 1388 PCIBAR_MEM32); 1389 } 1390 break; 1391 case PCIBAR_MEM64: 1392 addr = bar = *eax & mask; 1393 bar |= PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_64 | 1394 PCIM_BAR_MEM_PREFETCH; 1395 if (addr != (uint32_t)pi->pi_bar[idx].addr) { 1396 update_bar_address(pi, addr, idx, 1397 PCIBAR_MEM64); 1398 } 1399 break; 1400 case PCIBAR_MEMHI64: 1401 mask = ~(pi->pi_bar[idx - 1].size - 1); 1402 addr = ((uint64_t)*eax << 32) & mask; 1403 bar = addr >> 32; 1404 if (bar != pi->pi_bar[idx - 1].addr >> 32) { 1405 update_bar_address(pi, addr, idx - 1, 1406 PCIBAR_MEMHI64); 1407 } 1408 break; 1409 default: 1410 assert(0); 1411 } 1412 pci_set_cfgdata32(pi, coff, bar); 1413 1414 } else if (pci_emul_iscap(pi, coff)) { 1415 pci_emul_capwrite(pi, coff, bytes, *eax); 1416 } else if (coff == PCIR_COMMAND) { 1417 pci_emul_cmdwrite(pi, *eax, bytes); 1418 } else { 1419 CFGWRITE(pi, coff, *eax, bytes); 1420 } 1421 } 1422 1423 return (0); 1424 } 1425 1426 INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+0, IOPORT_F_INOUT, pci_emul_cfgdata); 1427 INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+1, IOPORT_F_INOUT, pci_emul_cfgdata); 1428 INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+2, IOPORT_F_INOUT, pci_emul_cfgdata); 1429 INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+3, IOPORT_F_INOUT, pci_emul_cfgdata); 1430 1431 /* 1432 * I/O ports to configure PCI IRQ routing. We ignore all writes to it. 1433 */ 1434 static int 1435 pci_irq_port_handler(struct vmctx *ctx, int vcpu, int in, int port, int bytes, 1436 uint32_t *eax, void *arg) 1437 { 1438 assert(in == 0); 1439 return (0); 1440 } 1441 INOUT_PORT(pci_irq, 0xC00, IOPORT_F_OUT, pci_irq_port_handler); 1442 INOUT_PORT(pci_irq, 0xC01, IOPORT_F_OUT, pci_irq_port_handler); 1443 1444 #define PCI_EMUL_TEST 1445 #ifdef PCI_EMUL_TEST 1446 /* 1447 * Define a dummy test device 1448 */ 1449 #define DIOSZ 20 1450 #define DMEMSZ 4096 1451 struct pci_emul_dsoftc { 1452 uint8_t ioregs[DIOSZ]; 1453 uint8_t memregs[DMEMSZ]; 1454 }; 1455 1456 #define PCI_EMUL_MSI_MSGS 4 1457 #define PCI_EMUL_MSIX_MSGS 16 1458 1459 static int 1460 pci_emul_dinit(struct vmctx *ctx, struct pci_devinst *pi, char *opts) 1461 { 1462 int error; 1463 struct pci_emul_dsoftc *sc; 1464 1465 sc = malloc(sizeof(struct pci_emul_dsoftc)); 1466 memset(sc, 0, sizeof(struct pci_emul_dsoftc)); 1467 1468 pi->pi_arg = sc; 1469 1470 pci_set_cfgdata16(pi, PCIR_DEVICE, 0x0001); 1471 pci_set_cfgdata16(pi, PCIR_VENDOR, 0x10DD); 1472 pci_set_cfgdata8(pi, PCIR_CLASS, 0x02); 1473 1474 error = pci_emul_add_msicap(pi, PCI_EMUL_MSI_MSGS); 1475 assert(error == 0); 1476 1477 error = pci_emul_alloc_bar(pi, 0, PCIBAR_IO, DIOSZ); 1478 assert(error == 0); 1479 1480 error = pci_emul_alloc_bar(pi, 1, PCIBAR_MEM32, DMEMSZ); 1481 assert(error == 0); 1482 1483 return (0); 1484 } 1485 1486 static void 1487 pci_emul_diow(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, int baridx, 1488 uint64_t offset, int size, uint64_t value) 1489 { 1490 int i; 1491 struct pci_emul_dsoftc *sc = pi->pi_arg; 1492 1493 if (baridx == 0) { 1494 if (offset + size > DIOSZ) { 1495 printf("diow: iow too large, offset %ld size %d\n", 1496 offset, size); 1497 return; 1498 } 1499 1500 if (size == 1) { 1501 sc->ioregs[offset] = value & 0xff; 1502 } else if (size == 2) { 1503 *(uint16_t *)&sc->ioregs[offset] = value & 0xffff; 1504 } else if (size == 4) { 1505 *(uint32_t *)&sc->ioregs[offset] = value; 1506 } else { 1507 printf("diow: iow unknown size %d\n", size); 1508 } 1509 1510 /* 1511 * Special magic value to generate an interrupt 1512 */ 1513 if (offset == 4 && size == 4 && pci_msi_enabled(pi)) 1514 pci_generate_msi(pi, value % pci_msi_msgnum(pi)); 1515 1516 if (value == 0xabcdef) { 1517 for (i = 0; i < pci_msi_msgnum(pi); i++) 1518 pci_generate_msi(pi, i); 1519 } 1520 } 1521 1522 if (baridx == 1) { 1523 if (offset + size > DMEMSZ) { 1524 printf("diow: memw too large, offset %ld size %d\n", 1525 offset, size); 1526 return; 1527 } 1528 1529 if (size == 1) { 1530 sc->memregs[offset] = value; 1531 } else if (size == 2) { 1532 *(uint16_t *)&sc->memregs[offset] = value; 1533 } else if (size == 4) { 1534 *(uint32_t *)&sc->memregs[offset] = value; 1535 } else if (size == 8) { 1536 *(uint64_t *)&sc->memregs[offset] = value; 1537 } else { 1538 printf("diow: memw unknown size %d\n", size); 1539 } 1540 1541 /* 1542 * magic interrupt ?? 1543 */ 1544 } 1545 1546 if (baridx > 1) { 1547 printf("diow: unknown bar idx %d\n", baridx); 1548 } 1549 } 1550 1551 static uint64_t 1552 pci_emul_dior(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, int baridx, 1553 uint64_t offset, int size) 1554 { 1555 struct pci_emul_dsoftc *sc = pi->pi_arg; 1556 uint32_t value; 1557 1558 if (baridx == 0) { 1559 if (offset + size > DIOSZ) { 1560 printf("dior: ior too large, offset %ld size %d\n", 1561 offset, size); 1562 return (0); 1563 } 1564 1565 if (size == 1) { 1566 value = sc->ioregs[offset]; 1567 } else if (size == 2) { 1568 value = *(uint16_t *) &sc->ioregs[offset]; 1569 } else if (size == 4) { 1570 value = *(uint32_t *) &sc->ioregs[offset]; 1571 } else { 1572 printf("dior: ior unknown size %d\n", size); 1573 } 1574 } 1575 1576 if (baridx == 1) { 1577 if (offset + size > DMEMSZ) { 1578 printf("dior: memr too large, offset %ld size %d\n", 1579 offset, size); 1580 return (0); 1581 } 1582 1583 if (size == 1) { 1584 value = sc->memregs[offset]; 1585 } else if (size == 2) { 1586 value = *(uint16_t *) &sc->memregs[offset]; 1587 } else if (size == 4) { 1588 value = *(uint32_t *) &sc->memregs[offset]; 1589 } else if (size == 8) { 1590 value = *(uint64_t *) &sc->memregs[offset]; 1591 } else { 1592 printf("dior: ior unknown size %d\n", size); 1593 } 1594 } 1595 1596 1597 if (baridx > 1) { 1598 printf("dior: unknown bar idx %d\n", baridx); 1599 return (0); 1600 } 1601 1602 return (value); 1603 } 1604 1605 struct pci_devemu pci_dummy = { 1606 .pe_emu = "dummy", 1607 .pe_init = pci_emul_dinit, 1608 .pe_barwrite = pci_emul_diow, 1609 .pe_barread = pci_emul_dior 1610 }; 1611 PCI_EMUL_SET(pci_dummy); 1612 1613 #endif /* PCI_EMUL_TEST */ 1614