1 /*- 2 * Copyright (c) 2011 NetApp, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 #include <sys/param.h> 33 #include <sys/linker_set.h> 34 #include <sys/errno.h> 35 36 #include <ctype.h> 37 #include <stdio.h> 38 #include <stdlib.h> 39 #include <string.h> 40 #include <strings.h> 41 #include <assert.h> 42 #include <stdbool.h> 43 44 #include <machine/vmm.h> 45 #include <vmmapi.h> 46 47 #include "bhyverun.h" 48 #include "inout.h" 49 #include "mem.h" 50 #include "pci_emul.h" 51 #include "ioapic.h" 52 53 #define CONF1_ADDR_PORT 0x0cf8 54 #define CONF1_DATA_PORT 0x0cfc 55 56 #define CONF1_ENABLE 0x80000000ul 57 58 #define CFGWRITE(pi,off,val,b) \ 59 do { \ 60 if ((b) == 1) { \ 61 pci_set_cfgdata8((pi),(off),(val)); \ 62 } else if ((b) == 2) { \ 63 pci_set_cfgdata16((pi),(off),(val)); \ 64 } else { \ 65 pci_set_cfgdata32((pi),(off),(val)); \ 66 } \ 67 } while (0) 68 69 #define MAXSLOTS (PCI_SLOTMAX + 1) 70 #define MAXFUNCS (PCI_FUNCMAX + 1) 71 72 static struct slotinfo { 73 char *si_name; 74 char *si_param; 75 struct pci_devinst *si_devi; 76 int si_legacy; 77 } pci_slotinfo[MAXSLOTS][MAXFUNCS]; 78 79 /* 80 * Used to keep track of legacy interrupt owners/requestors 81 */ 82 #define NLIRQ 16 83 84 static struct lirqinfo { 85 int li_generic; 86 int li_acount; 87 struct pci_devinst *li_owner; /* XXX should be a list */ 88 } lirq[NLIRQ]; 89 90 SET_DECLARE(pci_devemu_set, struct pci_devemu); 91 92 static uint64_t pci_emul_iobase; 93 static uint64_t pci_emul_membase32; 94 static uint64_t pci_emul_membase64; 95 96 #define PCI_EMUL_IOBASE 0x2000 97 #define PCI_EMUL_IOLIMIT 0x10000 98 99 #define PCI_EMUL_MEMLIMIT32 0xE0000000 /* 3.5GB */ 100 101 #define PCI_EMUL_MEMBASE64 0xD000000000UL 102 #define PCI_EMUL_MEMLIMIT64 0xFD00000000UL 103 104 static struct pci_devemu *pci_emul_finddev(char *name); 105 106 static int pci_emul_devices; 107 108 /* 109 * I/O access 110 */ 111 112 /* 113 * Slot options are in the form: 114 * 115 * <slot>[:<func>],<emul>[,<config>] 116 * 117 * slot is 0..31 118 * func is 0..7 119 * emul is a string describing the type of PCI device e.g. virtio-net 120 * config is an optional string, depending on the device, that can be 121 * used for configuration. 122 * Examples are: 123 * 1,virtio-net,tap0 124 * 3:0,dummy 125 */ 126 static void 127 pci_parse_slot_usage(char *aopt) 128 { 129 130 fprintf(stderr, "Invalid PCI slot info field \"%s\"\n", aopt); 131 } 132 133 int 134 pci_parse_slot(char *opt, int legacy) 135 { 136 char *slot, *func, *emul, *config; 137 char *str, *cpy; 138 int error, snum, fnum; 139 140 error = -1; 141 str = cpy = strdup(opt); 142 143 slot = strsep(&str, ","); 144 func = NULL; 145 if (strchr(slot, ':') != NULL) { 146 func = cpy; 147 (void) strsep(&func, ":"); 148 } 149 150 emul = strsep(&str, ","); 151 config = str; 152 153 if (emul == NULL) { 154 pci_parse_slot_usage(opt); 155 goto done; 156 } 157 158 snum = atoi(slot); 159 fnum = func ? atoi(func) : 0; 160 161 if (snum < 0 || snum >= MAXSLOTS || fnum < 0 || fnum >= MAXFUNCS) { 162 pci_parse_slot_usage(opt); 163 goto done; 164 } 165 166 if (pci_slotinfo[snum][fnum].si_name != NULL) { 167 fprintf(stderr, "pci slot %d:%d already occupied!\n", 168 snum, fnum); 169 goto done; 170 } 171 172 if (pci_emul_finddev(emul) == NULL) { 173 fprintf(stderr, "pci slot %d:%d: unknown device \"%s\"\n", 174 snum, fnum, emul); 175 goto done; 176 } 177 178 error = 0; 179 pci_slotinfo[snum][fnum].si_name = emul; 180 pci_slotinfo[snum][fnum].si_param = config; 181 pci_slotinfo[snum][fnum].si_legacy = legacy; 182 183 done: 184 if (error) 185 free(cpy); 186 187 return (error); 188 } 189 190 static int 191 pci_valid_pba_offset(struct pci_devinst *pi, uint64_t offset) 192 { 193 194 if (offset < pi->pi_msix.pba_offset) 195 return (0); 196 197 if (offset >= pi->pi_msix.pba_offset + pi->pi_msix.pba_size) { 198 return (0); 199 } 200 201 return (1); 202 } 203 204 int 205 pci_emul_msix_twrite(struct pci_devinst *pi, uint64_t offset, int size, 206 uint64_t value) 207 { 208 int msix_entry_offset; 209 int tab_index; 210 char *dest; 211 212 /* support only 4 or 8 byte writes */ 213 if (size != 4 && size != 8) 214 return (-1); 215 216 /* 217 * Return if table index is beyond what device supports 218 */ 219 tab_index = offset / MSIX_TABLE_ENTRY_SIZE; 220 if (tab_index >= pi->pi_msix.table_count) 221 return (-1); 222 223 msix_entry_offset = offset % MSIX_TABLE_ENTRY_SIZE; 224 225 /* support only aligned writes */ 226 if ((msix_entry_offset % size) != 0) 227 return (-1); 228 229 dest = (char *)(pi->pi_msix.table + tab_index); 230 dest += msix_entry_offset; 231 232 if (size == 4) 233 *((uint32_t *)dest) = value; 234 else 235 *((uint64_t *)dest) = value; 236 237 return (0); 238 } 239 240 uint64_t 241 pci_emul_msix_tread(struct pci_devinst *pi, uint64_t offset, int size) 242 { 243 char *dest; 244 int msix_entry_offset; 245 int tab_index; 246 uint64_t retval = ~0; 247 248 /* support only 4 or 8 byte reads */ 249 if (size != 4 && size != 8) 250 return (retval); 251 252 msix_entry_offset = offset % MSIX_TABLE_ENTRY_SIZE; 253 254 /* support only aligned reads */ 255 if ((msix_entry_offset % size) != 0) { 256 return (retval); 257 } 258 259 tab_index = offset / MSIX_TABLE_ENTRY_SIZE; 260 261 if (tab_index < pi->pi_msix.table_count) { 262 /* valid MSI-X Table access */ 263 dest = (char *)(pi->pi_msix.table + tab_index); 264 dest += msix_entry_offset; 265 266 if (size == 4) 267 retval = *((uint32_t *)dest); 268 else 269 retval = *((uint64_t *)dest); 270 } else if (pci_valid_pba_offset(pi, offset)) { 271 /* return 0 for PBA access */ 272 retval = 0; 273 } 274 275 return (retval); 276 } 277 278 int 279 pci_msix_table_bar(struct pci_devinst *pi) 280 { 281 282 if (pi->pi_msix.table != NULL) 283 return (pi->pi_msix.table_bar); 284 else 285 return (-1); 286 } 287 288 int 289 pci_msix_pba_bar(struct pci_devinst *pi) 290 { 291 292 if (pi->pi_msix.table != NULL) 293 return (pi->pi_msix.pba_bar); 294 else 295 return (-1); 296 } 297 298 static int 299 pci_emul_io_handler(struct vmctx *ctx, int vcpu, int in, int port, int bytes, 300 uint32_t *eax, void *arg) 301 { 302 struct pci_devinst *pdi = arg; 303 struct pci_devemu *pe = pdi->pi_d; 304 uint64_t offset; 305 int i; 306 307 for (i = 0; i <= PCI_BARMAX; i++) { 308 if (pdi->pi_bar[i].type == PCIBAR_IO && 309 port >= pdi->pi_bar[i].addr && 310 port + bytes <= pdi->pi_bar[i].addr + pdi->pi_bar[i].size) { 311 offset = port - pdi->pi_bar[i].addr; 312 if (in) 313 *eax = (*pe->pe_barread)(ctx, vcpu, pdi, i, 314 offset, bytes); 315 else 316 (*pe->pe_barwrite)(ctx, vcpu, pdi, i, offset, 317 bytes, *eax); 318 return (0); 319 } 320 } 321 return (-1); 322 } 323 324 static int 325 pci_emul_mem_handler(struct vmctx *ctx, int vcpu, int dir, uint64_t addr, 326 int size, uint64_t *val, void *arg1, long arg2) 327 { 328 struct pci_devinst *pdi = arg1; 329 struct pci_devemu *pe = pdi->pi_d; 330 uint64_t offset; 331 int bidx = (int) arg2; 332 333 assert(bidx <= PCI_BARMAX); 334 assert(pdi->pi_bar[bidx].type == PCIBAR_MEM32 || 335 pdi->pi_bar[bidx].type == PCIBAR_MEM64); 336 assert(addr >= pdi->pi_bar[bidx].addr && 337 addr + size <= pdi->pi_bar[bidx].addr + pdi->pi_bar[bidx].size); 338 339 offset = addr - pdi->pi_bar[bidx].addr; 340 341 if (dir == MEM_F_WRITE) 342 (*pe->pe_barwrite)(ctx, vcpu, pdi, bidx, offset, size, *val); 343 else 344 *val = (*pe->pe_barread)(ctx, vcpu, pdi, bidx, offset, size); 345 346 return (0); 347 } 348 349 350 static int 351 pci_emul_alloc_resource(uint64_t *baseptr, uint64_t limit, uint64_t size, 352 uint64_t *addr) 353 { 354 uint64_t base; 355 356 assert((size & (size - 1)) == 0); /* must be a power of 2 */ 357 358 base = roundup2(*baseptr, size); 359 360 if (base + size <= limit) { 361 *addr = base; 362 *baseptr = base + size; 363 return (0); 364 } else 365 return (-1); 366 } 367 368 int 369 pci_emul_alloc_bar(struct pci_devinst *pdi, int idx, enum pcibar_type type, 370 uint64_t size) 371 { 372 373 return (pci_emul_alloc_pbar(pdi, idx, 0, type, size)); 374 } 375 376 /* 377 * Register (or unregister) the MMIO or I/O region associated with the BAR 378 * register 'idx' of an emulated pci device. 379 */ 380 static void 381 modify_bar_registration(struct pci_devinst *pi, int idx, int registration) 382 { 383 int error; 384 struct inout_port iop; 385 struct mem_range mr; 386 387 switch (pi->pi_bar[idx].type) { 388 case PCIBAR_IO: 389 bzero(&iop, sizeof(struct inout_port)); 390 iop.name = pi->pi_name; 391 iop.port = pi->pi_bar[idx].addr; 392 iop.size = pi->pi_bar[idx].size; 393 if (registration) { 394 iop.flags = IOPORT_F_INOUT; 395 iop.handler = pci_emul_io_handler; 396 iop.arg = pi; 397 error = register_inout(&iop); 398 } else 399 error = unregister_inout(&iop); 400 break; 401 case PCIBAR_MEM32: 402 case PCIBAR_MEM64: 403 bzero(&mr, sizeof(struct mem_range)); 404 mr.name = pi->pi_name; 405 mr.base = pi->pi_bar[idx].addr; 406 mr.size = pi->pi_bar[idx].size; 407 if (registration) { 408 mr.flags = MEM_F_RW; 409 mr.handler = pci_emul_mem_handler; 410 mr.arg1 = pi; 411 mr.arg2 = idx; 412 error = register_mem(&mr); 413 } else 414 error = unregister_mem(&mr); 415 break; 416 default: 417 error = EINVAL; 418 break; 419 } 420 assert(error == 0); 421 } 422 423 static void 424 unregister_bar(struct pci_devinst *pi, int idx) 425 { 426 427 modify_bar_registration(pi, idx, 0); 428 } 429 430 static void 431 register_bar(struct pci_devinst *pi, int idx) 432 { 433 434 modify_bar_registration(pi, idx, 1); 435 } 436 437 /* Are we decoding i/o port accesses for the emulated pci device? */ 438 static int 439 porten(struct pci_devinst *pi) 440 { 441 uint16_t cmd; 442 443 cmd = pci_get_cfgdata16(pi, PCIR_COMMAND); 444 445 return (cmd & PCIM_CMD_PORTEN); 446 } 447 448 /* Are we decoding memory accesses for the emulated pci device? */ 449 static int 450 memen(struct pci_devinst *pi) 451 { 452 uint16_t cmd; 453 454 cmd = pci_get_cfgdata16(pi, PCIR_COMMAND); 455 456 return (cmd & PCIM_CMD_MEMEN); 457 } 458 459 /* 460 * Update the MMIO or I/O address that is decoded by the BAR register. 461 * 462 * If the pci device has enabled the address space decoding then intercept 463 * the address range decoded by the BAR register. 464 */ 465 static void 466 update_bar_address(struct pci_devinst *pi, uint64_t addr, int idx, int type) 467 { 468 int decode; 469 470 if (pi->pi_bar[idx].type == PCIBAR_IO) 471 decode = porten(pi); 472 else 473 decode = memen(pi); 474 475 if (decode) 476 unregister_bar(pi, idx); 477 478 switch (type) { 479 case PCIBAR_IO: 480 case PCIBAR_MEM32: 481 pi->pi_bar[idx].addr = addr; 482 break; 483 case PCIBAR_MEM64: 484 pi->pi_bar[idx].addr &= ~0xffffffffUL; 485 pi->pi_bar[idx].addr |= addr; 486 break; 487 case PCIBAR_MEMHI64: 488 pi->pi_bar[idx].addr &= 0xffffffff; 489 pi->pi_bar[idx].addr |= addr; 490 break; 491 default: 492 assert(0); 493 } 494 495 if (decode) 496 register_bar(pi, idx); 497 } 498 499 int 500 pci_emul_alloc_pbar(struct pci_devinst *pdi, int idx, uint64_t hostbase, 501 enum pcibar_type type, uint64_t size) 502 { 503 int error; 504 uint64_t *baseptr, limit, addr, mask, lobits, bar; 505 506 assert(idx >= 0 && idx <= PCI_BARMAX); 507 508 if ((size & (size - 1)) != 0) 509 size = 1UL << flsl(size); /* round up to a power of 2 */ 510 511 /* Enforce minimum BAR sizes required by the PCI standard */ 512 if (type == PCIBAR_IO) { 513 if (size < 4) 514 size = 4; 515 } else { 516 if (size < 16) 517 size = 16; 518 } 519 520 switch (type) { 521 case PCIBAR_NONE: 522 baseptr = NULL; 523 addr = mask = lobits = 0; 524 break; 525 case PCIBAR_IO: 526 if (hostbase && 527 pci_slotinfo[pdi->pi_slot][pdi->pi_func].si_legacy) { 528 assert(hostbase < PCI_EMUL_IOBASE); 529 baseptr = &hostbase; 530 } else { 531 baseptr = &pci_emul_iobase; 532 } 533 limit = PCI_EMUL_IOLIMIT; 534 mask = PCIM_BAR_IO_BASE; 535 lobits = PCIM_BAR_IO_SPACE; 536 break; 537 case PCIBAR_MEM64: 538 /* 539 * XXX 540 * Some drivers do not work well if the 64-bit BAR is allocated 541 * above 4GB. Allow for this by allocating small requests under 542 * 4GB unless then allocation size is larger than some arbitrary 543 * number (32MB currently). 544 */ 545 if (size > 32 * 1024 * 1024) { 546 /* 547 * XXX special case for device requiring peer-peer DMA 548 */ 549 if (size == 0x100000000UL) 550 baseptr = &hostbase; 551 else 552 baseptr = &pci_emul_membase64; 553 limit = PCI_EMUL_MEMLIMIT64; 554 mask = PCIM_BAR_MEM_BASE; 555 lobits = PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_64 | 556 PCIM_BAR_MEM_PREFETCH; 557 break; 558 } else { 559 baseptr = &pci_emul_membase32; 560 limit = PCI_EMUL_MEMLIMIT32; 561 mask = PCIM_BAR_MEM_BASE; 562 lobits = PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_64; 563 } 564 break; 565 case PCIBAR_MEM32: 566 baseptr = &pci_emul_membase32; 567 limit = PCI_EMUL_MEMLIMIT32; 568 mask = PCIM_BAR_MEM_BASE; 569 lobits = PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_32; 570 break; 571 default: 572 printf("pci_emul_alloc_base: invalid bar type %d\n", type); 573 assert(0); 574 } 575 576 if (baseptr != NULL) { 577 error = pci_emul_alloc_resource(baseptr, limit, size, &addr); 578 if (error != 0) 579 return (error); 580 } 581 582 pdi->pi_bar[idx].type = type; 583 pdi->pi_bar[idx].addr = addr; 584 pdi->pi_bar[idx].size = size; 585 586 /* Initialize the BAR register in config space */ 587 bar = (addr & mask) | lobits; 588 pci_set_cfgdata32(pdi, PCIR_BAR(idx), bar); 589 590 if (type == PCIBAR_MEM64) { 591 assert(idx + 1 <= PCI_BARMAX); 592 pdi->pi_bar[idx + 1].type = PCIBAR_MEMHI64; 593 pci_set_cfgdata32(pdi, PCIR_BAR(idx + 1), bar >> 32); 594 } 595 596 register_bar(pdi, idx); 597 598 return (0); 599 } 600 601 #define CAP_START_OFFSET 0x40 602 static int 603 pci_emul_add_capability(struct pci_devinst *pi, u_char *capdata, int caplen) 604 { 605 int i, capoff, capid, reallen; 606 uint16_t sts; 607 608 static u_char endofcap[4] = { 609 PCIY_RESERVED, 0, 0, 0 610 }; 611 612 assert(caplen > 0 && capdata[0] != PCIY_RESERVED); 613 614 reallen = roundup2(caplen, 4); /* dword aligned */ 615 616 sts = pci_get_cfgdata16(pi, PCIR_STATUS); 617 if ((sts & PCIM_STATUS_CAPPRESENT) == 0) { 618 capoff = CAP_START_OFFSET; 619 pci_set_cfgdata8(pi, PCIR_CAP_PTR, capoff); 620 pci_set_cfgdata16(pi, PCIR_STATUS, sts|PCIM_STATUS_CAPPRESENT); 621 } else { 622 capoff = pci_get_cfgdata8(pi, PCIR_CAP_PTR); 623 while (1) { 624 assert((capoff & 0x3) == 0); 625 capid = pci_get_cfgdata8(pi, capoff); 626 if (capid == PCIY_RESERVED) 627 break; 628 capoff = pci_get_cfgdata8(pi, capoff + 1); 629 } 630 } 631 632 /* Check if we have enough space */ 633 if (capoff + reallen + sizeof(endofcap) > PCI_REGMAX + 1) 634 return (-1); 635 636 /* Copy the capability */ 637 for (i = 0; i < caplen; i++) 638 pci_set_cfgdata8(pi, capoff + i, capdata[i]); 639 640 /* Set the next capability pointer */ 641 pci_set_cfgdata8(pi, capoff + 1, capoff + reallen); 642 643 /* Copy of the reserved capability which serves as the end marker */ 644 for (i = 0; i < sizeof(endofcap); i++) 645 pci_set_cfgdata8(pi, capoff + reallen + i, endofcap[i]); 646 647 return (0); 648 } 649 650 static struct pci_devemu * 651 pci_emul_finddev(char *name) 652 { 653 struct pci_devemu **pdpp, *pdp; 654 655 SET_FOREACH(pdpp, pci_devemu_set) { 656 pdp = *pdpp; 657 if (!strcmp(pdp->pe_emu, name)) { 658 return (pdp); 659 } 660 } 661 662 return (NULL); 663 } 664 665 static int 666 pci_emul_init(struct vmctx *ctx, struct pci_devemu *pde, int slot, int func, 667 char *params) 668 { 669 struct pci_devinst *pdi; 670 int err; 671 672 pdi = malloc(sizeof(struct pci_devinst)); 673 bzero(pdi, sizeof(*pdi)); 674 675 pdi->pi_vmctx = ctx; 676 pdi->pi_bus = 0; 677 pdi->pi_slot = slot; 678 pdi->pi_func = func; 679 pdi->pi_d = pde; 680 snprintf(pdi->pi_name, PI_NAMESZ, "%s-pci-%d", pde->pe_emu, slot); 681 682 /* Disable legacy interrupts */ 683 pci_set_cfgdata8(pdi, PCIR_INTLINE, 255); 684 pci_set_cfgdata8(pdi, PCIR_INTPIN, 0); 685 686 pci_set_cfgdata8(pdi, PCIR_COMMAND, 687 PCIM_CMD_PORTEN | PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN); 688 689 err = (*pde->pe_init)(ctx, pdi, params); 690 if (err != 0) { 691 free(pdi); 692 } else { 693 pci_emul_devices++; 694 pci_slotinfo[slot][func].si_devi = pdi; 695 } 696 697 return (err); 698 } 699 700 void 701 pci_populate_msicap(struct msicap *msicap, int msgnum, int nextptr) 702 { 703 int mmc; 704 705 CTASSERT(sizeof(struct msicap) == 14); 706 707 /* Number of msi messages must be a power of 2 between 1 and 32 */ 708 assert((msgnum & (msgnum - 1)) == 0 && msgnum >= 1 && msgnum <= 32); 709 mmc = ffs(msgnum) - 1; 710 711 bzero(msicap, sizeof(struct msicap)); 712 msicap->capid = PCIY_MSI; 713 msicap->nextptr = nextptr; 714 msicap->msgctrl = PCIM_MSICTRL_64BIT | (mmc << 1); 715 } 716 717 int 718 pci_emul_add_msicap(struct pci_devinst *pi, int msgnum) 719 { 720 struct msicap msicap; 721 722 pci_populate_msicap(&msicap, msgnum, 0); 723 724 return (pci_emul_add_capability(pi, (u_char *)&msicap, sizeof(msicap))); 725 } 726 727 static void 728 pci_populate_msixcap(struct msixcap *msixcap, int msgnum, int barnum, 729 uint32_t msix_tab_size, int nextptr) 730 { 731 CTASSERT(sizeof(struct msixcap) == 12); 732 733 assert(msix_tab_size % 4096 == 0); 734 735 bzero(msixcap, sizeof(struct msixcap)); 736 msixcap->capid = PCIY_MSIX; 737 msixcap->nextptr = nextptr; 738 739 /* 740 * Message Control Register, all fields set to 741 * zero except for the Table Size. 742 * Note: Table size N is encoded as N-1 743 */ 744 msixcap->msgctrl = msgnum - 1; 745 746 /* 747 * MSI-X BAR setup: 748 * - MSI-X table start at offset 0 749 * - PBA table starts at a 4K aligned offset after the MSI-X table 750 */ 751 msixcap->table_info = barnum & PCIM_MSIX_BIR_MASK; 752 msixcap->pba_info = msix_tab_size | (barnum & PCIM_MSIX_BIR_MASK); 753 } 754 755 static void 756 pci_msix_table_init(struct pci_devinst *pi, int table_entries) 757 { 758 int i, table_size; 759 760 assert(table_entries > 0); 761 assert(table_entries <= MAX_MSIX_TABLE_ENTRIES); 762 763 table_size = table_entries * MSIX_TABLE_ENTRY_SIZE; 764 pi->pi_msix.table = malloc(table_size); 765 bzero(pi->pi_msix.table, table_size); 766 767 /* set mask bit of vector control register */ 768 for (i = 0; i < table_entries; i++) 769 pi->pi_msix.table[i].vector_control |= PCIM_MSIX_VCTRL_MASK; 770 } 771 772 int 773 pci_emul_add_msixcap(struct pci_devinst *pi, int msgnum, int barnum) 774 { 775 uint16_t pba_index; 776 uint32_t tab_size; 777 struct msixcap msixcap; 778 779 assert(msgnum >= 1 && msgnum <= MAX_MSIX_TABLE_ENTRIES); 780 assert(barnum >= 0 && barnum <= PCIR_MAX_BAR_0); 781 782 tab_size = msgnum * MSIX_TABLE_ENTRY_SIZE; 783 784 /* Align table size to nearest 4K */ 785 tab_size = roundup2(tab_size, 4096); 786 787 pi->pi_msix.table_bar = barnum; 788 pi->pi_msix.pba_bar = barnum; 789 pi->pi_msix.table_offset = 0; 790 pi->pi_msix.table_count = msgnum; 791 pi->pi_msix.pba_offset = tab_size; 792 793 /* calculate the MMIO size required for MSI-X PBA */ 794 pba_index = (msgnum - 1) / (PBA_TABLE_ENTRY_SIZE * 8); 795 pi->pi_msix.pba_size = (pba_index + 1) * PBA_TABLE_ENTRY_SIZE; 796 797 pci_msix_table_init(pi, msgnum); 798 799 pci_populate_msixcap(&msixcap, msgnum, barnum, tab_size, 0); 800 801 /* allocate memory for MSI-X Table and PBA */ 802 pci_emul_alloc_bar(pi, barnum, PCIBAR_MEM32, 803 tab_size + pi->pi_msix.pba_size); 804 805 return (pci_emul_add_capability(pi, (u_char *)&msixcap, 806 sizeof(msixcap))); 807 } 808 809 void 810 msixcap_cfgwrite(struct pci_devinst *pi, int capoff, int offset, 811 int bytes, uint32_t val) 812 { 813 uint16_t msgctrl, rwmask; 814 int off, table_bar; 815 816 off = offset - capoff; 817 table_bar = pi->pi_msix.table_bar; 818 /* Message Control Register */ 819 if (off == 2 && bytes == 2) { 820 rwmask = PCIM_MSIXCTRL_MSIX_ENABLE | PCIM_MSIXCTRL_FUNCTION_MASK; 821 msgctrl = pci_get_cfgdata16(pi, offset); 822 msgctrl &= ~rwmask; 823 msgctrl |= val & rwmask; 824 val = msgctrl; 825 826 pi->pi_msix.enabled = val & PCIM_MSIXCTRL_MSIX_ENABLE; 827 pi->pi_msix.function_mask = val & PCIM_MSIXCTRL_FUNCTION_MASK; 828 } 829 830 CFGWRITE(pi, offset, val, bytes); 831 } 832 833 void 834 msicap_cfgwrite(struct pci_devinst *pi, int capoff, int offset, 835 int bytes, uint32_t val) 836 { 837 uint16_t msgctrl, rwmask, msgdata, mme; 838 uint32_t addrlo; 839 840 /* 841 * If guest is writing to the message control register make sure 842 * we do not overwrite read-only fields. 843 */ 844 if ((offset - capoff) == 2 && bytes == 2) { 845 rwmask = PCIM_MSICTRL_MME_MASK | PCIM_MSICTRL_MSI_ENABLE; 846 msgctrl = pci_get_cfgdata16(pi, offset); 847 msgctrl &= ~rwmask; 848 msgctrl |= val & rwmask; 849 val = msgctrl; 850 851 addrlo = pci_get_cfgdata32(pi, capoff + 4); 852 if (msgctrl & PCIM_MSICTRL_64BIT) 853 msgdata = pci_get_cfgdata16(pi, capoff + 12); 854 else 855 msgdata = pci_get_cfgdata16(pi, capoff + 8); 856 857 /* 858 * XXX check delivery mode, destination mode etc 859 */ 860 mme = msgctrl & PCIM_MSICTRL_MME_MASK; 861 pi->pi_msi.enabled = msgctrl & PCIM_MSICTRL_MSI_ENABLE ? 1 : 0; 862 if (pi->pi_msi.enabled) { 863 pi->pi_msi.cpu = (addrlo >> 12) & 0xff; 864 pi->pi_msi.vector = msgdata & 0xff; 865 pi->pi_msi.msgnum = 1 << (mme >> 4); 866 } else { 867 pi->pi_msi.cpu = 0; 868 pi->pi_msi.vector = 0; 869 pi->pi_msi.msgnum = 0; 870 } 871 } 872 873 CFGWRITE(pi, offset, val, bytes); 874 } 875 876 void 877 pciecap_cfgwrite(struct pci_devinst *pi, int capoff, int offset, 878 int bytes, uint32_t val) 879 { 880 881 /* XXX don't write to the readonly parts */ 882 CFGWRITE(pi, offset, val, bytes); 883 } 884 885 #define PCIECAP_VERSION 0x2 886 int 887 pci_emul_add_pciecap(struct pci_devinst *pi, int type) 888 { 889 int err; 890 struct pciecap pciecap; 891 892 CTASSERT(sizeof(struct pciecap) == 60); 893 894 if (type != PCIEM_TYPE_ROOT_PORT) 895 return (-1); 896 897 bzero(&pciecap, sizeof(pciecap)); 898 899 pciecap.capid = PCIY_EXPRESS; 900 pciecap.pcie_capabilities = PCIECAP_VERSION | PCIEM_TYPE_ROOT_PORT; 901 pciecap.link_capabilities = 0x411; /* gen1, x1 */ 902 pciecap.link_status = 0x11; /* gen1, x1 */ 903 904 err = pci_emul_add_capability(pi, (u_char *)&pciecap, sizeof(pciecap)); 905 return (err); 906 } 907 908 /* 909 * This function assumes that 'coff' is in the capabilities region of the 910 * config space. 911 */ 912 static void 913 pci_emul_capwrite(struct pci_devinst *pi, int offset, int bytes, uint32_t val) 914 { 915 int capid; 916 uint8_t capoff, nextoff; 917 918 /* Do not allow un-aligned writes */ 919 if ((offset & (bytes - 1)) != 0) 920 return; 921 922 /* Find the capability that we want to update */ 923 capoff = CAP_START_OFFSET; 924 while (1) { 925 capid = pci_get_cfgdata8(pi, capoff); 926 if (capid == PCIY_RESERVED) 927 break; 928 929 nextoff = pci_get_cfgdata8(pi, capoff + 1); 930 if (offset >= capoff && offset < nextoff) 931 break; 932 933 capoff = nextoff; 934 } 935 assert(offset >= capoff); 936 937 /* 938 * Capability ID and Next Capability Pointer are readonly 939 */ 940 if (offset == capoff || offset == capoff + 1) 941 return; 942 943 switch (capid) { 944 case PCIY_MSI: 945 msicap_cfgwrite(pi, capoff, offset, bytes, val); 946 break; 947 case PCIY_MSIX: 948 msixcap_cfgwrite(pi, capoff, offset, bytes, val); 949 break; 950 case PCIY_EXPRESS: 951 pciecap_cfgwrite(pi, capoff, offset, bytes, val); 952 break; 953 default: 954 break; 955 } 956 } 957 958 static int 959 pci_emul_iscap(struct pci_devinst *pi, int offset) 960 { 961 int found; 962 uint16_t sts; 963 uint8_t capid, lastoff; 964 965 found = 0; 966 sts = pci_get_cfgdata16(pi, PCIR_STATUS); 967 if ((sts & PCIM_STATUS_CAPPRESENT) != 0) { 968 lastoff = pci_get_cfgdata8(pi, PCIR_CAP_PTR); 969 while (1) { 970 assert((lastoff & 0x3) == 0); 971 capid = pci_get_cfgdata8(pi, lastoff); 972 if (capid == PCIY_RESERVED) 973 break; 974 lastoff = pci_get_cfgdata8(pi, lastoff + 1); 975 } 976 if (offset >= CAP_START_OFFSET && offset <= lastoff) 977 found = 1; 978 } 979 return (found); 980 } 981 982 static int 983 pci_emul_fallback_handler(struct vmctx *ctx, int vcpu, int dir, uint64_t addr, 984 int size, uint64_t *val, void *arg1, long arg2) 985 { 986 /* 987 * Ignore writes; return 0xff's for reads. The mem read code 988 * will take care of truncating to the correct size. 989 */ 990 if (dir == MEM_F_READ) { 991 *val = 0xffffffffffffffff; 992 } 993 994 return (0); 995 } 996 997 int 998 init_pci(struct vmctx *ctx) 999 { 1000 struct mem_range memp; 1001 struct pci_devemu *pde; 1002 struct slotinfo *si; 1003 size_t lowmem; 1004 int slot, func; 1005 int error; 1006 1007 pci_emul_iobase = PCI_EMUL_IOBASE; 1008 pci_emul_membase32 = vm_get_lowmem_limit(ctx); 1009 pci_emul_membase64 = PCI_EMUL_MEMBASE64; 1010 1011 for (slot = 0; slot < MAXSLOTS; slot++) { 1012 for (func = 0; func < MAXFUNCS; func++) { 1013 si = &pci_slotinfo[slot][func]; 1014 if (si->si_name != NULL) { 1015 pde = pci_emul_finddev(si->si_name); 1016 assert(pde != NULL); 1017 error = pci_emul_init(ctx, pde, slot, func, 1018 si->si_param); 1019 if (error) 1020 return (error); 1021 } 1022 } 1023 } 1024 1025 /* 1026 * Allow ISA IRQs 5,10,11,12, and 15 to be available for 1027 * generic use 1028 */ 1029 lirq[5].li_generic = 1; 1030 lirq[10].li_generic = 1; 1031 lirq[11].li_generic = 1; 1032 lirq[12].li_generic = 1; 1033 lirq[15].li_generic = 1; 1034 1035 /* 1036 * The guest physical memory map looks like the following: 1037 * [0, lowmem) guest system memory 1038 * [lowmem, lowmem_limit) memory hole (may be absent) 1039 * [lowmem_limit, 4GB) PCI hole (32-bit BAR allocation) 1040 * [4GB, 4GB + highmem) 1041 * 1042 * Accesses to memory addresses that are not allocated to system 1043 * memory or PCI devices return 0xff's. 1044 */ 1045 error = vm_get_memory_seg(ctx, 0, &lowmem); 1046 assert(error == 0); 1047 1048 memset(&memp, 0, sizeof(struct mem_range)); 1049 memp.name = "PCI hole"; 1050 memp.flags = MEM_F_RW; 1051 memp.base = lowmem; 1052 memp.size = (4ULL * 1024 * 1024 * 1024) - lowmem; 1053 memp.handler = pci_emul_fallback_handler; 1054 1055 error = register_mem_fallback(&memp); 1056 assert(error == 0); 1057 1058 return (0); 1059 } 1060 1061 int 1062 pci_msi_enabled(struct pci_devinst *pi) 1063 { 1064 return (pi->pi_msi.enabled); 1065 } 1066 1067 int 1068 pci_msi_msgnum(struct pci_devinst *pi) 1069 { 1070 if (pi->pi_msi.enabled) 1071 return (pi->pi_msi.msgnum); 1072 else 1073 return (0); 1074 } 1075 1076 int 1077 pci_msix_enabled(struct pci_devinst *pi) 1078 { 1079 1080 return (pi->pi_msix.enabled && !pi->pi_msi.enabled); 1081 } 1082 1083 void 1084 pci_generate_msix(struct pci_devinst *pi, int index) 1085 { 1086 struct msix_table_entry *mte; 1087 1088 if (!pci_msix_enabled(pi)) 1089 return; 1090 1091 if (pi->pi_msix.function_mask) 1092 return; 1093 1094 if (index >= pi->pi_msix.table_count) 1095 return; 1096 1097 mte = &pi->pi_msix.table[index]; 1098 if ((mte->vector_control & PCIM_MSIX_VCTRL_MASK) == 0) { 1099 /* XXX Set PBA bit if interrupt is disabled */ 1100 vm_lapic_irq(pi->pi_vmctx, 1101 (mte->addr >> 12) & 0xff, mte->msg_data & 0xff); 1102 } 1103 } 1104 1105 void 1106 pci_generate_msi(struct pci_devinst *pi, int msg) 1107 { 1108 1109 if (pci_msi_enabled(pi) && msg < pci_msi_msgnum(pi)) { 1110 vm_lapic_irq(pi->pi_vmctx, 1111 pi->pi_msi.cpu, 1112 pi->pi_msi.vector + msg); 1113 } 1114 } 1115 1116 int 1117 pci_is_legacy(struct pci_devinst *pi) 1118 { 1119 1120 return (pci_slotinfo[pi->pi_slot][pi->pi_func].si_legacy); 1121 } 1122 1123 static int 1124 pci_lintr_alloc(struct pci_devinst *pi, int vec) 1125 { 1126 int i; 1127 1128 assert(vec < NLIRQ); 1129 1130 if (vec == -1) { 1131 for (i = 0; i < NLIRQ; i++) { 1132 if (lirq[i].li_generic && 1133 lirq[i].li_owner == NULL) { 1134 vec = i; 1135 break; 1136 } 1137 } 1138 } else { 1139 if (lirq[vec].li_owner != NULL) { 1140 vec = -1; 1141 } 1142 } 1143 assert(vec != -1); 1144 1145 lirq[vec].li_owner = pi; 1146 pi->pi_lintr_pin = vec; 1147 1148 return (vec); 1149 } 1150 1151 int 1152 pci_lintr_request(struct pci_devinst *pi, int vec) 1153 { 1154 1155 vec = pci_lintr_alloc(pi, vec); 1156 pci_set_cfgdata8(pi, PCIR_INTLINE, vec); 1157 pci_set_cfgdata8(pi, PCIR_INTPIN, 1); 1158 return (0); 1159 } 1160 1161 void 1162 pci_lintr_assert(struct pci_devinst *pi) 1163 { 1164 1165 assert(pi->pi_lintr_pin); 1166 ioapic_assert_pin(pi->pi_vmctx, pi->pi_lintr_pin); 1167 } 1168 1169 void 1170 pci_lintr_deassert(struct pci_devinst *pi) 1171 { 1172 1173 assert(pi->pi_lintr_pin); 1174 ioapic_deassert_pin(pi->pi_vmctx, pi->pi_lintr_pin); 1175 } 1176 1177 /* 1178 * Return 1 if the emulated device in 'slot' is a multi-function device. 1179 * Return 0 otherwise. 1180 */ 1181 static int 1182 pci_emul_is_mfdev(int slot) 1183 { 1184 int f, numfuncs; 1185 1186 numfuncs = 0; 1187 for (f = 0; f < MAXFUNCS; f++) { 1188 if (pci_slotinfo[slot][f].si_devi != NULL) { 1189 numfuncs++; 1190 } 1191 } 1192 return (numfuncs > 1); 1193 } 1194 1195 /* 1196 * Ensure that the PCIM_MFDEV bit is properly set (or unset) depending on 1197 * whether or not is a multi-function being emulated in the pci 'slot'. 1198 */ 1199 static void 1200 pci_emul_hdrtype_fixup(int slot, int off, int bytes, uint32_t *rv) 1201 { 1202 int mfdev; 1203 1204 if (off <= PCIR_HDRTYPE && off + bytes > PCIR_HDRTYPE) { 1205 mfdev = pci_emul_is_mfdev(slot); 1206 switch (bytes) { 1207 case 1: 1208 case 2: 1209 *rv &= ~PCIM_MFDEV; 1210 if (mfdev) { 1211 *rv |= PCIM_MFDEV; 1212 } 1213 break; 1214 case 4: 1215 *rv &= ~(PCIM_MFDEV << 16); 1216 if (mfdev) { 1217 *rv |= (PCIM_MFDEV << 16); 1218 } 1219 break; 1220 } 1221 } 1222 } 1223 1224 static int cfgbus, cfgslot, cfgfunc, cfgoff; 1225 1226 static int 1227 pci_emul_cfgaddr(struct vmctx *ctx, int vcpu, int in, int port, int bytes, 1228 uint32_t *eax, void *arg) 1229 { 1230 uint32_t x; 1231 1232 if (bytes != 4) { 1233 if (in) 1234 *eax = (bytes == 2) ? 0xffff : 0xff; 1235 return (0); 1236 } 1237 1238 if (in) { 1239 x = (cfgbus << 16) | 1240 (cfgslot << 11) | 1241 (cfgfunc << 8) | 1242 cfgoff; 1243 *eax = x | CONF1_ENABLE; 1244 } else { 1245 x = *eax; 1246 cfgoff = x & PCI_REGMAX; 1247 cfgfunc = (x >> 8) & PCI_FUNCMAX; 1248 cfgslot = (x >> 11) & PCI_SLOTMAX; 1249 cfgbus = (x >> 16) & PCI_BUSMAX; 1250 } 1251 1252 return (0); 1253 } 1254 INOUT_PORT(pci_cfgaddr, CONF1_ADDR_PORT, IOPORT_F_INOUT, pci_emul_cfgaddr); 1255 1256 static uint32_t 1257 bits_changed(uint32_t old, uint32_t new, uint32_t mask) 1258 { 1259 1260 return ((old ^ new) & mask); 1261 } 1262 1263 static void 1264 pci_emul_cmdwrite(struct pci_devinst *pi, uint32_t new, int bytes) 1265 { 1266 int i; 1267 uint16_t old; 1268 1269 /* 1270 * The command register is at an offset of 4 bytes and thus the 1271 * guest could write 1, 2 or 4 bytes starting at this offset. 1272 */ 1273 1274 old = pci_get_cfgdata16(pi, PCIR_COMMAND); /* stash old value */ 1275 CFGWRITE(pi, PCIR_COMMAND, new, bytes); /* update config */ 1276 new = pci_get_cfgdata16(pi, PCIR_COMMAND); /* get updated value */ 1277 1278 /* 1279 * If the MMIO or I/O address space decoding has changed then 1280 * register/unregister all BARs that decode that address space. 1281 */ 1282 for (i = 0; i < PCI_BARMAX; i++) { 1283 switch (pi->pi_bar[i].type) { 1284 case PCIBAR_NONE: 1285 case PCIBAR_MEMHI64: 1286 break; 1287 case PCIBAR_IO: 1288 /* I/O address space decoding changed? */ 1289 if (bits_changed(old, new, PCIM_CMD_PORTEN)) { 1290 if (porten(pi)) 1291 register_bar(pi, i); 1292 else 1293 unregister_bar(pi, i); 1294 } 1295 break; 1296 case PCIBAR_MEM32: 1297 case PCIBAR_MEM64: 1298 /* MMIO address space decoding changed? */ 1299 if (bits_changed(old, new, PCIM_CMD_MEMEN)) { 1300 if (memen(pi)) 1301 register_bar(pi, i); 1302 else 1303 unregister_bar(pi, i); 1304 } 1305 break; 1306 default: 1307 assert(0); 1308 } 1309 } 1310 } 1311 1312 static int 1313 pci_emul_cfgdata(struct vmctx *ctx, int vcpu, int in, int port, int bytes, 1314 uint32_t *eax, void *arg) 1315 { 1316 struct pci_devinst *pi; 1317 struct pci_devemu *pe; 1318 int coff, idx, needcfg; 1319 uint64_t addr, bar, mask; 1320 1321 assert(bytes == 1 || bytes == 2 || bytes == 4); 1322 1323 if (cfgbus == 0) 1324 pi = pci_slotinfo[cfgslot][cfgfunc].si_devi; 1325 else 1326 pi = NULL; 1327 1328 coff = cfgoff + (port - CONF1_DATA_PORT); 1329 1330 #if 0 1331 printf("pcicfg-%s from 0x%0x of %d bytes (%d/%d/%d)\n\r", 1332 in ? "read" : "write", coff, bytes, cfgbus, cfgslot, cfgfunc); 1333 #endif 1334 1335 /* 1336 * Just return if there is no device at this cfgslot:cfgfunc or 1337 * if the guest is doing an un-aligned access 1338 */ 1339 if (pi == NULL || (coff & (bytes - 1)) != 0) { 1340 if (in) 1341 *eax = 0xffffffff; 1342 return (0); 1343 } 1344 1345 pe = pi->pi_d; 1346 1347 /* 1348 * Config read 1349 */ 1350 if (in) { 1351 /* Let the device emulation override the default handler */ 1352 if (pe->pe_cfgread != NULL) { 1353 needcfg = pe->pe_cfgread(ctx, vcpu, pi, 1354 coff, bytes, eax); 1355 } else { 1356 needcfg = 1; 1357 } 1358 1359 if (needcfg) { 1360 if (bytes == 1) 1361 *eax = pci_get_cfgdata8(pi, coff); 1362 else if (bytes == 2) 1363 *eax = pci_get_cfgdata16(pi, coff); 1364 else 1365 *eax = pci_get_cfgdata32(pi, coff); 1366 } 1367 1368 pci_emul_hdrtype_fixup(cfgslot, coff, bytes, eax); 1369 } else { 1370 /* Let the device emulation override the default handler */ 1371 if (pe->pe_cfgwrite != NULL && 1372 (*pe->pe_cfgwrite)(ctx, vcpu, pi, coff, bytes, *eax) == 0) 1373 return (0); 1374 1375 /* 1376 * Special handling for write to BAR registers 1377 */ 1378 if (coff >= PCIR_BAR(0) && coff < PCIR_BAR(PCI_BARMAX + 1)) { 1379 /* 1380 * Ignore writes to BAR registers that are not 1381 * 4-byte aligned. 1382 */ 1383 if (bytes != 4 || (coff & 0x3) != 0) 1384 return (0); 1385 idx = (coff - PCIR_BAR(0)) / 4; 1386 mask = ~(pi->pi_bar[idx].size - 1); 1387 switch (pi->pi_bar[idx].type) { 1388 case PCIBAR_NONE: 1389 pi->pi_bar[idx].addr = bar = 0; 1390 break; 1391 case PCIBAR_IO: 1392 addr = *eax & mask; 1393 addr &= 0xffff; 1394 bar = addr | PCIM_BAR_IO_SPACE; 1395 /* 1396 * Register the new BAR value for interception 1397 */ 1398 if (addr != pi->pi_bar[idx].addr) { 1399 update_bar_address(pi, addr, idx, 1400 PCIBAR_IO); 1401 } 1402 break; 1403 case PCIBAR_MEM32: 1404 addr = bar = *eax & mask; 1405 bar |= PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_32; 1406 if (addr != pi->pi_bar[idx].addr) { 1407 update_bar_address(pi, addr, idx, 1408 PCIBAR_MEM32); 1409 } 1410 break; 1411 case PCIBAR_MEM64: 1412 addr = bar = *eax & mask; 1413 bar |= PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_64 | 1414 PCIM_BAR_MEM_PREFETCH; 1415 if (addr != (uint32_t)pi->pi_bar[idx].addr) { 1416 update_bar_address(pi, addr, idx, 1417 PCIBAR_MEM64); 1418 } 1419 break; 1420 case PCIBAR_MEMHI64: 1421 mask = ~(pi->pi_bar[idx - 1].size - 1); 1422 addr = ((uint64_t)*eax << 32) & mask; 1423 bar = addr >> 32; 1424 if (bar != pi->pi_bar[idx - 1].addr >> 32) { 1425 update_bar_address(pi, addr, idx - 1, 1426 PCIBAR_MEMHI64); 1427 } 1428 break; 1429 default: 1430 assert(0); 1431 } 1432 pci_set_cfgdata32(pi, coff, bar); 1433 1434 } else if (pci_emul_iscap(pi, coff)) { 1435 pci_emul_capwrite(pi, coff, bytes, *eax); 1436 } else if (coff == PCIR_COMMAND) { 1437 pci_emul_cmdwrite(pi, *eax, bytes); 1438 } else { 1439 CFGWRITE(pi, coff, *eax, bytes); 1440 } 1441 } 1442 1443 return (0); 1444 } 1445 1446 INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+0, IOPORT_F_INOUT, pci_emul_cfgdata); 1447 INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+1, IOPORT_F_INOUT, pci_emul_cfgdata); 1448 INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+2, IOPORT_F_INOUT, pci_emul_cfgdata); 1449 INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+3, IOPORT_F_INOUT, pci_emul_cfgdata); 1450 1451 /* 1452 * I/O ports to configure PCI IRQ routing. We ignore all writes to it. 1453 */ 1454 static int 1455 pci_irq_port_handler(struct vmctx *ctx, int vcpu, int in, int port, int bytes, 1456 uint32_t *eax, void *arg) 1457 { 1458 assert(in == 0); 1459 return (0); 1460 } 1461 INOUT_PORT(pci_irq, 0xC00, IOPORT_F_OUT, pci_irq_port_handler); 1462 INOUT_PORT(pci_irq, 0xC01, IOPORT_F_OUT, pci_irq_port_handler); 1463 1464 #define PCI_EMUL_TEST 1465 #ifdef PCI_EMUL_TEST 1466 /* 1467 * Define a dummy test device 1468 */ 1469 #define DIOSZ 20 1470 #define DMEMSZ 4096 1471 struct pci_emul_dsoftc { 1472 uint8_t ioregs[DIOSZ]; 1473 uint8_t memregs[DMEMSZ]; 1474 }; 1475 1476 #define PCI_EMUL_MSI_MSGS 4 1477 #define PCI_EMUL_MSIX_MSGS 16 1478 1479 static int 1480 pci_emul_dinit(struct vmctx *ctx, struct pci_devinst *pi, char *opts) 1481 { 1482 int error; 1483 struct pci_emul_dsoftc *sc; 1484 1485 sc = malloc(sizeof(struct pci_emul_dsoftc)); 1486 memset(sc, 0, sizeof(struct pci_emul_dsoftc)); 1487 1488 pi->pi_arg = sc; 1489 1490 pci_set_cfgdata16(pi, PCIR_DEVICE, 0x0001); 1491 pci_set_cfgdata16(pi, PCIR_VENDOR, 0x10DD); 1492 pci_set_cfgdata8(pi, PCIR_CLASS, 0x02); 1493 1494 error = pci_emul_add_msicap(pi, PCI_EMUL_MSI_MSGS); 1495 assert(error == 0); 1496 1497 error = pci_emul_alloc_bar(pi, 0, PCIBAR_IO, DIOSZ); 1498 assert(error == 0); 1499 1500 error = pci_emul_alloc_bar(pi, 1, PCIBAR_MEM32, DMEMSZ); 1501 assert(error == 0); 1502 1503 return (0); 1504 } 1505 1506 static void 1507 pci_emul_diow(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, int baridx, 1508 uint64_t offset, int size, uint64_t value) 1509 { 1510 int i; 1511 struct pci_emul_dsoftc *sc = pi->pi_arg; 1512 1513 if (baridx == 0) { 1514 if (offset + size > DIOSZ) { 1515 printf("diow: iow too large, offset %ld size %d\n", 1516 offset, size); 1517 return; 1518 } 1519 1520 if (size == 1) { 1521 sc->ioregs[offset] = value & 0xff; 1522 } else if (size == 2) { 1523 *(uint16_t *)&sc->ioregs[offset] = value & 0xffff; 1524 } else if (size == 4) { 1525 *(uint32_t *)&sc->ioregs[offset] = value; 1526 } else { 1527 printf("diow: iow unknown size %d\n", size); 1528 } 1529 1530 /* 1531 * Special magic value to generate an interrupt 1532 */ 1533 if (offset == 4 && size == 4 && pci_msi_enabled(pi)) 1534 pci_generate_msi(pi, value % pci_msi_msgnum(pi)); 1535 1536 if (value == 0xabcdef) { 1537 for (i = 0; i < pci_msi_msgnum(pi); i++) 1538 pci_generate_msi(pi, i); 1539 } 1540 } 1541 1542 if (baridx == 1) { 1543 if (offset + size > DMEMSZ) { 1544 printf("diow: memw too large, offset %ld size %d\n", 1545 offset, size); 1546 return; 1547 } 1548 1549 if (size == 1) { 1550 sc->memregs[offset] = value; 1551 } else if (size == 2) { 1552 *(uint16_t *)&sc->memregs[offset] = value; 1553 } else if (size == 4) { 1554 *(uint32_t *)&sc->memregs[offset] = value; 1555 } else if (size == 8) { 1556 *(uint64_t *)&sc->memregs[offset] = value; 1557 } else { 1558 printf("diow: memw unknown size %d\n", size); 1559 } 1560 1561 /* 1562 * magic interrupt ?? 1563 */ 1564 } 1565 1566 if (baridx > 1) { 1567 printf("diow: unknown bar idx %d\n", baridx); 1568 } 1569 } 1570 1571 static uint64_t 1572 pci_emul_dior(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, int baridx, 1573 uint64_t offset, int size) 1574 { 1575 struct pci_emul_dsoftc *sc = pi->pi_arg; 1576 uint32_t value; 1577 1578 if (baridx == 0) { 1579 if (offset + size > DIOSZ) { 1580 printf("dior: ior too large, offset %ld size %d\n", 1581 offset, size); 1582 return (0); 1583 } 1584 1585 if (size == 1) { 1586 value = sc->ioregs[offset]; 1587 } else if (size == 2) { 1588 value = *(uint16_t *) &sc->ioregs[offset]; 1589 } else if (size == 4) { 1590 value = *(uint32_t *) &sc->ioregs[offset]; 1591 } else { 1592 printf("dior: ior unknown size %d\n", size); 1593 } 1594 } 1595 1596 if (baridx == 1) { 1597 if (offset + size > DMEMSZ) { 1598 printf("dior: memr too large, offset %ld size %d\n", 1599 offset, size); 1600 return (0); 1601 } 1602 1603 if (size == 1) { 1604 value = sc->memregs[offset]; 1605 } else if (size == 2) { 1606 value = *(uint16_t *) &sc->memregs[offset]; 1607 } else if (size == 4) { 1608 value = *(uint32_t *) &sc->memregs[offset]; 1609 } else if (size == 8) { 1610 value = *(uint64_t *) &sc->memregs[offset]; 1611 } else { 1612 printf("dior: ior unknown size %d\n", size); 1613 } 1614 } 1615 1616 1617 if (baridx > 1) { 1618 printf("dior: unknown bar idx %d\n", baridx); 1619 return (0); 1620 } 1621 1622 return (value); 1623 } 1624 1625 struct pci_devemu pci_dummy = { 1626 .pe_emu = "dummy", 1627 .pe_init = pci_emul_dinit, 1628 .pe_barwrite = pci_emul_diow, 1629 .pe_barread = pci_emul_dior 1630 }; 1631 PCI_EMUL_SET(pci_dummy); 1632 1633 #endif /* PCI_EMUL_TEST */ 1634