xref: /freebsd/usr.sbin/bhyve/pci_emul.c (revision 9f23cbd6cae82fd77edfad7173432fa8dccd0a95)
1 /*-
2  * SPDX-License-Identifier: BSD-2-Clause
3  *
4  * Copyright (c) 2011 NetApp, Inc.
5  * All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  * 1. Redistributions of source code must retain the above copyright
11  *    notice, this list of conditions and the following disclaimer.
12  * 2. Redistributions in binary form must reproduce the above copyright
13  *    notice, this list of conditions and the following disclaimer in the
14  *    documentation and/or other materials provided with the distribution.
15  *
16  * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19  * ARE DISCLAIMED.  IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
20  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26  * SUCH DAMAGE.
27  *
28  * $FreeBSD$
29  */
30 
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
33 
34 #include <sys/param.h>
35 #include <sys/linker_set.h>
36 #include <sys/mman.h>
37 
38 #include <ctype.h>
39 #include <err.h>
40 #include <errno.h>
41 #include <pthread.h>
42 #include <stdio.h>
43 #include <stdlib.h>
44 #include <string.h>
45 #include <strings.h>
46 #include <assert.h>
47 #include <stdbool.h>
48 #include <sysexits.h>
49 
50 #include <machine/vmm.h>
51 #include <machine/vmm_snapshot.h>
52 #include <vmmapi.h>
53 
54 #include "acpi.h"
55 #include "bhyverun.h"
56 #include "config.h"
57 #include "debug.h"
58 #include "inout.h"
59 #include "ioapic.h"
60 #include "mem.h"
61 #include "pci_emul.h"
62 #include "pci_irq.h"
63 #include "pci_lpc.h"
64 #include "pci_passthru.h"
65 #include "qemu_fwcfg.h"
66 
67 #define CONF1_ADDR_PORT	   0x0cf8
68 #define CONF1_DATA_PORT	   0x0cfc
69 
70 #define CONF1_ENABLE	   0x80000000ul
71 
72 #define	MAXBUSES	(PCI_BUSMAX + 1)
73 #define MAXSLOTS	(PCI_SLOTMAX + 1)
74 #define	MAXFUNCS	(PCI_FUNCMAX + 1)
75 
76 #define GB		(1024 * 1024 * 1024UL)
77 
78 struct funcinfo {
79 	nvlist_t *fi_config;
80 	struct pci_devemu *fi_pde;
81 	struct pci_devinst *fi_devi;
82 };
83 
84 struct intxinfo {
85 	int	ii_count;
86 	int	ii_pirq_pin;
87 	int	ii_ioapic_irq;
88 };
89 
90 struct slotinfo {
91 	struct intxinfo si_intpins[4];
92 	struct funcinfo si_funcs[MAXFUNCS];
93 };
94 
95 struct businfo {
96 	uint16_t iobase, iolimit;		/* I/O window */
97 	uint32_t membase32, memlimit32;		/* mmio window below 4GB */
98 	uint64_t membase64, memlimit64;		/* mmio window above 4GB */
99 	struct slotinfo slotinfo[MAXSLOTS];
100 };
101 
102 static struct businfo *pci_businfo[MAXBUSES];
103 
104 SET_DECLARE(pci_devemu_set, struct pci_devemu);
105 
106 static uint64_t pci_emul_iobase;
107 static uint8_t *pci_emul_rombase;
108 static uint64_t pci_emul_romoffset;
109 static uint8_t *pci_emul_romlim;
110 static uint64_t pci_emul_membase32;
111 static uint64_t pci_emul_membase64;
112 static uint64_t pci_emul_memlim64;
113 
114 struct pci_bar_allocation {
115 	TAILQ_ENTRY(pci_bar_allocation) chain;
116 	struct pci_devinst *pdi;
117 	int idx;
118 	enum pcibar_type type;
119 	uint64_t size;
120 };
121 
122 static TAILQ_HEAD(pci_bar_list, pci_bar_allocation) pci_bars =
123     TAILQ_HEAD_INITIALIZER(pci_bars);
124 
125 struct boot_device {
126 	TAILQ_ENTRY(boot_device) boot_device_chain;
127 	struct pci_devinst *pdi;
128 	int bootindex;
129 };
130 static TAILQ_HEAD(boot_list, boot_device) boot_devices = TAILQ_HEAD_INITIALIZER(
131     boot_devices);
132 
133 #define	PCI_EMUL_IOBASE		0x2000
134 #define	PCI_EMUL_IOLIMIT	0x10000
135 
136 #define PCI_EMUL_ROMSIZE 0x10000000
137 
138 #define	PCI_EMUL_ECFG_BASE	0xE0000000		    /* 3.5GB */
139 #define	PCI_EMUL_ECFG_SIZE	(MAXBUSES * 1024 * 1024)    /* 1MB per bus */
140 SYSRES_MEM(PCI_EMUL_ECFG_BASE, PCI_EMUL_ECFG_SIZE);
141 
142 /*
143  * OVMF always uses 0xC0000000 as base address for 32 bit PCI MMIO. Don't
144  * change this address without changing it in OVMF.
145  */
146 #define PCI_EMUL_MEMBASE32 0xC0000000
147 #define	PCI_EMUL_MEMLIMIT32	PCI_EMUL_ECFG_BASE
148 #define PCI_EMUL_MEMSIZE64	(32*GB)
149 
150 static struct pci_devemu *pci_emul_finddev(const char *name);
151 static void pci_lintr_route(struct pci_devinst *pi);
152 static void pci_lintr_update(struct pci_devinst *pi);
153 static void pci_cfgrw(int in, int bus, int slot, int func, int coff,
154     int bytes, uint32_t *val);
155 
156 static __inline void
157 CFGWRITE(struct pci_devinst *pi, int coff, uint32_t val, int bytes)
158 {
159 
160 	if (bytes == 1)
161 		pci_set_cfgdata8(pi, coff, val);
162 	else if (bytes == 2)
163 		pci_set_cfgdata16(pi, coff, val);
164 	else
165 		pci_set_cfgdata32(pi, coff, val);
166 }
167 
168 static __inline uint32_t
169 CFGREAD(struct pci_devinst *pi, int coff, int bytes)
170 {
171 
172 	if (bytes == 1)
173 		return (pci_get_cfgdata8(pi, coff));
174 	else if (bytes == 2)
175 		return (pci_get_cfgdata16(pi, coff));
176 	else
177 		return (pci_get_cfgdata32(pi, coff));
178 }
179 
180 static int
181 is_pcir_bar(int coff)
182 {
183 	return (coff >= PCIR_BAR(0) && coff < PCIR_BAR(PCI_BARMAX + 1));
184 }
185 
186 static int
187 is_pcir_bios(int coff)
188 {
189 	return (coff >= PCIR_BIOS && coff < PCIR_BIOS + 4);
190 }
191 
192 /*
193  * I/O access
194  */
195 
196 /*
197  * Slot options are in the form:
198  *
199  *  <bus>:<slot>:<func>,<emul>[,<config>]
200  *  <slot>[:<func>],<emul>[,<config>]
201  *
202  *  slot is 0..31
203  *  func is 0..7
204  *  emul is a string describing the type of PCI device e.g. virtio-net
205  *  config is an optional string, depending on the device, that can be
206  *  used for configuration.
207  *   Examples are:
208  *     1,virtio-net,tap0
209  *     3:0,dummy
210  */
211 static void
212 pci_parse_slot_usage(char *aopt)
213 {
214 
215 	EPRINTLN("Invalid PCI slot info field \"%s\"", aopt);
216 }
217 
218 /*
219  * Helper function to parse a list of comma-separated options where
220  * each option is formatted as "name[=value]".  If no value is
221  * provided, the option is treated as a boolean and is given a value
222  * of true.
223  */
224 int
225 pci_parse_legacy_config(nvlist_t *nvl, const char *opt)
226 {
227 	char *config, *name, *tofree, *value;
228 
229 	if (opt == NULL)
230 		return (0);
231 
232 	config = tofree = strdup(opt);
233 	while ((name = strsep(&config, ",")) != NULL) {
234 		value = strchr(name, '=');
235 		if (value != NULL) {
236 			*value = '\0';
237 			value++;
238 			set_config_value_node(nvl, name, value);
239 		} else
240 			set_config_bool_node(nvl, name, true);
241 	}
242 	free(tofree);
243 	return (0);
244 }
245 
246 /*
247  * PCI device configuration is stored in MIBs that encode the device's
248  * location:
249  *
250  * pci.<bus>.<slot>.<func>
251  *
252  * Where "bus", "slot", and "func" are all decimal values without
253  * leading zeroes.  Each valid device must have a "device" node which
254  * identifies the driver model of the device.
255  *
256  * Device backends can provide a parser for the "config" string.  If
257  * a custom parser is not provided, pci_parse_legacy_config() is used
258  * to parse the string.
259  */
260 int
261 pci_parse_slot(char *opt)
262 {
263 	char node_name[sizeof("pci.XXX.XX.X")];
264 	struct pci_devemu *pde;
265 	char *emul, *config, *str, *cp;
266 	int error, bnum, snum, fnum;
267 	nvlist_t *nvl;
268 
269 	error = -1;
270 	str = strdup(opt);
271 
272 	emul = config = NULL;
273 	if ((cp = strchr(str, ',')) != NULL) {
274 		*cp = '\0';
275 		emul = cp + 1;
276 		if ((cp = strchr(emul, ',')) != NULL) {
277 			*cp = '\0';
278 			config = cp + 1;
279 		}
280 	} else {
281 		pci_parse_slot_usage(opt);
282 		goto done;
283 	}
284 
285 	/* <bus>:<slot>:<func> */
286 	if (sscanf(str, "%d:%d:%d", &bnum, &snum, &fnum) != 3) {
287 		bnum = 0;
288 		/* <slot>:<func> */
289 		if (sscanf(str, "%d:%d", &snum, &fnum) != 2) {
290 			fnum = 0;
291 			/* <slot> */
292 			if (sscanf(str, "%d", &snum) != 1) {
293 				snum = -1;
294 			}
295 		}
296 	}
297 
298 	if (bnum < 0 || bnum >= MAXBUSES || snum < 0 || snum >= MAXSLOTS ||
299 	    fnum < 0 || fnum >= MAXFUNCS) {
300 		pci_parse_slot_usage(opt);
301 		goto done;
302 	}
303 
304 	pde = pci_emul_finddev(emul);
305 	if (pde == NULL) {
306 		EPRINTLN("pci slot %d:%d:%d: unknown device \"%s\"", bnum, snum,
307 		    fnum, emul);
308 		goto done;
309 	}
310 
311 	snprintf(node_name, sizeof(node_name), "pci.%d.%d.%d", bnum, snum,
312 	    fnum);
313 	nvl = find_config_node(node_name);
314 	if (nvl != NULL) {
315 		EPRINTLN("pci slot %d:%d:%d already occupied!", bnum, snum,
316 		    fnum);
317 		goto done;
318 	}
319 	nvl = create_config_node(node_name);
320 	if (pde->pe_alias != NULL)
321 		set_config_value_node(nvl, "device", pde->pe_alias);
322 	else
323 		set_config_value_node(nvl, "device", pde->pe_emu);
324 
325 	if (pde->pe_legacy_config != NULL)
326 		error = pde->pe_legacy_config(nvl, config);
327 	else
328 		error = pci_parse_legacy_config(nvl, config);
329 done:
330 	free(str);
331 	return (error);
332 }
333 
334 void
335 pci_print_supported_devices(void)
336 {
337 	struct pci_devemu **pdpp, *pdp;
338 
339 	SET_FOREACH(pdpp, pci_devemu_set) {
340 		pdp = *pdpp;
341 		printf("%s\n", pdp->pe_emu);
342 	}
343 }
344 
345 uint32_t
346 pci_config_read_reg(const struct pcisel *const host_sel, nvlist_t *nvl,
347     const uint32_t reg, const uint8_t size, const uint32_t def)
348 {
349 	const char *config;
350 	const nvlist_t *pci_regs;
351 
352 	assert(size == 1 || size == 2 || size == 4);
353 
354 	pci_regs = find_relative_config_node(nvl, "pcireg");
355 	if (pci_regs == NULL) {
356 		return def;
357 	}
358 
359 	switch (reg) {
360 	case PCIR_DEVICE:
361 		config = get_config_value_node(pci_regs, "device");
362 		break;
363 	case PCIR_VENDOR:
364 		config = get_config_value_node(pci_regs, "vendor");
365 		break;
366 	case PCIR_REVID:
367 		config = get_config_value_node(pci_regs, "revid");
368 		break;
369 	case PCIR_SUBVEND_0:
370 		config = get_config_value_node(pci_regs, "subvendor");
371 		break;
372 	case PCIR_SUBDEV_0:
373 		config = get_config_value_node(pci_regs, "subdevice");
374 		break;
375 	default:
376 		return (-1);
377 	}
378 
379 	if (config == NULL) {
380 		return def;
381 	} else if (host_sel != NULL && strcmp(config, "host") == 0) {
382 		return read_config(host_sel, reg, size);
383 	} else {
384 		return strtol(config, NULL, 16);
385 	}
386 }
387 
388 static int
389 pci_valid_pba_offset(struct pci_devinst *pi, uint64_t offset)
390 {
391 
392 	if (offset < pi->pi_msix.pba_offset)
393 		return (0);
394 
395 	if (offset >= pi->pi_msix.pba_offset + pi->pi_msix.pba_size) {
396 		return (0);
397 	}
398 
399 	return (1);
400 }
401 
402 int
403 pci_emul_msix_twrite(struct pci_devinst *pi, uint64_t offset, int size,
404 		     uint64_t value)
405 {
406 	int msix_entry_offset;
407 	int tab_index;
408 	char *dest;
409 
410 	/* support only 4 or 8 byte writes */
411 	if (size != 4 && size != 8)
412 		return (-1);
413 
414 	/*
415 	 * Return if table index is beyond what device supports
416 	 */
417 	tab_index = offset / MSIX_TABLE_ENTRY_SIZE;
418 	if (tab_index >= pi->pi_msix.table_count)
419 		return (-1);
420 
421 	msix_entry_offset = offset % MSIX_TABLE_ENTRY_SIZE;
422 
423 	/* support only aligned writes */
424 	if ((msix_entry_offset % size) != 0)
425 		return (-1);
426 
427 	dest = (char *)(pi->pi_msix.table + tab_index);
428 	dest += msix_entry_offset;
429 
430 	if (size == 4)
431 		*((uint32_t *)dest) = value;
432 	else
433 		*((uint64_t *)dest) = value;
434 
435 	return (0);
436 }
437 
438 uint64_t
439 pci_emul_msix_tread(struct pci_devinst *pi, uint64_t offset, int size)
440 {
441 	char *dest;
442 	int msix_entry_offset;
443 	int tab_index;
444 	uint64_t retval = ~0;
445 
446 	/*
447 	 * The PCI standard only allows 4 and 8 byte accesses to the MSI-X
448 	 * table but we also allow 1 byte access to accommodate reads from
449 	 * ddb.
450 	 */
451 	if (size != 1 && size != 4 && size != 8)
452 		return (retval);
453 
454 	msix_entry_offset = offset % MSIX_TABLE_ENTRY_SIZE;
455 
456 	/* support only aligned reads */
457 	if ((msix_entry_offset % size) != 0) {
458 		return (retval);
459 	}
460 
461 	tab_index = offset / MSIX_TABLE_ENTRY_SIZE;
462 
463 	if (tab_index < pi->pi_msix.table_count) {
464 		/* valid MSI-X Table access */
465 		dest = (char *)(pi->pi_msix.table + tab_index);
466 		dest += msix_entry_offset;
467 
468 		if (size == 1)
469 			retval = *((uint8_t *)dest);
470 		else if (size == 4)
471 			retval = *((uint32_t *)dest);
472 		else
473 			retval = *((uint64_t *)dest);
474 	} else if (pci_valid_pba_offset(pi, offset)) {
475 		/* return 0 for PBA access */
476 		retval = 0;
477 	}
478 
479 	return (retval);
480 }
481 
482 int
483 pci_msix_table_bar(struct pci_devinst *pi)
484 {
485 
486 	if (pi->pi_msix.table != NULL)
487 		return (pi->pi_msix.table_bar);
488 	else
489 		return (-1);
490 }
491 
492 int
493 pci_msix_pba_bar(struct pci_devinst *pi)
494 {
495 
496 	if (pi->pi_msix.table != NULL)
497 		return (pi->pi_msix.pba_bar);
498 	else
499 		return (-1);
500 }
501 
502 static int
503 pci_emul_io_handler(struct vmctx *ctx __unused, int in, int port,
504     int bytes, uint32_t *eax, void *arg)
505 {
506 	struct pci_devinst *pdi = arg;
507 	struct pci_devemu *pe = pdi->pi_d;
508 	uint64_t offset;
509 	int i;
510 
511 	assert(port >= 0);
512 
513 	for (i = 0; i <= PCI_BARMAX; i++) {
514 		if (pdi->pi_bar[i].type == PCIBAR_IO &&
515 		    (uint64_t)port >= pdi->pi_bar[i].addr &&
516 		    (uint64_t)port + bytes <=
517 		    pdi->pi_bar[i].addr + pdi->pi_bar[i].size) {
518 			offset = port - pdi->pi_bar[i].addr;
519 			if (in)
520 				*eax = (*pe->pe_barread)(pdi, i,
521 							 offset, bytes);
522 			else
523 				(*pe->pe_barwrite)(pdi, i, offset,
524 						   bytes, *eax);
525 			return (0);
526 		}
527 	}
528 	return (-1);
529 }
530 
531 static int
532 pci_emul_mem_handler(struct vcpu *vcpu __unused, int dir,
533     uint64_t addr, int size, uint64_t *val, void *arg1, long arg2)
534 {
535 	struct pci_devinst *pdi = arg1;
536 	struct pci_devemu *pe = pdi->pi_d;
537 	uint64_t offset;
538 	int bidx = (int) arg2;
539 
540 	assert(bidx <= PCI_BARMAX);
541 	assert(pdi->pi_bar[bidx].type == PCIBAR_MEM32 ||
542 	       pdi->pi_bar[bidx].type == PCIBAR_MEM64);
543 	assert(addr >= pdi->pi_bar[bidx].addr &&
544 	       addr + size <= pdi->pi_bar[bidx].addr + pdi->pi_bar[bidx].size);
545 
546 	offset = addr - pdi->pi_bar[bidx].addr;
547 
548 	if (dir == MEM_F_WRITE) {
549 		if (size == 8) {
550 			(*pe->pe_barwrite)(pdi, bidx, offset,
551 					   4, *val & 0xffffffff);
552 			(*pe->pe_barwrite)(pdi, bidx, offset + 4,
553 					   4, *val >> 32);
554 		} else {
555 			(*pe->pe_barwrite)(pdi, bidx, offset,
556 					   size, *val);
557 		}
558 	} else {
559 		if (size == 8) {
560 			*val = (*pe->pe_barread)(pdi, bidx,
561 						 offset, 4);
562 			*val |= (*pe->pe_barread)(pdi, bidx,
563 						  offset + 4, 4) << 32;
564 		} else {
565 			*val = (*pe->pe_barread)(pdi, bidx,
566 						 offset, size);
567 		}
568 	}
569 
570 	return (0);
571 }
572 
573 
574 static int
575 pci_emul_alloc_resource(uint64_t *baseptr, uint64_t limit, uint64_t size,
576 			uint64_t *addr)
577 {
578 	uint64_t base;
579 
580 	assert((size & (size - 1)) == 0);	/* must be a power of 2 */
581 
582 	base = roundup2(*baseptr, size);
583 
584 	if (base + size <= limit) {
585 		*addr = base;
586 		*baseptr = base + size;
587 		return (0);
588 	} else
589 		return (-1);
590 }
591 
592 /*
593  * Register (or unregister) the MMIO or I/O region associated with the BAR
594  * register 'idx' of an emulated pci device.
595  */
596 static void
597 modify_bar_registration(struct pci_devinst *pi, int idx, int registration)
598 {
599 	struct pci_devemu *pe;
600 	int error;
601 	struct inout_port iop;
602 	struct mem_range mr;
603 
604 	pe = pi->pi_d;
605 	switch (pi->pi_bar[idx].type) {
606 	case PCIBAR_IO:
607 		bzero(&iop, sizeof(struct inout_port));
608 		iop.name = pi->pi_name;
609 		iop.port = pi->pi_bar[idx].addr;
610 		iop.size = pi->pi_bar[idx].size;
611 		if (registration) {
612 			iop.flags = IOPORT_F_INOUT;
613 			iop.handler = pci_emul_io_handler;
614 			iop.arg = pi;
615 			error = register_inout(&iop);
616 		} else
617 			error = unregister_inout(&iop);
618 		break;
619 	case PCIBAR_MEM32:
620 	case PCIBAR_MEM64:
621 		bzero(&mr, sizeof(struct mem_range));
622 		mr.name = pi->pi_name;
623 		mr.base = pi->pi_bar[idx].addr;
624 		mr.size = pi->pi_bar[idx].size;
625 		if (registration) {
626 			mr.flags = MEM_F_RW;
627 			mr.handler = pci_emul_mem_handler;
628 			mr.arg1 = pi;
629 			mr.arg2 = idx;
630 			error = register_mem(&mr);
631 		} else
632 			error = unregister_mem(&mr);
633 		break;
634 	case PCIBAR_ROM:
635 		error = 0;
636 		break;
637 	default:
638 		error = EINVAL;
639 		break;
640 	}
641 	assert(error == 0);
642 
643 	if (pe->pe_baraddr != NULL)
644 		(*pe->pe_baraddr)(pi, idx, registration, pi->pi_bar[idx].addr);
645 }
646 
647 static void
648 unregister_bar(struct pci_devinst *pi, int idx)
649 {
650 
651 	modify_bar_registration(pi, idx, 0);
652 }
653 
654 static void
655 register_bar(struct pci_devinst *pi, int idx)
656 {
657 
658 	modify_bar_registration(pi, idx, 1);
659 }
660 
661 /* Is the ROM enabled for the emulated pci device? */
662 static int
663 romen(struct pci_devinst *pi)
664 {
665 	return (pi->pi_bar[PCI_ROM_IDX].lobits & PCIM_BIOS_ENABLE) ==
666 	    PCIM_BIOS_ENABLE;
667 }
668 
669 /* Are we decoding i/o port accesses for the emulated pci device? */
670 static int
671 porten(struct pci_devinst *pi)
672 {
673 	uint16_t cmd;
674 
675 	cmd = pci_get_cfgdata16(pi, PCIR_COMMAND);
676 
677 	return (cmd & PCIM_CMD_PORTEN);
678 }
679 
680 /* Are we decoding memory accesses for the emulated pci device? */
681 static int
682 memen(struct pci_devinst *pi)
683 {
684 	uint16_t cmd;
685 
686 	cmd = pci_get_cfgdata16(pi, PCIR_COMMAND);
687 
688 	return (cmd & PCIM_CMD_MEMEN);
689 }
690 
691 /*
692  * Update the MMIO or I/O address that is decoded by the BAR register.
693  *
694  * If the pci device has enabled the address space decoding then intercept
695  * the address range decoded by the BAR register.
696  */
697 static void
698 update_bar_address(struct pci_devinst *pi, uint64_t addr, int idx, int type)
699 {
700 	int decode;
701 
702 	if (pi->pi_bar[idx].type == PCIBAR_IO)
703 		decode = porten(pi);
704 	else
705 		decode = memen(pi);
706 
707 	if (decode)
708 		unregister_bar(pi, idx);
709 
710 	switch (type) {
711 	case PCIBAR_IO:
712 	case PCIBAR_MEM32:
713 		pi->pi_bar[idx].addr = addr;
714 		break;
715 	case PCIBAR_MEM64:
716 		pi->pi_bar[idx].addr &= ~0xffffffffUL;
717 		pi->pi_bar[idx].addr |= addr;
718 		break;
719 	case PCIBAR_MEMHI64:
720 		pi->pi_bar[idx].addr &= 0xffffffff;
721 		pi->pi_bar[idx].addr |= addr;
722 		break;
723 	default:
724 		assert(0);
725 	}
726 
727 	if (decode)
728 		register_bar(pi, idx);
729 }
730 
731 int
732 pci_emul_alloc_bar(struct pci_devinst *pdi, int idx, enum pcibar_type type,
733     uint64_t size)
734 {
735 	assert((type == PCIBAR_ROM) || (idx >= 0 && idx <= PCI_BARMAX));
736 	assert((type != PCIBAR_ROM) || (idx == PCI_ROM_IDX));
737 
738 	if ((size & (size - 1)) != 0)
739 		size = 1UL << flsl(size);	/* round up to a power of 2 */
740 
741 	/* Enforce minimum BAR sizes required by the PCI standard */
742 	if (type == PCIBAR_IO) {
743 		if (size < 4)
744 			size = 4;
745 	} else if (type == PCIBAR_ROM) {
746 		if (size < ~PCIM_BIOS_ADDR_MASK + 1)
747 			size = ~PCIM_BIOS_ADDR_MASK + 1;
748 	} else {
749 		if (size < 16)
750 			size = 16;
751 	}
752 
753 	/*
754 	 * To reduce fragmentation of the MMIO space, we allocate the BARs by
755 	 * size. Therefore, don't allocate the BAR yet. We create a list of all
756 	 * BAR allocation which is sorted by BAR size. When all PCI devices are
757 	 * initialized, we will assign an address to the BARs.
758 	 */
759 
760 	/* create a new list entry */
761 	struct pci_bar_allocation *const new_bar = malloc(sizeof(*new_bar));
762 	memset(new_bar, 0, sizeof(*new_bar));
763 	new_bar->pdi = pdi;
764 	new_bar->idx = idx;
765 	new_bar->type = type;
766 	new_bar->size = size;
767 
768 	/*
769 	 * Search for a BAR which size is lower than the size of our newly
770 	 * allocated BAR.
771 	 */
772 	struct pci_bar_allocation *bar = NULL;
773 	TAILQ_FOREACH(bar, &pci_bars, chain) {
774 		if (bar->size < size) {
775 			break;
776 		}
777 	}
778 
779 	if (bar == NULL) {
780 		/*
781 		 * Either the list is empty or new BAR is the smallest BAR of
782 		 * the list. Append it to the end of our list.
783 		 */
784 		TAILQ_INSERT_TAIL(&pci_bars, new_bar, chain);
785 	} else {
786 		/*
787 		 * The found BAR is smaller than our new BAR. For that reason,
788 		 * insert our new BAR before the found BAR.
789 		 */
790 		TAILQ_INSERT_BEFORE(bar, new_bar, chain);
791 	}
792 
793 	/*
794 	 * pci_passthru devices synchronize their physical and virtual command
795 	 * register on init. For that reason, the virtual cmd reg should be
796 	 * updated as early as possible.
797 	 */
798 	uint16_t enbit = 0;
799 	switch (type) {
800 	case PCIBAR_IO:
801 		enbit = PCIM_CMD_PORTEN;
802 		break;
803 	case PCIBAR_MEM64:
804 	case PCIBAR_MEM32:
805 		enbit = PCIM_CMD_MEMEN;
806 		break;
807 	default:
808 		enbit = 0;
809 		break;
810 	}
811 
812 	const uint16_t cmd = pci_get_cfgdata16(pdi, PCIR_COMMAND);
813 	pci_set_cfgdata16(pdi, PCIR_COMMAND, cmd | enbit);
814 
815 	return (0);
816 }
817 
818 static int
819 pci_emul_assign_bar(struct pci_devinst *const pdi, const int idx,
820     const enum pcibar_type type, const uint64_t size)
821 {
822 	int error;
823 	uint64_t *baseptr, limit, addr, mask, lobits, bar;
824 
825 	switch (type) {
826 	case PCIBAR_NONE:
827 		baseptr = NULL;
828 		addr = mask = lobits = 0;
829 		break;
830 	case PCIBAR_IO:
831 		baseptr = &pci_emul_iobase;
832 		limit = PCI_EMUL_IOLIMIT;
833 		mask = PCIM_BAR_IO_BASE;
834 		lobits = PCIM_BAR_IO_SPACE;
835 		break;
836 	case PCIBAR_MEM64:
837 		/*
838 		 * XXX
839 		 * Some drivers do not work well if the 64-bit BAR is allocated
840 		 * above 4GB. Allow for this by allocating small requests under
841 		 * 4GB unless then allocation size is larger than some arbitrary
842 		 * number (128MB currently).
843 		 */
844 		if (size > 128 * 1024 * 1024) {
845 			baseptr = &pci_emul_membase64;
846 			limit = pci_emul_memlim64;
847 			mask = PCIM_BAR_MEM_BASE;
848 			lobits = PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_64 |
849 				 PCIM_BAR_MEM_PREFETCH;
850 		} else {
851 			baseptr = &pci_emul_membase32;
852 			limit = PCI_EMUL_MEMLIMIT32;
853 			mask = PCIM_BAR_MEM_BASE;
854 			lobits = PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_64;
855 		}
856 		break;
857 	case PCIBAR_MEM32:
858 		baseptr = &pci_emul_membase32;
859 		limit = PCI_EMUL_MEMLIMIT32;
860 		mask = PCIM_BAR_MEM_BASE;
861 		lobits = PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_32;
862 		break;
863 	case PCIBAR_ROM:
864 		/* do not claim memory for ROM. OVMF will do it for us. */
865 		baseptr = NULL;
866 		limit = 0;
867 		mask = PCIM_BIOS_ADDR_MASK;
868 		lobits = 0;
869 		break;
870 	default:
871 		printf("pci_emul_alloc_base: invalid bar type %d\n", type);
872 		assert(0);
873 	}
874 
875 	if (baseptr != NULL) {
876 		error = pci_emul_alloc_resource(baseptr, limit, size, &addr);
877 		if (error != 0)
878 			return (error);
879 	} else {
880 		addr = 0;
881 	}
882 
883 	pdi->pi_bar[idx].type = type;
884 	pdi->pi_bar[idx].addr = addr;
885 	pdi->pi_bar[idx].size = size;
886 	/*
887 	 * passthru devices are using same lobits as physical device they set
888 	 * this property
889 	 */
890 	if (pdi->pi_bar[idx].lobits != 0) {
891 		lobits = pdi->pi_bar[idx].lobits;
892 	} else {
893 		pdi->pi_bar[idx].lobits = lobits;
894 	}
895 
896 	/* Initialize the BAR register in config space */
897 	bar = (addr & mask) | lobits;
898 	pci_set_cfgdata32(pdi, PCIR_BAR(idx), bar);
899 
900 	if (type == PCIBAR_MEM64) {
901 		assert(idx + 1 <= PCI_BARMAX);
902 		pdi->pi_bar[idx + 1].type = PCIBAR_MEMHI64;
903 		pci_set_cfgdata32(pdi, PCIR_BAR(idx + 1), bar >> 32);
904 	}
905 
906 	if (type != PCIBAR_ROM) {
907 		register_bar(pdi, idx);
908 	}
909 
910 	return (0);
911 }
912 
913 int
914 pci_emul_alloc_rom(struct pci_devinst *const pdi, const uint64_t size,
915     void **const addr)
916 {
917 	/* allocate ROM space once on first call */
918 	if (pci_emul_rombase == 0) {
919 		pci_emul_rombase = vm_create_devmem(pdi->pi_vmctx, VM_PCIROM,
920 		    "pcirom", PCI_EMUL_ROMSIZE);
921 		if (pci_emul_rombase == MAP_FAILED) {
922 			warnx("%s: failed to create rom segment", __func__);
923 			return (-1);
924 		}
925 		pci_emul_romlim = pci_emul_rombase + PCI_EMUL_ROMSIZE;
926 		pci_emul_romoffset = 0;
927 	}
928 
929 	/* ROM size should be a power of 2 and greater than 2 KB */
930 	const uint64_t rom_size = MAX(1UL << flsl(size),
931 	    ~PCIM_BIOS_ADDR_MASK + 1);
932 
933 	/* check if ROM fits into ROM space */
934 	if (pci_emul_romoffset + rom_size > PCI_EMUL_ROMSIZE) {
935 		warnx("%s: no space left in rom segment:", __func__);
936 		warnx("%16lu bytes left",
937 		    PCI_EMUL_ROMSIZE - pci_emul_romoffset);
938 		warnx("%16lu bytes required by %d/%d/%d", rom_size, pdi->pi_bus,
939 		    pdi->pi_slot, pdi->pi_func);
940 		return (-1);
941 	}
942 
943 	/* allocate ROM BAR */
944 	const int error = pci_emul_alloc_bar(pdi, PCI_ROM_IDX, PCIBAR_ROM,
945 	    rom_size);
946 	if (error)
947 		return error;
948 
949 	/* return address */
950 	*addr = pci_emul_rombase + pci_emul_romoffset;
951 
952 	/* save offset into ROM Space */
953 	pdi->pi_romoffset = pci_emul_romoffset;
954 
955 	/* increase offset for next ROM */
956 	pci_emul_romoffset += rom_size;
957 
958 	return (0);
959 }
960 
961 int
962 pci_emul_add_boot_device(struct pci_devinst *pi, int bootindex)
963 {
964 	struct boot_device *new_device, *device;
965 
966 	/* don't permit a negative bootindex */
967 	if (bootindex < 0) {
968 		errx(4, "Invalid bootindex %d for %s", bootindex, pi->pi_name);
969 	}
970 
971 	/* alloc new boot device */
972 	new_device = calloc(1, sizeof(struct boot_device));
973 	if (new_device == NULL) {
974 		return (ENOMEM);
975 	}
976 	new_device->pdi = pi;
977 	new_device->bootindex = bootindex;
978 
979 	/* search for boot device with higher boot index */
980 	TAILQ_FOREACH(device, &boot_devices, boot_device_chain) {
981 		if (device->bootindex == bootindex) {
982 			errx(4,
983 			    "Could not set bootindex %d for %s. Bootindex already occupied by %s",
984 			    bootindex, pi->pi_name, device->pdi->pi_name);
985 		} else if (device->bootindex > bootindex) {
986 			break;
987 		}
988 	}
989 
990 	/* add boot device to queue */
991 	if (device == NULL) {
992 		TAILQ_INSERT_TAIL(&boot_devices, new_device, boot_device_chain);
993 	} else {
994 		TAILQ_INSERT_BEFORE(device, new_device, boot_device_chain);
995 	}
996 
997 	return (0);
998 }
999 
1000 #define	CAP_START_OFFSET	0x40
1001 static int
1002 pci_emul_add_capability(struct pci_devinst *pi, u_char *capdata, int caplen)
1003 {
1004 	int i, capoff, reallen;
1005 	uint16_t sts;
1006 
1007 	assert(caplen > 0);
1008 
1009 	reallen = roundup2(caplen, 4);		/* dword aligned */
1010 
1011 	sts = pci_get_cfgdata16(pi, PCIR_STATUS);
1012 	if ((sts & PCIM_STATUS_CAPPRESENT) == 0)
1013 		capoff = CAP_START_OFFSET;
1014 	else
1015 		capoff = pi->pi_capend + 1;
1016 
1017 	/* Check if we have enough space */
1018 	if (capoff + reallen > PCI_REGMAX + 1)
1019 		return (-1);
1020 
1021 	/* Set the previous capability pointer */
1022 	if ((sts & PCIM_STATUS_CAPPRESENT) == 0) {
1023 		pci_set_cfgdata8(pi, PCIR_CAP_PTR, capoff);
1024 		pci_set_cfgdata16(pi, PCIR_STATUS, sts|PCIM_STATUS_CAPPRESENT);
1025 	} else
1026 		pci_set_cfgdata8(pi, pi->pi_prevcap + 1, capoff);
1027 
1028 	/* Copy the capability */
1029 	for (i = 0; i < caplen; i++)
1030 		pci_set_cfgdata8(pi, capoff + i, capdata[i]);
1031 
1032 	/* Set the next capability pointer */
1033 	pci_set_cfgdata8(pi, capoff + 1, 0);
1034 
1035 	pi->pi_prevcap = capoff;
1036 	pi->pi_capend = capoff + reallen - 1;
1037 	return (0);
1038 }
1039 
1040 static struct pci_devemu *
1041 pci_emul_finddev(const char *name)
1042 {
1043 	struct pci_devemu **pdpp, *pdp;
1044 
1045 	SET_FOREACH(pdpp, pci_devemu_set) {
1046 		pdp = *pdpp;
1047 		if (!strcmp(pdp->pe_emu, name)) {
1048 			return (pdp);
1049 		}
1050 	}
1051 
1052 	return (NULL);
1053 }
1054 
1055 static int
1056 pci_emul_init(struct vmctx *ctx, struct pci_devemu *pde, int bus, int slot,
1057     int func, struct funcinfo *fi)
1058 {
1059 	struct pci_devinst *pdi;
1060 	int err;
1061 
1062 	pdi = calloc(1, sizeof(struct pci_devinst));
1063 
1064 	pdi->pi_vmctx = ctx;
1065 	pdi->pi_bus = bus;
1066 	pdi->pi_slot = slot;
1067 	pdi->pi_func = func;
1068 	pthread_mutex_init(&pdi->pi_lintr.lock, NULL);
1069 	pdi->pi_lintr.pin = 0;
1070 	pdi->pi_lintr.state = IDLE;
1071 	pdi->pi_lintr.pirq_pin = 0;
1072 	pdi->pi_lintr.ioapic_irq = 0;
1073 	pdi->pi_d = pde;
1074 	snprintf(pdi->pi_name, PI_NAMESZ, "%s@pci.%d.%d.%d", pde->pe_emu, bus,
1075 	    slot, func);
1076 
1077 	/* Disable legacy interrupts */
1078 	pci_set_cfgdata8(pdi, PCIR_INTLINE, 255);
1079 	pci_set_cfgdata8(pdi, PCIR_INTPIN, 0);
1080 
1081 	pci_set_cfgdata8(pdi, PCIR_COMMAND, PCIM_CMD_BUSMASTEREN);
1082 
1083 	err = (*pde->pe_init)(pdi, fi->fi_config);
1084 	if (err == 0)
1085 		fi->fi_devi = pdi;
1086 	else
1087 		free(pdi);
1088 
1089 	return (err);
1090 }
1091 
1092 void
1093 pci_populate_msicap(struct msicap *msicap, int msgnum, int nextptr)
1094 {
1095 	int mmc;
1096 
1097 	/* Number of msi messages must be a power of 2 between 1 and 32 */
1098 	assert((msgnum & (msgnum - 1)) == 0 && msgnum >= 1 && msgnum <= 32);
1099 	mmc = ffs(msgnum) - 1;
1100 
1101 	bzero(msicap, sizeof(struct msicap));
1102 	msicap->capid = PCIY_MSI;
1103 	msicap->nextptr = nextptr;
1104 	msicap->msgctrl = PCIM_MSICTRL_64BIT | (mmc << 1);
1105 }
1106 
1107 int
1108 pci_emul_add_msicap(struct pci_devinst *pi, int msgnum)
1109 {
1110 	struct msicap msicap;
1111 
1112 	pci_populate_msicap(&msicap, msgnum, 0);
1113 
1114 	return (pci_emul_add_capability(pi, (u_char *)&msicap, sizeof(msicap)));
1115 }
1116 
1117 static void
1118 pci_populate_msixcap(struct msixcap *msixcap, int msgnum, int barnum,
1119 		     uint32_t msix_tab_size)
1120 {
1121 
1122 	assert(msix_tab_size % 4096 == 0);
1123 
1124 	bzero(msixcap, sizeof(struct msixcap));
1125 	msixcap->capid = PCIY_MSIX;
1126 
1127 	/*
1128 	 * Message Control Register, all fields set to
1129 	 * zero except for the Table Size.
1130 	 * Note: Table size N is encoded as N-1
1131 	 */
1132 	msixcap->msgctrl = msgnum - 1;
1133 
1134 	/*
1135 	 * MSI-X BAR setup:
1136 	 * - MSI-X table start at offset 0
1137 	 * - PBA table starts at a 4K aligned offset after the MSI-X table
1138 	 */
1139 	msixcap->table_info = barnum & PCIM_MSIX_BIR_MASK;
1140 	msixcap->pba_info = msix_tab_size | (barnum & PCIM_MSIX_BIR_MASK);
1141 }
1142 
1143 static void
1144 pci_msix_table_init(struct pci_devinst *pi, int table_entries)
1145 {
1146 	int i, table_size;
1147 
1148 	assert(table_entries > 0);
1149 	assert(table_entries <= MAX_MSIX_TABLE_ENTRIES);
1150 
1151 	table_size = table_entries * MSIX_TABLE_ENTRY_SIZE;
1152 	pi->pi_msix.table = calloc(1, table_size);
1153 
1154 	/* set mask bit of vector control register */
1155 	for (i = 0; i < table_entries; i++)
1156 		pi->pi_msix.table[i].vector_control |= PCIM_MSIX_VCTRL_MASK;
1157 }
1158 
1159 int
1160 pci_emul_add_msixcap(struct pci_devinst *pi, int msgnum, int barnum)
1161 {
1162 	uint32_t tab_size;
1163 	struct msixcap msixcap;
1164 
1165 	assert(msgnum >= 1 && msgnum <= MAX_MSIX_TABLE_ENTRIES);
1166 	assert(barnum >= 0 && barnum <= PCIR_MAX_BAR_0);
1167 
1168 	tab_size = msgnum * MSIX_TABLE_ENTRY_SIZE;
1169 
1170 	/* Align table size to nearest 4K */
1171 	tab_size = roundup2(tab_size, 4096);
1172 
1173 	pi->pi_msix.table_bar = barnum;
1174 	pi->pi_msix.pba_bar   = barnum;
1175 	pi->pi_msix.table_offset = 0;
1176 	pi->pi_msix.table_count = msgnum;
1177 	pi->pi_msix.pba_offset = tab_size;
1178 	pi->pi_msix.pba_size = PBA_SIZE(msgnum);
1179 
1180 	pci_msix_table_init(pi, msgnum);
1181 
1182 	pci_populate_msixcap(&msixcap, msgnum, barnum, tab_size);
1183 
1184 	/* allocate memory for MSI-X Table and PBA */
1185 	pci_emul_alloc_bar(pi, barnum, PCIBAR_MEM32,
1186 				tab_size + pi->pi_msix.pba_size);
1187 
1188 	return (pci_emul_add_capability(pi, (u_char *)&msixcap,
1189 					sizeof(msixcap)));
1190 }
1191 
1192 static void
1193 msixcap_cfgwrite(struct pci_devinst *pi, int capoff, int offset,
1194 		 int bytes, uint32_t val)
1195 {
1196 	uint16_t msgctrl, rwmask;
1197 	int off;
1198 
1199 	off = offset - capoff;
1200 	/* Message Control Register */
1201 	if (off == 2 && bytes == 2) {
1202 		rwmask = PCIM_MSIXCTRL_MSIX_ENABLE | PCIM_MSIXCTRL_FUNCTION_MASK;
1203 		msgctrl = pci_get_cfgdata16(pi, offset);
1204 		msgctrl &= ~rwmask;
1205 		msgctrl |= val & rwmask;
1206 		val = msgctrl;
1207 
1208 		pi->pi_msix.enabled = val & PCIM_MSIXCTRL_MSIX_ENABLE;
1209 		pi->pi_msix.function_mask = val & PCIM_MSIXCTRL_FUNCTION_MASK;
1210 		pci_lintr_update(pi);
1211 	}
1212 
1213 	CFGWRITE(pi, offset, val, bytes);
1214 }
1215 
1216 static void
1217 msicap_cfgwrite(struct pci_devinst *pi, int capoff, int offset,
1218 		int bytes, uint32_t val)
1219 {
1220 	uint16_t msgctrl, rwmask, msgdata, mme;
1221 	uint32_t addrlo;
1222 
1223 	/*
1224 	 * If guest is writing to the message control register make sure
1225 	 * we do not overwrite read-only fields.
1226 	 */
1227 	if ((offset - capoff) == 2 && bytes == 2) {
1228 		rwmask = PCIM_MSICTRL_MME_MASK | PCIM_MSICTRL_MSI_ENABLE;
1229 		msgctrl = pci_get_cfgdata16(pi, offset);
1230 		msgctrl &= ~rwmask;
1231 		msgctrl |= val & rwmask;
1232 		val = msgctrl;
1233 	}
1234 	CFGWRITE(pi, offset, val, bytes);
1235 
1236 	msgctrl = pci_get_cfgdata16(pi, capoff + 2);
1237 	addrlo = pci_get_cfgdata32(pi, capoff + 4);
1238 	if (msgctrl & PCIM_MSICTRL_64BIT)
1239 		msgdata = pci_get_cfgdata16(pi, capoff + 12);
1240 	else
1241 		msgdata = pci_get_cfgdata16(pi, capoff + 8);
1242 
1243 	mme = msgctrl & PCIM_MSICTRL_MME_MASK;
1244 	pi->pi_msi.enabled = msgctrl & PCIM_MSICTRL_MSI_ENABLE ? 1 : 0;
1245 	if (pi->pi_msi.enabled) {
1246 		pi->pi_msi.addr = addrlo;
1247 		pi->pi_msi.msg_data = msgdata;
1248 		pi->pi_msi.maxmsgnum = 1 << (mme >> 4);
1249 	} else {
1250 		pi->pi_msi.maxmsgnum = 0;
1251 	}
1252 	pci_lintr_update(pi);
1253 }
1254 
1255 static void
1256 pciecap_cfgwrite(struct pci_devinst *pi, int capoff __unused, int offset,
1257     int bytes, uint32_t val)
1258 {
1259 
1260 	/* XXX don't write to the readonly parts */
1261 	CFGWRITE(pi, offset, val, bytes);
1262 }
1263 
1264 #define	PCIECAP_VERSION	0x2
1265 int
1266 pci_emul_add_pciecap(struct pci_devinst *pi, int type)
1267 {
1268 	int err;
1269 	struct pciecap pciecap;
1270 
1271 	bzero(&pciecap, sizeof(pciecap));
1272 
1273 	/*
1274 	 * Use the integrated endpoint type for endpoints on a root complex bus.
1275 	 *
1276 	 * NB: bhyve currently only supports a single PCI bus that is the root
1277 	 * complex bus, so all endpoints are integrated.
1278 	 */
1279 	if ((type == PCIEM_TYPE_ENDPOINT) && (pi->pi_bus == 0))
1280 		type = PCIEM_TYPE_ROOT_INT_EP;
1281 
1282 	pciecap.capid = PCIY_EXPRESS;
1283 	pciecap.pcie_capabilities = PCIECAP_VERSION | type;
1284 	if (type != PCIEM_TYPE_ROOT_INT_EP) {
1285 		pciecap.link_capabilities = 0x411;	/* gen1, x1 */
1286 		pciecap.link_status = 0x11;		/* gen1, x1 */
1287 	}
1288 
1289 	err = pci_emul_add_capability(pi, (u_char *)&pciecap, sizeof(pciecap));
1290 	return (err);
1291 }
1292 
1293 /*
1294  * This function assumes that 'coff' is in the capabilities region of the
1295  * config space. A capoff parameter of zero will force a search for the
1296  * offset and type.
1297  */
1298 void
1299 pci_emul_capwrite(struct pci_devinst *pi, int offset, int bytes, uint32_t val,
1300     uint8_t capoff, int capid)
1301 {
1302 	uint8_t nextoff;
1303 
1304 	/* Do not allow un-aligned writes */
1305 	if ((offset & (bytes - 1)) != 0)
1306 		return;
1307 
1308 	if (capoff == 0) {
1309 		/* Find the capability that we want to update */
1310 		capoff = CAP_START_OFFSET;
1311 		while (1) {
1312 			nextoff = pci_get_cfgdata8(pi, capoff + 1);
1313 			if (nextoff == 0)
1314 				break;
1315 			if (offset >= capoff && offset < nextoff)
1316 				break;
1317 
1318 			capoff = nextoff;
1319 		}
1320 		assert(offset >= capoff);
1321 		capid = pci_get_cfgdata8(pi, capoff);
1322 	}
1323 
1324 	/*
1325 	 * Capability ID and Next Capability Pointer are readonly.
1326 	 * However, some o/s's do 4-byte writes that include these.
1327 	 * For this case, trim the write back to 2 bytes and adjust
1328 	 * the data.
1329 	 */
1330 	if (offset == capoff || offset == capoff + 1) {
1331 		if (offset == capoff && bytes == 4) {
1332 			bytes = 2;
1333 			offset += 2;
1334 			val >>= 16;
1335 		} else
1336 			return;
1337 	}
1338 
1339 	switch (capid) {
1340 	case PCIY_MSI:
1341 		msicap_cfgwrite(pi, capoff, offset, bytes, val);
1342 		break;
1343 	case PCIY_MSIX:
1344 		msixcap_cfgwrite(pi, capoff, offset, bytes, val);
1345 		break;
1346 	case PCIY_EXPRESS:
1347 		pciecap_cfgwrite(pi, capoff, offset, bytes, val);
1348 		break;
1349 	default:
1350 		break;
1351 	}
1352 }
1353 
1354 static int
1355 pci_emul_iscap(struct pci_devinst *pi, int offset)
1356 {
1357 	uint16_t sts;
1358 
1359 	sts = pci_get_cfgdata16(pi, PCIR_STATUS);
1360 	if ((sts & PCIM_STATUS_CAPPRESENT) != 0) {
1361 		if (offset >= CAP_START_OFFSET && offset <= pi->pi_capend)
1362 			return (1);
1363 	}
1364 	return (0);
1365 }
1366 
1367 static int
1368 pci_emul_fallback_handler(struct vcpu *vcpu __unused, int dir,
1369     uint64_t addr __unused, int size __unused, uint64_t *val,
1370     void *arg1 __unused, long arg2 __unused)
1371 {
1372 	/*
1373 	 * Ignore writes; return 0xff's for reads. The mem read code
1374 	 * will take care of truncating to the correct size.
1375 	 */
1376 	if (dir == MEM_F_READ) {
1377 		*val = 0xffffffffffffffff;
1378 	}
1379 
1380 	return (0);
1381 }
1382 
1383 static int
1384 pci_emul_ecfg_handler(struct vcpu *vcpu __unused, int dir, uint64_t addr,
1385     int bytes, uint64_t *val, void *arg1 __unused, long arg2 __unused)
1386 {
1387 	int bus, slot, func, coff, in;
1388 
1389 	coff = addr & 0xfff;
1390 	func = (addr >> 12) & 0x7;
1391 	slot = (addr >> 15) & 0x1f;
1392 	bus = (addr >> 20) & 0xff;
1393 	in = (dir == MEM_F_READ);
1394 	if (in)
1395 		*val = ~0UL;
1396 	pci_cfgrw(in, bus, slot, func, coff, bytes, (uint32_t *)val);
1397 	return (0);
1398 }
1399 
1400 uint64_t
1401 pci_ecfg_base(void)
1402 {
1403 
1404 	return (PCI_EMUL_ECFG_BASE);
1405 }
1406 
1407 static int
1408 init_bootorder(void)
1409 {
1410 	struct boot_device *device;
1411 	FILE *fp;
1412 	char *bootorder;
1413 	size_t bootorder_len;
1414 
1415 	if (TAILQ_EMPTY(&boot_devices))
1416 		return (0);
1417 
1418 	fp = open_memstream(&bootorder, &bootorder_len);
1419 	TAILQ_FOREACH(device, &boot_devices, boot_device_chain) {
1420 		fprintf(fp, "/pci@i0cf8/pci@%d,%d\n",
1421 		    device->pdi->pi_slot, device->pdi->pi_func);
1422 	}
1423 	fclose(fp);
1424 
1425 	return (qemu_fwcfg_add_file("bootorder", bootorder_len, bootorder));
1426 }
1427 
1428 #define	BUSIO_ROUNDUP		32
1429 #define	BUSMEM32_ROUNDUP	(1024 * 1024)
1430 #define	BUSMEM64_ROUNDUP	(512 * 1024 * 1024)
1431 
1432 int
1433 init_pci(struct vmctx *ctx)
1434 {
1435 	char node_name[sizeof("pci.XXX.XX.X")];
1436 	struct mem_range mr;
1437 	struct pci_devemu *pde;
1438 	struct businfo *bi;
1439 	struct slotinfo *si;
1440 	struct funcinfo *fi;
1441 	nvlist_t *nvl;
1442 	const char *emul;
1443 	size_t lowmem;
1444 	int bus, slot, func;
1445 	int error;
1446 
1447 	if (vm_get_lowmem_limit(ctx) > PCI_EMUL_MEMBASE32)
1448 		errx(EX_OSERR, "Invalid lowmem limit");
1449 
1450 	pci_emul_iobase = PCI_EMUL_IOBASE;
1451 	pci_emul_membase32 = PCI_EMUL_MEMBASE32;
1452 
1453 	pci_emul_membase64 = 4*GB + vm_get_highmem_size(ctx);
1454 	pci_emul_membase64 = roundup2(pci_emul_membase64, PCI_EMUL_MEMSIZE64);
1455 	pci_emul_memlim64 = pci_emul_membase64 + PCI_EMUL_MEMSIZE64;
1456 
1457 	TAILQ_INIT(&boot_devices);
1458 
1459 	for (bus = 0; bus < MAXBUSES; bus++) {
1460 		snprintf(node_name, sizeof(node_name), "pci.%d", bus);
1461 		nvl = find_config_node(node_name);
1462 		if (nvl == NULL)
1463 			continue;
1464 		pci_businfo[bus] = calloc(1, sizeof(struct businfo));
1465 		bi = pci_businfo[bus];
1466 
1467 		/*
1468 		 * Keep track of the i/o and memory resources allocated to
1469 		 * this bus.
1470 		 */
1471 		bi->iobase = pci_emul_iobase;
1472 		bi->membase32 = pci_emul_membase32;
1473 		bi->membase64 = pci_emul_membase64;
1474 
1475 		/* first run: init devices */
1476 		for (slot = 0; slot < MAXSLOTS; slot++) {
1477 			si = &bi->slotinfo[slot];
1478 			for (func = 0; func < MAXFUNCS; func++) {
1479 				fi = &si->si_funcs[func];
1480 				snprintf(node_name, sizeof(node_name),
1481 				    "pci.%d.%d.%d", bus, slot, func);
1482 				nvl = find_config_node(node_name);
1483 				if (nvl == NULL)
1484 					continue;
1485 
1486 				fi->fi_config = nvl;
1487 				emul = get_config_value_node(nvl, "device");
1488 				if (emul == NULL) {
1489 					EPRINTLN("pci slot %d:%d:%d: missing "
1490 					    "\"device\" value", bus, slot, func);
1491 					return (EINVAL);
1492 				}
1493 				pde = pci_emul_finddev(emul);
1494 				if (pde == NULL) {
1495 					EPRINTLN("pci slot %d:%d:%d: unknown "
1496 					    "device \"%s\"", bus, slot, func,
1497 					    emul);
1498 					return (EINVAL);
1499 				}
1500 				if (pde->pe_alias != NULL) {
1501 					EPRINTLN("pci slot %d:%d:%d: legacy "
1502 					    "device \"%s\", use \"%s\" instead",
1503 					    bus, slot, func, emul,
1504 					    pde->pe_alias);
1505 					return (EINVAL);
1506 				}
1507 				fi->fi_pde = pde;
1508 				error = pci_emul_init(ctx, pde, bus, slot,
1509 				    func, fi);
1510 				if (error)
1511 					return (error);
1512 			}
1513 		}
1514 
1515 		/* second run: assign BARs and free list */
1516 		struct pci_bar_allocation *bar;
1517 		struct pci_bar_allocation *bar_tmp;
1518 		TAILQ_FOREACH_SAFE(bar, &pci_bars, chain, bar_tmp) {
1519 			pci_emul_assign_bar(bar->pdi, bar->idx, bar->type,
1520 			    bar->size);
1521 			free(bar);
1522 		}
1523 		TAILQ_INIT(&pci_bars);
1524 
1525 		/*
1526 		 * Add some slop to the I/O and memory resources decoded by
1527 		 * this bus to give a guest some flexibility if it wants to
1528 		 * reprogram the BARs.
1529 		 */
1530 		pci_emul_iobase += BUSIO_ROUNDUP;
1531 		pci_emul_iobase = roundup2(pci_emul_iobase, BUSIO_ROUNDUP);
1532 		bi->iolimit = pci_emul_iobase;
1533 
1534 		pci_emul_membase32 += BUSMEM32_ROUNDUP;
1535 		pci_emul_membase32 = roundup2(pci_emul_membase32,
1536 		    BUSMEM32_ROUNDUP);
1537 		bi->memlimit32 = pci_emul_membase32;
1538 
1539 		pci_emul_membase64 += BUSMEM64_ROUNDUP;
1540 		pci_emul_membase64 = roundup2(pci_emul_membase64,
1541 		    BUSMEM64_ROUNDUP);
1542 		bi->memlimit64 = pci_emul_membase64;
1543 	}
1544 
1545 	/*
1546 	 * PCI backends are initialized before routing INTx interrupts
1547 	 * so that LPC devices are able to reserve ISA IRQs before
1548 	 * routing PIRQ pins.
1549 	 */
1550 	for (bus = 0; bus < MAXBUSES; bus++) {
1551 		if ((bi = pci_businfo[bus]) == NULL)
1552 			continue;
1553 
1554 		for (slot = 0; slot < MAXSLOTS; slot++) {
1555 			si = &bi->slotinfo[slot];
1556 			for (func = 0; func < MAXFUNCS; func++) {
1557 				fi = &si->si_funcs[func];
1558 				if (fi->fi_devi == NULL)
1559 					continue;
1560 				pci_lintr_route(fi->fi_devi);
1561 			}
1562 		}
1563 	}
1564 	lpc_pirq_routed();
1565 
1566 	if ((error = init_bootorder()) != 0) {
1567 		warnx("%s: Unable to init bootorder", __func__);
1568 		return (error);
1569 	}
1570 
1571 	/*
1572 	 * The guest physical memory map looks like the following:
1573 	 * [0,		    lowmem)		guest system memory
1574 	 * [lowmem,	    0xC0000000)		memory hole (may be absent)
1575 	 * [0xC0000000,     0xE0000000)		PCI hole (32-bit BAR allocation)
1576 	 * [0xE0000000,	    0xF0000000)		PCI extended config window
1577 	 * [0xF0000000,	    4GB)		LAPIC, IOAPIC, HPET, firmware
1578 	 * [4GB,	    4GB + highmem)
1579 	 */
1580 
1581 	/*
1582 	 * Accesses to memory addresses that are not allocated to system
1583 	 * memory or PCI devices return 0xff's.
1584 	 */
1585 	lowmem = vm_get_lowmem_size(ctx);
1586 	bzero(&mr, sizeof(struct mem_range));
1587 	mr.name = "PCI hole";
1588 	mr.flags = MEM_F_RW | MEM_F_IMMUTABLE;
1589 	mr.base = lowmem;
1590 	mr.size = (4ULL * 1024 * 1024 * 1024) - lowmem;
1591 	mr.handler = pci_emul_fallback_handler;
1592 	error = register_mem_fallback(&mr);
1593 	assert(error == 0);
1594 
1595 	/* PCI extended config space */
1596 	bzero(&mr, sizeof(struct mem_range));
1597 	mr.name = "PCI ECFG";
1598 	mr.flags = MEM_F_RW | MEM_F_IMMUTABLE;
1599 	mr.base = PCI_EMUL_ECFG_BASE;
1600 	mr.size = PCI_EMUL_ECFG_SIZE;
1601 	mr.handler = pci_emul_ecfg_handler;
1602 	error = register_mem(&mr);
1603 	assert(error == 0);
1604 
1605 	return (0);
1606 }
1607 
1608 static void
1609 pci_apic_prt_entry(int bus __unused, int slot, int pin, int pirq_pin __unused,
1610     int ioapic_irq, void *arg __unused)
1611 {
1612 
1613 	dsdt_line("  Package ()");
1614 	dsdt_line("  {");
1615 	dsdt_line("    0x%X,", slot << 16 | 0xffff);
1616 	dsdt_line("    0x%02X,", pin - 1);
1617 	dsdt_line("    Zero,");
1618 	dsdt_line("    0x%X", ioapic_irq);
1619 	dsdt_line("  },");
1620 }
1621 
1622 static void
1623 pci_pirq_prt_entry(int bus __unused, int slot, int pin, int pirq_pin,
1624     int ioapic_irq __unused, void *arg __unused)
1625 {
1626 	char *name;
1627 
1628 	name = lpc_pirq_name(pirq_pin);
1629 	if (name == NULL)
1630 		return;
1631 	dsdt_line("  Package ()");
1632 	dsdt_line("  {");
1633 	dsdt_line("    0x%X,", slot << 16 | 0xffff);
1634 	dsdt_line("    0x%02X,", pin - 1);
1635 	dsdt_line("    %s,", name);
1636 	dsdt_line("    0x00");
1637 	dsdt_line("  },");
1638 	free(name);
1639 }
1640 
1641 /*
1642  * A bhyve virtual machine has a flat PCI hierarchy with a root port
1643  * corresponding to each PCI bus.
1644  */
1645 static void
1646 pci_bus_write_dsdt(int bus)
1647 {
1648 	struct businfo *bi;
1649 	struct slotinfo *si;
1650 	struct pci_devinst *pi;
1651 	int count, func, slot;
1652 
1653 	/*
1654 	 * If there are no devices on this 'bus' then just return.
1655 	 */
1656 	if ((bi = pci_businfo[bus]) == NULL) {
1657 		/*
1658 		 * Bus 0 is special because it decodes the I/O ports used
1659 		 * for PCI config space access even if there are no devices
1660 		 * on it.
1661 		 */
1662 		if (bus != 0)
1663 			return;
1664 	}
1665 
1666 	dsdt_line("  Device (PC%02X)", bus);
1667 	dsdt_line("  {");
1668 	dsdt_line("    Name (_HID, EisaId (\"PNP0A03\"))");
1669 
1670 	dsdt_line("    Method (_BBN, 0, NotSerialized)");
1671 	dsdt_line("    {");
1672 	dsdt_line("        Return (0x%08X)", bus);
1673 	dsdt_line("    }");
1674 	dsdt_line("    Name (_CRS, ResourceTemplate ()");
1675 	dsdt_line("    {");
1676 	dsdt_line("      WordBusNumber (ResourceProducer, MinFixed, "
1677 	    "MaxFixed, PosDecode,");
1678 	dsdt_line("        0x0000,             // Granularity");
1679 	dsdt_line("        0x%04X,             // Range Minimum", bus);
1680 	dsdt_line("        0x%04X,             // Range Maximum", bus);
1681 	dsdt_line("        0x0000,             // Translation Offset");
1682 	dsdt_line("        0x0001,             // Length");
1683 	dsdt_line("        ,, )");
1684 
1685 	if (bus == 0) {
1686 		dsdt_indent(3);
1687 		dsdt_fixed_ioport(0xCF8, 8);
1688 		dsdt_unindent(3);
1689 
1690 		dsdt_line("      WordIO (ResourceProducer, MinFixed, MaxFixed, "
1691 		    "PosDecode, EntireRange,");
1692 		dsdt_line("        0x0000,             // Granularity");
1693 		dsdt_line("        0x0000,             // Range Minimum");
1694 		dsdt_line("        0x0CF7,             // Range Maximum");
1695 		dsdt_line("        0x0000,             // Translation Offset");
1696 		dsdt_line("        0x0CF8,             // Length");
1697 		dsdt_line("        ,, , TypeStatic)");
1698 
1699 		dsdt_line("      WordIO (ResourceProducer, MinFixed, MaxFixed, "
1700 		    "PosDecode, EntireRange,");
1701 		dsdt_line("        0x0000,             // Granularity");
1702 		dsdt_line("        0x0D00,             // Range Minimum");
1703 		dsdt_line("        0x%04X,             // Range Maximum",
1704 		    PCI_EMUL_IOBASE - 1);
1705 		dsdt_line("        0x0000,             // Translation Offset");
1706 		dsdt_line("        0x%04X,             // Length",
1707 		    PCI_EMUL_IOBASE - 0x0D00);
1708 		dsdt_line("        ,, , TypeStatic)");
1709 
1710 		if (bi == NULL) {
1711 			dsdt_line("    })");
1712 			goto done;
1713 		}
1714 	}
1715 	assert(bi != NULL);
1716 
1717 	/* i/o window */
1718 	dsdt_line("      WordIO (ResourceProducer, MinFixed, MaxFixed, "
1719 	    "PosDecode, EntireRange,");
1720 	dsdt_line("        0x0000,             // Granularity");
1721 	dsdt_line("        0x%04X,             // Range Minimum", bi->iobase);
1722 	dsdt_line("        0x%04X,             // Range Maximum",
1723 	    bi->iolimit - 1);
1724 	dsdt_line("        0x0000,             // Translation Offset");
1725 	dsdt_line("        0x%04X,             // Length",
1726 	    bi->iolimit - bi->iobase);
1727 	dsdt_line("        ,, , TypeStatic)");
1728 
1729 	/* mmio window (32-bit) */
1730 	dsdt_line("      DWordMemory (ResourceProducer, PosDecode, "
1731 	    "MinFixed, MaxFixed, NonCacheable, ReadWrite,");
1732 	dsdt_line("        0x00000000,         // Granularity");
1733 	dsdt_line("        0x%08X,         // Range Minimum\n", bi->membase32);
1734 	dsdt_line("        0x%08X,         // Range Maximum\n",
1735 	    bi->memlimit32 - 1);
1736 	dsdt_line("        0x00000000,         // Translation Offset");
1737 	dsdt_line("        0x%08X,         // Length\n",
1738 	    bi->memlimit32 - bi->membase32);
1739 	dsdt_line("        ,, , AddressRangeMemory, TypeStatic)");
1740 
1741 	/* mmio window (64-bit) */
1742 	dsdt_line("      QWordMemory (ResourceProducer, PosDecode, "
1743 	    "MinFixed, MaxFixed, NonCacheable, ReadWrite,");
1744 	dsdt_line("        0x0000000000000000, // Granularity");
1745 	dsdt_line("        0x%016lX, // Range Minimum\n", bi->membase64);
1746 	dsdt_line("        0x%016lX, // Range Maximum\n",
1747 	    bi->memlimit64 - 1);
1748 	dsdt_line("        0x0000000000000000, // Translation Offset");
1749 	dsdt_line("        0x%016lX, // Length\n",
1750 	    bi->memlimit64 - bi->membase64);
1751 	dsdt_line("        ,, , AddressRangeMemory, TypeStatic)");
1752 	dsdt_line("    })");
1753 
1754 	count = pci_count_lintr(bus);
1755 	if (count != 0) {
1756 		dsdt_indent(2);
1757 		dsdt_line("Name (PPRT, Package ()");
1758 		dsdt_line("{");
1759 		pci_walk_lintr(bus, pci_pirq_prt_entry, NULL);
1760 		dsdt_line("})");
1761 		dsdt_line("Name (APRT, Package ()");
1762 		dsdt_line("{");
1763 		pci_walk_lintr(bus, pci_apic_prt_entry, NULL);
1764 		dsdt_line("})");
1765 		dsdt_line("Method (_PRT, 0, NotSerialized)");
1766 		dsdt_line("{");
1767 		dsdt_line("  If (PICM)");
1768 		dsdt_line("  {");
1769 		dsdt_line("    Return (APRT)");
1770 		dsdt_line("  }");
1771 		dsdt_line("  Else");
1772 		dsdt_line("  {");
1773 		dsdt_line("    Return (PPRT)");
1774 		dsdt_line("  }");
1775 		dsdt_line("}");
1776 		dsdt_unindent(2);
1777 	}
1778 
1779 	dsdt_indent(2);
1780 	for (slot = 0; slot < MAXSLOTS; slot++) {
1781 		si = &bi->slotinfo[slot];
1782 		for (func = 0; func < MAXFUNCS; func++) {
1783 			pi = si->si_funcs[func].fi_devi;
1784 			if (pi != NULL && pi->pi_d->pe_write_dsdt != NULL)
1785 				pi->pi_d->pe_write_dsdt(pi);
1786 		}
1787 	}
1788 	dsdt_unindent(2);
1789 done:
1790 	dsdt_line("  }");
1791 }
1792 
1793 void
1794 pci_write_dsdt(void)
1795 {
1796 	int bus;
1797 
1798 	dsdt_indent(1);
1799 	dsdt_line("Name (PICM, 0x00)");
1800 	dsdt_line("Method (_PIC, 1, NotSerialized)");
1801 	dsdt_line("{");
1802 	dsdt_line("  Store (Arg0, PICM)");
1803 	dsdt_line("}");
1804 	dsdt_line("");
1805 	dsdt_line("Scope (_SB)");
1806 	dsdt_line("{");
1807 	for (bus = 0; bus < MAXBUSES; bus++)
1808 		pci_bus_write_dsdt(bus);
1809 	dsdt_line("}");
1810 	dsdt_unindent(1);
1811 }
1812 
1813 int
1814 pci_bus_configured(int bus)
1815 {
1816 	assert(bus >= 0 && bus < MAXBUSES);
1817 	return (pci_businfo[bus] != NULL);
1818 }
1819 
1820 int
1821 pci_msi_enabled(struct pci_devinst *pi)
1822 {
1823 	return (pi->pi_msi.enabled);
1824 }
1825 
1826 int
1827 pci_msi_maxmsgnum(struct pci_devinst *pi)
1828 {
1829 	if (pi->pi_msi.enabled)
1830 		return (pi->pi_msi.maxmsgnum);
1831 	else
1832 		return (0);
1833 }
1834 
1835 int
1836 pci_msix_enabled(struct pci_devinst *pi)
1837 {
1838 
1839 	return (pi->pi_msix.enabled && !pi->pi_msi.enabled);
1840 }
1841 
1842 void
1843 pci_generate_msix(struct pci_devinst *pi, int index)
1844 {
1845 	struct msix_table_entry *mte;
1846 
1847 	if (!pci_msix_enabled(pi))
1848 		return;
1849 
1850 	if (pi->pi_msix.function_mask)
1851 		return;
1852 
1853 	if (index >= pi->pi_msix.table_count)
1854 		return;
1855 
1856 	mte = &pi->pi_msix.table[index];
1857 	if ((mte->vector_control & PCIM_MSIX_VCTRL_MASK) == 0) {
1858 		/* XXX Set PBA bit if interrupt is disabled */
1859 		vm_lapic_msi(pi->pi_vmctx, mte->addr, mte->msg_data);
1860 	}
1861 }
1862 
1863 void
1864 pci_generate_msi(struct pci_devinst *pi, int index)
1865 {
1866 
1867 	if (pci_msi_enabled(pi) && index < pci_msi_maxmsgnum(pi)) {
1868 		vm_lapic_msi(pi->pi_vmctx, pi->pi_msi.addr,
1869 			     pi->pi_msi.msg_data + index);
1870 	}
1871 }
1872 
1873 static bool
1874 pci_lintr_permitted(struct pci_devinst *pi)
1875 {
1876 	uint16_t cmd;
1877 
1878 	cmd = pci_get_cfgdata16(pi, PCIR_COMMAND);
1879 	return (!(pi->pi_msi.enabled || pi->pi_msix.enabled ||
1880 		(cmd & PCIM_CMD_INTxDIS)));
1881 }
1882 
1883 void
1884 pci_lintr_request(struct pci_devinst *pi)
1885 {
1886 	struct businfo *bi;
1887 	struct slotinfo *si;
1888 	int bestpin, bestcount, pin;
1889 
1890 	bi = pci_businfo[pi->pi_bus];
1891 	assert(bi != NULL);
1892 
1893 	/*
1894 	 * Just allocate a pin from our slot.  The pin will be
1895 	 * assigned IRQs later when interrupts are routed.
1896 	 */
1897 	si = &bi->slotinfo[pi->pi_slot];
1898 	bestpin = 0;
1899 	bestcount = si->si_intpins[0].ii_count;
1900 	for (pin = 1; pin < 4; pin++) {
1901 		if (si->si_intpins[pin].ii_count < bestcount) {
1902 			bestpin = pin;
1903 			bestcount = si->si_intpins[pin].ii_count;
1904 		}
1905 	}
1906 
1907 	si->si_intpins[bestpin].ii_count++;
1908 	pi->pi_lintr.pin = bestpin + 1;
1909 	pci_set_cfgdata8(pi, PCIR_INTPIN, bestpin + 1);
1910 }
1911 
1912 static void
1913 pci_lintr_route(struct pci_devinst *pi)
1914 {
1915 	struct businfo *bi;
1916 	struct intxinfo *ii;
1917 
1918 	if (pi->pi_lintr.pin == 0)
1919 		return;
1920 
1921 	bi = pci_businfo[pi->pi_bus];
1922 	assert(bi != NULL);
1923 	ii = &bi->slotinfo[pi->pi_slot].si_intpins[pi->pi_lintr.pin - 1];
1924 
1925 	/*
1926 	 * Attempt to allocate an I/O APIC pin for this intpin if one
1927 	 * is not yet assigned.
1928 	 */
1929 	if (ii->ii_ioapic_irq == 0)
1930 		ii->ii_ioapic_irq = ioapic_pci_alloc_irq(pi);
1931 	assert(ii->ii_ioapic_irq > 0);
1932 
1933 	/*
1934 	 * Attempt to allocate a PIRQ pin for this intpin if one is
1935 	 * not yet assigned.
1936 	 */
1937 	if (ii->ii_pirq_pin == 0)
1938 		ii->ii_pirq_pin = pirq_alloc_pin(pi);
1939 	assert(ii->ii_pirq_pin > 0);
1940 
1941 	pi->pi_lintr.ioapic_irq = ii->ii_ioapic_irq;
1942 	pi->pi_lintr.pirq_pin = ii->ii_pirq_pin;
1943 	pci_set_cfgdata8(pi, PCIR_INTLINE, pirq_irq(ii->ii_pirq_pin));
1944 }
1945 
1946 void
1947 pci_lintr_assert(struct pci_devinst *pi)
1948 {
1949 
1950 	assert(pi->pi_lintr.pin > 0);
1951 
1952 	pthread_mutex_lock(&pi->pi_lintr.lock);
1953 	if (pi->pi_lintr.state == IDLE) {
1954 		if (pci_lintr_permitted(pi)) {
1955 			pi->pi_lintr.state = ASSERTED;
1956 			pci_irq_assert(pi);
1957 		} else
1958 			pi->pi_lintr.state = PENDING;
1959 	}
1960 	pthread_mutex_unlock(&pi->pi_lintr.lock);
1961 }
1962 
1963 void
1964 pci_lintr_deassert(struct pci_devinst *pi)
1965 {
1966 
1967 	assert(pi->pi_lintr.pin > 0);
1968 
1969 	pthread_mutex_lock(&pi->pi_lintr.lock);
1970 	if (pi->pi_lintr.state == ASSERTED) {
1971 		pi->pi_lintr.state = IDLE;
1972 		pci_irq_deassert(pi);
1973 	} else if (pi->pi_lintr.state == PENDING)
1974 		pi->pi_lintr.state = IDLE;
1975 	pthread_mutex_unlock(&pi->pi_lintr.lock);
1976 }
1977 
1978 static void
1979 pci_lintr_update(struct pci_devinst *pi)
1980 {
1981 
1982 	pthread_mutex_lock(&pi->pi_lintr.lock);
1983 	if (pi->pi_lintr.state == ASSERTED && !pci_lintr_permitted(pi)) {
1984 		pci_irq_deassert(pi);
1985 		pi->pi_lintr.state = PENDING;
1986 	} else if (pi->pi_lintr.state == PENDING && pci_lintr_permitted(pi)) {
1987 		pi->pi_lintr.state = ASSERTED;
1988 		pci_irq_assert(pi);
1989 	}
1990 	pthread_mutex_unlock(&pi->pi_lintr.lock);
1991 }
1992 
1993 int
1994 pci_count_lintr(int bus)
1995 {
1996 	int count, slot, pin;
1997 	struct slotinfo *slotinfo;
1998 
1999 	count = 0;
2000 	if (pci_businfo[bus] != NULL) {
2001 		for (slot = 0; slot < MAXSLOTS; slot++) {
2002 			slotinfo = &pci_businfo[bus]->slotinfo[slot];
2003 			for (pin = 0; pin < 4; pin++) {
2004 				if (slotinfo->si_intpins[pin].ii_count != 0)
2005 					count++;
2006 			}
2007 		}
2008 	}
2009 	return (count);
2010 }
2011 
2012 void
2013 pci_walk_lintr(int bus, pci_lintr_cb cb, void *arg)
2014 {
2015 	struct businfo *bi;
2016 	struct slotinfo *si;
2017 	struct intxinfo *ii;
2018 	int slot, pin;
2019 
2020 	if ((bi = pci_businfo[bus]) == NULL)
2021 		return;
2022 
2023 	for (slot = 0; slot < MAXSLOTS; slot++) {
2024 		si = &bi->slotinfo[slot];
2025 		for (pin = 0; pin < 4; pin++) {
2026 			ii = &si->si_intpins[pin];
2027 			if (ii->ii_count != 0)
2028 				cb(bus, slot, pin + 1, ii->ii_pirq_pin,
2029 				    ii->ii_ioapic_irq, arg);
2030 		}
2031 	}
2032 }
2033 
2034 /*
2035  * Return 1 if the emulated device in 'slot' is a multi-function device.
2036  * Return 0 otherwise.
2037  */
2038 static int
2039 pci_emul_is_mfdev(int bus, int slot)
2040 {
2041 	struct businfo *bi;
2042 	struct slotinfo *si;
2043 	int f, numfuncs;
2044 
2045 	numfuncs = 0;
2046 	if ((bi = pci_businfo[bus]) != NULL) {
2047 		si = &bi->slotinfo[slot];
2048 		for (f = 0; f < MAXFUNCS; f++) {
2049 			if (si->si_funcs[f].fi_devi != NULL) {
2050 				numfuncs++;
2051 			}
2052 		}
2053 	}
2054 	return (numfuncs > 1);
2055 }
2056 
2057 /*
2058  * Ensure that the PCIM_MFDEV bit is properly set (or unset) depending on
2059  * whether or not is a multi-function being emulated in the pci 'slot'.
2060  */
2061 static void
2062 pci_emul_hdrtype_fixup(int bus, int slot, int off, int bytes, uint32_t *rv)
2063 {
2064 	int mfdev;
2065 
2066 	if (off <= PCIR_HDRTYPE && off + bytes > PCIR_HDRTYPE) {
2067 		mfdev = pci_emul_is_mfdev(bus, slot);
2068 		switch (bytes) {
2069 		case 1:
2070 		case 2:
2071 			*rv &= ~PCIM_MFDEV;
2072 			if (mfdev) {
2073 				*rv |= PCIM_MFDEV;
2074 			}
2075 			break;
2076 		case 4:
2077 			*rv &= ~(PCIM_MFDEV << 16);
2078 			if (mfdev) {
2079 				*rv |= (PCIM_MFDEV << 16);
2080 			}
2081 			break;
2082 		}
2083 	}
2084 }
2085 
2086 /*
2087  * Update device state in response to changes to the PCI command
2088  * register.
2089  */
2090 void
2091 pci_emul_cmd_changed(struct pci_devinst *pi, uint16_t old)
2092 {
2093 	int i;
2094 	uint16_t changed, new;
2095 
2096 	new = pci_get_cfgdata16(pi, PCIR_COMMAND);
2097 	changed = old ^ new;
2098 
2099 	/*
2100 	 * If the MMIO or I/O address space decoding has changed then
2101 	 * register/unregister all BARs that decode that address space.
2102 	 */
2103 	for (i = 0; i <= PCI_BARMAX_WITH_ROM; i++) {
2104 		switch (pi->pi_bar[i].type) {
2105 			case PCIBAR_NONE:
2106 			case PCIBAR_MEMHI64:
2107 				break;
2108 			case PCIBAR_IO:
2109 				/* I/O address space decoding changed? */
2110 				if (changed & PCIM_CMD_PORTEN) {
2111 					if (new & PCIM_CMD_PORTEN)
2112 						register_bar(pi, i);
2113 					else
2114 						unregister_bar(pi, i);
2115 				}
2116 				break;
2117 			case PCIBAR_ROM:
2118 				/* skip (un-)register of ROM if it disabled */
2119 				if (!romen(pi))
2120 					break;
2121 				/* fallthrough */
2122 			case PCIBAR_MEM32:
2123 			case PCIBAR_MEM64:
2124 				/* MMIO address space decoding changed? */
2125 				if (changed & PCIM_CMD_MEMEN) {
2126 					if (new & PCIM_CMD_MEMEN)
2127 						register_bar(pi, i);
2128 					else
2129 						unregister_bar(pi, i);
2130 				}
2131 				break;
2132 			default:
2133 				assert(0);
2134 		}
2135 	}
2136 
2137 	/*
2138 	 * If INTx has been unmasked and is pending, assert the
2139 	 * interrupt.
2140 	 */
2141 	pci_lintr_update(pi);
2142 }
2143 
2144 static void
2145 pci_emul_cmdsts_write(struct pci_devinst *pi, int coff, uint32_t new, int bytes)
2146 {
2147 	int rshift;
2148 	uint32_t cmd, old, readonly;
2149 
2150 	cmd = pci_get_cfgdata16(pi, PCIR_COMMAND);	/* stash old value */
2151 
2152 	/*
2153 	 * From PCI Local Bus Specification 3.0 sections 6.2.2 and 6.2.3.
2154 	 *
2155 	 * XXX Bits 8, 11, 12, 13, 14 and 15 in the status register are
2156 	 * 'write 1 to clear'. However these bits are not set to '1' by
2157 	 * any device emulation so it is simpler to treat them as readonly.
2158 	 */
2159 	rshift = (coff & 0x3) * 8;
2160 	readonly = 0xFFFFF880 >> rshift;
2161 
2162 	old = CFGREAD(pi, coff, bytes);
2163 	new &= ~readonly;
2164 	new |= (old & readonly);
2165 	CFGWRITE(pi, coff, new, bytes);			/* update config */
2166 
2167 	pci_emul_cmd_changed(pi, cmd);
2168 }
2169 
2170 static void
2171 pci_cfgrw(int in, int bus, int slot, int func, int coff, int bytes,
2172     uint32_t *valp)
2173 {
2174 	struct businfo *bi;
2175 	struct slotinfo *si;
2176 	struct pci_devinst *pi;
2177 	struct pci_devemu *pe;
2178 	int idx, needcfg;
2179 	uint64_t addr, bar, mask;
2180 
2181 	if ((bi = pci_businfo[bus]) != NULL) {
2182 		si = &bi->slotinfo[slot];
2183 		pi = si->si_funcs[func].fi_devi;
2184 	} else
2185 		pi = NULL;
2186 
2187 	/*
2188 	 * Just return if there is no device at this slot:func or if the
2189 	 * the guest is doing an un-aligned access.
2190 	 */
2191 	if (pi == NULL || (bytes != 1 && bytes != 2 && bytes != 4) ||
2192 	    (coff & (bytes - 1)) != 0) {
2193 		if (in)
2194 			*valp = 0xffffffff;
2195 		return;
2196 	}
2197 
2198 	/*
2199 	 * Ignore all writes beyond the standard config space and return all
2200 	 * ones on reads.
2201 	 */
2202 	if (coff >= PCI_REGMAX + 1) {
2203 		if (in) {
2204 			*valp = 0xffffffff;
2205 			/*
2206 			 * Extended capabilities begin at offset 256 in config
2207 			 * space. Absence of extended capabilities is signaled
2208 			 * with all 0s in the extended capability header at
2209 			 * offset 256.
2210 			 */
2211 			if (coff <= PCI_REGMAX + 4)
2212 				*valp = 0x00000000;
2213 		}
2214 		return;
2215 	}
2216 
2217 	pe = pi->pi_d;
2218 
2219 	/*
2220 	 * Config read
2221 	 */
2222 	if (in) {
2223 		/* Let the device emulation override the default handler */
2224 		if (pe->pe_cfgread != NULL) {
2225 			needcfg = pe->pe_cfgread(pi, coff, bytes, valp);
2226 		} else {
2227 			needcfg = 1;
2228 		}
2229 
2230 		if (needcfg)
2231 			*valp = CFGREAD(pi, coff, bytes);
2232 
2233 		pci_emul_hdrtype_fixup(bus, slot, coff, bytes, valp);
2234 	} else {
2235 		/* Let the device emulation override the default handler */
2236 		if (pe->pe_cfgwrite != NULL &&
2237 		    (*pe->pe_cfgwrite)(pi, coff, bytes, *valp) == 0)
2238 			return;
2239 
2240 		/*
2241 		 * Special handling for write to BAR and ROM registers
2242 		 */
2243 		if (is_pcir_bar(coff) || is_pcir_bios(coff)) {
2244 			/*
2245 			 * Ignore writes to BAR registers that are not
2246 			 * 4-byte aligned.
2247 			 */
2248 			if (bytes != 4 || (coff & 0x3) != 0)
2249 				return;
2250 
2251 			if (is_pcir_bar(coff)) {
2252 				idx = (coff - PCIR_BAR(0)) / 4;
2253 			} else if (is_pcir_bios(coff)) {
2254 				idx = PCI_ROM_IDX;
2255 			} else {
2256 				errx(4, "%s: invalid BAR offset %d", __func__,
2257 				    coff);
2258 			}
2259 
2260 			mask = ~(pi->pi_bar[idx].size - 1);
2261 			switch (pi->pi_bar[idx].type) {
2262 			case PCIBAR_NONE:
2263 				pi->pi_bar[idx].addr = bar = 0;
2264 				break;
2265 			case PCIBAR_IO:
2266 				addr = *valp & mask;
2267 				addr &= 0xffff;
2268 				bar = addr | pi->pi_bar[idx].lobits;
2269 				/*
2270 				 * Register the new BAR value for interception
2271 				 */
2272 				if (addr != pi->pi_bar[idx].addr) {
2273 					update_bar_address(pi, addr, idx,
2274 							   PCIBAR_IO);
2275 				}
2276 				break;
2277 			case PCIBAR_MEM32:
2278 				addr = bar = *valp & mask;
2279 				bar |= pi->pi_bar[idx].lobits;
2280 				if (addr != pi->pi_bar[idx].addr) {
2281 					update_bar_address(pi, addr, idx,
2282 							   PCIBAR_MEM32);
2283 				}
2284 				break;
2285 			case PCIBAR_MEM64:
2286 				addr = bar = *valp & mask;
2287 				bar |= pi->pi_bar[idx].lobits;
2288 				if (addr != (uint32_t)pi->pi_bar[idx].addr) {
2289 					update_bar_address(pi, addr, idx,
2290 							   PCIBAR_MEM64);
2291 				}
2292 				break;
2293 			case PCIBAR_MEMHI64:
2294 				mask = ~(pi->pi_bar[idx - 1].size - 1);
2295 				addr = ((uint64_t)*valp << 32) & mask;
2296 				bar = addr >> 32;
2297 				if (bar != pi->pi_bar[idx - 1].addr >> 32) {
2298 					update_bar_address(pi, addr, idx - 1,
2299 							   PCIBAR_MEMHI64);
2300 				}
2301 				break;
2302 			case PCIBAR_ROM:
2303 				addr = bar = *valp & mask;
2304 				if (memen(pi) && romen(pi)) {
2305 					unregister_bar(pi, idx);
2306 				}
2307 				pi->pi_bar[idx].addr = addr;
2308 				pi->pi_bar[idx].lobits = *valp &
2309 				    PCIM_BIOS_ENABLE;
2310 				/* romen could have changed it value */
2311 				if (memen(pi) && romen(pi)) {
2312 					register_bar(pi, idx);
2313 				}
2314 				bar |= pi->pi_bar[idx].lobits;
2315 				break;
2316 			default:
2317 				assert(0);
2318 			}
2319 			pci_set_cfgdata32(pi, coff, bar);
2320 
2321 		} else if (pci_emul_iscap(pi, coff)) {
2322 			pci_emul_capwrite(pi, coff, bytes, *valp, 0, 0);
2323 		} else if (coff >= PCIR_COMMAND && coff < PCIR_REVID) {
2324 			pci_emul_cmdsts_write(pi, coff, *valp, bytes);
2325 		} else {
2326 			CFGWRITE(pi, coff, *valp, bytes);
2327 		}
2328 	}
2329 }
2330 
2331 static int cfgenable, cfgbus, cfgslot, cfgfunc, cfgoff;
2332 
2333 static int
2334 pci_emul_cfgaddr(struct vmctx *ctx __unused, int in,
2335     int port __unused, int bytes, uint32_t *eax, void *arg __unused)
2336 {
2337 	uint32_t x;
2338 
2339 	if (bytes != 4) {
2340 		if (in)
2341 			*eax = (bytes == 2) ? 0xffff : 0xff;
2342 		return (0);
2343 	}
2344 
2345 	if (in) {
2346 		x = (cfgbus << 16) | (cfgslot << 11) | (cfgfunc << 8) | cfgoff;
2347 		if (cfgenable)
2348 			x |= CONF1_ENABLE;
2349 		*eax = x;
2350 	} else {
2351 		x = *eax;
2352 		cfgenable = (x & CONF1_ENABLE) == CONF1_ENABLE;
2353 		cfgoff = (x & PCI_REGMAX) & ~0x03;
2354 		cfgfunc = (x >> 8) & PCI_FUNCMAX;
2355 		cfgslot = (x >> 11) & PCI_SLOTMAX;
2356 		cfgbus = (x >> 16) & PCI_BUSMAX;
2357 	}
2358 
2359 	return (0);
2360 }
2361 INOUT_PORT(pci_cfgaddr, CONF1_ADDR_PORT, IOPORT_F_INOUT, pci_emul_cfgaddr);
2362 
2363 static int
2364 pci_emul_cfgdata(struct vmctx *ctx __unused, int in, int port,
2365     int bytes, uint32_t *eax, void *arg __unused)
2366 {
2367 	int coff;
2368 
2369 	assert(bytes == 1 || bytes == 2 || bytes == 4);
2370 
2371 	coff = cfgoff + (port - CONF1_DATA_PORT);
2372 	if (cfgenable) {
2373 		pci_cfgrw(in, cfgbus, cfgslot, cfgfunc, coff, bytes, eax);
2374 	} else {
2375 		/* Ignore accesses to cfgdata if not enabled by cfgaddr */
2376 		if (in)
2377 			*eax = 0xffffffff;
2378 	}
2379 	return (0);
2380 }
2381 
2382 INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+0, IOPORT_F_INOUT, pci_emul_cfgdata);
2383 INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+1, IOPORT_F_INOUT, pci_emul_cfgdata);
2384 INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+2, IOPORT_F_INOUT, pci_emul_cfgdata);
2385 INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+3, IOPORT_F_INOUT, pci_emul_cfgdata);
2386 
2387 #ifdef BHYVE_SNAPSHOT
2388 /*
2389  * Saves/restores PCI device emulated state. Returns 0 on success.
2390  */
2391 static int
2392 pci_snapshot_pci_dev(struct vm_snapshot_meta *meta)
2393 {
2394 	struct pci_devinst *pi;
2395 	int i;
2396 	int ret;
2397 
2398 	pi = meta->dev_data;
2399 
2400 	SNAPSHOT_VAR_OR_LEAVE(pi->pi_msi.enabled, meta, ret, done);
2401 	SNAPSHOT_VAR_OR_LEAVE(pi->pi_msi.addr, meta, ret, done);
2402 	SNAPSHOT_VAR_OR_LEAVE(pi->pi_msi.msg_data, meta, ret, done);
2403 	SNAPSHOT_VAR_OR_LEAVE(pi->pi_msi.maxmsgnum, meta, ret, done);
2404 
2405 	SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.enabled, meta, ret, done);
2406 	SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.table_bar, meta, ret, done);
2407 	SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.pba_bar, meta, ret, done);
2408 	SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.table_offset, meta, ret, done);
2409 	SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.table_count, meta, ret, done);
2410 	SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.pba_offset, meta, ret, done);
2411 	SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.pba_size, meta, ret, done);
2412 	SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.function_mask, meta, ret, done);
2413 
2414 	SNAPSHOT_BUF_OR_LEAVE(pi->pi_cfgdata, sizeof(pi->pi_cfgdata),
2415 			      meta, ret, done);
2416 
2417 	for (i = 0; i < (int)nitems(pi->pi_bar); i++) {
2418 		SNAPSHOT_VAR_OR_LEAVE(pi->pi_bar[i].type, meta, ret, done);
2419 		SNAPSHOT_VAR_OR_LEAVE(pi->pi_bar[i].size, meta, ret, done);
2420 		SNAPSHOT_VAR_OR_LEAVE(pi->pi_bar[i].addr, meta, ret, done);
2421 	}
2422 
2423 	/* Restore MSI-X table. */
2424 	for (i = 0; i < pi->pi_msix.table_count; i++) {
2425 		SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.table[i].addr,
2426 				      meta, ret, done);
2427 		SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.table[i].msg_data,
2428 				      meta, ret, done);
2429 		SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.table[i].vector_control,
2430 				      meta, ret, done);
2431 	}
2432 
2433 done:
2434 	return (ret);
2435 }
2436 
2437 int
2438 pci_snapshot(struct vm_snapshot_meta *meta)
2439 {
2440 	struct pci_devemu *pde;
2441 	struct pci_devinst *pdi;
2442 	int ret;
2443 
2444 	assert(meta->dev_name != NULL);
2445 
2446 	pdi = meta->dev_data;
2447 	pde = pdi->pi_d;
2448 
2449 	if (pde->pe_snapshot == NULL)
2450 		return (ENOTSUP);
2451 
2452 	ret = pci_snapshot_pci_dev(meta);
2453 	if (ret == 0)
2454 		ret = (*pde->pe_snapshot)(meta);
2455 
2456 	return (ret);
2457 }
2458 
2459 int
2460 pci_pause(struct pci_devinst *pdi)
2461 {
2462 	struct pci_devemu *pde = pdi->pi_d;
2463 
2464 	if (pde->pe_pause == NULL) {
2465 		/* The pause/resume functionality is optional. */
2466 		return (0);
2467 	}
2468 
2469 	return (*pde->pe_pause)(pdi);
2470 }
2471 
2472 int
2473 pci_resume(struct pci_devinst *pdi)
2474 {
2475 	struct pci_devemu *pde = pdi->pi_d;
2476 
2477 	if (pde->pe_resume == NULL) {
2478 		/* The pause/resume functionality is optional. */
2479 		return (0);
2480 	}
2481 
2482 	return (*pde->pe_resume)(pdi);
2483 }
2484 #endif
2485 
2486 #define PCI_EMUL_TEST
2487 #ifdef PCI_EMUL_TEST
2488 /*
2489  * Define a dummy test device
2490  */
2491 #define DIOSZ	8
2492 #define DMEMSZ	4096
2493 struct pci_emul_dsoftc {
2494 	uint8_t   ioregs[DIOSZ];
2495 	uint8_t	  memregs[2][DMEMSZ];
2496 };
2497 
2498 #define	PCI_EMUL_MSI_MSGS	 4
2499 #define	PCI_EMUL_MSIX_MSGS	16
2500 
2501 static int
2502 pci_emul_dinit(struct pci_devinst *pi, nvlist_t *nvl __unused)
2503 {
2504 	int error;
2505 	struct pci_emul_dsoftc *sc;
2506 
2507 	sc = calloc(1, sizeof(struct pci_emul_dsoftc));
2508 
2509 	pi->pi_arg = sc;
2510 
2511 	pci_set_cfgdata16(pi, PCIR_DEVICE, 0x0001);
2512 	pci_set_cfgdata16(pi, PCIR_VENDOR, 0x10DD);
2513 	pci_set_cfgdata8(pi, PCIR_CLASS, 0x02);
2514 
2515 	error = pci_emul_add_msicap(pi, PCI_EMUL_MSI_MSGS);
2516 	assert(error == 0);
2517 
2518 	error = pci_emul_alloc_bar(pi, 0, PCIBAR_IO, DIOSZ);
2519 	assert(error == 0);
2520 
2521 	error = pci_emul_alloc_bar(pi, 1, PCIBAR_MEM32, DMEMSZ);
2522 	assert(error == 0);
2523 
2524 	error = pci_emul_alloc_bar(pi, 2, PCIBAR_MEM32, DMEMSZ);
2525 	assert(error == 0);
2526 
2527 	return (0);
2528 }
2529 
2530 static void
2531 pci_emul_diow(struct pci_devinst *pi, int baridx, uint64_t offset, int size,
2532     uint64_t value)
2533 {
2534 	int i;
2535 	struct pci_emul_dsoftc *sc = pi->pi_arg;
2536 
2537 	if (baridx == 0) {
2538 		if (offset + size > DIOSZ) {
2539 			printf("diow: iow too large, offset %ld size %d\n",
2540 			       offset, size);
2541 			return;
2542 		}
2543 
2544 		if (size == 1) {
2545 			sc->ioregs[offset] = value & 0xff;
2546 		} else if (size == 2) {
2547 			*(uint16_t *)&sc->ioregs[offset] = value & 0xffff;
2548 		} else if (size == 4) {
2549 			*(uint32_t *)&sc->ioregs[offset] = value;
2550 		} else {
2551 			printf("diow: iow unknown size %d\n", size);
2552 		}
2553 
2554 		/*
2555 		 * Special magic value to generate an interrupt
2556 		 */
2557 		if (offset == 4 && size == 4 && pci_msi_enabled(pi))
2558 			pci_generate_msi(pi, value % pci_msi_maxmsgnum(pi));
2559 
2560 		if (value == 0xabcdef) {
2561 			for (i = 0; i < pci_msi_maxmsgnum(pi); i++)
2562 				pci_generate_msi(pi, i);
2563 		}
2564 	}
2565 
2566 	if (baridx == 1 || baridx == 2) {
2567 		if (offset + size > DMEMSZ) {
2568 			printf("diow: memw too large, offset %ld size %d\n",
2569 			       offset, size);
2570 			return;
2571 		}
2572 
2573 		i = baridx - 1;		/* 'memregs' index */
2574 
2575 		if (size == 1) {
2576 			sc->memregs[i][offset] = value;
2577 		} else if (size == 2) {
2578 			*(uint16_t *)&sc->memregs[i][offset] = value;
2579 		} else if (size == 4) {
2580 			*(uint32_t *)&sc->memregs[i][offset] = value;
2581 		} else if (size == 8) {
2582 			*(uint64_t *)&sc->memregs[i][offset] = value;
2583 		} else {
2584 			printf("diow: memw unknown size %d\n", size);
2585 		}
2586 
2587 		/*
2588 		 * magic interrupt ??
2589 		 */
2590 	}
2591 
2592 	if (baridx > 2 || baridx < 0) {
2593 		printf("diow: unknown bar idx %d\n", baridx);
2594 	}
2595 }
2596 
2597 static uint64_t
2598 pci_emul_dior(struct pci_devinst *pi, int baridx, uint64_t offset, int size)
2599 {
2600 	struct pci_emul_dsoftc *sc = pi->pi_arg;
2601 	uint32_t value;
2602 	int i;
2603 
2604 	if (baridx == 0) {
2605 		if (offset + size > DIOSZ) {
2606 			printf("dior: ior too large, offset %ld size %d\n",
2607 			       offset, size);
2608 			return (0);
2609 		}
2610 
2611 		value = 0;
2612 		if (size == 1) {
2613 			value = sc->ioregs[offset];
2614 		} else if (size == 2) {
2615 			value = *(uint16_t *) &sc->ioregs[offset];
2616 		} else if (size == 4) {
2617 			value = *(uint32_t *) &sc->ioregs[offset];
2618 		} else {
2619 			printf("dior: ior unknown size %d\n", size);
2620 		}
2621 	}
2622 
2623 	if (baridx == 1 || baridx == 2) {
2624 		if (offset + size > DMEMSZ) {
2625 			printf("dior: memr too large, offset %ld size %d\n",
2626 			       offset, size);
2627 			return (0);
2628 		}
2629 
2630 		i = baridx - 1;		/* 'memregs' index */
2631 
2632 		if (size == 1) {
2633 			value = sc->memregs[i][offset];
2634 		} else if (size == 2) {
2635 			value = *(uint16_t *) &sc->memregs[i][offset];
2636 		} else if (size == 4) {
2637 			value = *(uint32_t *) &sc->memregs[i][offset];
2638 		} else if (size == 8) {
2639 			value = *(uint64_t *) &sc->memregs[i][offset];
2640 		} else {
2641 			printf("dior: ior unknown size %d\n", size);
2642 		}
2643 	}
2644 
2645 
2646 	if (baridx > 2 || baridx < 0) {
2647 		printf("dior: unknown bar idx %d\n", baridx);
2648 		return (0);
2649 	}
2650 
2651 	return (value);
2652 }
2653 
2654 #ifdef BHYVE_SNAPSHOT
2655 struct pci_devinst *
2656 pci_next(const struct pci_devinst *cursor)
2657 {
2658 	unsigned bus = 0, slot = 0, func = 0;
2659 	struct businfo *bi;
2660 	struct slotinfo *si;
2661 	struct funcinfo *fi;
2662 
2663 	bus = cursor ? cursor->pi_bus : 0;
2664 	slot = cursor ? cursor->pi_slot : 0;
2665 	func = cursor ? (cursor->pi_func + 1) : 0;
2666 
2667 	for (; bus < MAXBUSES; bus++) {
2668 		if ((bi = pci_businfo[bus]) == NULL)
2669 			continue;
2670 
2671 		if (slot >= MAXSLOTS)
2672 			slot = 0;
2673 
2674 		for (; slot < MAXSLOTS; slot++) {
2675 			si = &bi->slotinfo[slot];
2676 			if (func >= MAXFUNCS)
2677 				func = 0;
2678 			for (; func < MAXFUNCS; func++) {
2679 				fi = &si->si_funcs[func];
2680 				if (fi->fi_devi == NULL)
2681 					continue;
2682 
2683 				return (fi->fi_devi);
2684 			}
2685 		}
2686 	}
2687 
2688 	return (NULL);
2689 }
2690 
2691 static int
2692 pci_emul_snapshot(struct vm_snapshot_meta *meta __unused)
2693 {
2694 	return (0);
2695 }
2696 #endif
2697 
2698 static const struct pci_devemu pci_dummy = {
2699 	.pe_emu = "dummy",
2700 	.pe_init = pci_emul_dinit,
2701 	.pe_barwrite = pci_emul_diow,
2702 	.pe_barread = pci_emul_dior,
2703 #ifdef BHYVE_SNAPSHOT
2704 	.pe_snapshot = pci_emul_snapshot,
2705 #endif
2706 };
2707 PCI_EMUL_SET(pci_dummy);
2708 
2709 #endif /* PCI_EMUL_TEST */
2710