1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2011 NetApp, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 */ 30 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD$"); 33 34 #include <sys/param.h> 35 #include <sys/linker_set.h> 36 37 #include <ctype.h> 38 #include <errno.h> 39 #include <pthread.h> 40 #include <stdio.h> 41 #include <stdlib.h> 42 #include <string.h> 43 #include <strings.h> 44 #include <assert.h> 45 #include <stdbool.h> 46 47 #include <machine/vmm.h> 48 #include <vmmapi.h> 49 50 #include "acpi.h" 51 #include "bhyverun.h" 52 #include "inout.h" 53 #include "ioapic.h" 54 #include "mem.h" 55 #include "pci_emul.h" 56 #include "pci_irq.h" 57 #include "pci_lpc.h" 58 59 #define CONF1_ADDR_PORT 0x0cf8 60 #define CONF1_DATA_PORT 0x0cfc 61 62 #define CONF1_ENABLE 0x80000000ul 63 64 #define MAXBUSES (PCI_BUSMAX + 1) 65 #define MAXSLOTS (PCI_SLOTMAX + 1) 66 #define MAXFUNCS (PCI_FUNCMAX + 1) 67 68 struct funcinfo { 69 char *fi_name; 70 char *fi_param; 71 struct pci_devinst *fi_devi; 72 }; 73 74 struct intxinfo { 75 int ii_count; 76 int ii_pirq_pin; 77 int ii_ioapic_irq; 78 }; 79 80 struct slotinfo { 81 struct intxinfo si_intpins[4]; 82 struct funcinfo si_funcs[MAXFUNCS]; 83 }; 84 85 struct businfo { 86 uint16_t iobase, iolimit; /* I/O window */ 87 uint32_t membase32, memlimit32; /* mmio window below 4GB */ 88 uint64_t membase64, memlimit64; /* mmio window above 4GB */ 89 struct slotinfo slotinfo[MAXSLOTS]; 90 }; 91 92 static struct businfo *pci_businfo[MAXBUSES]; 93 94 SET_DECLARE(pci_devemu_set, struct pci_devemu); 95 96 static uint64_t pci_emul_iobase; 97 static uint64_t pci_emul_membase32; 98 static uint64_t pci_emul_membase64; 99 100 #define PCI_EMUL_IOBASE 0x2000 101 #define PCI_EMUL_IOLIMIT 0x10000 102 103 #define PCI_EMUL_ECFG_BASE 0xE0000000 /* 3.5GB */ 104 #define PCI_EMUL_ECFG_SIZE (MAXBUSES * 1024 * 1024) /* 1MB per bus */ 105 SYSRES_MEM(PCI_EMUL_ECFG_BASE, PCI_EMUL_ECFG_SIZE); 106 107 #define PCI_EMUL_MEMLIMIT32 PCI_EMUL_ECFG_BASE 108 109 #define PCI_EMUL_MEMBASE64 0xD000000000UL 110 #define PCI_EMUL_MEMLIMIT64 0xFD00000000UL 111 112 static struct pci_devemu *pci_emul_finddev(char *name); 113 static void pci_lintr_route(struct pci_devinst *pi); 114 static void pci_lintr_update(struct pci_devinst *pi); 115 static void pci_cfgrw(struct vmctx *ctx, int vcpu, int in, int bus, int slot, 116 int func, int coff, int bytes, uint32_t *val); 117 118 static __inline void 119 CFGWRITE(struct pci_devinst *pi, int coff, uint32_t val, int bytes) 120 { 121 122 if (bytes == 1) 123 pci_set_cfgdata8(pi, coff, val); 124 else if (bytes == 2) 125 pci_set_cfgdata16(pi, coff, val); 126 else 127 pci_set_cfgdata32(pi, coff, val); 128 } 129 130 static __inline uint32_t 131 CFGREAD(struct pci_devinst *pi, int coff, int bytes) 132 { 133 134 if (bytes == 1) 135 return (pci_get_cfgdata8(pi, coff)); 136 else if (bytes == 2) 137 return (pci_get_cfgdata16(pi, coff)); 138 else 139 return (pci_get_cfgdata32(pi, coff)); 140 } 141 142 /* 143 * I/O access 144 */ 145 146 /* 147 * Slot options are in the form: 148 * 149 * <bus>:<slot>:<func>,<emul>[,<config>] 150 * <slot>[:<func>],<emul>[,<config>] 151 * 152 * slot is 0..31 153 * func is 0..7 154 * emul is a string describing the type of PCI device e.g. virtio-net 155 * config is an optional string, depending on the device, that can be 156 * used for configuration. 157 * Examples are: 158 * 1,virtio-net,tap0 159 * 3:0,dummy 160 */ 161 static void 162 pci_parse_slot_usage(char *aopt) 163 { 164 165 fprintf(stderr, "Invalid PCI slot info field \"%s\"\n", aopt); 166 } 167 168 int 169 pci_parse_slot(char *opt) 170 { 171 struct businfo *bi; 172 struct slotinfo *si; 173 char *emul, *config, *str, *cp; 174 int error, bnum, snum, fnum; 175 176 error = -1; 177 str = strdup(opt); 178 179 emul = config = NULL; 180 if ((cp = strchr(str, ',')) != NULL) { 181 *cp = '\0'; 182 emul = cp + 1; 183 if ((cp = strchr(emul, ',')) != NULL) { 184 *cp = '\0'; 185 config = cp + 1; 186 } 187 } else { 188 pci_parse_slot_usage(opt); 189 goto done; 190 } 191 192 /* <bus>:<slot>:<func> */ 193 if (sscanf(str, "%d:%d:%d", &bnum, &snum, &fnum) != 3) { 194 bnum = 0; 195 /* <slot>:<func> */ 196 if (sscanf(str, "%d:%d", &snum, &fnum) != 2) { 197 fnum = 0; 198 /* <slot> */ 199 if (sscanf(str, "%d", &snum) != 1) { 200 snum = -1; 201 } 202 } 203 } 204 205 if (bnum < 0 || bnum >= MAXBUSES || snum < 0 || snum >= MAXSLOTS || 206 fnum < 0 || fnum >= MAXFUNCS) { 207 pci_parse_slot_usage(opt); 208 goto done; 209 } 210 211 if (pci_businfo[bnum] == NULL) 212 pci_businfo[bnum] = calloc(1, sizeof(struct businfo)); 213 214 bi = pci_businfo[bnum]; 215 si = &bi->slotinfo[snum]; 216 217 if (si->si_funcs[fnum].fi_name != NULL) { 218 fprintf(stderr, "pci slot %d:%d already occupied!\n", 219 snum, fnum); 220 goto done; 221 } 222 223 if (pci_emul_finddev(emul) == NULL) { 224 fprintf(stderr, "pci slot %d:%d: unknown device \"%s\"\n", 225 snum, fnum, emul); 226 goto done; 227 } 228 229 error = 0; 230 si->si_funcs[fnum].fi_name = emul; 231 si->si_funcs[fnum].fi_param = config; 232 233 done: 234 if (error) 235 free(str); 236 237 return (error); 238 } 239 240 void 241 pci_print_supported_devices() 242 { 243 struct pci_devemu **pdpp, *pdp; 244 245 SET_FOREACH(pdpp, pci_devemu_set) { 246 pdp = *pdpp; 247 printf("%s\n", pdp->pe_emu); 248 } 249 } 250 251 static int 252 pci_valid_pba_offset(struct pci_devinst *pi, uint64_t offset) 253 { 254 255 if (offset < pi->pi_msix.pba_offset) 256 return (0); 257 258 if (offset >= pi->pi_msix.pba_offset + pi->pi_msix.pba_size) { 259 return (0); 260 } 261 262 return (1); 263 } 264 265 int 266 pci_emul_msix_twrite(struct pci_devinst *pi, uint64_t offset, int size, 267 uint64_t value) 268 { 269 int msix_entry_offset; 270 int tab_index; 271 char *dest; 272 273 /* support only 4 or 8 byte writes */ 274 if (size != 4 && size != 8) 275 return (-1); 276 277 /* 278 * Return if table index is beyond what device supports 279 */ 280 tab_index = offset / MSIX_TABLE_ENTRY_SIZE; 281 if (tab_index >= pi->pi_msix.table_count) 282 return (-1); 283 284 msix_entry_offset = offset % MSIX_TABLE_ENTRY_SIZE; 285 286 /* support only aligned writes */ 287 if ((msix_entry_offset % size) != 0) 288 return (-1); 289 290 dest = (char *)(pi->pi_msix.table + tab_index); 291 dest += msix_entry_offset; 292 293 if (size == 4) 294 *((uint32_t *)dest) = value; 295 else 296 *((uint64_t *)dest) = value; 297 298 return (0); 299 } 300 301 uint64_t 302 pci_emul_msix_tread(struct pci_devinst *pi, uint64_t offset, int size) 303 { 304 char *dest; 305 int msix_entry_offset; 306 int tab_index; 307 uint64_t retval = ~0; 308 309 /* 310 * The PCI standard only allows 4 and 8 byte accesses to the MSI-X 311 * table but we also allow 1 byte access to accommodate reads from 312 * ddb. 313 */ 314 if (size != 1 && size != 4 && size != 8) 315 return (retval); 316 317 msix_entry_offset = offset % MSIX_TABLE_ENTRY_SIZE; 318 319 /* support only aligned reads */ 320 if ((msix_entry_offset % size) != 0) { 321 return (retval); 322 } 323 324 tab_index = offset / MSIX_TABLE_ENTRY_SIZE; 325 326 if (tab_index < pi->pi_msix.table_count) { 327 /* valid MSI-X Table access */ 328 dest = (char *)(pi->pi_msix.table + tab_index); 329 dest += msix_entry_offset; 330 331 if (size == 1) 332 retval = *((uint8_t *)dest); 333 else if (size == 4) 334 retval = *((uint32_t *)dest); 335 else 336 retval = *((uint64_t *)dest); 337 } else if (pci_valid_pba_offset(pi, offset)) { 338 /* return 0 for PBA access */ 339 retval = 0; 340 } 341 342 return (retval); 343 } 344 345 int 346 pci_msix_table_bar(struct pci_devinst *pi) 347 { 348 349 if (pi->pi_msix.table != NULL) 350 return (pi->pi_msix.table_bar); 351 else 352 return (-1); 353 } 354 355 int 356 pci_msix_pba_bar(struct pci_devinst *pi) 357 { 358 359 if (pi->pi_msix.table != NULL) 360 return (pi->pi_msix.pba_bar); 361 else 362 return (-1); 363 } 364 365 static int 366 pci_emul_io_handler(struct vmctx *ctx, int vcpu, int in, int port, int bytes, 367 uint32_t *eax, void *arg) 368 { 369 struct pci_devinst *pdi = arg; 370 struct pci_devemu *pe = pdi->pi_d; 371 uint64_t offset; 372 int i; 373 374 for (i = 0; i <= PCI_BARMAX; i++) { 375 if (pdi->pi_bar[i].type == PCIBAR_IO && 376 port >= pdi->pi_bar[i].addr && 377 port + bytes <= pdi->pi_bar[i].addr + pdi->pi_bar[i].size) { 378 offset = port - pdi->pi_bar[i].addr; 379 if (in) 380 *eax = (*pe->pe_barread)(ctx, vcpu, pdi, i, 381 offset, bytes); 382 else 383 (*pe->pe_barwrite)(ctx, vcpu, pdi, i, offset, 384 bytes, *eax); 385 return (0); 386 } 387 } 388 return (-1); 389 } 390 391 static int 392 pci_emul_mem_handler(struct vmctx *ctx, int vcpu, int dir, uint64_t addr, 393 int size, uint64_t *val, void *arg1, long arg2) 394 { 395 struct pci_devinst *pdi = arg1; 396 struct pci_devemu *pe = pdi->pi_d; 397 uint64_t offset; 398 int bidx = (int) arg2; 399 400 assert(bidx <= PCI_BARMAX); 401 assert(pdi->pi_bar[bidx].type == PCIBAR_MEM32 || 402 pdi->pi_bar[bidx].type == PCIBAR_MEM64); 403 assert(addr >= pdi->pi_bar[bidx].addr && 404 addr + size <= pdi->pi_bar[bidx].addr + pdi->pi_bar[bidx].size); 405 406 offset = addr - pdi->pi_bar[bidx].addr; 407 408 if (dir == MEM_F_WRITE) { 409 if (size == 8) { 410 (*pe->pe_barwrite)(ctx, vcpu, pdi, bidx, offset, 411 4, *val & 0xffffffff); 412 (*pe->pe_barwrite)(ctx, vcpu, pdi, bidx, offset + 4, 413 4, *val >> 32); 414 } else { 415 (*pe->pe_barwrite)(ctx, vcpu, pdi, bidx, offset, 416 size, *val); 417 } 418 } else { 419 if (size == 8) { 420 *val = (*pe->pe_barread)(ctx, vcpu, pdi, bidx, 421 offset, 4); 422 *val |= (*pe->pe_barread)(ctx, vcpu, pdi, bidx, 423 offset + 4, 4) << 32; 424 } else { 425 *val = (*pe->pe_barread)(ctx, vcpu, pdi, bidx, 426 offset, size); 427 } 428 } 429 430 return (0); 431 } 432 433 434 static int 435 pci_emul_alloc_resource(uint64_t *baseptr, uint64_t limit, uint64_t size, 436 uint64_t *addr) 437 { 438 uint64_t base; 439 440 assert((size & (size - 1)) == 0); /* must be a power of 2 */ 441 442 base = roundup2(*baseptr, size); 443 444 if (base + size <= limit) { 445 *addr = base; 446 *baseptr = base + size; 447 return (0); 448 } else 449 return (-1); 450 } 451 452 int 453 pci_emul_alloc_bar(struct pci_devinst *pdi, int idx, enum pcibar_type type, 454 uint64_t size) 455 { 456 457 return (pci_emul_alloc_pbar(pdi, idx, 0, type, size)); 458 } 459 460 /* 461 * Register (or unregister) the MMIO or I/O region associated with the BAR 462 * register 'idx' of an emulated pci device. 463 */ 464 static void 465 modify_bar_registration(struct pci_devinst *pi, int idx, int registration) 466 { 467 int error; 468 struct inout_port iop; 469 struct mem_range mr; 470 471 switch (pi->pi_bar[idx].type) { 472 case PCIBAR_IO: 473 bzero(&iop, sizeof(struct inout_port)); 474 iop.name = pi->pi_name; 475 iop.port = pi->pi_bar[idx].addr; 476 iop.size = pi->pi_bar[idx].size; 477 if (registration) { 478 iop.flags = IOPORT_F_INOUT; 479 iop.handler = pci_emul_io_handler; 480 iop.arg = pi; 481 error = register_inout(&iop); 482 } else 483 error = unregister_inout(&iop); 484 break; 485 case PCIBAR_MEM32: 486 case PCIBAR_MEM64: 487 bzero(&mr, sizeof(struct mem_range)); 488 mr.name = pi->pi_name; 489 mr.base = pi->pi_bar[idx].addr; 490 mr.size = pi->pi_bar[idx].size; 491 if (registration) { 492 mr.flags = MEM_F_RW; 493 mr.handler = pci_emul_mem_handler; 494 mr.arg1 = pi; 495 mr.arg2 = idx; 496 error = register_mem(&mr); 497 } else 498 error = unregister_mem(&mr); 499 break; 500 default: 501 error = EINVAL; 502 break; 503 } 504 assert(error == 0); 505 } 506 507 static void 508 unregister_bar(struct pci_devinst *pi, int idx) 509 { 510 511 modify_bar_registration(pi, idx, 0); 512 } 513 514 static void 515 register_bar(struct pci_devinst *pi, int idx) 516 { 517 518 modify_bar_registration(pi, idx, 1); 519 } 520 521 /* Are we decoding i/o port accesses for the emulated pci device? */ 522 static int 523 porten(struct pci_devinst *pi) 524 { 525 uint16_t cmd; 526 527 cmd = pci_get_cfgdata16(pi, PCIR_COMMAND); 528 529 return (cmd & PCIM_CMD_PORTEN); 530 } 531 532 /* Are we decoding memory accesses for the emulated pci device? */ 533 static int 534 memen(struct pci_devinst *pi) 535 { 536 uint16_t cmd; 537 538 cmd = pci_get_cfgdata16(pi, PCIR_COMMAND); 539 540 return (cmd & PCIM_CMD_MEMEN); 541 } 542 543 /* 544 * Update the MMIO or I/O address that is decoded by the BAR register. 545 * 546 * If the pci device has enabled the address space decoding then intercept 547 * the address range decoded by the BAR register. 548 */ 549 static void 550 update_bar_address(struct pci_devinst *pi, uint64_t addr, int idx, int type) 551 { 552 int decode; 553 554 if (pi->pi_bar[idx].type == PCIBAR_IO) 555 decode = porten(pi); 556 else 557 decode = memen(pi); 558 559 if (decode) 560 unregister_bar(pi, idx); 561 562 switch (type) { 563 case PCIBAR_IO: 564 case PCIBAR_MEM32: 565 pi->pi_bar[idx].addr = addr; 566 break; 567 case PCIBAR_MEM64: 568 pi->pi_bar[idx].addr &= ~0xffffffffUL; 569 pi->pi_bar[idx].addr |= addr; 570 break; 571 case PCIBAR_MEMHI64: 572 pi->pi_bar[idx].addr &= 0xffffffff; 573 pi->pi_bar[idx].addr |= addr; 574 break; 575 default: 576 assert(0); 577 } 578 579 if (decode) 580 register_bar(pi, idx); 581 } 582 583 int 584 pci_emul_alloc_pbar(struct pci_devinst *pdi, int idx, uint64_t hostbase, 585 enum pcibar_type type, uint64_t size) 586 { 587 int error; 588 uint64_t *baseptr, limit, addr, mask, lobits, bar; 589 uint16_t cmd, enbit; 590 591 assert(idx >= 0 && idx <= PCI_BARMAX); 592 593 if ((size & (size - 1)) != 0) 594 size = 1UL << flsl(size); /* round up to a power of 2 */ 595 596 /* Enforce minimum BAR sizes required by the PCI standard */ 597 if (type == PCIBAR_IO) { 598 if (size < 4) 599 size = 4; 600 } else { 601 if (size < 16) 602 size = 16; 603 } 604 605 switch (type) { 606 case PCIBAR_NONE: 607 baseptr = NULL; 608 addr = mask = lobits = enbit = 0; 609 break; 610 case PCIBAR_IO: 611 baseptr = &pci_emul_iobase; 612 limit = PCI_EMUL_IOLIMIT; 613 mask = PCIM_BAR_IO_BASE; 614 lobits = PCIM_BAR_IO_SPACE; 615 enbit = PCIM_CMD_PORTEN; 616 break; 617 case PCIBAR_MEM64: 618 /* 619 * XXX 620 * Some drivers do not work well if the 64-bit BAR is allocated 621 * above 4GB. Allow for this by allocating small requests under 622 * 4GB unless then allocation size is larger than some arbitrary 623 * number (32MB currently). 624 */ 625 if (size > 32 * 1024 * 1024) { 626 /* 627 * XXX special case for device requiring peer-peer DMA 628 */ 629 if (size == 0x100000000UL) 630 baseptr = &hostbase; 631 else 632 baseptr = &pci_emul_membase64; 633 limit = PCI_EMUL_MEMLIMIT64; 634 mask = PCIM_BAR_MEM_BASE; 635 lobits = PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_64 | 636 PCIM_BAR_MEM_PREFETCH; 637 break; 638 } else { 639 baseptr = &pci_emul_membase32; 640 limit = PCI_EMUL_MEMLIMIT32; 641 mask = PCIM_BAR_MEM_BASE; 642 lobits = PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_64; 643 } 644 enbit = PCIM_CMD_MEMEN; 645 break; 646 case PCIBAR_MEM32: 647 baseptr = &pci_emul_membase32; 648 limit = PCI_EMUL_MEMLIMIT32; 649 mask = PCIM_BAR_MEM_BASE; 650 lobits = PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_32; 651 enbit = PCIM_CMD_MEMEN; 652 break; 653 default: 654 printf("pci_emul_alloc_base: invalid bar type %d\n", type); 655 assert(0); 656 } 657 658 if (baseptr != NULL) { 659 error = pci_emul_alloc_resource(baseptr, limit, size, &addr); 660 if (error != 0) 661 return (error); 662 } 663 664 pdi->pi_bar[idx].type = type; 665 pdi->pi_bar[idx].addr = addr; 666 pdi->pi_bar[idx].size = size; 667 668 /* Initialize the BAR register in config space */ 669 bar = (addr & mask) | lobits; 670 pci_set_cfgdata32(pdi, PCIR_BAR(idx), bar); 671 672 if (type == PCIBAR_MEM64) { 673 assert(idx + 1 <= PCI_BARMAX); 674 pdi->pi_bar[idx + 1].type = PCIBAR_MEMHI64; 675 pci_set_cfgdata32(pdi, PCIR_BAR(idx + 1), bar >> 32); 676 } 677 678 cmd = pci_get_cfgdata16(pdi, PCIR_COMMAND); 679 if ((cmd & enbit) != enbit) 680 pci_set_cfgdata16(pdi, PCIR_COMMAND, cmd | enbit); 681 register_bar(pdi, idx); 682 683 return (0); 684 } 685 686 #define CAP_START_OFFSET 0x40 687 static int 688 pci_emul_add_capability(struct pci_devinst *pi, u_char *capdata, int caplen) 689 { 690 int i, capoff, reallen; 691 uint16_t sts; 692 693 assert(caplen > 0); 694 695 reallen = roundup2(caplen, 4); /* dword aligned */ 696 697 sts = pci_get_cfgdata16(pi, PCIR_STATUS); 698 if ((sts & PCIM_STATUS_CAPPRESENT) == 0) 699 capoff = CAP_START_OFFSET; 700 else 701 capoff = pi->pi_capend + 1; 702 703 /* Check if we have enough space */ 704 if (capoff + reallen > PCI_REGMAX + 1) 705 return (-1); 706 707 /* Set the previous capability pointer */ 708 if ((sts & PCIM_STATUS_CAPPRESENT) == 0) { 709 pci_set_cfgdata8(pi, PCIR_CAP_PTR, capoff); 710 pci_set_cfgdata16(pi, PCIR_STATUS, sts|PCIM_STATUS_CAPPRESENT); 711 } else 712 pci_set_cfgdata8(pi, pi->pi_prevcap + 1, capoff); 713 714 /* Copy the capability */ 715 for (i = 0; i < caplen; i++) 716 pci_set_cfgdata8(pi, capoff + i, capdata[i]); 717 718 /* Set the next capability pointer */ 719 pci_set_cfgdata8(pi, capoff + 1, 0); 720 721 pi->pi_prevcap = capoff; 722 pi->pi_capend = capoff + reallen - 1; 723 return (0); 724 } 725 726 static struct pci_devemu * 727 pci_emul_finddev(char *name) 728 { 729 struct pci_devemu **pdpp, *pdp; 730 731 SET_FOREACH(pdpp, pci_devemu_set) { 732 pdp = *pdpp; 733 if (!strcmp(pdp->pe_emu, name)) { 734 return (pdp); 735 } 736 } 737 738 return (NULL); 739 } 740 741 static int 742 pci_emul_init(struct vmctx *ctx, struct pci_devemu *pde, int bus, int slot, 743 int func, struct funcinfo *fi) 744 { 745 struct pci_devinst *pdi; 746 int err; 747 748 pdi = calloc(1, sizeof(struct pci_devinst)); 749 750 pdi->pi_vmctx = ctx; 751 pdi->pi_bus = bus; 752 pdi->pi_slot = slot; 753 pdi->pi_func = func; 754 pthread_mutex_init(&pdi->pi_lintr.lock, NULL); 755 pdi->pi_lintr.pin = 0; 756 pdi->pi_lintr.state = IDLE; 757 pdi->pi_lintr.pirq_pin = 0; 758 pdi->pi_lintr.ioapic_irq = 0; 759 pdi->pi_d = pde; 760 snprintf(pdi->pi_name, PI_NAMESZ, "%s-pci-%d", pde->pe_emu, slot); 761 762 /* Disable legacy interrupts */ 763 pci_set_cfgdata8(pdi, PCIR_INTLINE, 255); 764 pci_set_cfgdata8(pdi, PCIR_INTPIN, 0); 765 766 pci_set_cfgdata8(pdi, PCIR_COMMAND, PCIM_CMD_BUSMASTEREN); 767 768 err = (*pde->pe_init)(ctx, pdi, fi->fi_param); 769 if (err == 0) 770 fi->fi_devi = pdi; 771 else 772 free(pdi); 773 774 return (err); 775 } 776 777 void 778 pci_populate_msicap(struct msicap *msicap, int msgnum, int nextptr) 779 { 780 int mmc; 781 782 /* Number of msi messages must be a power of 2 between 1 and 32 */ 783 assert((msgnum & (msgnum - 1)) == 0 && msgnum >= 1 && msgnum <= 32); 784 mmc = ffs(msgnum) - 1; 785 786 bzero(msicap, sizeof(struct msicap)); 787 msicap->capid = PCIY_MSI; 788 msicap->nextptr = nextptr; 789 msicap->msgctrl = PCIM_MSICTRL_64BIT | (mmc << 1); 790 } 791 792 int 793 pci_emul_add_msicap(struct pci_devinst *pi, int msgnum) 794 { 795 struct msicap msicap; 796 797 pci_populate_msicap(&msicap, msgnum, 0); 798 799 return (pci_emul_add_capability(pi, (u_char *)&msicap, sizeof(msicap))); 800 } 801 802 static void 803 pci_populate_msixcap(struct msixcap *msixcap, int msgnum, int barnum, 804 uint32_t msix_tab_size) 805 { 806 807 assert(msix_tab_size % 4096 == 0); 808 809 bzero(msixcap, sizeof(struct msixcap)); 810 msixcap->capid = PCIY_MSIX; 811 812 /* 813 * Message Control Register, all fields set to 814 * zero except for the Table Size. 815 * Note: Table size N is encoded as N-1 816 */ 817 msixcap->msgctrl = msgnum - 1; 818 819 /* 820 * MSI-X BAR setup: 821 * - MSI-X table start at offset 0 822 * - PBA table starts at a 4K aligned offset after the MSI-X table 823 */ 824 msixcap->table_info = barnum & PCIM_MSIX_BIR_MASK; 825 msixcap->pba_info = msix_tab_size | (barnum & PCIM_MSIX_BIR_MASK); 826 } 827 828 static void 829 pci_msix_table_init(struct pci_devinst *pi, int table_entries) 830 { 831 int i, table_size; 832 833 assert(table_entries > 0); 834 assert(table_entries <= MAX_MSIX_TABLE_ENTRIES); 835 836 table_size = table_entries * MSIX_TABLE_ENTRY_SIZE; 837 pi->pi_msix.table = calloc(1, table_size); 838 839 /* set mask bit of vector control register */ 840 for (i = 0; i < table_entries; i++) 841 pi->pi_msix.table[i].vector_control |= PCIM_MSIX_VCTRL_MASK; 842 } 843 844 int 845 pci_emul_add_msixcap(struct pci_devinst *pi, int msgnum, int barnum) 846 { 847 uint32_t tab_size; 848 struct msixcap msixcap; 849 850 assert(msgnum >= 1 && msgnum <= MAX_MSIX_TABLE_ENTRIES); 851 assert(barnum >= 0 && barnum <= PCIR_MAX_BAR_0); 852 853 tab_size = msgnum * MSIX_TABLE_ENTRY_SIZE; 854 855 /* Align table size to nearest 4K */ 856 tab_size = roundup2(tab_size, 4096); 857 858 pi->pi_msix.table_bar = barnum; 859 pi->pi_msix.pba_bar = barnum; 860 pi->pi_msix.table_offset = 0; 861 pi->pi_msix.table_count = msgnum; 862 pi->pi_msix.pba_offset = tab_size; 863 pi->pi_msix.pba_size = PBA_SIZE(msgnum); 864 865 pci_msix_table_init(pi, msgnum); 866 867 pci_populate_msixcap(&msixcap, msgnum, barnum, tab_size); 868 869 /* allocate memory for MSI-X Table and PBA */ 870 pci_emul_alloc_bar(pi, barnum, PCIBAR_MEM32, 871 tab_size + pi->pi_msix.pba_size); 872 873 return (pci_emul_add_capability(pi, (u_char *)&msixcap, 874 sizeof(msixcap))); 875 } 876 877 void 878 msixcap_cfgwrite(struct pci_devinst *pi, int capoff, int offset, 879 int bytes, uint32_t val) 880 { 881 uint16_t msgctrl, rwmask; 882 int off; 883 884 off = offset - capoff; 885 /* Message Control Register */ 886 if (off == 2 && bytes == 2) { 887 rwmask = PCIM_MSIXCTRL_MSIX_ENABLE | PCIM_MSIXCTRL_FUNCTION_MASK; 888 msgctrl = pci_get_cfgdata16(pi, offset); 889 msgctrl &= ~rwmask; 890 msgctrl |= val & rwmask; 891 val = msgctrl; 892 893 pi->pi_msix.enabled = val & PCIM_MSIXCTRL_MSIX_ENABLE; 894 pi->pi_msix.function_mask = val & PCIM_MSIXCTRL_FUNCTION_MASK; 895 pci_lintr_update(pi); 896 } 897 898 CFGWRITE(pi, offset, val, bytes); 899 } 900 901 void 902 msicap_cfgwrite(struct pci_devinst *pi, int capoff, int offset, 903 int bytes, uint32_t val) 904 { 905 uint16_t msgctrl, rwmask, msgdata, mme; 906 uint32_t addrlo; 907 908 /* 909 * If guest is writing to the message control register make sure 910 * we do not overwrite read-only fields. 911 */ 912 if ((offset - capoff) == 2 && bytes == 2) { 913 rwmask = PCIM_MSICTRL_MME_MASK | PCIM_MSICTRL_MSI_ENABLE; 914 msgctrl = pci_get_cfgdata16(pi, offset); 915 msgctrl &= ~rwmask; 916 msgctrl |= val & rwmask; 917 val = msgctrl; 918 919 addrlo = pci_get_cfgdata32(pi, capoff + 4); 920 if (msgctrl & PCIM_MSICTRL_64BIT) 921 msgdata = pci_get_cfgdata16(pi, capoff + 12); 922 else 923 msgdata = pci_get_cfgdata16(pi, capoff + 8); 924 925 mme = msgctrl & PCIM_MSICTRL_MME_MASK; 926 pi->pi_msi.enabled = msgctrl & PCIM_MSICTRL_MSI_ENABLE ? 1 : 0; 927 if (pi->pi_msi.enabled) { 928 pi->pi_msi.addr = addrlo; 929 pi->pi_msi.msg_data = msgdata; 930 pi->pi_msi.maxmsgnum = 1 << (mme >> 4); 931 } else { 932 pi->pi_msi.maxmsgnum = 0; 933 } 934 pci_lintr_update(pi); 935 } 936 937 CFGWRITE(pi, offset, val, bytes); 938 } 939 940 void 941 pciecap_cfgwrite(struct pci_devinst *pi, int capoff, int offset, 942 int bytes, uint32_t val) 943 { 944 945 /* XXX don't write to the readonly parts */ 946 CFGWRITE(pi, offset, val, bytes); 947 } 948 949 #define PCIECAP_VERSION 0x2 950 int 951 pci_emul_add_pciecap(struct pci_devinst *pi, int type) 952 { 953 int err; 954 struct pciecap pciecap; 955 956 bzero(&pciecap, sizeof(pciecap)); 957 958 /* 959 * Use the integrated endpoint type for endpoints on a root complex bus. 960 * 961 * NB: bhyve currently only supports a single PCI bus that is the root 962 * complex bus, so all endpoints are integrated. 963 */ 964 if ((type == PCIEM_TYPE_ENDPOINT) && (pi->pi_bus == 0)) 965 type = PCIEM_TYPE_ROOT_INT_EP; 966 967 pciecap.capid = PCIY_EXPRESS; 968 pciecap.pcie_capabilities = PCIECAP_VERSION | type; 969 if (type != PCIEM_TYPE_ROOT_INT_EP) { 970 pciecap.link_capabilities = 0x411; /* gen1, x1 */ 971 pciecap.link_status = 0x11; /* gen1, x1 */ 972 } 973 974 err = pci_emul_add_capability(pi, (u_char *)&pciecap, sizeof(pciecap)); 975 return (err); 976 } 977 978 /* 979 * This function assumes that 'coff' is in the capabilities region of the 980 * config space. 981 */ 982 static void 983 pci_emul_capwrite(struct pci_devinst *pi, int offset, int bytes, uint32_t val) 984 { 985 int capid; 986 uint8_t capoff, nextoff; 987 988 /* Do not allow un-aligned writes */ 989 if ((offset & (bytes - 1)) != 0) 990 return; 991 992 /* Find the capability that we want to update */ 993 capoff = CAP_START_OFFSET; 994 while (1) { 995 nextoff = pci_get_cfgdata8(pi, capoff + 1); 996 if (nextoff == 0) 997 break; 998 if (offset >= capoff && offset < nextoff) 999 break; 1000 1001 capoff = nextoff; 1002 } 1003 assert(offset >= capoff); 1004 1005 /* 1006 * Capability ID and Next Capability Pointer are readonly. 1007 * However, some o/s's do 4-byte writes that include these. 1008 * For this case, trim the write back to 2 bytes and adjust 1009 * the data. 1010 */ 1011 if (offset == capoff || offset == capoff + 1) { 1012 if (offset == capoff && bytes == 4) { 1013 bytes = 2; 1014 offset += 2; 1015 val >>= 16; 1016 } else 1017 return; 1018 } 1019 1020 capid = pci_get_cfgdata8(pi, capoff); 1021 switch (capid) { 1022 case PCIY_MSI: 1023 msicap_cfgwrite(pi, capoff, offset, bytes, val); 1024 break; 1025 case PCIY_MSIX: 1026 msixcap_cfgwrite(pi, capoff, offset, bytes, val); 1027 break; 1028 case PCIY_EXPRESS: 1029 pciecap_cfgwrite(pi, capoff, offset, bytes, val); 1030 break; 1031 default: 1032 break; 1033 } 1034 } 1035 1036 static int 1037 pci_emul_iscap(struct pci_devinst *pi, int offset) 1038 { 1039 uint16_t sts; 1040 1041 sts = pci_get_cfgdata16(pi, PCIR_STATUS); 1042 if ((sts & PCIM_STATUS_CAPPRESENT) != 0) { 1043 if (offset >= CAP_START_OFFSET && offset <= pi->pi_capend) 1044 return (1); 1045 } 1046 return (0); 1047 } 1048 1049 static int 1050 pci_emul_fallback_handler(struct vmctx *ctx, int vcpu, int dir, uint64_t addr, 1051 int size, uint64_t *val, void *arg1, long arg2) 1052 { 1053 /* 1054 * Ignore writes; return 0xff's for reads. The mem read code 1055 * will take care of truncating to the correct size. 1056 */ 1057 if (dir == MEM_F_READ) { 1058 *val = 0xffffffffffffffff; 1059 } 1060 1061 return (0); 1062 } 1063 1064 static int 1065 pci_emul_ecfg_handler(struct vmctx *ctx, int vcpu, int dir, uint64_t addr, 1066 int bytes, uint64_t *val, void *arg1, long arg2) 1067 { 1068 int bus, slot, func, coff, in; 1069 1070 coff = addr & 0xfff; 1071 func = (addr >> 12) & 0x7; 1072 slot = (addr >> 15) & 0x1f; 1073 bus = (addr >> 20) & 0xff; 1074 in = (dir == MEM_F_READ); 1075 if (in) 1076 *val = ~0UL; 1077 pci_cfgrw(ctx, vcpu, in, bus, slot, func, coff, bytes, (uint32_t *)val); 1078 return (0); 1079 } 1080 1081 uint64_t 1082 pci_ecfg_base(void) 1083 { 1084 1085 return (PCI_EMUL_ECFG_BASE); 1086 } 1087 1088 #define BUSIO_ROUNDUP 32 1089 #define BUSMEM_ROUNDUP (1024 * 1024) 1090 1091 int 1092 init_pci(struct vmctx *ctx) 1093 { 1094 struct mem_range mr; 1095 struct pci_devemu *pde; 1096 struct businfo *bi; 1097 struct slotinfo *si; 1098 struct funcinfo *fi; 1099 size_t lowmem; 1100 int bus, slot, func; 1101 int error; 1102 1103 pci_emul_iobase = PCI_EMUL_IOBASE; 1104 pci_emul_membase32 = vm_get_lowmem_limit(ctx); 1105 pci_emul_membase64 = PCI_EMUL_MEMBASE64; 1106 1107 for (bus = 0; bus < MAXBUSES; bus++) { 1108 if ((bi = pci_businfo[bus]) == NULL) 1109 continue; 1110 /* 1111 * Keep track of the i/o and memory resources allocated to 1112 * this bus. 1113 */ 1114 bi->iobase = pci_emul_iobase; 1115 bi->membase32 = pci_emul_membase32; 1116 bi->membase64 = pci_emul_membase64; 1117 1118 for (slot = 0; slot < MAXSLOTS; slot++) { 1119 si = &bi->slotinfo[slot]; 1120 for (func = 0; func < MAXFUNCS; func++) { 1121 fi = &si->si_funcs[func]; 1122 if (fi->fi_name == NULL) 1123 continue; 1124 pde = pci_emul_finddev(fi->fi_name); 1125 assert(pde != NULL); 1126 error = pci_emul_init(ctx, pde, bus, slot, 1127 func, fi); 1128 if (error) 1129 return (error); 1130 } 1131 } 1132 1133 /* 1134 * Add some slop to the I/O and memory resources decoded by 1135 * this bus to give a guest some flexibility if it wants to 1136 * reprogram the BARs. 1137 */ 1138 pci_emul_iobase += BUSIO_ROUNDUP; 1139 pci_emul_iobase = roundup2(pci_emul_iobase, BUSIO_ROUNDUP); 1140 bi->iolimit = pci_emul_iobase; 1141 1142 pci_emul_membase32 += BUSMEM_ROUNDUP; 1143 pci_emul_membase32 = roundup2(pci_emul_membase32, 1144 BUSMEM_ROUNDUP); 1145 bi->memlimit32 = pci_emul_membase32; 1146 1147 pci_emul_membase64 += BUSMEM_ROUNDUP; 1148 pci_emul_membase64 = roundup2(pci_emul_membase64, 1149 BUSMEM_ROUNDUP); 1150 bi->memlimit64 = pci_emul_membase64; 1151 } 1152 1153 /* 1154 * PCI backends are initialized before routing INTx interrupts 1155 * so that LPC devices are able to reserve ISA IRQs before 1156 * routing PIRQ pins. 1157 */ 1158 for (bus = 0; bus < MAXBUSES; bus++) { 1159 if ((bi = pci_businfo[bus]) == NULL) 1160 continue; 1161 1162 for (slot = 0; slot < MAXSLOTS; slot++) { 1163 si = &bi->slotinfo[slot]; 1164 for (func = 0; func < MAXFUNCS; func++) { 1165 fi = &si->si_funcs[func]; 1166 if (fi->fi_devi == NULL) 1167 continue; 1168 pci_lintr_route(fi->fi_devi); 1169 } 1170 } 1171 } 1172 lpc_pirq_routed(); 1173 1174 /* 1175 * The guest physical memory map looks like the following: 1176 * [0, lowmem) guest system memory 1177 * [lowmem, lowmem_limit) memory hole (may be absent) 1178 * [lowmem_limit, 0xE0000000) PCI hole (32-bit BAR allocation) 1179 * [0xE0000000, 0xF0000000) PCI extended config window 1180 * [0xF0000000, 4GB) LAPIC, IOAPIC, HPET, firmware 1181 * [4GB, 4GB + highmem) 1182 */ 1183 1184 /* 1185 * Accesses to memory addresses that are not allocated to system 1186 * memory or PCI devices return 0xff's. 1187 */ 1188 lowmem = vm_get_lowmem_size(ctx); 1189 bzero(&mr, sizeof(struct mem_range)); 1190 mr.name = "PCI hole"; 1191 mr.flags = MEM_F_RW | MEM_F_IMMUTABLE; 1192 mr.base = lowmem; 1193 mr.size = (4ULL * 1024 * 1024 * 1024) - lowmem; 1194 mr.handler = pci_emul_fallback_handler; 1195 error = register_mem_fallback(&mr); 1196 assert(error == 0); 1197 1198 /* PCI extended config space */ 1199 bzero(&mr, sizeof(struct mem_range)); 1200 mr.name = "PCI ECFG"; 1201 mr.flags = MEM_F_RW | MEM_F_IMMUTABLE; 1202 mr.base = PCI_EMUL_ECFG_BASE; 1203 mr.size = PCI_EMUL_ECFG_SIZE; 1204 mr.handler = pci_emul_ecfg_handler; 1205 error = register_mem(&mr); 1206 assert(error == 0); 1207 1208 return (0); 1209 } 1210 1211 static void 1212 pci_apic_prt_entry(int bus, int slot, int pin, int pirq_pin, int ioapic_irq, 1213 void *arg) 1214 { 1215 1216 dsdt_line(" Package ()"); 1217 dsdt_line(" {"); 1218 dsdt_line(" 0x%X,", slot << 16 | 0xffff); 1219 dsdt_line(" 0x%02X,", pin - 1); 1220 dsdt_line(" Zero,"); 1221 dsdt_line(" 0x%X", ioapic_irq); 1222 dsdt_line(" },"); 1223 } 1224 1225 static void 1226 pci_pirq_prt_entry(int bus, int slot, int pin, int pirq_pin, int ioapic_irq, 1227 void *arg) 1228 { 1229 char *name; 1230 1231 name = lpc_pirq_name(pirq_pin); 1232 if (name == NULL) 1233 return; 1234 dsdt_line(" Package ()"); 1235 dsdt_line(" {"); 1236 dsdt_line(" 0x%X,", slot << 16 | 0xffff); 1237 dsdt_line(" 0x%02X,", pin - 1); 1238 dsdt_line(" %s,", name); 1239 dsdt_line(" 0x00"); 1240 dsdt_line(" },"); 1241 free(name); 1242 } 1243 1244 /* 1245 * A bhyve virtual machine has a flat PCI hierarchy with a root port 1246 * corresponding to each PCI bus. 1247 */ 1248 static void 1249 pci_bus_write_dsdt(int bus) 1250 { 1251 struct businfo *bi; 1252 struct slotinfo *si; 1253 struct pci_devinst *pi; 1254 int count, func, slot; 1255 1256 /* 1257 * If there are no devices on this 'bus' then just return. 1258 */ 1259 if ((bi = pci_businfo[bus]) == NULL) { 1260 /* 1261 * Bus 0 is special because it decodes the I/O ports used 1262 * for PCI config space access even if there are no devices 1263 * on it. 1264 */ 1265 if (bus != 0) 1266 return; 1267 } 1268 1269 dsdt_line(" Device (PC%02X)", bus); 1270 dsdt_line(" {"); 1271 dsdt_line(" Name (_HID, EisaId (\"PNP0A03\"))"); 1272 dsdt_line(" Name (_ADR, Zero)"); 1273 1274 dsdt_line(" Method (_BBN, 0, NotSerialized)"); 1275 dsdt_line(" {"); 1276 dsdt_line(" Return (0x%08X)", bus); 1277 dsdt_line(" }"); 1278 dsdt_line(" Name (_CRS, ResourceTemplate ()"); 1279 dsdt_line(" {"); 1280 dsdt_line(" WordBusNumber (ResourceProducer, MinFixed, " 1281 "MaxFixed, PosDecode,"); 1282 dsdt_line(" 0x0000, // Granularity"); 1283 dsdt_line(" 0x%04X, // Range Minimum", bus); 1284 dsdt_line(" 0x%04X, // Range Maximum", bus); 1285 dsdt_line(" 0x0000, // Translation Offset"); 1286 dsdt_line(" 0x0001, // Length"); 1287 dsdt_line(" ,, )"); 1288 1289 if (bus == 0) { 1290 dsdt_indent(3); 1291 dsdt_fixed_ioport(0xCF8, 8); 1292 dsdt_unindent(3); 1293 1294 dsdt_line(" WordIO (ResourceProducer, MinFixed, MaxFixed, " 1295 "PosDecode, EntireRange,"); 1296 dsdt_line(" 0x0000, // Granularity"); 1297 dsdt_line(" 0x0000, // Range Minimum"); 1298 dsdt_line(" 0x0CF7, // Range Maximum"); 1299 dsdt_line(" 0x0000, // Translation Offset"); 1300 dsdt_line(" 0x0CF8, // Length"); 1301 dsdt_line(" ,, , TypeStatic)"); 1302 1303 dsdt_line(" WordIO (ResourceProducer, MinFixed, MaxFixed, " 1304 "PosDecode, EntireRange,"); 1305 dsdt_line(" 0x0000, // Granularity"); 1306 dsdt_line(" 0x0D00, // Range Minimum"); 1307 dsdt_line(" 0x%04X, // Range Maximum", 1308 PCI_EMUL_IOBASE - 1); 1309 dsdt_line(" 0x0000, // Translation Offset"); 1310 dsdt_line(" 0x%04X, // Length", 1311 PCI_EMUL_IOBASE - 0x0D00); 1312 dsdt_line(" ,, , TypeStatic)"); 1313 1314 if (bi == NULL) { 1315 dsdt_line(" })"); 1316 goto done; 1317 } 1318 } 1319 assert(bi != NULL); 1320 1321 /* i/o window */ 1322 dsdt_line(" WordIO (ResourceProducer, MinFixed, MaxFixed, " 1323 "PosDecode, EntireRange,"); 1324 dsdt_line(" 0x0000, // Granularity"); 1325 dsdt_line(" 0x%04X, // Range Minimum", bi->iobase); 1326 dsdt_line(" 0x%04X, // Range Maximum", 1327 bi->iolimit - 1); 1328 dsdt_line(" 0x0000, // Translation Offset"); 1329 dsdt_line(" 0x%04X, // Length", 1330 bi->iolimit - bi->iobase); 1331 dsdt_line(" ,, , TypeStatic)"); 1332 1333 /* mmio window (32-bit) */ 1334 dsdt_line(" DWordMemory (ResourceProducer, PosDecode, " 1335 "MinFixed, MaxFixed, NonCacheable, ReadWrite,"); 1336 dsdt_line(" 0x00000000, // Granularity"); 1337 dsdt_line(" 0x%08X, // Range Minimum\n", bi->membase32); 1338 dsdt_line(" 0x%08X, // Range Maximum\n", 1339 bi->memlimit32 - 1); 1340 dsdt_line(" 0x00000000, // Translation Offset"); 1341 dsdt_line(" 0x%08X, // Length\n", 1342 bi->memlimit32 - bi->membase32); 1343 dsdt_line(" ,, , AddressRangeMemory, TypeStatic)"); 1344 1345 /* mmio window (64-bit) */ 1346 dsdt_line(" QWordMemory (ResourceProducer, PosDecode, " 1347 "MinFixed, MaxFixed, NonCacheable, ReadWrite,"); 1348 dsdt_line(" 0x0000000000000000, // Granularity"); 1349 dsdt_line(" 0x%016lX, // Range Minimum\n", bi->membase64); 1350 dsdt_line(" 0x%016lX, // Range Maximum\n", 1351 bi->memlimit64 - 1); 1352 dsdt_line(" 0x0000000000000000, // Translation Offset"); 1353 dsdt_line(" 0x%016lX, // Length\n", 1354 bi->memlimit64 - bi->membase64); 1355 dsdt_line(" ,, , AddressRangeMemory, TypeStatic)"); 1356 dsdt_line(" })"); 1357 1358 count = pci_count_lintr(bus); 1359 if (count != 0) { 1360 dsdt_indent(2); 1361 dsdt_line("Name (PPRT, Package ()"); 1362 dsdt_line("{"); 1363 pci_walk_lintr(bus, pci_pirq_prt_entry, NULL); 1364 dsdt_line("})"); 1365 dsdt_line("Name (APRT, Package ()"); 1366 dsdt_line("{"); 1367 pci_walk_lintr(bus, pci_apic_prt_entry, NULL); 1368 dsdt_line("})"); 1369 dsdt_line("Method (_PRT, 0, NotSerialized)"); 1370 dsdt_line("{"); 1371 dsdt_line(" If (PICM)"); 1372 dsdt_line(" {"); 1373 dsdt_line(" Return (APRT)"); 1374 dsdt_line(" }"); 1375 dsdt_line(" Else"); 1376 dsdt_line(" {"); 1377 dsdt_line(" Return (PPRT)"); 1378 dsdt_line(" }"); 1379 dsdt_line("}"); 1380 dsdt_unindent(2); 1381 } 1382 1383 dsdt_indent(2); 1384 for (slot = 0; slot < MAXSLOTS; slot++) { 1385 si = &bi->slotinfo[slot]; 1386 for (func = 0; func < MAXFUNCS; func++) { 1387 pi = si->si_funcs[func].fi_devi; 1388 if (pi != NULL && pi->pi_d->pe_write_dsdt != NULL) 1389 pi->pi_d->pe_write_dsdt(pi); 1390 } 1391 } 1392 dsdt_unindent(2); 1393 done: 1394 dsdt_line(" }"); 1395 } 1396 1397 void 1398 pci_write_dsdt(void) 1399 { 1400 int bus; 1401 1402 dsdt_indent(1); 1403 dsdt_line("Name (PICM, 0x00)"); 1404 dsdt_line("Method (_PIC, 1, NotSerialized)"); 1405 dsdt_line("{"); 1406 dsdt_line(" Store (Arg0, PICM)"); 1407 dsdt_line("}"); 1408 dsdt_line(""); 1409 dsdt_line("Scope (_SB)"); 1410 dsdt_line("{"); 1411 for (bus = 0; bus < MAXBUSES; bus++) 1412 pci_bus_write_dsdt(bus); 1413 dsdt_line("}"); 1414 dsdt_unindent(1); 1415 } 1416 1417 int 1418 pci_bus_configured(int bus) 1419 { 1420 assert(bus >= 0 && bus < MAXBUSES); 1421 return (pci_businfo[bus] != NULL); 1422 } 1423 1424 int 1425 pci_msi_enabled(struct pci_devinst *pi) 1426 { 1427 return (pi->pi_msi.enabled); 1428 } 1429 1430 int 1431 pci_msi_maxmsgnum(struct pci_devinst *pi) 1432 { 1433 if (pi->pi_msi.enabled) 1434 return (pi->pi_msi.maxmsgnum); 1435 else 1436 return (0); 1437 } 1438 1439 int 1440 pci_msix_enabled(struct pci_devinst *pi) 1441 { 1442 1443 return (pi->pi_msix.enabled && !pi->pi_msi.enabled); 1444 } 1445 1446 void 1447 pci_generate_msix(struct pci_devinst *pi, int index) 1448 { 1449 struct msix_table_entry *mte; 1450 1451 if (!pci_msix_enabled(pi)) 1452 return; 1453 1454 if (pi->pi_msix.function_mask) 1455 return; 1456 1457 if (index >= pi->pi_msix.table_count) 1458 return; 1459 1460 mte = &pi->pi_msix.table[index]; 1461 if ((mte->vector_control & PCIM_MSIX_VCTRL_MASK) == 0) { 1462 /* XXX Set PBA bit if interrupt is disabled */ 1463 vm_lapic_msi(pi->pi_vmctx, mte->addr, mte->msg_data); 1464 } 1465 } 1466 1467 void 1468 pci_generate_msi(struct pci_devinst *pi, int index) 1469 { 1470 1471 if (pci_msi_enabled(pi) && index < pci_msi_maxmsgnum(pi)) { 1472 vm_lapic_msi(pi->pi_vmctx, pi->pi_msi.addr, 1473 pi->pi_msi.msg_data + index); 1474 } 1475 } 1476 1477 static bool 1478 pci_lintr_permitted(struct pci_devinst *pi) 1479 { 1480 uint16_t cmd; 1481 1482 cmd = pci_get_cfgdata16(pi, PCIR_COMMAND); 1483 return (!(pi->pi_msi.enabled || pi->pi_msix.enabled || 1484 (cmd & PCIM_CMD_INTxDIS))); 1485 } 1486 1487 void 1488 pci_lintr_request(struct pci_devinst *pi) 1489 { 1490 struct businfo *bi; 1491 struct slotinfo *si; 1492 int bestpin, bestcount, pin; 1493 1494 bi = pci_businfo[pi->pi_bus]; 1495 assert(bi != NULL); 1496 1497 /* 1498 * Just allocate a pin from our slot. The pin will be 1499 * assigned IRQs later when interrupts are routed. 1500 */ 1501 si = &bi->slotinfo[pi->pi_slot]; 1502 bestpin = 0; 1503 bestcount = si->si_intpins[0].ii_count; 1504 for (pin = 1; pin < 4; pin++) { 1505 if (si->si_intpins[pin].ii_count < bestcount) { 1506 bestpin = pin; 1507 bestcount = si->si_intpins[pin].ii_count; 1508 } 1509 } 1510 1511 si->si_intpins[bestpin].ii_count++; 1512 pi->pi_lintr.pin = bestpin + 1; 1513 pci_set_cfgdata8(pi, PCIR_INTPIN, bestpin + 1); 1514 } 1515 1516 static void 1517 pci_lintr_route(struct pci_devinst *pi) 1518 { 1519 struct businfo *bi; 1520 struct intxinfo *ii; 1521 1522 if (pi->pi_lintr.pin == 0) 1523 return; 1524 1525 bi = pci_businfo[pi->pi_bus]; 1526 assert(bi != NULL); 1527 ii = &bi->slotinfo[pi->pi_slot].si_intpins[pi->pi_lintr.pin - 1]; 1528 1529 /* 1530 * Attempt to allocate an I/O APIC pin for this intpin if one 1531 * is not yet assigned. 1532 */ 1533 if (ii->ii_ioapic_irq == 0) 1534 ii->ii_ioapic_irq = ioapic_pci_alloc_irq(pi); 1535 assert(ii->ii_ioapic_irq > 0); 1536 1537 /* 1538 * Attempt to allocate a PIRQ pin for this intpin if one is 1539 * not yet assigned. 1540 */ 1541 if (ii->ii_pirq_pin == 0) 1542 ii->ii_pirq_pin = pirq_alloc_pin(pi); 1543 assert(ii->ii_pirq_pin > 0); 1544 1545 pi->pi_lintr.ioapic_irq = ii->ii_ioapic_irq; 1546 pi->pi_lintr.pirq_pin = ii->ii_pirq_pin; 1547 pci_set_cfgdata8(pi, PCIR_INTLINE, pirq_irq(ii->ii_pirq_pin)); 1548 } 1549 1550 void 1551 pci_lintr_assert(struct pci_devinst *pi) 1552 { 1553 1554 assert(pi->pi_lintr.pin > 0); 1555 1556 pthread_mutex_lock(&pi->pi_lintr.lock); 1557 if (pi->pi_lintr.state == IDLE) { 1558 if (pci_lintr_permitted(pi)) { 1559 pi->pi_lintr.state = ASSERTED; 1560 pci_irq_assert(pi); 1561 } else 1562 pi->pi_lintr.state = PENDING; 1563 } 1564 pthread_mutex_unlock(&pi->pi_lintr.lock); 1565 } 1566 1567 void 1568 pci_lintr_deassert(struct pci_devinst *pi) 1569 { 1570 1571 assert(pi->pi_lintr.pin > 0); 1572 1573 pthread_mutex_lock(&pi->pi_lintr.lock); 1574 if (pi->pi_lintr.state == ASSERTED) { 1575 pi->pi_lintr.state = IDLE; 1576 pci_irq_deassert(pi); 1577 } else if (pi->pi_lintr.state == PENDING) 1578 pi->pi_lintr.state = IDLE; 1579 pthread_mutex_unlock(&pi->pi_lintr.lock); 1580 } 1581 1582 static void 1583 pci_lintr_update(struct pci_devinst *pi) 1584 { 1585 1586 pthread_mutex_lock(&pi->pi_lintr.lock); 1587 if (pi->pi_lintr.state == ASSERTED && !pci_lintr_permitted(pi)) { 1588 pci_irq_deassert(pi); 1589 pi->pi_lintr.state = PENDING; 1590 } else if (pi->pi_lintr.state == PENDING && pci_lintr_permitted(pi)) { 1591 pi->pi_lintr.state = ASSERTED; 1592 pci_irq_assert(pi); 1593 } 1594 pthread_mutex_unlock(&pi->pi_lintr.lock); 1595 } 1596 1597 int 1598 pci_count_lintr(int bus) 1599 { 1600 int count, slot, pin; 1601 struct slotinfo *slotinfo; 1602 1603 count = 0; 1604 if (pci_businfo[bus] != NULL) { 1605 for (slot = 0; slot < MAXSLOTS; slot++) { 1606 slotinfo = &pci_businfo[bus]->slotinfo[slot]; 1607 for (pin = 0; pin < 4; pin++) { 1608 if (slotinfo->si_intpins[pin].ii_count != 0) 1609 count++; 1610 } 1611 } 1612 } 1613 return (count); 1614 } 1615 1616 void 1617 pci_walk_lintr(int bus, pci_lintr_cb cb, void *arg) 1618 { 1619 struct businfo *bi; 1620 struct slotinfo *si; 1621 struct intxinfo *ii; 1622 int slot, pin; 1623 1624 if ((bi = pci_businfo[bus]) == NULL) 1625 return; 1626 1627 for (slot = 0; slot < MAXSLOTS; slot++) { 1628 si = &bi->slotinfo[slot]; 1629 for (pin = 0; pin < 4; pin++) { 1630 ii = &si->si_intpins[pin]; 1631 if (ii->ii_count != 0) 1632 cb(bus, slot, pin + 1, ii->ii_pirq_pin, 1633 ii->ii_ioapic_irq, arg); 1634 } 1635 } 1636 } 1637 1638 /* 1639 * Return 1 if the emulated device in 'slot' is a multi-function device. 1640 * Return 0 otherwise. 1641 */ 1642 static int 1643 pci_emul_is_mfdev(int bus, int slot) 1644 { 1645 struct businfo *bi; 1646 struct slotinfo *si; 1647 int f, numfuncs; 1648 1649 numfuncs = 0; 1650 if ((bi = pci_businfo[bus]) != NULL) { 1651 si = &bi->slotinfo[slot]; 1652 for (f = 0; f < MAXFUNCS; f++) { 1653 if (si->si_funcs[f].fi_devi != NULL) { 1654 numfuncs++; 1655 } 1656 } 1657 } 1658 return (numfuncs > 1); 1659 } 1660 1661 /* 1662 * Ensure that the PCIM_MFDEV bit is properly set (or unset) depending on 1663 * whether or not is a multi-function being emulated in the pci 'slot'. 1664 */ 1665 static void 1666 pci_emul_hdrtype_fixup(int bus, int slot, int off, int bytes, uint32_t *rv) 1667 { 1668 int mfdev; 1669 1670 if (off <= PCIR_HDRTYPE && off + bytes > PCIR_HDRTYPE) { 1671 mfdev = pci_emul_is_mfdev(bus, slot); 1672 switch (bytes) { 1673 case 1: 1674 case 2: 1675 *rv &= ~PCIM_MFDEV; 1676 if (mfdev) { 1677 *rv |= PCIM_MFDEV; 1678 } 1679 break; 1680 case 4: 1681 *rv &= ~(PCIM_MFDEV << 16); 1682 if (mfdev) { 1683 *rv |= (PCIM_MFDEV << 16); 1684 } 1685 break; 1686 } 1687 } 1688 } 1689 1690 /* 1691 * Update device state in response to changes to the PCI command 1692 * register. 1693 */ 1694 void 1695 pci_emul_cmd_changed(struct pci_devinst *pi, uint16_t old) 1696 { 1697 int i; 1698 uint16_t changed, new; 1699 1700 new = pci_get_cfgdata16(pi, PCIR_COMMAND); 1701 changed = old ^ new; 1702 1703 /* 1704 * If the MMIO or I/O address space decoding has changed then 1705 * register/unregister all BARs that decode that address space. 1706 */ 1707 for (i = 0; i <= PCI_BARMAX; i++) { 1708 switch (pi->pi_bar[i].type) { 1709 case PCIBAR_NONE: 1710 case PCIBAR_MEMHI64: 1711 break; 1712 case PCIBAR_IO: 1713 /* I/O address space decoding changed? */ 1714 if (changed & PCIM_CMD_PORTEN) { 1715 if (new & PCIM_CMD_PORTEN) 1716 register_bar(pi, i); 1717 else 1718 unregister_bar(pi, i); 1719 } 1720 break; 1721 case PCIBAR_MEM32: 1722 case PCIBAR_MEM64: 1723 /* MMIO address space decoding changed? */ 1724 if (changed & PCIM_CMD_MEMEN) { 1725 if (new & PCIM_CMD_MEMEN) 1726 register_bar(pi, i); 1727 else 1728 unregister_bar(pi, i); 1729 } 1730 break; 1731 default: 1732 assert(0); 1733 } 1734 } 1735 1736 /* 1737 * If INTx has been unmasked and is pending, assert the 1738 * interrupt. 1739 */ 1740 pci_lintr_update(pi); 1741 } 1742 1743 static void 1744 pci_emul_cmdsts_write(struct pci_devinst *pi, int coff, uint32_t new, int bytes) 1745 { 1746 int rshift; 1747 uint32_t cmd, old, readonly; 1748 1749 cmd = pci_get_cfgdata16(pi, PCIR_COMMAND); /* stash old value */ 1750 1751 /* 1752 * From PCI Local Bus Specification 3.0 sections 6.2.2 and 6.2.3. 1753 * 1754 * XXX Bits 8, 11, 12, 13, 14 and 15 in the status register are 1755 * 'write 1 to clear'. However these bits are not set to '1' by 1756 * any device emulation so it is simpler to treat them as readonly. 1757 */ 1758 rshift = (coff & 0x3) * 8; 1759 readonly = 0xFFFFF880 >> rshift; 1760 1761 old = CFGREAD(pi, coff, bytes); 1762 new &= ~readonly; 1763 new |= (old & readonly); 1764 CFGWRITE(pi, coff, new, bytes); /* update config */ 1765 1766 pci_emul_cmd_changed(pi, cmd); 1767 } 1768 1769 static void 1770 pci_cfgrw(struct vmctx *ctx, int vcpu, int in, int bus, int slot, int func, 1771 int coff, int bytes, uint32_t *eax) 1772 { 1773 struct businfo *bi; 1774 struct slotinfo *si; 1775 struct pci_devinst *pi; 1776 struct pci_devemu *pe; 1777 int idx, needcfg; 1778 uint64_t addr, bar, mask; 1779 1780 if ((bi = pci_businfo[bus]) != NULL) { 1781 si = &bi->slotinfo[slot]; 1782 pi = si->si_funcs[func].fi_devi; 1783 } else 1784 pi = NULL; 1785 1786 /* 1787 * Just return if there is no device at this slot:func or if the 1788 * the guest is doing an un-aligned access. 1789 */ 1790 if (pi == NULL || (bytes != 1 && bytes != 2 && bytes != 4) || 1791 (coff & (bytes - 1)) != 0) { 1792 if (in) 1793 *eax = 0xffffffff; 1794 return; 1795 } 1796 1797 /* 1798 * Ignore all writes beyond the standard config space and return all 1799 * ones on reads. 1800 */ 1801 if (coff >= PCI_REGMAX + 1) { 1802 if (in) { 1803 *eax = 0xffffffff; 1804 /* 1805 * Extended capabilities begin at offset 256 in config 1806 * space. Absence of extended capabilities is signaled 1807 * with all 0s in the extended capability header at 1808 * offset 256. 1809 */ 1810 if (coff <= PCI_REGMAX + 4) 1811 *eax = 0x00000000; 1812 } 1813 return; 1814 } 1815 1816 pe = pi->pi_d; 1817 1818 /* 1819 * Config read 1820 */ 1821 if (in) { 1822 /* Let the device emulation override the default handler */ 1823 if (pe->pe_cfgread != NULL) { 1824 needcfg = pe->pe_cfgread(ctx, vcpu, pi, coff, bytes, 1825 eax); 1826 } else { 1827 needcfg = 1; 1828 } 1829 1830 if (needcfg) 1831 *eax = CFGREAD(pi, coff, bytes); 1832 1833 pci_emul_hdrtype_fixup(bus, slot, coff, bytes, eax); 1834 } else { 1835 /* Let the device emulation override the default handler */ 1836 if (pe->pe_cfgwrite != NULL && 1837 (*pe->pe_cfgwrite)(ctx, vcpu, pi, coff, bytes, *eax) == 0) 1838 return; 1839 1840 /* 1841 * Special handling for write to BAR registers 1842 */ 1843 if (coff >= PCIR_BAR(0) && coff < PCIR_BAR(PCI_BARMAX + 1)) { 1844 /* 1845 * Ignore writes to BAR registers that are not 1846 * 4-byte aligned. 1847 */ 1848 if (bytes != 4 || (coff & 0x3) != 0) 1849 return; 1850 idx = (coff - PCIR_BAR(0)) / 4; 1851 mask = ~(pi->pi_bar[idx].size - 1); 1852 switch (pi->pi_bar[idx].type) { 1853 case PCIBAR_NONE: 1854 pi->pi_bar[idx].addr = bar = 0; 1855 break; 1856 case PCIBAR_IO: 1857 addr = *eax & mask; 1858 addr &= 0xffff; 1859 bar = addr | PCIM_BAR_IO_SPACE; 1860 /* 1861 * Register the new BAR value for interception 1862 */ 1863 if (addr != pi->pi_bar[idx].addr) { 1864 update_bar_address(pi, addr, idx, 1865 PCIBAR_IO); 1866 } 1867 break; 1868 case PCIBAR_MEM32: 1869 addr = bar = *eax & mask; 1870 bar |= PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_32; 1871 if (addr != pi->pi_bar[idx].addr) { 1872 update_bar_address(pi, addr, idx, 1873 PCIBAR_MEM32); 1874 } 1875 break; 1876 case PCIBAR_MEM64: 1877 addr = bar = *eax & mask; 1878 bar |= PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_64 | 1879 PCIM_BAR_MEM_PREFETCH; 1880 if (addr != (uint32_t)pi->pi_bar[idx].addr) { 1881 update_bar_address(pi, addr, idx, 1882 PCIBAR_MEM64); 1883 } 1884 break; 1885 case PCIBAR_MEMHI64: 1886 mask = ~(pi->pi_bar[idx - 1].size - 1); 1887 addr = ((uint64_t)*eax << 32) & mask; 1888 bar = addr >> 32; 1889 if (bar != pi->pi_bar[idx - 1].addr >> 32) { 1890 update_bar_address(pi, addr, idx - 1, 1891 PCIBAR_MEMHI64); 1892 } 1893 break; 1894 default: 1895 assert(0); 1896 } 1897 pci_set_cfgdata32(pi, coff, bar); 1898 1899 } else if (pci_emul_iscap(pi, coff)) { 1900 pci_emul_capwrite(pi, coff, bytes, *eax); 1901 } else if (coff >= PCIR_COMMAND && coff < PCIR_REVID) { 1902 pci_emul_cmdsts_write(pi, coff, *eax, bytes); 1903 } else { 1904 CFGWRITE(pi, coff, *eax, bytes); 1905 } 1906 } 1907 } 1908 1909 static int cfgenable, cfgbus, cfgslot, cfgfunc, cfgoff; 1910 1911 static int 1912 pci_emul_cfgaddr(struct vmctx *ctx, int vcpu, int in, int port, int bytes, 1913 uint32_t *eax, void *arg) 1914 { 1915 uint32_t x; 1916 1917 if (bytes != 4) { 1918 if (in) 1919 *eax = (bytes == 2) ? 0xffff : 0xff; 1920 return (0); 1921 } 1922 1923 if (in) { 1924 x = (cfgbus << 16) | (cfgslot << 11) | (cfgfunc << 8) | cfgoff; 1925 if (cfgenable) 1926 x |= CONF1_ENABLE; 1927 *eax = x; 1928 } else { 1929 x = *eax; 1930 cfgenable = (x & CONF1_ENABLE) == CONF1_ENABLE; 1931 cfgoff = x & PCI_REGMAX; 1932 cfgfunc = (x >> 8) & PCI_FUNCMAX; 1933 cfgslot = (x >> 11) & PCI_SLOTMAX; 1934 cfgbus = (x >> 16) & PCI_BUSMAX; 1935 } 1936 1937 return (0); 1938 } 1939 INOUT_PORT(pci_cfgaddr, CONF1_ADDR_PORT, IOPORT_F_INOUT, pci_emul_cfgaddr); 1940 1941 static int 1942 pci_emul_cfgdata(struct vmctx *ctx, int vcpu, int in, int port, int bytes, 1943 uint32_t *eax, void *arg) 1944 { 1945 int coff; 1946 1947 assert(bytes == 1 || bytes == 2 || bytes == 4); 1948 1949 coff = cfgoff + (port - CONF1_DATA_PORT); 1950 if (cfgenable) { 1951 pci_cfgrw(ctx, vcpu, in, cfgbus, cfgslot, cfgfunc, coff, bytes, 1952 eax); 1953 } else { 1954 /* Ignore accesses to cfgdata if not enabled by cfgaddr */ 1955 if (in) 1956 *eax = 0xffffffff; 1957 } 1958 return (0); 1959 } 1960 1961 INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+0, IOPORT_F_INOUT, pci_emul_cfgdata); 1962 INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+1, IOPORT_F_INOUT, pci_emul_cfgdata); 1963 INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+2, IOPORT_F_INOUT, pci_emul_cfgdata); 1964 INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+3, IOPORT_F_INOUT, pci_emul_cfgdata); 1965 1966 #define PCI_EMUL_TEST 1967 #ifdef PCI_EMUL_TEST 1968 /* 1969 * Define a dummy test device 1970 */ 1971 #define DIOSZ 8 1972 #define DMEMSZ 4096 1973 struct pci_emul_dsoftc { 1974 uint8_t ioregs[DIOSZ]; 1975 uint8_t memregs[2][DMEMSZ]; 1976 }; 1977 1978 #define PCI_EMUL_MSI_MSGS 4 1979 #define PCI_EMUL_MSIX_MSGS 16 1980 1981 static int 1982 pci_emul_dinit(struct vmctx *ctx, struct pci_devinst *pi, char *opts) 1983 { 1984 int error; 1985 struct pci_emul_dsoftc *sc; 1986 1987 sc = calloc(1, sizeof(struct pci_emul_dsoftc)); 1988 1989 pi->pi_arg = sc; 1990 1991 pci_set_cfgdata16(pi, PCIR_DEVICE, 0x0001); 1992 pci_set_cfgdata16(pi, PCIR_VENDOR, 0x10DD); 1993 pci_set_cfgdata8(pi, PCIR_CLASS, 0x02); 1994 1995 error = pci_emul_add_msicap(pi, PCI_EMUL_MSI_MSGS); 1996 assert(error == 0); 1997 1998 error = pci_emul_alloc_bar(pi, 0, PCIBAR_IO, DIOSZ); 1999 assert(error == 0); 2000 2001 error = pci_emul_alloc_bar(pi, 1, PCIBAR_MEM32, DMEMSZ); 2002 assert(error == 0); 2003 2004 error = pci_emul_alloc_bar(pi, 2, PCIBAR_MEM32, DMEMSZ); 2005 assert(error == 0); 2006 2007 return (0); 2008 } 2009 2010 static void 2011 pci_emul_diow(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, int baridx, 2012 uint64_t offset, int size, uint64_t value) 2013 { 2014 int i; 2015 struct pci_emul_dsoftc *sc = pi->pi_arg; 2016 2017 if (baridx == 0) { 2018 if (offset + size > DIOSZ) { 2019 printf("diow: iow too large, offset %ld size %d\n", 2020 offset, size); 2021 return; 2022 } 2023 2024 if (size == 1) { 2025 sc->ioregs[offset] = value & 0xff; 2026 } else if (size == 2) { 2027 *(uint16_t *)&sc->ioregs[offset] = value & 0xffff; 2028 } else if (size == 4) { 2029 *(uint32_t *)&sc->ioregs[offset] = value; 2030 } else { 2031 printf("diow: iow unknown size %d\n", size); 2032 } 2033 2034 /* 2035 * Special magic value to generate an interrupt 2036 */ 2037 if (offset == 4 && size == 4 && pci_msi_enabled(pi)) 2038 pci_generate_msi(pi, value % pci_msi_maxmsgnum(pi)); 2039 2040 if (value == 0xabcdef) { 2041 for (i = 0; i < pci_msi_maxmsgnum(pi); i++) 2042 pci_generate_msi(pi, i); 2043 } 2044 } 2045 2046 if (baridx == 1 || baridx == 2) { 2047 if (offset + size > DMEMSZ) { 2048 printf("diow: memw too large, offset %ld size %d\n", 2049 offset, size); 2050 return; 2051 } 2052 2053 i = baridx - 1; /* 'memregs' index */ 2054 2055 if (size == 1) { 2056 sc->memregs[i][offset] = value; 2057 } else if (size == 2) { 2058 *(uint16_t *)&sc->memregs[i][offset] = value; 2059 } else if (size == 4) { 2060 *(uint32_t *)&sc->memregs[i][offset] = value; 2061 } else if (size == 8) { 2062 *(uint64_t *)&sc->memregs[i][offset] = value; 2063 } else { 2064 printf("diow: memw unknown size %d\n", size); 2065 } 2066 2067 /* 2068 * magic interrupt ?? 2069 */ 2070 } 2071 2072 if (baridx > 2 || baridx < 0) { 2073 printf("diow: unknown bar idx %d\n", baridx); 2074 } 2075 } 2076 2077 static uint64_t 2078 pci_emul_dior(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, int baridx, 2079 uint64_t offset, int size) 2080 { 2081 struct pci_emul_dsoftc *sc = pi->pi_arg; 2082 uint32_t value; 2083 int i; 2084 2085 if (baridx == 0) { 2086 if (offset + size > DIOSZ) { 2087 printf("dior: ior too large, offset %ld size %d\n", 2088 offset, size); 2089 return (0); 2090 } 2091 2092 value = 0; 2093 if (size == 1) { 2094 value = sc->ioregs[offset]; 2095 } else if (size == 2) { 2096 value = *(uint16_t *) &sc->ioregs[offset]; 2097 } else if (size == 4) { 2098 value = *(uint32_t *) &sc->ioregs[offset]; 2099 } else { 2100 printf("dior: ior unknown size %d\n", size); 2101 } 2102 } 2103 2104 if (baridx == 1 || baridx == 2) { 2105 if (offset + size > DMEMSZ) { 2106 printf("dior: memr too large, offset %ld size %d\n", 2107 offset, size); 2108 return (0); 2109 } 2110 2111 i = baridx - 1; /* 'memregs' index */ 2112 2113 if (size == 1) { 2114 value = sc->memregs[i][offset]; 2115 } else if (size == 2) { 2116 value = *(uint16_t *) &sc->memregs[i][offset]; 2117 } else if (size == 4) { 2118 value = *(uint32_t *) &sc->memregs[i][offset]; 2119 } else if (size == 8) { 2120 value = *(uint64_t *) &sc->memregs[i][offset]; 2121 } else { 2122 printf("dior: ior unknown size %d\n", size); 2123 } 2124 } 2125 2126 2127 if (baridx > 2 || baridx < 0) { 2128 printf("dior: unknown bar idx %d\n", baridx); 2129 return (0); 2130 } 2131 2132 return (value); 2133 } 2134 2135 struct pci_devemu pci_dummy = { 2136 .pe_emu = "dummy", 2137 .pe_init = pci_emul_dinit, 2138 .pe_barwrite = pci_emul_diow, 2139 .pe_barread = pci_emul_dior 2140 }; 2141 PCI_EMUL_SET(pci_dummy); 2142 2143 #endif /* PCI_EMUL_TEST */ 2144