1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2011 NetApp, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 #include <sys/param.h> 31 #include <sys/linker_set.h> 32 #include <sys/mman.h> 33 34 #include <ctype.h> 35 #include <err.h> 36 #include <errno.h> 37 #include <pthread.h> 38 #include <stdio.h> 39 #include <stdlib.h> 40 #include <string.h> 41 #include <strings.h> 42 #include <assert.h> 43 #include <stdbool.h> 44 #include <sysexits.h> 45 46 #include <machine/vmm.h> 47 #include <machine/vmm_snapshot.h> 48 #include <vmmapi.h> 49 50 #include "acpi.h" 51 #include "bhyverun.h" 52 #include "config.h" 53 #include "debug.h" 54 #ifdef __amd64__ 55 #include "amd64/inout.h" 56 #include "amd64/ioapic.h" 57 #endif 58 #include "mem.h" 59 #include "pci_emul.h" 60 #ifdef __amd64__ 61 #include "amd64/pci_irq.h" 62 #include "amd64/pci_lpc.h" 63 #endif 64 #include "pci_passthru.h" 65 #include "qemu_fwcfg.h" 66 67 #define CONF1_ADDR_PORT 0x0cf8 68 #define CONF1_DATA_PORT 0x0cfc 69 70 #define CONF1_ENABLE 0x80000000ul 71 72 #define MAXBUSES (PCI_BUSMAX + 1) 73 #define MAXSLOTS (PCI_SLOTMAX + 1) 74 #define MAXFUNCS (PCI_FUNCMAX + 1) 75 76 #define GB (1024 * 1024 * 1024UL) 77 78 struct funcinfo { 79 nvlist_t *fi_config; 80 struct pci_devemu *fi_pde; 81 struct pci_devinst *fi_devi; 82 }; 83 84 struct intxinfo { 85 int ii_count; 86 int ii_pirq_pin; 87 int ii_ioapic_irq; 88 }; 89 90 struct slotinfo { 91 struct intxinfo si_intpins[4]; 92 struct funcinfo si_funcs[MAXFUNCS]; 93 }; 94 95 struct businfo { 96 uint16_t iobase, iolimit; /* I/O window */ 97 uint32_t membase32, memlimit32; /* mmio window below 4GB */ 98 uint64_t membase64, memlimit64; /* mmio window above 4GB */ 99 struct slotinfo slotinfo[MAXSLOTS]; 100 }; 101 102 static struct businfo *pci_businfo[MAXBUSES]; 103 104 SET_DECLARE(pci_devemu_set, struct pci_devemu); 105 106 static uint64_t pci_emul_iobase; 107 static uint8_t *pci_emul_rombase; 108 static uint64_t pci_emul_romoffset; 109 static uint8_t *pci_emul_romlim; 110 static uint64_t pci_emul_membase32; 111 static uint64_t pci_emul_membase64; 112 static uint64_t pci_emul_memlim64; 113 114 struct pci_bar_allocation { 115 TAILQ_ENTRY(pci_bar_allocation) chain; 116 struct pci_devinst *pdi; 117 int idx; 118 enum pcibar_type type; 119 uint64_t size; 120 }; 121 122 static TAILQ_HEAD(pci_bar_list, pci_bar_allocation) pci_bars = 123 TAILQ_HEAD_INITIALIZER(pci_bars); 124 125 struct boot_device { 126 TAILQ_ENTRY(boot_device) boot_device_chain; 127 struct pci_devinst *pdi; 128 int bootindex; 129 }; 130 static TAILQ_HEAD(boot_list, boot_device) boot_devices = TAILQ_HEAD_INITIALIZER( 131 boot_devices); 132 133 #define PCI_EMUL_IOBASE 0x2000 134 #define PCI_EMUL_IOLIMIT 0x10000 135 136 #define PCI_EMUL_ROMSIZE 0x10000000 137 138 #define PCI_EMUL_ECFG_BASE 0xE0000000 /* 3.5GB */ 139 #define PCI_EMUL_ECFG_SIZE (MAXBUSES * 1024 * 1024) /* 1MB per bus */ 140 SYSRES_MEM(PCI_EMUL_ECFG_BASE, PCI_EMUL_ECFG_SIZE); 141 142 /* 143 * OVMF always uses 0xC0000000 as base address for 32 bit PCI MMIO. Don't 144 * change this address without changing it in OVMF. 145 */ 146 #define PCI_EMUL_MEMBASE32 0xC0000000 147 #define PCI_EMUL_MEMLIMIT32 PCI_EMUL_ECFG_BASE 148 #define PCI_EMUL_MEMSIZE64 (32*GB) 149 150 #ifdef __amd64__ 151 static void pci_lintr_route(struct pci_devinst *pi); 152 static void pci_lintr_update(struct pci_devinst *pi); 153 #endif 154 155 static struct pci_devemu *pci_emul_finddev(const char *name); 156 static void pci_cfgrw(int in, int bus, int slot, int func, int coff, 157 int bytes, uint32_t *val); 158 159 static __inline void 160 CFGWRITE(struct pci_devinst *pi, int coff, uint32_t val, int bytes) 161 { 162 163 if (bytes == 1) 164 pci_set_cfgdata8(pi, coff, val); 165 else if (bytes == 2) 166 pci_set_cfgdata16(pi, coff, val); 167 else 168 pci_set_cfgdata32(pi, coff, val); 169 } 170 171 static __inline uint32_t 172 CFGREAD(struct pci_devinst *pi, int coff, int bytes) 173 { 174 175 if (bytes == 1) 176 return (pci_get_cfgdata8(pi, coff)); 177 else if (bytes == 2) 178 return (pci_get_cfgdata16(pi, coff)); 179 else 180 return (pci_get_cfgdata32(pi, coff)); 181 } 182 183 static int 184 is_pcir_bar(int coff) 185 { 186 return (coff >= PCIR_BAR(0) && coff < PCIR_BAR(PCI_BARMAX + 1)); 187 } 188 189 static int 190 is_pcir_bios(int coff) 191 { 192 return (coff >= PCIR_BIOS && coff < PCIR_BIOS + 4); 193 } 194 195 /* 196 * I/O access 197 */ 198 199 /* 200 * Slot options are in the form: 201 * 202 * <bus>:<slot>:<func>,<emul>[,<config>] 203 * <slot>[:<func>],<emul>[,<config>] 204 * 205 * slot is 0..31 206 * func is 0..7 207 * emul is a string describing the type of PCI device e.g. virtio-net 208 * config is an optional string, depending on the device, that can be 209 * used for configuration. 210 * Examples are: 211 * 1,virtio-net,tap0 212 * 3:0,dummy 213 */ 214 static void 215 pci_parse_slot_usage(char *aopt) 216 { 217 218 EPRINTLN("Invalid PCI slot info field \"%s\"", aopt); 219 } 220 221 /* 222 * Helper function to parse a list of comma-separated options where 223 * each option is formatted as "name[=value]". If no value is 224 * provided, the option is treated as a boolean and is given a value 225 * of true. 226 */ 227 int 228 pci_parse_legacy_config(nvlist_t *nvl, const char *opt) 229 { 230 char *config, *name, *tofree, *value; 231 232 if (opt == NULL) 233 return (0); 234 235 config = tofree = strdup(opt); 236 while ((name = strsep(&config, ",")) != NULL) { 237 value = strchr(name, '='); 238 if (value != NULL) { 239 *value = '\0'; 240 value++; 241 set_config_value_node(nvl, name, value); 242 } else 243 set_config_bool_node(nvl, name, true); 244 } 245 free(tofree); 246 return (0); 247 } 248 249 /* 250 * PCI device configuration is stored in MIBs that encode the device's 251 * location: 252 * 253 * pci.<bus>.<slot>.<func> 254 * 255 * Where "bus", "slot", and "func" are all decimal values without 256 * leading zeroes. Each valid device must have a "device" node which 257 * identifies the driver model of the device. 258 * 259 * Device backends can provide a parser for the "config" string. If 260 * a custom parser is not provided, pci_parse_legacy_config() is used 261 * to parse the string. 262 */ 263 int 264 pci_parse_slot(char *opt) 265 { 266 char node_name[sizeof("pci.XXX.XX.X")]; 267 struct pci_devemu *pde; 268 char *emul, *config, *str, *cp; 269 int error, bnum, snum, fnum; 270 nvlist_t *nvl; 271 272 error = -1; 273 str = strdup(opt); 274 275 emul = config = NULL; 276 if ((cp = strchr(str, ',')) != NULL) { 277 *cp = '\0'; 278 emul = cp + 1; 279 if ((cp = strchr(emul, ',')) != NULL) { 280 *cp = '\0'; 281 config = cp + 1; 282 } 283 } else { 284 pci_parse_slot_usage(opt); 285 goto done; 286 } 287 288 /* <bus>:<slot>:<func> */ 289 if (sscanf(str, "%d:%d:%d", &bnum, &snum, &fnum) != 3) { 290 bnum = 0; 291 /* <slot>:<func> */ 292 if (sscanf(str, "%d:%d", &snum, &fnum) != 2) { 293 fnum = 0; 294 /* <slot> */ 295 if (sscanf(str, "%d", &snum) != 1) { 296 snum = -1; 297 } 298 } 299 } 300 301 if (bnum < 0 || bnum >= MAXBUSES || snum < 0 || snum >= MAXSLOTS || 302 fnum < 0 || fnum >= MAXFUNCS) { 303 pci_parse_slot_usage(opt); 304 goto done; 305 } 306 307 pde = pci_emul_finddev(emul); 308 if (pde == NULL) { 309 EPRINTLN("pci slot %d:%d:%d: unknown device \"%s\"", bnum, snum, 310 fnum, emul); 311 goto done; 312 } 313 314 snprintf(node_name, sizeof(node_name), "pci.%d.%d.%d", bnum, snum, 315 fnum); 316 nvl = find_config_node(node_name); 317 if (nvl != NULL) { 318 EPRINTLN("pci slot %d:%d:%d already occupied!", bnum, snum, 319 fnum); 320 goto done; 321 } 322 nvl = create_config_node(node_name); 323 if (pde->pe_alias != NULL) 324 set_config_value_node(nvl, "device", pde->pe_alias); 325 else 326 set_config_value_node(nvl, "device", pde->pe_emu); 327 328 if (pde->pe_legacy_config != NULL) 329 error = pde->pe_legacy_config(nvl, config); 330 else 331 error = pci_parse_legacy_config(nvl, config); 332 done: 333 free(str); 334 return (error); 335 } 336 337 void 338 pci_print_supported_devices(void) 339 { 340 struct pci_devemu **pdpp, *pdp; 341 342 SET_FOREACH(pdpp, pci_devemu_set) { 343 pdp = *pdpp; 344 printf("%s\n", pdp->pe_emu); 345 } 346 } 347 348 uint32_t 349 pci_config_read_reg(const struct pcisel *const host_sel, nvlist_t *nvl, 350 const uint32_t reg, const uint8_t size, const uint32_t def) 351 { 352 const char *config; 353 const nvlist_t *pci_regs; 354 355 assert(size == 1 || size == 2 || size == 4); 356 357 pci_regs = find_relative_config_node(nvl, "pcireg"); 358 if (pci_regs == NULL) { 359 return def; 360 } 361 362 switch (reg) { 363 case PCIR_DEVICE: 364 config = get_config_value_node(pci_regs, "device"); 365 break; 366 case PCIR_VENDOR: 367 config = get_config_value_node(pci_regs, "vendor"); 368 break; 369 case PCIR_REVID: 370 config = get_config_value_node(pci_regs, "revid"); 371 break; 372 case PCIR_SUBVEND_0: 373 config = get_config_value_node(pci_regs, "subvendor"); 374 break; 375 case PCIR_SUBDEV_0: 376 config = get_config_value_node(pci_regs, "subdevice"); 377 break; 378 default: 379 return (-1); 380 } 381 382 if (config == NULL) { 383 return def; 384 } else if (host_sel != NULL && strcmp(config, "host") == 0) { 385 return pci_host_read_config(host_sel, reg, size); 386 } else { 387 return strtol(config, NULL, 16); 388 } 389 } 390 391 static int 392 pci_valid_pba_offset(struct pci_devinst *pi, uint64_t offset) 393 { 394 395 if (offset < pi->pi_msix.pba_offset) 396 return (0); 397 398 if (offset >= pi->pi_msix.pba_offset + pi->pi_msix.pba_size) { 399 return (0); 400 } 401 402 return (1); 403 } 404 405 int 406 pci_emul_msix_twrite(struct pci_devinst *pi, uint64_t offset, int size, 407 uint64_t value) 408 { 409 int msix_entry_offset; 410 int tab_index; 411 char *dest; 412 413 /* support only 4 or 8 byte writes */ 414 if (size != 4 && size != 8) 415 return (-1); 416 417 /* 418 * Return if table index is beyond what device supports 419 */ 420 tab_index = offset / MSIX_TABLE_ENTRY_SIZE; 421 if (tab_index >= pi->pi_msix.table_count) 422 return (-1); 423 424 msix_entry_offset = offset % MSIX_TABLE_ENTRY_SIZE; 425 426 /* support only aligned writes */ 427 if ((msix_entry_offset % size) != 0) 428 return (-1); 429 430 dest = (char *)(pi->pi_msix.table + tab_index); 431 dest += msix_entry_offset; 432 433 if (size == 4) 434 *((uint32_t *)dest) = value; 435 else 436 *((uint64_t *)dest) = value; 437 438 return (0); 439 } 440 441 uint64_t 442 pci_emul_msix_tread(struct pci_devinst *pi, uint64_t offset, int size) 443 { 444 char *dest; 445 int msix_entry_offset; 446 int tab_index; 447 uint64_t retval = ~0; 448 449 /* 450 * The PCI standard only allows 4 and 8 byte accesses to the MSI-X 451 * table but we also allow 1 byte access to accommodate reads from 452 * ddb. 453 */ 454 if (size != 1 && size != 4 && size != 8) 455 return (retval); 456 457 msix_entry_offset = offset % MSIX_TABLE_ENTRY_SIZE; 458 459 /* support only aligned reads */ 460 if ((msix_entry_offset % size) != 0) { 461 return (retval); 462 } 463 464 tab_index = offset / MSIX_TABLE_ENTRY_SIZE; 465 466 if (tab_index < pi->pi_msix.table_count) { 467 /* valid MSI-X Table access */ 468 dest = (char *)(pi->pi_msix.table + tab_index); 469 dest += msix_entry_offset; 470 471 if (size == 1) 472 retval = *((uint8_t *)dest); 473 else if (size == 4) 474 retval = *((uint32_t *)dest); 475 else 476 retval = *((uint64_t *)dest); 477 } else if (pci_valid_pba_offset(pi, offset)) { 478 /* return 0 for PBA access */ 479 retval = 0; 480 } 481 482 return (retval); 483 } 484 485 int 486 pci_msix_table_bar(struct pci_devinst *pi) 487 { 488 489 if (pi->pi_msix.table != NULL) 490 return (pi->pi_msix.table_bar); 491 else 492 return (-1); 493 } 494 495 int 496 pci_msix_pba_bar(struct pci_devinst *pi) 497 { 498 499 if (pi->pi_msix.table != NULL) 500 return (pi->pi_msix.pba_bar); 501 else 502 return (-1); 503 } 504 505 #ifdef __amd64__ 506 static int 507 pci_emul_io_handler(struct vmctx *ctx __unused, int in, int port, 508 int bytes, uint32_t *eax, void *arg) 509 { 510 struct pci_devinst *pdi = arg; 511 struct pci_devemu *pe = pdi->pi_d; 512 uint64_t offset; 513 int i; 514 515 assert(port >= 0); 516 517 for (i = 0; i <= PCI_BARMAX; i++) { 518 if (pdi->pi_bar[i].type == PCIBAR_IO && 519 (uint64_t)port >= pdi->pi_bar[i].addr && 520 (uint64_t)port + bytes <= 521 pdi->pi_bar[i].addr + pdi->pi_bar[i].size) { 522 offset = port - pdi->pi_bar[i].addr; 523 if (in) 524 *eax = (*pe->pe_barread)(pdi, i, 525 offset, bytes); 526 else 527 (*pe->pe_barwrite)(pdi, i, offset, 528 bytes, *eax); 529 return (0); 530 } 531 } 532 return (-1); 533 } 534 #else 535 static int 536 pci_emul_iomem_handler(struct vcpu *vcpu __unused, int dir, 537 uint64_t addr, int size, uint64_t *val, void *arg1, long arg2) 538 { 539 struct pci_devinst *pdi = arg1; 540 struct pci_devemu *pe = pdi->pi_d; 541 uint64_t offset; 542 int bidx = (int)arg2; 543 544 assert(bidx <= PCI_BARMAX); 545 assert(pdi->pi_bar[bidx].type == PCIBAR_IO); 546 assert(addr >= pdi->pi_bar[bidx].addr && 547 addr + size <= pdi->pi_bar[bidx].addr + pdi->pi_bar[bidx].size); 548 assert(size == 1 || size == 2 || size == 4); 549 550 offset = addr - pdi->pi_bar[bidx].addr; 551 if (dir == MEM_F_READ) 552 *val = (*pe->pe_barread)(pdi, bidx, offset, size); 553 else 554 (*pe->pe_barwrite)(pdi, bidx, offset, size, *val); 555 556 return (0); 557 } 558 #endif /* !__amd64__ */ 559 560 static int 561 pci_emul_mem_handler(struct vcpu *vcpu __unused, int dir, 562 uint64_t addr, int size, uint64_t *val, void *arg1, long arg2) 563 { 564 struct pci_devinst *pdi = arg1; 565 struct pci_devemu *pe = pdi->pi_d; 566 uint64_t offset; 567 int bidx = (int)arg2; 568 569 assert(bidx <= PCI_BARMAX); 570 assert(pdi->pi_bar[bidx].type == PCIBAR_MEM32 || 571 pdi->pi_bar[bidx].type == PCIBAR_MEM64); 572 assert(addr >= pdi->pi_bar[bidx].addr && 573 addr + size <= pdi->pi_bar[bidx].addr + pdi->pi_bar[bidx].size); 574 575 offset = addr - pdi->pi_bar[bidx].addr; 576 577 if (dir == MEM_F_WRITE) { 578 if (size == 8) { 579 (*pe->pe_barwrite)(pdi, bidx, offset, 580 4, *val & 0xffffffff); 581 (*pe->pe_barwrite)(pdi, bidx, offset + 4, 582 4, *val >> 32); 583 } else { 584 (*pe->pe_barwrite)(pdi, bidx, offset, 585 size, *val); 586 } 587 } else { 588 if (size == 8) { 589 *val = (*pe->pe_barread)(pdi, bidx, 590 offset, 4); 591 *val |= (*pe->pe_barread)(pdi, bidx, 592 offset + 4, 4) << 32; 593 } else { 594 *val = (*pe->pe_barread)(pdi, bidx, 595 offset, size); 596 } 597 } 598 599 return (0); 600 } 601 602 603 static int 604 pci_emul_alloc_resource(uint64_t *baseptr, uint64_t limit, uint64_t size, 605 uint64_t *addr) 606 { 607 uint64_t base; 608 609 assert((size & (size - 1)) == 0); /* must be a power of 2 */ 610 611 base = roundup2(*baseptr, size); 612 613 if (base + size <= limit) { 614 *addr = base; 615 *baseptr = base + size; 616 return (0); 617 } else 618 return (-1); 619 } 620 621 /* 622 * Register (or unregister) the MMIO or I/O region associated with the BAR 623 * register 'idx' of an emulated pci device. 624 */ 625 static void 626 modify_bar_registration(struct pci_devinst *pi, int idx, int registration) 627 { 628 struct pci_devemu *pe; 629 int error; 630 enum pcibar_type type; 631 632 pe = pi->pi_d; 633 type = pi->pi_bar[idx].type; 634 switch (type) { 635 case PCIBAR_IO: 636 { 637 #ifdef __amd64__ 638 struct inout_port iop; 639 640 bzero(&iop, sizeof(struct inout_port)); 641 iop.name = pi->pi_name; 642 iop.port = pi->pi_bar[idx].addr; 643 iop.size = pi->pi_bar[idx].size; 644 if (registration) { 645 iop.flags = IOPORT_F_INOUT; 646 iop.handler = pci_emul_io_handler; 647 iop.arg = pi; 648 error = register_inout(&iop); 649 } else 650 error = unregister_inout(&iop); 651 #else 652 struct mem_range mr; 653 654 bzero(&mr, sizeof(struct mem_range)); 655 mr.name = pi->pi_name; 656 mr.base = pi->pi_bar[idx].addr; 657 mr.size = pi->pi_bar[idx].size; 658 if (registration) { 659 mr.flags = MEM_F_RW; 660 mr.handler = pci_emul_iomem_handler; 661 mr.arg1 = pi; 662 mr.arg2 = idx; 663 error = register_mem(&mr); 664 } else 665 error = unregister_mem(&mr); 666 #endif 667 break; 668 } 669 case PCIBAR_MEM32: 670 case PCIBAR_MEM64: 671 { 672 struct mem_range mr; 673 674 bzero(&mr, sizeof(struct mem_range)); 675 mr.name = pi->pi_name; 676 mr.base = pi->pi_bar[idx].addr; 677 mr.size = pi->pi_bar[idx].size; 678 if (registration) { 679 mr.flags = MEM_F_RW; 680 mr.handler = pci_emul_mem_handler; 681 mr.arg1 = pi; 682 mr.arg2 = idx; 683 error = register_mem(&mr); 684 } else 685 error = unregister_mem(&mr); 686 break; 687 } 688 case PCIBAR_ROM: 689 error = 0; 690 break; 691 default: 692 error = EINVAL; 693 break; 694 } 695 assert(error == 0); 696 697 if (pe->pe_baraddr != NULL) 698 (*pe->pe_baraddr)(pi, idx, registration, pi->pi_bar[idx].addr); 699 } 700 701 static void 702 unregister_bar(struct pci_devinst *pi, int idx) 703 { 704 705 modify_bar_registration(pi, idx, 0); 706 } 707 708 static void 709 register_bar(struct pci_devinst *pi, int idx) 710 { 711 712 modify_bar_registration(pi, idx, 1); 713 } 714 715 /* Is the ROM enabled for the emulated pci device? */ 716 static int 717 romen(struct pci_devinst *pi) 718 { 719 return (pi->pi_bar[PCI_ROM_IDX].lobits & PCIM_BIOS_ENABLE) == 720 PCIM_BIOS_ENABLE; 721 } 722 723 /* Are we decoding i/o port accesses for the emulated pci device? */ 724 static int 725 porten(struct pci_devinst *pi) 726 { 727 uint16_t cmd; 728 729 cmd = pci_get_cfgdata16(pi, PCIR_COMMAND); 730 731 return (cmd & PCIM_CMD_PORTEN); 732 } 733 734 /* Are we decoding memory accesses for the emulated pci device? */ 735 static int 736 memen(struct pci_devinst *pi) 737 { 738 uint16_t cmd; 739 740 cmd = pci_get_cfgdata16(pi, PCIR_COMMAND); 741 742 return (cmd & PCIM_CMD_MEMEN); 743 } 744 745 /* 746 * Update the MMIO or I/O address that is decoded by the BAR register. 747 * 748 * If the pci device has enabled the address space decoding then intercept 749 * the address range decoded by the BAR register. 750 */ 751 static void 752 update_bar_address(struct pci_devinst *pi, uint64_t addr, int idx, int type) 753 { 754 int decode; 755 756 if (pi->pi_bar[idx].type == PCIBAR_IO) 757 decode = porten(pi); 758 else 759 decode = memen(pi); 760 761 if (decode) 762 unregister_bar(pi, idx); 763 764 switch (type) { 765 case PCIBAR_IO: 766 case PCIBAR_MEM32: 767 pi->pi_bar[idx].addr = addr; 768 break; 769 case PCIBAR_MEM64: 770 pi->pi_bar[idx].addr &= ~0xffffffffUL; 771 pi->pi_bar[idx].addr |= addr; 772 break; 773 case PCIBAR_MEMHI64: 774 pi->pi_bar[idx].addr &= 0xffffffff; 775 pi->pi_bar[idx].addr |= addr; 776 break; 777 default: 778 assert(0); 779 } 780 781 if (decode) 782 register_bar(pi, idx); 783 } 784 785 int 786 pci_emul_alloc_bar(struct pci_devinst *pdi, int idx, enum pcibar_type type, 787 uint64_t size) 788 { 789 assert((type == PCIBAR_ROM) || (idx >= 0 && idx <= PCI_BARMAX)); 790 assert((type != PCIBAR_ROM) || (idx == PCI_ROM_IDX)); 791 792 if ((size & (size - 1)) != 0) 793 size = 1UL << flsl(size); /* round up to a power of 2 */ 794 795 /* Enforce minimum BAR sizes required by the PCI standard */ 796 if (type == PCIBAR_IO) { 797 if (size < 4) 798 size = 4; 799 } else if (type == PCIBAR_ROM) { 800 if (size < ~PCIM_BIOS_ADDR_MASK + 1) 801 size = ~PCIM_BIOS_ADDR_MASK + 1; 802 } else { 803 if (size < 16) 804 size = 16; 805 } 806 807 /* 808 * To reduce fragmentation of the MMIO space, we allocate the BARs by 809 * size. Therefore, don't allocate the BAR yet. We create a list of all 810 * BAR allocation which is sorted by BAR size. When all PCI devices are 811 * initialized, we will assign an address to the BARs. 812 */ 813 814 /* create a new list entry */ 815 struct pci_bar_allocation *const new_bar = malloc(sizeof(*new_bar)); 816 memset(new_bar, 0, sizeof(*new_bar)); 817 new_bar->pdi = pdi; 818 new_bar->idx = idx; 819 new_bar->type = type; 820 new_bar->size = size; 821 822 /* 823 * Search for a BAR which size is lower than the size of our newly 824 * allocated BAR. 825 */ 826 struct pci_bar_allocation *bar = NULL; 827 TAILQ_FOREACH(bar, &pci_bars, chain) { 828 if (bar->size < size) { 829 break; 830 } 831 } 832 833 if (bar == NULL) { 834 /* 835 * Either the list is empty or new BAR is the smallest BAR of 836 * the list. Append it to the end of our list. 837 */ 838 TAILQ_INSERT_TAIL(&pci_bars, new_bar, chain); 839 } else { 840 /* 841 * The found BAR is smaller than our new BAR. For that reason, 842 * insert our new BAR before the found BAR. 843 */ 844 TAILQ_INSERT_BEFORE(bar, new_bar, chain); 845 } 846 847 /* 848 * pci_passthru devices synchronize their physical and virtual command 849 * register on init. For that reason, the virtual cmd reg should be 850 * updated as early as possible. 851 */ 852 uint16_t enbit = 0; 853 switch (type) { 854 case PCIBAR_IO: 855 enbit = PCIM_CMD_PORTEN; 856 break; 857 case PCIBAR_MEM64: 858 case PCIBAR_MEM32: 859 enbit = PCIM_CMD_MEMEN; 860 break; 861 default: 862 enbit = 0; 863 break; 864 } 865 866 const uint16_t cmd = pci_get_cfgdata16(pdi, PCIR_COMMAND); 867 pci_set_cfgdata16(pdi, PCIR_COMMAND, cmd | enbit); 868 869 return (0); 870 } 871 872 static int 873 pci_emul_assign_bar(struct pci_devinst *const pdi, const int idx, 874 const enum pcibar_type type, const uint64_t size) 875 { 876 int error; 877 uint64_t *baseptr, limit, addr, mask, lobits, bar; 878 879 switch (type) { 880 case PCIBAR_NONE: 881 baseptr = NULL; 882 addr = mask = lobits = 0; 883 break; 884 case PCIBAR_IO: 885 baseptr = &pci_emul_iobase; 886 limit = PCI_EMUL_IOLIMIT; 887 mask = PCIM_BAR_IO_BASE; 888 lobits = PCIM_BAR_IO_SPACE; 889 break; 890 case PCIBAR_MEM64: 891 /* 892 * XXX 893 * Some drivers do not work well if the 64-bit BAR is allocated 894 * above 4GB. Allow for this by allocating small requests under 895 * 4GB unless then allocation size is larger than some arbitrary 896 * number (128MB currently). 897 */ 898 if (size > 128 * 1024 * 1024) { 899 baseptr = &pci_emul_membase64; 900 limit = pci_emul_memlim64; 901 mask = PCIM_BAR_MEM_BASE; 902 lobits = PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_64 | 903 PCIM_BAR_MEM_PREFETCH; 904 } else { 905 baseptr = &pci_emul_membase32; 906 limit = PCI_EMUL_MEMLIMIT32; 907 mask = PCIM_BAR_MEM_BASE; 908 lobits = PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_64; 909 } 910 break; 911 case PCIBAR_MEM32: 912 baseptr = &pci_emul_membase32; 913 limit = PCI_EMUL_MEMLIMIT32; 914 mask = PCIM_BAR_MEM_BASE; 915 lobits = PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_32; 916 break; 917 case PCIBAR_ROM: 918 /* do not claim memory for ROM. OVMF will do it for us. */ 919 baseptr = NULL; 920 limit = 0; 921 mask = PCIM_BIOS_ADDR_MASK; 922 lobits = 0; 923 break; 924 default: 925 printf("pci_emul_alloc_base: invalid bar type %d\n", type); 926 assert(0); 927 } 928 929 if (baseptr != NULL) { 930 error = pci_emul_alloc_resource(baseptr, limit, size, &addr); 931 if (error != 0) 932 return (error); 933 } else { 934 addr = 0; 935 } 936 937 pdi->pi_bar[idx].type = type; 938 pdi->pi_bar[idx].addr = addr; 939 pdi->pi_bar[idx].size = size; 940 /* 941 * passthru devices are using same lobits as physical device they set 942 * this property 943 */ 944 if (pdi->pi_bar[idx].lobits != 0) { 945 lobits = pdi->pi_bar[idx].lobits; 946 } else { 947 pdi->pi_bar[idx].lobits = lobits; 948 } 949 950 /* Initialize the BAR register in config space */ 951 bar = (addr & mask) | lobits; 952 pci_set_cfgdata32(pdi, PCIR_BAR(idx), bar); 953 954 if (type == PCIBAR_MEM64) { 955 assert(idx + 1 <= PCI_BARMAX); 956 pdi->pi_bar[idx + 1].type = PCIBAR_MEMHI64; 957 pci_set_cfgdata32(pdi, PCIR_BAR(idx + 1), bar >> 32); 958 } 959 960 if (type != PCIBAR_ROM) { 961 register_bar(pdi, idx); 962 } 963 964 return (0); 965 } 966 967 int 968 pci_emul_alloc_rom(struct pci_devinst *const pdi, const uint64_t size, 969 void **const addr) 970 { 971 /* allocate ROM space once on first call */ 972 if (pci_emul_rombase == 0) { 973 pci_emul_rombase = vm_create_devmem(pdi->pi_vmctx, VM_PCIROM, 974 "pcirom", PCI_EMUL_ROMSIZE); 975 if (pci_emul_rombase == MAP_FAILED) { 976 warnx("%s: failed to create rom segment", __func__); 977 return (-1); 978 } 979 pci_emul_romlim = pci_emul_rombase + PCI_EMUL_ROMSIZE; 980 pci_emul_romoffset = 0; 981 } 982 983 /* ROM size should be a power of 2 and greater than 2 KB */ 984 const uint64_t rom_size = MAX(1UL << flsl(size), 985 ~PCIM_BIOS_ADDR_MASK + 1); 986 987 /* check if ROM fits into ROM space */ 988 if (pci_emul_romoffset + rom_size > PCI_EMUL_ROMSIZE) { 989 warnx("%s: no space left in rom segment:", __func__); 990 warnx("%16lu bytes left", 991 PCI_EMUL_ROMSIZE - pci_emul_romoffset); 992 warnx("%16lu bytes required by %d/%d/%d", rom_size, pdi->pi_bus, 993 pdi->pi_slot, pdi->pi_func); 994 return (-1); 995 } 996 997 /* allocate ROM BAR */ 998 const int error = pci_emul_alloc_bar(pdi, PCI_ROM_IDX, PCIBAR_ROM, 999 rom_size); 1000 if (error) 1001 return error; 1002 1003 /* return address */ 1004 *addr = pci_emul_rombase + pci_emul_romoffset; 1005 1006 /* save offset into ROM Space */ 1007 pdi->pi_romoffset = pci_emul_romoffset; 1008 1009 /* increase offset for next ROM */ 1010 pci_emul_romoffset += rom_size; 1011 1012 return (0); 1013 } 1014 1015 int 1016 pci_emul_add_boot_device(struct pci_devinst *pi, int bootindex) 1017 { 1018 struct boot_device *new_device, *device; 1019 1020 /* don't permit a negative bootindex */ 1021 if (bootindex < 0) { 1022 errx(4, "Invalid bootindex %d for %s", bootindex, pi->pi_name); 1023 } 1024 1025 /* alloc new boot device */ 1026 new_device = calloc(1, sizeof(struct boot_device)); 1027 if (new_device == NULL) { 1028 return (ENOMEM); 1029 } 1030 new_device->pdi = pi; 1031 new_device->bootindex = bootindex; 1032 1033 /* search for boot device with higher boot index */ 1034 TAILQ_FOREACH(device, &boot_devices, boot_device_chain) { 1035 if (device->bootindex == bootindex) { 1036 errx(4, 1037 "Could not set bootindex %d for %s. Bootindex already occupied by %s", 1038 bootindex, pi->pi_name, device->pdi->pi_name); 1039 } else if (device->bootindex > bootindex) { 1040 break; 1041 } 1042 } 1043 1044 /* add boot device to queue */ 1045 if (device == NULL) { 1046 TAILQ_INSERT_TAIL(&boot_devices, new_device, boot_device_chain); 1047 } else { 1048 TAILQ_INSERT_BEFORE(device, new_device, boot_device_chain); 1049 } 1050 1051 return (0); 1052 } 1053 1054 #define CAP_START_OFFSET 0x40 1055 static int 1056 pci_emul_add_capability(struct pci_devinst *pi, u_char *capdata, int caplen) 1057 { 1058 int i, capoff, reallen; 1059 uint16_t sts; 1060 1061 assert(caplen > 0); 1062 1063 reallen = roundup2(caplen, 4); /* dword aligned */ 1064 1065 sts = pci_get_cfgdata16(pi, PCIR_STATUS); 1066 if ((sts & PCIM_STATUS_CAPPRESENT) == 0) 1067 capoff = CAP_START_OFFSET; 1068 else 1069 capoff = pi->pi_capend + 1; 1070 1071 /* Check if we have enough space */ 1072 if (capoff + reallen > PCI_REGMAX + 1) 1073 return (-1); 1074 1075 /* Set the previous capability pointer */ 1076 if ((sts & PCIM_STATUS_CAPPRESENT) == 0) { 1077 pci_set_cfgdata8(pi, PCIR_CAP_PTR, capoff); 1078 pci_set_cfgdata16(pi, PCIR_STATUS, sts|PCIM_STATUS_CAPPRESENT); 1079 } else 1080 pci_set_cfgdata8(pi, pi->pi_prevcap + 1, capoff); 1081 1082 /* Copy the capability */ 1083 for (i = 0; i < caplen; i++) 1084 pci_set_cfgdata8(pi, capoff + i, capdata[i]); 1085 1086 /* Set the next capability pointer */ 1087 pci_set_cfgdata8(pi, capoff + 1, 0); 1088 1089 pi->pi_prevcap = capoff; 1090 pi->pi_capend = capoff + reallen - 1; 1091 return (0); 1092 } 1093 1094 static struct pci_devemu * 1095 pci_emul_finddev(const char *name) 1096 { 1097 struct pci_devemu **pdpp, *pdp; 1098 1099 SET_FOREACH(pdpp, pci_devemu_set) { 1100 pdp = *pdpp; 1101 if (!strcmp(pdp->pe_emu, name)) { 1102 return (pdp); 1103 } 1104 } 1105 1106 return (NULL); 1107 } 1108 1109 static int 1110 pci_emul_init(struct vmctx *ctx, struct pci_devemu *pde, int bus, int slot, 1111 int func, struct funcinfo *fi) 1112 { 1113 struct pci_devinst *pdi; 1114 int err; 1115 1116 pdi = calloc(1, sizeof(struct pci_devinst)); 1117 1118 pdi->pi_vmctx = ctx; 1119 pdi->pi_bus = bus; 1120 pdi->pi_slot = slot; 1121 pdi->pi_func = func; 1122 #ifdef __amd64__ 1123 pthread_mutex_init(&pdi->pi_lintr.lock, NULL); 1124 pdi->pi_lintr.pin = 0; 1125 pdi->pi_lintr.state = IDLE; 1126 pdi->pi_lintr.pirq_pin = 0; 1127 pdi->pi_lintr.ioapic_irq = 0; 1128 #endif 1129 pdi->pi_d = pde; 1130 snprintf(pdi->pi_name, PI_NAMESZ, "%s@pci.%d.%d.%d", pde->pe_emu, bus, 1131 slot, func); 1132 1133 /* Disable legacy interrupts */ 1134 pci_set_cfgdata8(pdi, PCIR_INTLINE, 255); 1135 pci_set_cfgdata8(pdi, PCIR_INTPIN, 0); 1136 1137 pci_set_cfgdata8(pdi, PCIR_COMMAND, PCIM_CMD_BUSMASTEREN); 1138 1139 err = (*pde->pe_init)(pdi, fi->fi_config); 1140 if (err == 0) 1141 fi->fi_devi = pdi; 1142 else 1143 free(pdi); 1144 1145 return (err); 1146 } 1147 1148 void 1149 pci_populate_msicap(struct msicap *msicap, int msgnum, int nextptr) 1150 { 1151 int mmc; 1152 1153 /* Number of msi messages must be a power of 2 between 1 and 32 */ 1154 assert((msgnum & (msgnum - 1)) == 0 && msgnum >= 1 && msgnum <= 32); 1155 mmc = ffs(msgnum) - 1; 1156 1157 bzero(msicap, sizeof(struct msicap)); 1158 msicap->capid = PCIY_MSI; 1159 msicap->nextptr = nextptr; 1160 msicap->msgctrl = PCIM_MSICTRL_64BIT | (mmc << 1); 1161 } 1162 1163 int 1164 pci_emul_add_msicap(struct pci_devinst *pi, int msgnum) 1165 { 1166 struct msicap msicap; 1167 1168 pci_populate_msicap(&msicap, msgnum, 0); 1169 1170 return (pci_emul_add_capability(pi, (u_char *)&msicap, sizeof(msicap))); 1171 } 1172 1173 static void 1174 pci_populate_msixcap(struct msixcap *msixcap, int msgnum, int barnum, 1175 uint32_t msix_tab_size) 1176 { 1177 1178 assert(msix_tab_size % 4096 == 0); 1179 1180 bzero(msixcap, sizeof(struct msixcap)); 1181 msixcap->capid = PCIY_MSIX; 1182 1183 /* 1184 * Message Control Register, all fields set to 1185 * zero except for the Table Size. 1186 * Note: Table size N is encoded as N-1 1187 */ 1188 msixcap->msgctrl = msgnum - 1; 1189 1190 /* 1191 * MSI-X BAR setup: 1192 * - MSI-X table start at offset 0 1193 * - PBA table starts at a 4K aligned offset after the MSI-X table 1194 */ 1195 msixcap->table_info = barnum & PCIM_MSIX_BIR_MASK; 1196 msixcap->pba_info = msix_tab_size | (barnum & PCIM_MSIX_BIR_MASK); 1197 } 1198 1199 static void 1200 pci_msix_table_init(struct pci_devinst *pi, int table_entries) 1201 { 1202 int i, table_size; 1203 1204 assert(table_entries > 0); 1205 assert(table_entries <= MAX_MSIX_TABLE_ENTRIES); 1206 1207 table_size = table_entries * MSIX_TABLE_ENTRY_SIZE; 1208 pi->pi_msix.table = calloc(1, table_size); 1209 1210 /* set mask bit of vector control register */ 1211 for (i = 0; i < table_entries; i++) 1212 pi->pi_msix.table[i].vector_control |= PCIM_MSIX_VCTRL_MASK; 1213 } 1214 1215 int 1216 pci_emul_add_msixcap(struct pci_devinst *pi, int msgnum, int barnum) 1217 { 1218 uint32_t tab_size; 1219 struct msixcap msixcap; 1220 1221 assert(msgnum >= 1 && msgnum <= MAX_MSIX_TABLE_ENTRIES); 1222 assert(barnum >= 0 && barnum <= PCIR_MAX_BAR_0); 1223 1224 tab_size = msgnum * MSIX_TABLE_ENTRY_SIZE; 1225 1226 /* Align table size to nearest 4K */ 1227 tab_size = roundup2(tab_size, 4096); 1228 1229 pi->pi_msix.table_bar = barnum; 1230 pi->pi_msix.pba_bar = barnum; 1231 pi->pi_msix.table_offset = 0; 1232 pi->pi_msix.table_count = msgnum; 1233 pi->pi_msix.pba_offset = tab_size; 1234 pi->pi_msix.pba_size = PBA_SIZE(msgnum); 1235 1236 pci_msix_table_init(pi, msgnum); 1237 1238 pci_populate_msixcap(&msixcap, msgnum, barnum, tab_size); 1239 1240 /* allocate memory for MSI-X Table and PBA */ 1241 pci_emul_alloc_bar(pi, barnum, PCIBAR_MEM32, 1242 tab_size + pi->pi_msix.pba_size); 1243 1244 return (pci_emul_add_capability(pi, (u_char *)&msixcap, 1245 sizeof(msixcap))); 1246 } 1247 1248 static void 1249 msixcap_cfgwrite(struct pci_devinst *pi, int capoff, int offset, 1250 int bytes, uint32_t val) 1251 { 1252 uint16_t msgctrl, rwmask; 1253 int off; 1254 1255 off = offset - capoff; 1256 /* Message Control Register */ 1257 if (off == 2 && bytes == 2) { 1258 rwmask = PCIM_MSIXCTRL_MSIX_ENABLE | PCIM_MSIXCTRL_FUNCTION_MASK; 1259 msgctrl = pci_get_cfgdata16(pi, offset); 1260 msgctrl &= ~rwmask; 1261 msgctrl |= val & rwmask; 1262 val = msgctrl; 1263 1264 pi->pi_msix.enabled = val & PCIM_MSIXCTRL_MSIX_ENABLE; 1265 pi->pi_msix.function_mask = val & PCIM_MSIXCTRL_FUNCTION_MASK; 1266 #ifdef __amd64__ 1267 pci_lintr_update(pi); 1268 #endif 1269 } 1270 1271 CFGWRITE(pi, offset, val, bytes); 1272 } 1273 1274 static void 1275 msicap_cfgwrite(struct pci_devinst *pi, int capoff, int offset, 1276 int bytes, uint32_t val) 1277 { 1278 uint16_t msgctrl, rwmask, msgdata, mme; 1279 uint32_t addrlo; 1280 1281 /* 1282 * If guest is writing to the message control register make sure 1283 * we do not overwrite read-only fields. 1284 */ 1285 if ((offset - capoff) == 2 && bytes == 2) { 1286 rwmask = PCIM_MSICTRL_MME_MASK | PCIM_MSICTRL_MSI_ENABLE; 1287 msgctrl = pci_get_cfgdata16(pi, offset); 1288 msgctrl &= ~rwmask; 1289 msgctrl |= val & rwmask; 1290 val = msgctrl; 1291 } 1292 CFGWRITE(pi, offset, val, bytes); 1293 1294 msgctrl = pci_get_cfgdata16(pi, capoff + 2); 1295 addrlo = pci_get_cfgdata32(pi, capoff + 4); 1296 if (msgctrl & PCIM_MSICTRL_64BIT) 1297 msgdata = pci_get_cfgdata16(pi, capoff + 12); 1298 else 1299 msgdata = pci_get_cfgdata16(pi, capoff + 8); 1300 1301 mme = msgctrl & PCIM_MSICTRL_MME_MASK; 1302 pi->pi_msi.enabled = msgctrl & PCIM_MSICTRL_MSI_ENABLE ? 1 : 0; 1303 if (pi->pi_msi.enabled) { 1304 pi->pi_msi.addr = addrlo; 1305 pi->pi_msi.msg_data = msgdata; 1306 pi->pi_msi.maxmsgnum = 1 << (mme >> 4); 1307 } else { 1308 pi->pi_msi.maxmsgnum = 0; 1309 } 1310 #ifdef __amd64__ 1311 pci_lintr_update(pi); 1312 #endif 1313 } 1314 1315 static void 1316 pciecap_cfgwrite(struct pci_devinst *pi, int capoff __unused, int offset, 1317 int bytes, uint32_t val) 1318 { 1319 1320 /* XXX don't write to the readonly parts */ 1321 CFGWRITE(pi, offset, val, bytes); 1322 } 1323 1324 #define PCIECAP_VERSION 0x2 1325 int 1326 pci_emul_add_pciecap(struct pci_devinst *pi, int type) 1327 { 1328 int err; 1329 struct pciecap pciecap; 1330 1331 bzero(&pciecap, sizeof(pciecap)); 1332 1333 /* 1334 * Use the integrated endpoint type for endpoints on a root complex bus. 1335 * 1336 * NB: bhyve currently only supports a single PCI bus that is the root 1337 * complex bus, so all endpoints are integrated. 1338 */ 1339 if ((type == PCIEM_TYPE_ENDPOINT) && (pi->pi_bus == 0)) 1340 type = PCIEM_TYPE_ROOT_INT_EP; 1341 1342 pciecap.capid = PCIY_EXPRESS; 1343 pciecap.pcie_capabilities = PCIECAP_VERSION | type; 1344 if (type != PCIEM_TYPE_ROOT_INT_EP) { 1345 pciecap.link_capabilities = 0x411; /* gen1, x1 */ 1346 pciecap.link_status = 0x11; /* gen1, x1 */ 1347 } 1348 1349 err = pci_emul_add_capability(pi, (u_char *)&pciecap, sizeof(pciecap)); 1350 return (err); 1351 } 1352 1353 /* 1354 * This function assumes that 'coff' is in the capabilities region of the 1355 * config space. A capoff parameter of zero will force a search for the 1356 * offset and type. 1357 */ 1358 void 1359 pci_emul_capwrite(struct pci_devinst *pi, int offset, int bytes, uint32_t val, 1360 uint8_t capoff, int capid) 1361 { 1362 uint8_t nextoff; 1363 1364 /* Do not allow un-aligned writes */ 1365 if ((offset & (bytes - 1)) != 0) 1366 return; 1367 1368 if (capoff == 0) { 1369 /* Find the capability that we want to update */ 1370 capoff = CAP_START_OFFSET; 1371 while (1) { 1372 nextoff = pci_get_cfgdata8(pi, capoff + 1); 1373 if (nextoff == 0) 1374 break; 1375 if (offset >= capoff && offset < nextoff) 1376 break; 1377 1378 capoff = nextoff; 1379 } 1380 assert(offset >= capoff); 1381 capid = pci_get_cfgdata8(pi, capoff); 1382 } 1383 1384 /* 1385 * Capability ID and Next Capability Pointer are readonly. 1386 * However, some o/s's do 4-byte writes that include these. 1387 * For this case, trim the write back to 2 bytes and adjust 1388 * the data. 1389 */ 1390 if (offset == capoff || offset == capoff + 1) { 1391 if (offset == capoff && bytes == 4) { 1392 bytes = 2; 1393 offset += 2; 1394 val >>= 16; 1395 } else 1396 return; 1397 } 1398 1399 switch (capid) { 1400 case PCIY_MSI: 1401 msicap_cfgwrite(pi, capoff, offset, bytes, val); 1402 break; 1403 case PCIY_MSIX: 1404 msixcap_cfgwrite(pi, capoff, offset, bytes, val); 1405 break; 1406 case PCIY_EXPRESS: 1407 pciecap_cfgwrite(pi, capoff, offset, bytes, val); 1408 break; 1409 default: 1410 break; 1411 } 1412 } 1413 1414 static int 1415 pci_emul_iscap(struct pci_devinst *pi, int offset) 1416 { 1417 uint16_t sts; 1418 1419 sts = pci_get_cfgdata16(pi, PCIR_STATUS); 1420 if ((sts & PCIM_STATUS_CAPPRESENT) != 0) { 1421 if (offset >= CAP_START_OFFSET && offset <= pi->pi_capend) 1422 return (1); 1423 } 1424 return (0); 1425 } 1426 1427 static int 1428 pci_emul_fallback_handler(struct vcpu *vcpu __unused, int dir, 1429 uint64_t addr __unused, int size __unused, uint64_t *val, 1430 void *arg1 __unused, long arg2 __unused) 1431 { 1432 /* 1433 * Ignore writes; return 0xff's for reads. The mem read code 1434 * will take care of truncating to the correct size. 1435 */ 1436 if (dir == MEM_F_READ) { 1437 *val = 0xffffffffffffffff; 1438 } 1439 1440 return (0); 1441 } 1442 1443 static int 1444 pci_emul_ecfg_handler(struct vcpu *vcpu __unused, int dir, uint64_t addr, 1445 int bytes, uint64_t *val, void *arg1 __unused, long arg2 __unused) 1446 { 1447 int bus, slot, func, coff, in; 1448 1449 coff = addr & 0xfff; 1450 func = (addr >> 12) & 0x7; 1451 slot = (addr >> 15) & 0x1f; 1452 bus = (addr >> 20) & 0xff; 1453 in = (dir == MEM_F_READ); 1454 if (in) 1455 *val = ~0UL; 1456 pci_cfgrw(in, bus, slot, func, coff, bytes, (uint32_t *)val); 1457 return (0); 1458 } 1459 1460 uint64_t 1461 pci_ecfg_base(void) 1462 { 1463 1464 return (PCI_EMUL_ECFG_BASE); 1465 } 1466 1467 static int 1468 init_bootorder(void) 1469 { 1470 struct boot_device *device; 1471 FILE *fp; 1472 char *bootorder; 1473 size_t bootorder_len; 1474 1475 if (TAILQ_EMPTY(&boot_devices)) 1476 return (0); 1477 1478 fp = open_memstream(&bootorder, &bootorder_len); 1479 TAILQ_FOREACH(device, &boot_devices, boot_device_chain) { 1480 fprintf(fp, "/pci@i0cf8/pci@%d,%d\n", 1481 device->pdi->pi_slot, device->pdi->pi_func); 1482 } 1483 fclose(fp); 1484 1485 return (qemu_fwcfg_add_file("bootorder", bootorder_len, bootorder)); 1486 } 1487 1488 #define BUSIO_ROUNDUP 32 1489 #define BUSMEM32_ROUNDUP (1024 * 1024) 1490 #define BUSMEM64_ROUNDUP (512 * 1024 * 1024) 1491 1492 int 1493 init_pci(struct vmctx *ctx) 1494 { 1495 char node_name[sizeof("pci.XXX.XX.X")]; 1496 struct mem_range mr; 1497 struct pci_devemu *pde; 1498 struct businfo *bi; 1499 struct slotinfo *si; 1500 struct funcinfo *fi; 1501 nvlist_t *nvl; 1502 const char *emul; 1503 size_t lowmem; 1504 int bus, slot, func; 1505 int error; 1506 1507 if (vm_get_lowmem_limit(ctx) > PCI_EMUL_MEMBASE32) 1508 errx(EX_OSERR, "Invalid lowmem limit"); 1509 1510 pci_emul_iobase = PCI_EMUL_IOBASE; 1511 pci_emul_membase32 = PCI_EMUL_MEMBASE32; 1512 1513 pci_emul_membase64 = 4*GB + vm_get_highmem_size(ctx); 1514 pci_emul_membase64 = roundup2(pci_emul_membase64, PCI_EMUL_MEMSIZE64); 1515 pci_emul_memlim64 = pci_emul_membase64 + PCI_EMUL_MEMSIZE64; 1516 1517 TAILQ_INIT(&boot_devices); 1518 1519 for (bus = 0; bus < MAXBUSES; bus++) { 1520 snprintf(node_name, sizeof(node_name), "pci.%d", bus); 1521 nvl = find_config_node(node_name); 1522 if (nvl == NULL) 1523 continue; 1524 pci_businfo[bus] = calloc(1, sizeof(struct businfo)); 1525 bi = pci_businfo[bus]; 1526 1527 /* 1528 * Keep track of the i/o and memory resources allocated to 1529 * this bus. 1530 */ 1531 bi->iobase = pci_emul_iobase; 1532 bi->membase32 = pci_emul_membase32; 1533 bi->membase64 = pci_emul_membase64; 1534 1535 /* first run: init devices */ 1536 for (slot = 0; slot < MAXSLOTS; slot++) { 1537 si = &bi->slotinfo[slot]; 1538 for (func = 0; func < MAXFUNCS; func++) { 1539 fi = &si->si_funcs[func]; 1540 snprintf(node_name, sizeof(node_name), 1541 "pci.%d.%d.%d", bus, slot, func); 1542 nvl = find_config_node(node_name); 1543 if (nvl == NULL) 1544 continue; 1545 1546 fi->fi_config = nvl; 1547 emul = get_config_value_node(nvl, "device"); 1548 if (emul == NULL) { 1549 EPRINTLN("pci slot %d:%d:%d: missing " 1550 "\"device\" value", bus, slot, func); 1551 return (EINVAL); 1552 } 1553 pde = pci_emul_finddev(emul); 1554 if (pde == NULL) { 1555 EPRINTLN("pci slot %d:%d:%d: unknown " 1556 "device \"%s\"", bus, slot, func, 1557 emul); 1558 return (EINVAL); 1559 } 1560 if (pde->pe_alias != NULL) { 1561 EPRINTLN("pci slot %d:%d:%d: legacy " 1562 "device \"%s\", use \"%s\" instead", 1563 bus, slot, func, emul, 1564 pde->pe_alias); 1565 return (EINVAL); 1566 } 1567 fi->fi_pde = pde; 1568 error = pci_emul_init(ctx, pde, bus, slot, 1569 func, fi); 1570 if (error) 1571 return (error); 1572 } 1573 } 1574 1575 /* second run: assign BARs and free list */ 1576 struct pci_bar_allocation *bar; 1577 struct pci_bar_allocation *bar_tmp; 1578 TAILQ_FOREACH_SAFE(bar, &pci_bars, chain, bar_tmp) { 1579 pci_emul_assign_bar(bar->pdi, bar->idx, bar->type, 1580 bar->size); 1581 free(bar); 1582 } 1583 TAILQ_INIT(&pci_bars); 1584 1585 /* 1586 * Add some slop to the I/O and memory resources decoded by 1587 * this bus to give a guest some flexibility if it wants to 1588 * reprogram the BARs. 1589 */ 1590 pci_emul_iobase += BUSIO_ROUNDUP; 1591 pci_emul_iobase = roundup2(pci_emul_iobase, BUSIO_ROUNDUP); 1592 bi->iolimit = pci_emul_iobase; 1593 1594 pci_emul_membase32 += BUSMEM32_ROUNDUP; 1595 pci_emul_membase32 = roundup2(pci_emul_membase32, 1596 BUSMEM32_ROUNDUP); 1597 bi->memlimit32 = pci_emul_membase32; 1598 1599 pci_emul_membase64 += BUSMEM64_ROUNDUP; 1600 pci_emul_membase64 = roundup2(pci_emul_membase64, 1601 BUSMEM64_ROUNDUP); 1602 bi->memlimit64 = pci_emul_membase64; 1603 } 1604 1605 #ifdef __amd64__ 1606 /* 1607 * PCI backends are initialized before routing INTx interrupts 1608 * so that LPC devices are able to reserve ISA IRQs before 1609 * routing PIRQ pins. 1610 */ 1611 for (bus = 0; bus < MAXBUSES; bus++) { 1612 if ((bi = pci_businfo[bus]) == NULL) 1613 continue; 1614 1615 for (slot = 0; slot < MAXSLOTS; slot++) { 1616 si = &bi->slotinfo[slot]; 1617 for (func = 0; func < MAXFUNCS; func++) { 1618 fi = &si->si_funcs[func]; 1619 if (fi->fi_devi == NULL) 1620 continue; 1621 pci_lintr_route(fi->fi_devi); 1622 } 1623 } 1624 } 1625 lpc_pirq_routed(); 1626 #endif 1627 1628 if ((error = init_bootorder()) != 0) { 1629 warnx("%s: Unable to init bootorder", __func__); 1630 return (error); 1631 } 1632 1633 /* 1634 * The guest physical memory map looks like the following: 1635 * [0, lowmem) guest system memory 1636 * [lowmem, 0xC0000000) memory hole (may be absent) 1637 * [0xC0000000, 0xE0000000) PCI hole (32-bit BAR allocation) 1638 * [0xE0000000, 0xF0000000) PCI extended config window 1639 * [0xF0000000, 4GB) LAPIC, IOAPIC, HPET, firmware 1640 * [4GB, 4GB + highmem) 1641 */ 1642 1643 /* 1644 * Accesses to memory addresses that are not allocated to system 1645 * memory or PCI devices return 0xff's. 1646 */ 1647 lowmem = vm_get_lowmem_size(ctx); 1648 bzero(&mr, sizeof(struct mem_range)); 1649 mr.name = "PCI hole"; 1650 mr.flags = MEM_F_RW | MEM_F_IMMUTABLE; 1651 mr.base = lowmem; 1652 mr.size = (4ULL * 1024 * 1024 * 1024) - lowmem; 1653 mr.handler = pci_emul_fallback_handler; 1654 error = register_mem_fallback(&mr); 1655 assert(error == 0); 1656 1657 /* PCI extended config space */ 1658 bzero(&mr, sizeof(struct mem_range)); 1659 mr.name = "PCI ECFG"; 1660 mr.flags = MEM_F_RW | MEM_F_IMMUTABLE; 1661 mr.base = PCI_EMUL_ECFG_BASE; 1662 mr.size = PCI_EMUL_ECFG_SIZE; 1663 mr.handler = pci_emul_ecfg_handler; 1664 error = register_mem(&mr); 1665 assert(error == 0); 1666 1667 return (0); 1668 } 1669 1670 #ifdef __amd64__ 1671 static void 1672 pci_apic_prt_entry(int bus __unused, int slot, int pin, int pirq_pin __unused, 1673 int ioapic_irq, void *arg __unused) 1674 { 1675 1676 dsdt_line(" Package ()"); 1677 dsdt_line(" {"); 1678 dsdt_line(" 0x%X,", slot << 16 | 0xffff); 1679 dsdt_line(" 0x%02X,", pin - 1); 1680 dsdt_line(" Zero,"); 1681 dsdt_line(" 0x%X", ioapic_irq); 1682 dsdt_line(" },"); 1683 } 1684 1685 static void 1686 pci_pirq_prt_entry(int bus __unused, int slot, int pin, int pirq_pin, 1687 int ioapic_irq __unused, void *arg __unused) 1688 { 1689 char *name; 1690 1691 name = lpc_pirq_name(pirq_pin); 1692 if (name == NULL) 1693 return; 1694 dsdt_line(" Package ()"); 1695 dsdt_line(" {"); 1696 dsdt_line(" 0x%X,", slot << 16 | 0xffff); 1697 dsdt_line(" 0x%02X,", pin - 1); 1698 dsdt_line(" %s,", name); 1699 dsdt_line(" 0x00"); 1700 dsdt_line(" },"); 1701 free(name); 1702 } 1703 #endif 1704 1705 /* 1706 * A bhyve virtual machine has a flat PCI hierarchy with a root port 1707 * corresponding to each PCI bus. 1708 */ 1709 static void 1710 pci_bus_write_dsdt(int bus) 1711 { 1712 struct businfo *bi; 1713 struct slotinfo *si; 1714 struct pci_devinst *pi; 1715 int func, slot; 1716 1717 /* 1718 * If there are no devices on this 'bus' then just return. 1719 */ 1720 if ((bi = pci_businfo[bus]) == NULL) { 1721 /* 1722 * Bus 0 is special because it decodes the I/O ports used 1723 * for PCI config space access even if there are no devices 1724 * on it. 1725 */ 1726 if (bus != 0) 1727 return; 1728 } 1729 1730 dsdt_line(" Device (PC%02X)", bus); 1731 dsdt_line(" {"); 1732 dsdt_line(" Name (_HID, EisaId (\"PNP0A03\"))"); 1733 1734 dsdt_line(" Method (_BBN, 0, NotSerialized)"); 1735 dsdt_line(" {"); 1736 dsdt_line(" Return (0x%08X)", bus); 1737 dsdt_line(" }"); 1738 dsdt_line(" Name (_CRS, ResourceTemplate ()"); 1739 dsdt_line(" {"); 1740 dsdt_line(" WordBusNumber (ResourceProducer, MinFixed, " 1741 "MaxFixed, PosDecode,"); 1742 dsdt_line(" 0x0000, // Granularity"); 1743 dsdt_line(" 0x%04X, // Range Minimum", bus); 1744 dsdt_line(" 0x%04X, // Range Maximum", bus); 1745 dsdt_line(" 0x0000, // Translation Offset"); 1746 dsdt_line(" 0x0001, // Length"); 1747 dsdt_line(" ,, )"); 1748 1749 if (bus == 0) { 1750 dsdt_indent(3); 1751 dsdt_fixed_ioport(0xCF8, 8); 1752 dsdt_unindent(3); 1753 1754 dsdt_line(" WordIO (ResourceProducer, MinFixed, MaxFixed, " 1755 "PosDecode, EntireRange,"); 1756 dsdt_line(" 0x0000, // Granularity"); 1757 dsdt_line(" 0x0000, // Range Minimum"); 1758 dsdt_line(" 0x0CF7, // Range Maximum"); 1759 dsdt_line(" 0x0000, // Translation Offset"); 1760 dsdt_line(" 0x0CF8, // Length"); 1761 dsdt_line(" ,, , TypeStatic)"); 1762 1763 dsdt_line(" WordIO (ResourceProducer, MinFixed, MaxFixed, " 1764 "PosDecode, EntireRange,"); 1765 dsdt_line(" 0x0000, // Granularity"); 1766 dsdt_line(" 0x0D00, // Range Minimum"); 1767 dsdt_line(" 0x%04X, // Range Maximum", 1768 PCI_EMUL_IOBASE - 1); 1769 dsdt_line(" 0x0000, // Translation Offset"); 1770 dsdt_line(" 0x%04X, // Length", 1771 PCI_EMUL_IOBASE - 0x0D00); 1772 dsdt_line(" ,, , TypeStatic)"); 1773 1774 if (bi == NULL) { 1775 dsdt_line(" })"); 1776 goto done; 1777 } 1778 } 1779 assert(bi != NULL); 1780 1781 /* i/o window */ 1782 dsdt_line(" WordIO (ResourceProducer, MinFixed, MaxFixed, " 1783 "PosDecode, EntireRange,"); 1784 dsdt_line(" 0x0000, // Granularity"); 1785 dsdt_line(" 0x%04X, // Range Minimum", bi->iobase); 1786 dsdt_line(" 0x%04X, // Range Maximum", 1787 bi->iolimit - 1); 1788 dsdt_line(" 0x0000, // Translation Offset"); 1789 dsdt_line(" 0x%04X, // Length", 1790 bi->iolimit - bi->iobase); 1791 dsdt_line(" ,, , TypeStatic)"); 1792 1793 /* mmio window (32-bit) */ 1794 dsdt_line(" DWordMemory (ResourceProducer, PosDecode, " 1795 "MinFixed, MaxFixed, NonCacheable, ReadWrite,"); 1796 dsdt_line(" 0x00000000, // Granularity"); 1797 dsdt_line(" 0x%08X, // Range Minimum\n", bi->membase32); 1798 dsdt_line(" 0x%08X, // Range Maximum\n", 1799 bi->memlimit32 - 1); 1800 dsdt_line(" 0x00000000, // Translation Offset"); 1801 dsdt_line(" 0x%08X, // Length\n", 1802 bi->memlimit32 - bi->membase32); 1803 dsdt_line(" ,, , AddressRangeMemory, TypeStatic)"); 1804 1805 /* mmio window (64-bit) */ 1806 dsdt_line(" QWordMemory (ResourceProducer, PosDecode, " 1807 "MinFixed, MaxFixed, NonCacheable, ReadWrite,"); 1808 dsdt_line(" 0x0000000000000000, // Granularity"); 1809 dsdt_line(" 0x%016lX, // Range Minimum\n", bi->membase64); 1810 dsdt_line(" 0x%016lX, // Range Maximum\n", 1811 bi->memlimit64 - 1); 1812 dsdt_line(" 0x0000000000000000, // Translation Offset"); 1813 dsdt_line(" 0x%016lX, // Length\n", 1814 bi->memlimit64 - bi->membase64); 1815 dsdt_line(" ,, , AddressRangeMemory, TypeStatic)"); 1816 dsdt_line(" })"); 1817 1818 #ifdef __amd64__ 1819 if (pci_count_lintr(bus) != 0) { 1820 dsdt_indent(2); 1821 dsdt_line("Name (PPRT, Package ()"); 1822 dsdt_line("{"); 1823 pci_walk_lintr(bus, pci_pirq_prt_entry, NULL); 1824 dsdt_line("})"); 1825 dsdt_line("Name (APRT, Package ()"); 1826 dsdt_line("{"); 1827 pci_walk_lintr(bus, pci_apic_prt_entry, NULL); 1828 dsdt_line("})"); 1829 dsdt_line("Method (_PRT, 0, NotSerialized)"); 1830 dsdt_line("{"); 1831 dsdt_line(" If (PICM)"); 1832 dsdt_line(" {"); 1833 dsdt_line(" Return (APRT)"); 1834 dsdt_line(" }"); 1835 dsdt_line(" Else"); 1836 dsdt_line(" {"); 1837 dsdt_line(" Return (PPRT)"); 1838 dsdt_line(" }"); 1839 dsdt_line("}"); 1840 dsdt_unindent(2); 1841 } 1842 #endif 1843 1844 dsdt_indent(2); 1845 for (slot = 0; slot < MAXSLOTS; slot++) { 1846 si = &bi->slotinfo[slot]; 1847 for (func = 0; func < MAXFUNCS; func++) { 1848 pi = si->si_funcs[func].fi_devi; 1849 if (pi != NULL && pi->pi_d->pe_write_dsdt != NULL) 1850 pi->pi_d->pe_write_dsdt(pi); 1851 } 1852 } 1853 dsdt_unindent(2); 1854 done: 1855 dsdt_line(" }"); 1856 } 1857 1858 void 1859 pci_write_dsdt(void) 1860 { 1861 int bus; 1862 1863 dsdt_indent(1); 1864 dsdt_line("Name (PICM, 0x00)"); 1865 dsdt_line("Method (_PIC, 1, NotSerialized)"); 1866 dsdt_line("{"); 1867 dsdt_line(" Store (Arg0, PICM)"); 1868 dsdt_line("}"); 1869 dsdt_line(""); 1870 dsdt_line("Scope (_SB)"); 1871 dsdt_line("{"); 1872 for (bus = 0; bus < MAXBUSES; bus++) 1873 pci_bus_write_dsdt(bus); 1874 dsdt_line("}"); 1875 dsdt_unindent(1); 1876 } 1877 1878 int 1879 pci_bus_configured(int bus) 1880 { 1881 assert(bus >= 0 && bus < MAXBUSES); 1882 return (pci_businfo[bus] != NULL); 1883 } 1884 1885 int 1886 pci_msi_enabled(struct pci_devinst *pi) 1887 { 1888 return (pi->pi_msi.enabled); 1889 } 1890 1891 int 1892 pci_msi_maxmsgnum(struct pci_devinst *pi) 1893 { 1894 if (pi->pi_msi.enabled) 1895 return (pi->pi_msi.maxmsgnum); 1896 else 1897 return (0); 1898 } 1899 1900 int 1901 pci_msix_enabled(struct pci_devinst *pi) 1902 { 1903 1904 return (pi->pi_msix.enabled && !pi->pi_msi.enabled); 1905 } 1906 1907 void 1908 pci_generate_msix(struct pci_devinst *pi, int index) 1909 { 1910 struct msix_table_entry *mte; 1911 1912 if (!pci_msix_enabled(pi)) 1913 return; 1914 1915 if (pi->pi_msix.function_mask) 1916 return; 1917 1918 if (index >= pi->pi_msix.table_count) 1919 return; 1920 1921 mte = &pi->pi_msix.table[index]; 1922 if ((mte->vector_control & PCIM_MSIX_VCTRL_MASK) == 0) { 1923 /* XXX Set PBA bit if interrupt is disabled */ 1924 vm_lapic_msi(pi->pi_vmctx, mte->addr, mte->msg_data); 1925 } 1926 } 1927 1928 void 1929 pci_generate_msi(struct pci_devinst *pi, int index) 1930 { 1931 1932 if (pci_msi_enabled(pi) && index < pci_msi_maxmsgnum(pi)) { 1933 vm_lapic_msi(pi->pi_vmctx, pi->pi_msi.addr, 1934 pi->pi_msi.msg_data + index); 1935 } 1936 } 1937 1938 #ifdef __amd64__ 1939 static bool 1940 pci_lintr_permitted(struct pci_devinst *pi) 1941 { 1942 uint16_t cmd; 1943 1944 cmd = pci_get_cfgdata16(pi, PCIR_COMMAND); 1945 return (!(pi->pi_msi.enabled || pi->pi_msix.enabled || 1946 (cmd & PCIM_CMD_INTxDIS))); 1947 } 1948 1949 void 1950 pci_lintr_request(struct pci_devinst *pi) 1951 { 1952 struct businfo *bi; 1953 struct slotinfo *si; 1954 int bestpin, bestcount, pin; 1955 1956 bi = pci_businfo[pi->pi_bus]; 1957 assert(bi != NULL); 1958 1959 /* 1960 * Just allocate a pin from our slot. The pin will be 1961 * assigned IRQs later when interrupts are routed. 1962 */ 1963 si = &bi->slotinfo[pi->pi_slot]; 1964 bestpin = 0; 1965 bestcount = si->si_intpins[0].ii_count; 1966 for (pin = 1; pin < 4; pin++) { 1967 if (si->si_intpins[pin].ii_count < bestcount) { 1968 bestpin = pin; 1969 bestcount = si->si_intpins[pin].ii_count; 1970 } 1971 } 1972 1973 si->si_intpins[bestpin].ii_count++; 1974 pi->pi_lintr.pin = bestpin + 1; 1975 pci_set_cfgdata8(pi, PCIR_INTPIN, bestpin + 1); 1976 } 1977 1978 static void 1979 pci_lintr_route(struct pci_devinst *pi) 1980 { 1981 struct businfo *bi; 1982 struct intxinfo *ii; 1983 1984 if (pi->pi_lintr.pin == 0) 1985 return; 1986 1987 bi = pci_businfo[pi->pi_bus]; 1988 assert(bi != NULL); 1989 ii = &bi->slotinfo[pi->pi_slot].si_intpins[pi->pi_lintr.pin - 1]; 1990 1991 /* 1992 * Attempt to allocate an I/O APIC pin for this intpin if one 1993 * is not yet assigned. 1994 */ 1995 if (ii->ii_ioapic_irq == 0) 1996 ii->ii_ioapic_irq = ioapic_pci_alloc_irq(pi); 1997 assert(ii->ii_ioapic_irq > 0); 1998 1999 /* 2000 * Attempt to allocate a PIRQ pin for this intpin if one is 2001 * not yet assigned. 2002 */ 2003 if (ii->ii_pirq_pin == 0) 2004 ii->ii_pirq_pin = pirq_alloc_pin(pi); 2005 assert(ii->ii_pirq_pin > 0); 2006 2007 pi->pi_lintr.ioapic_irq = ii->ii_ioapic_irq; 2008 pi->pi_lintr.pirq_pin = ii->ii_pirq_pin; 2009 pci_set_cfgdata8(pi, PCIR_INTLINE, pirq_irq(ii->ii_pirq_pin)); 2010 } 2011 2012 void 2013 pci_lintr_assert(struct pci_devinst *pi) 2014 { 2015 2016 assert(pi->pi_lintr.pin > 0); 2017 2018 pthread_mutex_lock(&pi->pi_lintr.lock); 2019 if (pi->pi_lintr.state == IDLE) { 2020 if (pci_lintr_permitted(pi)) { 2021 pi->pi_lintr.state = ASSERTED; 2022 pci_irq_assert(pi); 2023 } else 2024 pi->pi_lintr.state = PENDING; 2025 } 2026 pthread_mutex_unlock(&pi->pi_lintr.lock); 2027 } 2028 2029 void 2030 pci_lintr_deassert(struct pci_devinst *pi) 2031 { 2032 2033 assert(pi->pi_lintr.pin > 0); 2034 2035 pthread_mutex_lock(&pi->pi_lintr.lock); 2036 if (pi->pi_lintr.state == ASSERTED) { 2037 pi->pi_lintr.state = IDLE; 2038 pci_irq_deassert(pi); 2039 } else if (pi->pi_lintr.state == PENDING) 2040 pi->pi_lintr.state = IDLE; 2041 pthread_mutex_unlock(&pi->pi_lintr.lock); 2042 } 2043 2044 static void 2045 pci_lintr_update(struct pci_devinst *pi) 2046 { 2047 2048 pthread_mutex_lock(&pi->pi_lintr.lock); 2049 if (pi->pi_lintr.state == ASSERTED && !pci_lintr_permitted(pi)) { 2050 pci_irq_deassert(pi); 2051 pi->pi_lintr.state = PENDING; 2052 } else if (pi->pi_lintr.state == PENDING && pci_lintr_permitted(pi)) { 2053 pi->pi_lintr.state = ASSERTED; 2054 pci_irq_assert(pi); 2055 } 2056 pthread_mutex_unlock(&pi->pi_lintr.lock); 2057 } 2058 2059 int 2060 pci_count_lintr(int bus) 2061 { 2062 int count, slot, pin; 2063 struct slotinfo *slotinfo; 2064 2065 count = 0; 2066 if (pci_businfo[bus] != NULL) { 2067 for (slot = 0; slot < MAXSLOTS; slot++) { 2068 slotinfo = &pci_businfo[bus]->slotinfo[slot]; 2069 for (pin = 0; pin < 4; pin++) { 2070 if (slotinfo->si_intpins[pin].ii_count != 0) 2071 count++; 2072 } 2073 } 2074 } 2075 return (count); 2076 } 2077 2078 void 2079 pci_walk_lintr(int bus, pci_lintr_cb cb, void *arg) 2080 { 2081 struct businfo *bi; 2082 struct slotinfo *si; 2083 struct intxinfo *ii; 2084 int slot, pin; 2085 2086 if ((bi = pci_businfo[bus]) == NULL) 2087 return; 2088 2089 for (slot = 0; slot < MAXSLOTS; slot++) { 2090 si = &bi->slotinfo[slot]; 2091 for (pin = 0; pin < 4; pin++) { 2092 ii = &si->si_intpins[pin]; 2093 if (ii->ii_count != 0) 2094 cb(bus, slot, pin + 1, ii->ii_pirq_pin, 2095 ii->ii_ioapic_irq, arg); 2096 } 2097 } 2098 } 2099 #endif /* __amd64__ */ 2100 2101 /* 2102 * Return 1 if the emulated device in 'slot' is a multi-function device. 2103 * Return 0 otherwise. 2104 */ 2105 static int 2106 pci_emul_is_mfdev(int bus, int slot) 2107 { 2108 struct businfo *bi; 2109 struct slotinfo *si; 2110 int f, numfuncs; 2111 2112 numfuncs = 0; 2113 if ((bi = pci_businfo[bus]) != NULL) { 2114 si = &bi->slotinfo[slot]; 2115 for (f = 0; f < MAXFUNCS; f++) { 2116 if (si->si_funcs[f].fi_devi != NULL) { 2117 numfuncs++; 2118 } 2119 } 2120 } 2121 return (numfuncs > 1); 2122 } 2123 2124 /* 2125 * Ensure that the PCIM_MFDEV bit is properly set (or unset) depending on 2126 * whether or not is a multi-function being emulated in the pci 'slot'. 2127 */ 2128 static void 2129 pci_emul_hdrtype_fixup(int bus, int slot, int off, int bytes, uint32_t *rv) 2130 { 2131 int mfdev; 2132 2133 if (off <= PCIR_HDRTYPE && off + bytes > PCIR_HDRTYPE) { 2134 mfdev = pci_emul_is_mfdev(bus, slot); 2135 switch (bytes) { 2136 case 1: 2137 case 2: 2138 *rv &= ~PCIM_MFDEV; 2139 if (mfdev) { 2140 *rv |= PCIM_MFDEV; 2141 } 2142 break; 2143 case 4: 2144 *rv &= ~(PCIM_MFDEV << 16); 2145 if (mfdev) { 2146 *rv |= (PCIM_MFDEV << 16); 2147 } 2148 break; 2149 } 2150 } 2151 } 2152 2153 /* 2154 * Update device state in response to changes to the PCI command 2155 * register. 2156 */ 2157 void 2158 pci_emul_cmd_changed(struct pci_devinst *pi, uint16_t old) 2159 { 2160 int i; 2161 uint16_t changed, new; 2162 2163 new = pci_get_cfgdata16(pi, PCIR_COMMAND); 2164 changed = old ^ new; 2165 2166 /* 2167 * If the MMIO or I/O address space decoding has changed then 2168 * register/unregister all BARs that decode that address space. 2169 */ 2170 for (i = 0; i <= PCI_BARMAX_WITH_ROM; i++) { 2171 switch (pi->pi_bar[i].type) { 2172 case PCIBAR_NONE: 2173 case PCIBAR_MEMHI64: 2174 break; 2175 case PCIBAR_IO: 2176 /* I/O address space decoding changed? */ 2177 if (changed & PCIM_CMD_PORTEN) { 2178 if (new & PCIM_CMD_PORTEN) 2179 register_bar(pi, i); 2180 else 2181 unregister_bar(pi, i); 2182 } 2183 break; 2184 case PCIBAR_ROM: 2185 /* skip (un-)register of ROM if it disabled */ 2186 if (!romen(pi)) 2187 break; 2188 /* fallthrough */ 2189 case PCIBAR_MEM32: 2190 case PCIBAR_MEM64: 2191 /* MMIO address space decoding changed? */ 2192 if (changed & PCIM_CMD_MEMEN) { 2193 if (new & PCIM_CMD_MEMEN) 2194 register_bar(pi, i); 2195 else 2196 unregister_bar(pi, i); 2197 } 2198 break; 2199 default: 2200 assert(0); 2201 } 2202 } 2203 2204 #ifdef __amd64__ 2205 /* 2206 * If INTx has been unmasked and is pending, assert the 2207 * interrupt. 2208 */ 2209 pci_lintr_update(pi); 2210 #endif 2211 } 2212 2213 static void 2214 pci_emul_cmdsts_write(struct pci_devinst *pi, int coff, uint32_t new, int bytes) 2215 { 2216 int rshift; 2217 uint32_t cmd, old, readonly; 2218 2219 cmd = pci_get_cfgdata16(pi, PCIR_COMMAND); /* stash old value */ 2220 2221 /* 2222 * From PCI Local Bus Specification 3.0 sections 6.2.2 and 6.2.3. 2223 * 2224 * XXX Bits 8, 11, 12, 13, 14 and 15 in the status register are 2225 * 'write 1 to clear'. However these bits are not set to '1' by 2226 * any device emulation so it is simpler to treat them as readonly. 2227 */ 2228 rshift = (coff & 0x3) * 8; 2229 readonly = 0xFFFFF880 >> rshift; 2230 2231 old = CFGREAD(pi, coff, bytes); 2232 new &= ~readonly; 2233 new |= (old & readonly); 2234 CFGWRITE(pi, coff, new, bytes); /* update config */ 2235 2236 pci_emul_cmd_changed(pi, cmd); 2237 } 2238 2239 static void 2240 pci_cfgrw(int in, int bus, int slot, int func, int coff, int bytes, 2241 uint32_t *valp) 2242 { 2243 struct businfo *bi; 2244 struct slotinfo *si; 2245 struct pci_devinst *pi; 2246 struct pci_devemu *pe; 2247 int idx, needcfg; 2248 uint64_t addr, bar, mask; 2249 2250 if ((bi = pci_businfo[bus]) != NULL) { 2251 si = &bi->slotinfo[slot]; 2252 pi = si->si_funcs[func].fi_devi; 2253 } else 2254 pi = NULL; 2255 2256 /* 2257 * Just return if there is no device at this slot:func or if the 2258 * the guest is doing an un-aligned access. 2259 */ 2260 if (pi == NULL || (bytes != 1 && bytes != 2 && bytes != 4) || 2261 (coff & (bytes - 1)) != 0) { 2262 if (in) 2263 *valp = 0xffffffff; 2264 return; 2265 } 2266 2267 /* 2268 * Ignore all writes beyond the standard config space and return all 2269 * ones on reads. 2270 */ 2271 if (coff >= PCI_REGMAX + 1) { 2272 if (in) { 2273 *valp = 0xffffffff; 2274 /* 2275 * Extended capabilities begin at offset 256 in config 2276 * space. Absence of extended capabilities is signaled 2277 * with all 0s in the extended capability header at 2278 * offset 256. 2279 */ 2280 if (coff <= PCI_REGMAX + 4) 2281 *valp = 0x00000000; 2282 } 2283 return; 2284 } 2285 2286 pe = pi->pi_d; 2287 2288 /* 2289 * Config read 2290 */ 2291 if (in) { 2292 /* Let the device emulation override the default handler */ 2293 if (pe->pe_cfgread != NULL) { 2294 needcfg = pe->pe_cfgread(pi, coff, bytes, valp); 2295 } else { 2296 needcfg = 1; 2297 } 2298 2299 if (needcfg) 2300 *valp = CFGREAD(pi, coff, bytes); 2301 2302 pci_emul_hdrtype_fixup(bus, slot, coff, bytes, valp); 2303 } else { 2304 /* Let the device emulation override the default handler */ 2305 if (pe->pe_cfgwrite != NULL && 2306 (*pe->pe_cfgwrite)(pi, coff, bytes, *valp) == 0) 2307 return; 2308 2309 /* 2310 * Special handling for write to BAR and ROM registers 2311 */ 2312 if (is_pcir_bar(coff) || is_pcir_bios(coff)) { 2313 /* 2314 * Ignore writes to BAR registers that are not 2315 * 4-byte aligned. 2316 */ 2317 if (bytes != 4 || (coff & 0x3) != 0) 2318 return; 2319 2320 if (is_pcir_bar(coff)) { 2321 idx = (coff - PCIR_BAR(0)) / 4; 2322 } else if (is_pcir_bios(coff)) { 2323 idx = PCI_ROM_IDX; 2324 } else { 2325 errx(4, "%s: invalid BAR offset %d", __func__, 2326 coff); 2327 } 2328 2329 mask = ~(pi->pi_bar[idx].size - 1); 2330 switch (pi->pi_bar[idx].type) { 2331 case PCIBAR_NONE: 2332 pi->pi_bar[idx].addr = bar = 0; 2333 break; 2334 case PCIBAR_IO: 2335 addr = *valp & mask; 2336 addr &= 0xffff; 2337 bar = addr | pi->pi_bar[idx].lobits; 2338 /* 2339 * Register the new BAR value for interception 2340 */ 2341 if (addr != pi->pi_bar[idx].addr) { 2342 update_bar_address(pi, addr, idx, 2343 PCIBAR_IO); 2344 } 2345 break; 2346 case PCIBAR_MEM32: 2347 addr = bar = *valp & mask; 2348 bar |= pi->pi_bar[idx].lobits; 2349 if (addr != pi->pi_bar[idx].addr) { 2350 update_bar_address(pi, addr, idx, 2351 PCIBAR_MEM32); 2352 } 2353 break; 2354 case PCIBAR_MEM64: 2355 addr = bar = *valp & mask; 2356 bar |= pi->pi_bar[idx].lobits; 2357 if (addr != (uint32_t)pi->pi_bar[idx].addr) { 2358 update_bar_address(pi, addr, idx, 2359 PCIBAR_MEM64); 2360 } 2361 break; 2362 case PCIBAR_MEMHI64: 2363 mask = ~(pi->pi_bar[idx - 1].size - 1); 2364 addr = ((uint64_t)*valp << 32) & mask; 2365 bar = addr >> 32; 2366 if (bar != pi->pi_bar[idx - 1].addr >> 32) { 2367 update_bar_address(pi, addr, idx - 1, 2368 PCIBAR_MEMHI64); 2369 } 2370 break; 2371 case PCIBAR_ROM: 2372 addr = bar = *valp & mask; 2373 if (memen(pi) && romen(pi)) { 2374 unregister_bar(pi, idx); 2375 } 2376 pi->pi_bar[idx].addr = addr; 2377 pi->pi_bar[idx].lobits = *valp & 2378 PCIM_BIOS_ENABLE; 2379 /* romen could have changed it value */ 2380 if (memen(pi) && romen(pi)) { 2381 register_bar(pi, idx); 2382 } 2383 bar |= pi->pi_bar[idx].lobits; 2384 break; 2385 default: 2386 assert(0); 2387 } 2388 pci_set_cfgdata32(pi, coff, bar); 2389 2390 } else if (pci_emul_iscap(pi, coff)) { 2391 pci_emul_capwrite(pi, coff, bytes, *valp, 0, 0); 2392 } else if (coff >= PCIR_COMMAND && coff < PCIR_REVID) { 2393 pci_emul_cmdsts_write(pi, coff, *valp, bytes); 2394 } else { 2395 CFGWRITE(pi, coff, *valp, bytes); 2396 } 2397 } 2398 } 2399 2400 #ifdef __amd64__ 2401 static int cfgenable, cfgbus, cfgslot, cfgfunc, cfgoff; 2402 2403 static int 2404 pci_emul_cfgaddr(struct vmctx *ctx __unused, int in, 2405 int port __unused, int bytes, uint32_t *eax, void *arg __unused) 2406 { 2407 uint32_t x; 2408 2409 if (bytes != 4) { 2410 if (in) 2411 *eax = (bytes == 2) ? 0xffff : 0xff; 2412 return (0); 2413 } 2414 2415 if (in) { 2416 x = (cfgbus << 16) | (cfgslot << 11) | (cfgfunc << 8) | cfgoff; 2417 if (cfgenable) 2418 x |= CONF1_ENABLE; 2419 *eax = x; 2420 } else { 2421 x = *eax; 2422 cfgenable = (x & CONF1_ENABLE) == CONF1_ENABLE; 2423 cfgoff = (x & PCI_REGMAX) & ~0x03; 2424 cfgfunc = (x >> 8) & PCI_FUNCMAX; 2425 cfgslot = (x >> 11) & PCI_SLOTMAX; 2426 cfgbus = (x >> 16) & PCI_BUSMAX; 2427 } 2428 2429 return (0); 2430 } 2431 INOUT_PORT(pci_cfgaddr, CONF1_ADDR_PORT, IOPORT_F_INOUT, pci_emul_cfgaddr); 2432 2433 static int 2434 pci_emul_cfgdata(struct vmctx *ctx __unused, int in, int port, 2435 int bytes, uint32_t *eax, void *arg __unused) 2436 { 2437 int coff; 2438 2439 assert(bytes == 1 || bytes == 2 || bytes == 4); 2440 2441 coff = cfgoff + (port - CONF1_DATA_PORT); 2442 if (cfgenable) { 2443 pci_cfgrw(in, cfgbus, cfgslot, cfgfunc, coff, bytes, eax); 2444 } else { 2445 /* Ignore accesses to cfgdata if not enabled by cfgaddr */ 2446 if (in) 2447 *eax = 0xffffffff; 2448 } 2449 return (0); 2450 } 2451 2452 INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+0, IOPORT_F_INOUT, pci_emul_cfgdata); 2453 INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+1, IOPORT_F_INOUT, pci_emul_cfgdata); 2454 INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+2, IOPORT_F_INOUT, pci_emul_cfgdata); 2455 INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+3, IOPORT_F_INOUT, pci_emul_cfgdata); 2456 #endif 2457 2458 #ifdef BHYVE_SNAPSHOT 2459 /* 2460 * Saves/restores PCI device emulated state. Returns 0 on success. 2461 */ 2462 static int 2463 pci_snapshot_pci_dev(struct vm_snapshot_meta *meta) 2464 { 2465 struct pci_devinst *pi; 2466 int i; 2467 int ret; 2468 2469 pi = meta->dev_data; 2470 2471 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msi.enabled, meta, ret, done); 2472 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msi.addr, meta, ret, done); 2473 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msi.msg_data, meta, ret, done); 2474 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msi.maxmsgnum, meta, ret, done); 2475 2476 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.enabled, meta, ret, done); 2477 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.table_bar, meta, ret, done); 2478 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.pba_bar, meta, ret, done); 2479 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.table_offset, meta, ret, done); 2480 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.table_count, meta, ret, done); 2481 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.pba_offset, meta, ret, done); 2482 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.pba_size, meta, ret, done); 2483 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.function_mask, meta, ret, done); 2484 2485 SNAPSHOT_BUF_OR_LEAVE(pi->pi_cfgdata, sizeof(pi->pi_cfgdata), 2486 meta, ret, done); 2487 2488 for (i = 0; i < (int)nitems(pi->pi_bar); i++) { 2489 SNAPSHOT_VAR_OR_LEAVE(pi->pi_bar[i].type, meta, ret, done); 2490 SNAPSHOT_VAR_OR_LEAVE(pi->pi_bar[i].size, meta, ret, done); 2491 SNAPSHOT_VAR_OR_LEAVE(pi->pi_bar[i].addr, meta, ret, done); 2492 } 2493 2494 /* Restore MSI-X table. */ 2495 for (i = 0; i < pi->pi_msix.table_count; i++) { 2496 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.table[i].addr, 2497 meta, ret, done); 2498 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.table[i].msg_data, 2499 meta, ret, done); 2500 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.table[i].vector_control, 2501 meta, ret, done); 2502 } 2503 2504 done: 2505 return (ret); 2506 } 2507 2508 int 2509 pci_snapshot(struct vm_snapshot_meta *meta) 2510 { 2511 struct pci_devemu *pde; 2512 struct pci_devinst *pdi; 2513 int ret; 2514 2515 assert(meta->dev_name != NULL); 2516 2517 pdi = meta->dev_data; 2518 pde = pdi->pi_d; 2519 2520 if (pde->pe_snapshot == NULL) 2521 return (ENOTSUP); 2522 2523 ret = pci_snapshot_pci_dev(meta); 2524 if (ret == 0) 2525 ret = (*pde->pe_snapshot)(meta); 2526 2527 return (ret); 2528 } 2529 2530 int 2531 pci_pause(struct pci_devinst *pdi) 2532 { 2533 struct pci_devemu *pde = pdi->pi_d; 2534 2535 if (pde->pe_pause == NULL) { 2536 /* The pause/resume functionality is optional. */ 2537 return (0); 2538 } 2539 2540 return (*pde->pe_pause)(pdi); 2541 } 2542 2543 int 2544 pci_resume(struct pci_devinst *pdi) 2545 { 2546 struct pci_devemu *pde = pdi->pi_d; 2547 2548 if (pde->pe_resume == NULL) { 2549 /* The pause/resume functionality is optional. */ 2550 return (0); 2551 } 2552 2553 return (*pde->pe_resume)(pdi); 2554 } 2555 #endif 2556 2557 #define PCI_EMUL_TEST 2558 #ifdef PCI_EMUL_TEST 2559 /* 2560 * Define a dummy test device 2561 */ 2562 #define DIOSZ 8 2563 #define DMEMSZ 4096 2564 struct pci_emul_dsoftc { 2565 uint8_t ioregs[DIOSZ]; 2566 uint8_t memregs[2][DMEMSZ]; 2567 }; 2568 2569 #define PCI_EMUL_MSI_MSGS 4 2570 #define PCI_EMUL_MSIX_MSGS 16 2571 2572 static int 2573 pci_emul_dinit(struct pci_devinst *pi, nvlist_t *nvl __unused) 2574 { 2575 int error; 2576 struct pci_emul_dsoftc *sc; 2577 2578 sc = calloc(1, sizeof(struct pci_emul_dsoftc)); 2579 2580 pi->pi_arg = sc; 2581 2582 pci_set_cfgdata16(pi, PCIR_DEVICE, 0x0001); 2583 pci_set_cfgdata16(pi, PCIR_VENDOR, 0x10DD); 2584 pci_set_cfgdata8(pi, PCIR_CLASS, 0x02); 2585 2586 error = pci_emul_add_msicap(pi, PCI_EMUL_MSI_MSGS); 2587 assert(error == 0); 2588 2589 error = pci_emul_alloc_bar(pi, 0, PCIBAR_IO, DIOSZ); 2590 assert(error == 0); 2591 2592 error = pci_emul_alloc_bar(pi, 1, PCIBAR_MEM32, DMEMSZ); 2593 assert(error == 0); 2594 2595 error = pci_emul_alloc_bar(pi, 2, PCIBAR_MEM32, DMEMSZ); 2596 assert(error == 0); 2597 2598 return (0); 2599 } 2600 2601 static void 2602 pci_emul_diow(struct pci_devinst *pi, int baridx, uint64_t offset, int size, 2603 uint64_t value) 2604 { 2605 int i; 2606 struct pci_emul_dsoftc *sc = pi->pi_arg; 2607 2608 if (baridx == 0) { 2609 if (offset + size > DIOSZ) { 2610 printf("diow: iow too large, offset %ld size %d\n", 2611 offset, size); 2612 return; 2613 } 2614 2615 if (size == 1) { 2616 sc->ioregs[offset] = value & 0xff; 2617 } else if (size == 2) { 2618 *(uint16_t *)&sc->ioregs[offset] = value & 0xffff; 2619 } else if (size == 4) { 2620 *(uint32_t *)&sc->ioregs[offset] = value; 2621 } else { 2622 printf("diow: iow unknown size %d\n", size); 2623 } 2624 2625 /* 2626 * Special magic value to generate an interrupt 2627 */ 2628 if (offset == 4 && size == 4 && pci_msi_enabled(pi)) 2629 pci_generate_msi(pi, value % pci_msi_maxmsgnum(pi)); 2630 2631 if (value == 0xabcdef) { 2632 for (i = 0; i < pci_msi_maxmsgnum(pi); i++) 2633 pci_generate_msi(pi, i); 2634 } 2635 } 2636 2637 if (baridx == 1 || baridx == 2) { 2638 if (offset + size > DMEMSZ) { 2639 printf("diow: memw too large, offset %ld size %d\n", 2640 offset, size); 2641 return; 2642 } 2643 2644 i = baridx - 1; /* 'memregs' index */ 2645 2646 if (size == 1) { 2647 sc->memregs[i][offset] = value; 2648 } else if (size == 2) { 2649 *(uint16_t *)&sc->memregs[i][offset] = value; 2650 } else if (size == 4) { 2651 *(uint32_t *)&sc->memregs[i][offset] = value; 2652 } else if (size == 8) { 2653 *(uint64_t *)&sc->memregs[i][offset] = value; 2654 } else { 2655 printf("diow: memw unknown size %d\n", size); 2656 } 2657 2658 /* 2659 * magic interrupt ?? 2660 */ 2661 } 2662 2663 if (baridx > 2 || baridx < 0) { 2664 printf("diow: unknown bar idx %d\n", baridx); 2665 } 2666 } 2667 2668 static uint64_t 2669 pci_emul_dior(struct pci_devinst *pi, int baridx, uint64_t offset, int size) 2670 { 2671 struct pci_emul_dsoftc *sc = pi->pi_arg; 2672 uint32_t value; 2673 int i; 2674 2675 if (baridx == 0) { 2676 if (offset + size > DIOSZ) { 2677 printf("dior: ior too large, offset %ld size %d\n", 2678 offset, size); 2679 return (0); 2680 } 2681 2682 value = 0; 2683 if (size == 1) { 2684 value = sc->ioregs[offset]; 2685 } else if (size == 2) { 2686 value = *(uint16_t *) &sc->ioregs[offset]; 2687 } else if (size == 4) { 2688 value = *(uint32_t *) &sc->ioregs[offset]; 2689 } else { 2690 printf("dior: ior unknown size %d\n", size); 2691 } 2692 } 2693 2694 if (baridx == 1 || baridx == 2) { 2695 if (offset + size > DMEMSZ) { 2696 printf("dior: memr too large, offset %ld size %d\n", 2697 offset, size); 2698 return (0); 2699 } 2700 2701 i = baridx - 1; /* 'memregs' index */ 2702 2703 if (size == 1) { 2704 value = sc->memregs[i][offset]; 2705 } else if (size == 2) { 2706 value = *(uint16_t *) &sc->memregs[i][offset]; 2707 } else if (size == 4) { 2708 value = *(uint32_t *) &sc->memregs[i][offset]; 2709 } else if (size == 8) { 2710 value = *(uint64_t *) &sc->memregs[i][offset]; 2711 } else { 2712 printf("dior: ior unknown size %d\n", size); 2713 } 2714 } 2715 2716 2717 if (baridx > 2 || baridx < 0) { 2718 printf("dior: unknown bar idx %d\n", baridx); 2719 return (0); 2720 } 2721 2722 return (value); 2723 } 2724 2725 #ifdef BHYVE_SNAPSHOT 2726 struct pci_devinst * 2727 pci_next(const struct pci_devinst *cursor) 2728 { 2729 unsigned bus = 0, slot = 0, func = 0; 2730 struct businfo *bi; 2731 struct slotinfo *si; 2732 struct funcinfo *fi; 2733 2734 bus = cursor ? cursor->pi_bus : 0; 2735 slot = cursor ? cursor->pi_slot : 0; 2736 func = cursor ? (cursor->pi_func + 1) : 0; 2737 2738 for (; bus < MAXBUSES; bus++) { 2739 if ((bi = pci_businfo[bus]) == NULL) 2740 continue; 2741 2742 if (slot >= MAXSLOTS) 2743 slot = 0; 2744 2745 for (; slot < MAXSLOTS; slot++) { 2746 si = &bi->slotinfo[slot]; 2747 if (func >= MAXFUNCS) 2748 func = 0; 2749 for (; func < MAXFUNCS; func++) { 2750 fi = &si->si_funcs[func]; 2751 if (fi->fi_devi == NULL) 2752 continue; 2753 2754 return (fi->fi_devi); 2755 } 2756 } 2757 } 2758 2759 return (NULL); 2760 } 2761 2762 static int 2763 pci_emul_snapshot(struct vm_snapshot_meta *meta __unused) 2764 { 2765 return (0); 2766 } 2767 #endif 2768 2769 static const struct pci_devemu pci_dummy = { 2770 .pe_emu = "dummy", 2771 .pe_init = pci_emul_dinit, 2772 .pe_barwrite = pci_emul_diow, 2773 .pe_barread = pci_emul_dior, 2774 #ifdef BHYVE_SNAPSHOT 2775 .pe_snapshot = pci_emul_snapshot, 2776 #endif 2777 }; 2778 PCI_EMUL_SET(pci_dummy); 2779 2780 #endif /* PCI_EMUL_TEST */ 2781