1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2011 NetApp, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 */ 30 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD$"); 33 34 #include <sys/param.h> 35 #include <sys/linker_set.h> 36 37 #include <ctype.h> 38 #include <errno.h> 39 #include <pthread.h> 40 #include <stdio.h> 41 #include <stdlib.h> 42 #include <string.h> 43 #include <strings.h> 44 #include <assert.h> 45 #include <stdbool.h> 46 47 #include <machine/vmm.h> 48 #include <vmmapi.h> 49 50 #include "acpi.h" 51 #include "bhyverun.h" 52 #include "inout.h" 53 #include "ioapic.h" 54 #include "mem.h" 55 #include "pci_emul.h" 56 #include "pci_irq.h" 57 #include "pci_lpc.h" 58 59 #define CONF1_ADDR_PORT 0x0cf8 60 #define CONF1_DATA_PORT 0x0cfc 61 62 #define CONF1_ENABLE 0x80000000ul 63 64 #define MAXBUSES (PCI_BUSMAX + 1) 65 #define MAXSLOTS (PCI_SLOTMAX + 1) 66 #define MAXFUNCS (PCI_FUNCMAX + 1) 67 68 struct funcinfo { 69 char *fi_name; 70 char *fi_param; 71 struct pci_devinst *fi_devi; 72 }; 73 74 struct intxinfo { 75 int ii_count; 76 int ii_pirq_pin; 77 int ii_ioapic_irq; 78 }; 79 80 struct slotinfo { 81 struct intxinfo si_intpins[4]; 82 struct funcinfo si_funcs[MAXFUNCS]; 83 }; 84 85 struct businfo { 86 uint16_t iobase, iolimit; /* I/O window */ 87 uint32_t membase32, memlimit32; /* mmio window below 4GB */ 88 uint64_t membase64, memlimit64; /* mmio window above 4GB */ 89 struct slotinfo slotinfo[MAXSLOTS]; 90 }; 91 92 static struct businfo *pci_businfo[MAXBUSES]; 93 94 SET_DECLARE(pci_devemu_set, struct pci_devemu); 95 96 static uint64_t pci_emul_iobase; 97 static uint64_t pci_emul_membase32; 98 static uint64_t pci_emul_membase64; 99 100 #define PCI_EMUL_IOBASE 0x2000 101 #define PCI_EMUL_IOLIMIT 0x10000 102 103 #define PCI_EMUL_ECFG_BASE 0xE0000000 /* 3.5GB */ 104 #define PCI_EMUL_ECFG_SIZE (MAXBUSES * 1024 * 1024) /* 1MB per bus */ 105 SYSRES_MEM(PCI_EMUL_ECFG_BASE, PCI_EMUL_ECFG_SIZE); 106 107 #define PCI_EMUL_MEMLIMIT32 PCI_EMUL_ECFG_BASE 108 109 #define PCI_EMUL_MEMBASE64 0xD000000000UL 110 #define PCI_EMUL_MEMLIMIT64 0xFD00000000UL 111 112 static struct pci_devemu *pci_emul_finddev(char *name); 113 static void pci_lintr_route(struct pci_devinst *pi); 114 static void pci_lintr_update(struct pci_devinst *pi); 115 static void pci_cfgrw(struct vmctx *ctx, int vcpu, int in, int bus, int slot, 116 int func, int coff, int bytes, uint32_t *val); 117 118 static __inline void 119 CFGWRITE(struct pci_devinst *pi, int coff, uint32_t val, int bytes) 120 { 121 122 if (bytes == 1) 123 pci_set_cfgdata8(pi, coff, val); 124 else if (bytes == 2) 125 pci_set_cfgdata16(pi, coff, val); 126 else 127 pci_set_cfgdata32(pi, coff, val); 128 } 129 130 static __inline uint32_t 131 CFGREAD(struct pci_devinst *pi, int coff, int bytes) 132 { 133 134 if (bytes == 1) 135 return (pci_get_cfgdata8(pi, coff)); 136 else if (bytes == 2) 137 return (pci_get_cfgdata16(pi, coff)); 138 else 139 return (pci_get_cfgdata32(pi, coff)); 140 } 141 142 /* 143 * I/O access 144 */ 145 146 /* 147 * Slot options are in the form: 148 * 149 * <bus>:<slot>:<func>,<emul>[,<config>] 150 * <slot>[:<func>],<emul>[,<config>] 151 * 152 * slot is 0..31 153 * func is 0..7 154 * emul is a string describing the type of PCI device e.g. virtio-net 155 * config is an optional string, depending on the device, that can be 156 * used for configuration. 157 * Examples are: 158 * 1,virtio-net,tap0 159 * 3:0,dummy 160 */ 161 static void 162 pci_parse_slot_usage(char *aopt) 163 { 164 165 fprintf(stderr, "Invalid PCI slot info field \"%s\"\n", aopt); 166 } 167 168 int 169 pci_parse_slot(char *opt) 170 { 171 struct businfo *bi; 172 struct slotinfo *si; 173 char *emul, *config, *str, *cp; 174 int error, bnum, snum, fnum; 175 176 error = -1; 177 str = strdup(opt); 178 179 emul = config = NULL; 180 if ((cp = strchr(str, ',')) != NULL) { 181 *cp = '\0'; 182 emul = cp + 1; 183 if ((cp = strchr(emul, ',')) != NULL) { 184 *cp = '\0'; 185 config = cp + 1; 186 } 187 } else { 188 pci_parse_slot_usage(opt); 189 goto done; 190 } 191 192 /* <bus>:<slot>:<func> */ 193 if (sscanf(str, "%d:%d:%d", &bnum, &snum, &fnum) != 3) { 194 bnum = 0; 195 /* <slot>:<func> */ 196 if (sscanf(str, "%d:%d", &snum, &fnum) != 2) { 197 fnum = 0; 198 /* <slot> */ 199 if (sscanf(str, "%d", &snum) != 1) { 200 snum = -1; 201 } 202 } 203 } 204 205 if (bnum < 0 || bnum >= MAXBUSES || snum < 0 || snum >= MAXSLOTS || 206 fnum < 0 || fnum >= MAXFUNCS) { 207 pci_parse_slot_usage(opt); 208 goto done; 209 } 210 211 if (pci_businfo[bnum] == NULL) 212 pci_businfo[bnum] = calloc(1, sizeof(struct businfo)); 213 214 bi = pci_businfo[bnum]; 215 si = &bi->slotinfo[snum]; 216 217 if (si->si_funcs[fnum].fi_name != NULL) { 218 fprintf(stderr, "pci slot %d:%d already occupied!\n", 219 snum, fnum); 220 goto done; 221 } 222 223 if (pci_emul_finddev(emul) == NULL) { 224 fprintf(stderr, "pci slot %d:%d: unknown device \"%s\"\n", 225 snum, fnum, emul); 226 goto done; 227 } 228 229 error = 0; 230 si->si_funcs[fnum].fi_name = emul; 231 si->si_funcs[fnum].fi_param = config; 232 233 done: 234 if (error) 235 free(str); 236 237 return (error); 238 } 239 240 void 241 pci_print_supported_devices() 242 { 243 struct pci_devemu **pdpp, *pdp; 244 245 SET_FOREACH(pdpp, pci_devemu_set) { 246 pdp = *pdpp; 247 printf("%s\n", pdp->pe_emu); 248 } 249 } 250 251 static int 252 pci_valid_pba_offset(struct pci_devinst *pi, uint64_t offset) 253 { 254 255 if (offset < pi->pi_msix.pba_offset) 256 return (0); 257 258 if (offset >= pi->pi_msix.pba_offset + pi->pi_msix.pba_size) { 259 return (0); 260 } 261 262 return (1); 263 } 264 265 int 266 pci_emul_msix_twrite(struct pci_devinst *pi, uint64_t offset, int size, 267 uint64_t value) 268 { 269 int msix_entry_offset; 270 int tab_index; 271 char *dest; 272 273 /* support only 4 or 8 byte writes */ 274 if (size != 4 && size != 8) 275 return (-1); 276 277 /* 278 * Return if table index is beyond what device supports 279 */ 280 tab_index = offset / MSIX_TABLE_ENTRY_SIZE; 281 if (tab_index >= pi->pi_msix.table_count) 282 return (-1); 283 284 msix_entry_offset = offset % MSIX_TABLE_ENTRY_SIZE; 285 286 /* support only aligned writes */ 287 if ((msix_entry_offset % size) != 0) 288 return (-1); 289 290 dest = (char *)(pi->pi_msix.table + tab_index); 291 dest += msix_entry_offset; 292 293 if (size == 4) 294 *((uint32_t *)dest) = value; 295 else 296 *((uint64_t *)dest) = value; 297 298 return (0); 299 } 300 301 uint64_t 302 pci_emul_msix_tread(struct pci_devinst *pi, uint64_t offset, int size) 303 { 304 char *dest; 305 int msix_entry_offset; 306 int tab_index; 307 uint64_t retval = ~0; 308 309 /* 310 * The PCI standard only allows 4 and 8 byte accesses to the MSI-X 311 * table but we also allow 1 byte access to accommodate reads from 312 * ddb. 313 */ 314 if (size != 1 && size != 4 && size != 8) 315 return (retval); 316 317 msix_entry_offset = offset % MSIX_TABLE_ENTRY_SIZE; 318 319 /* support only aligned reads */ 320 if ((msix_entry_offset % size) != 0) { 321 return (retval); 322 } 323 324 tab_index = offset / MSIX_TABLE_ENTRY_SIZE; 325 326 if (tab_index < pi->pi_msix.table_count) { 327 /* valid MSI-X Table access */ 328 dest = (char *)(pi->pi_msix.table + tab_index); 329 dest += msix_entry_offset; 330 331 if (size == 1) 332 retval = *((uint8_t *)dest); 333 else if (size == 4) 334 retval = *((uint32_t *)dest); 335 else 336 retval = *((uint64_t *)dest); 337 } else if (pci_valid_pba_offset(pi, offset)) { 338 /* return 0 for PBA access */ 339 retval = 0; 340 } 341 342 return (retval); 343 } 344 345 int 346 pci_msix_table_bar(struct pci_devinst *pi) 347 { 348 349 if (pi->pi_msix.table != NULL) 350 return (pi->pi_msix.table_bar); 351 else 352 return (-1); 353 } 354 355 int 356 pci_msix_pba_bar(struct pci_devinst *pi) 357 { 358 359 if (pi->pi_msix.table != NULL) 360 return (pi->pi_msix.pba_bar); 361 else 362 return (-1); 363 } 364 365 static int 366 pci_emul_io_handler(struct vmctx *ctx, int vcpu, int in, int port, int bytes, 367 uint32_t *eax, void *arg) 368 { 369 struct pci_devinst *pdi = arg; 370 struct pci_devemu *pe = pdi->pi_d; 371 uint64_t offset; 372 int i; 373 374 for (i = 0; i <= PCI_BARMAX; i++) { 375 if (pdi->pi_bar[i].type == PCIBAR_IO && 376 port >= pdi->pi_bar[i].addr && 377 port + bytes <= pdi->pi_bar[i].addr + pdi->pi_bar[i].size) { 378 offset = port - pdi->pi_bar[i].addr; 379 if (in) 380 *eax = (*pe->pe_barread)(ctx, vcpu, pdi, i, 381 offset, bytes); 382 else 383 (*pe->pe_barwrite)(ctx, vcpu, pdi, i, offset, 384 bytes, *eax); 385 return (0); 386 } 387 } 388 return (-1); 389 } 390 391 static int 392 pci_emul_mem_handler(struct vmctx *ctx, int vcpu, int dir, uint64_t addr, 393 int size, uint64_t *val, void *arg1, long arg2) 394 { 395 struct pci_devinst *pdi = arg1; 396 struct pci_devemu *pe = pdi->pi_d; 397 uint64_t offset; 398 int bidx = (int) arg2; 399 400 assert(bidx <= PCI_BARMAX); 401 assert(pdi->pi_bar[bidx].type == PCIBAR_MEM32 || 402 pdi->pi_bar[bidx].type == PCIBAR_MEM64); 403 assert(addr >= pdi->pi_bar[bidx].addr && 404 addr + size <= pdi->pi_bar[bidx].addr + pdi->pi_bar[bidx].size); 405 406 offset = addr - pdi->pi_bar[bidx].addr; 407 408 if (dir == MEM_F_WRITE) { 409 if (size == 8) { 410 (*pe->pe_barwrite)(ctx, vcpu, pdi, bidx, offset, 411 4, *val & 0xffffffff); 412 (*pe->pe_barwrite)(ctx, vcpu, pdi, bidx, offset + 4, 413 4, *val >> 32); 414 } else { 415 (*pe->pe_barwrite)(ctx, vcpu, pdi, bidx, offset, 416 size, *val); 417 } 418 } else { 419 if (size == 8) { 420 *val = (*pe->pe_barread)(ctx, vcpu, pdi, bidx, 421 offset, 4); 422 *val |= (*pe->pe_barread)(ctx, vcpu, pdi, bidx, 423 offset + 4, 4) << 32; 424 } else { 425 *val = (*pe->pe_barread)(ctx, vcpu, pdi, bidx, 426 offset, size); 427 } 428 } 429 430 return (0); 431 } 432 433 434 static int 435 pci_emul_alloc_resource(uint64_t *baseptr, uint64_t limit, uint64_t size, 436 uint64_t *addr) 437 { 438 uint64_t base; 439 440 assert((size & (size - 1)) == 0); /* must be a power of 2 */ 441 442 base = roundup2(*baseptr, size); 443 444 if (base + size <= limit) { 445 *addr = base; 446 *baseptr = base + size; 447 return (0); 448 } else 449 return (-1); 450 } 451 452 int 453 pci_emul_alloc_bar(struct pci_devinst *pdi, int idx, enum pcibar_type type, 454 uint64_t size) 455 { 456 457 return (pci_emul_alloc_pbar(pdi, idx, 0, type, size)); 458 } 459 460 /* 461 * Register (or unregister) the MMIO or I/O region associated with the BAR 462 * register 'idx' of an emulated pci device. 463 */ 464 static void 465 modify_bar_registration(struct pci_devinst *pi, int idx, int registration) 466 { 467 int error; 468 struct inout_port iop; 469 struct mem_range mr; 470 471 switch (pi->pi_bar[idx].type) { 472 case PCIBAR_IO: 473 bzero(&iop, sizeof(struct inout_port)); 474 iop.name = pi->pi_name; 475 iop.port = pi->pi_bar[idx].addr; 476 iop.size = pi->pi_bar[idx].size; 477 if (registration) { 478 iop.flags = IOPORT_F_INOUT; 479 iop.handler = pci_emul_io_handler; 480 iop.arg = pi; 481 error = register_inout(&iop); 482 } else 483 error = unregister_inout(&iop); 484 break; 485 case PCIBAR_MEM32: 486 case PCIBAR_MEM64: 487 bzero(&mr, sizeof(struct mem_range)); 488 mr.name = pi->pi_name; 489 mr.base = pi->pi_bar[idx].addr; 490 mr.size = pi->pi_bar[idx].size; 491 if (registration) { 492 mr.flags = MEM_F_RW; 493 mr.handler = pci_emul_mem_handler; 494 mr.arg1 = pi; 495 mr.arg2 = idx; 496 error = register_mem(&mr); 497 } else 498 error = unregister_mem(&mr); 499 break; 500 default: 501 error = EINVAL; 502 break; 503 } 504 assert(error == 0); 505 } 506 507 static void 508 unregister_bar(struct pci_devinst *pi, int idx) 509 { 510 511 modify_bar_registration(pi, idx, 0); 512 } 513 514 static void 515 register_bar(struct pci_devinst *pi, int idx) 516 { 517 518 modify_bar_registration(pi, idx, 1); 519 } 520 521 /* Are we decoding i/o port accesses for the emulated pci device? */ 522 static int 523 porten(struct pci_devinst *pi) 524 { 525 uint16_t cmd; 526 527 cmd = pci_get_cfgdata16(pi, PCIR_COMMAND); 528 529 return (cmd & PCIM_CMD_PORTEN); 530 } 531 532 /* Are we decoding memory accesses for the emulated pci device? */ 533 static int 534 memen(struct pci_devinst *pi) 535 { 536 uint16_t cmd; 537 538 cmd = pci_get_cfgdata16(pi, PCIR_COMMAND); 539 540 return (cmd & PCIM_CMD_MEMEN); 541 } 542 543 /* 544 * Update the MMIO or I/O address that is decoded by the BAR register. 545 * 546 * If the pci device has enabled the address space decoding then intercept 547 * the address range decoded by the BAR register. 548 */ 549 static void 550 update_bar_address(struct pci_devinst *pi, uint64_t addr, int idx, int type) 551 { 552 int decode; 553 554 if (pi->pi_bar[idx].type == PCIBAR_IO) 555 decode = porten(pi); 556 else 557 decode = memen(pi); 558 559 if (decode) 560 unregister_bar(pi, idx); 561 562 switch (type) { 563 case PCIBAR_IO: 564 case PCIBAR_MEM32: 565 pi->pi_bar[idx].addr = addr; 566 break; 567 case PCIBAR_MEM64: 568 pi->pi_bar[idx].addr &= ~0xffffffffUL; 569 pi->pi_bar[idx].addr |= addr; 570 break; 571 case PCIBAR_MEMHI64: 572 pi->pi_bar[idx].addr &= 0xffffffff; 573 pi->pi_bar[idx].addr |= addr; 574 break; 575 default: 576 assert(0); 577 } 578 579 if (decode) 580 register_bar(pi, idx); 581 } 582 583 int 584 pci_emul_alloc_pbar(struct pci_devinst *pdi, int idx, uint64_t hostbase, 585 enum pcibar_type type, uint64_t size) 586 { 587 int error; 588 uint64_t *baseptr, limit, addr, mask, lobits, bar; 589 uint16_t cmd, enbit; 590 591 assert(idx >= 0 && idx <= PCI_BARMAX); 592 593 if ((size & (size - 1)) != 0) 594 size = 1UL << flsl(size); /* round up to a power of 2 */ 595 596 /* Enforce minimum BAR sizes required by the PCI standard */ 597 if (type == PCIBAR_IO) { 598 if (size < 4) 599 size = 4; 600 } else { 601 if (size < 16) 602 size = 16; 603 } 604 605 switch (type) { 606 case PCIBAR_NONE: 607 baseptr = NULL; 608 addr = mask = lobits = enbit = 0; 609 break; 610 case PCIBAR_IO: 611 baseptr = &pci_emul_iobase; 612 limit = PCI_EMUL_IOLIMIT; 613 mask = PCIM_BAR_IO_BASE; 614 lobits = PCIM_BAR_IO_SPACE; 615 enbit = PCIM_CMD_PORTEN; 616 break; 617 case PCIBAR_MEM64: 618 /* 619 * XXX 620 * Some drivers do not work well if the 64-bit BAR is allocated 621 * above 4GB. Allow for this by allocating small requests under 622 * 4GB unless then allocation size is larger than some arbitrary 623 * number (32MB currently). 624 */ 625 if (size > 32 * 1024 * 1024) { 626 /* 627 * XXX special case for device requiring peer-peer DMA 628 */ 629 if (size == 0x100000000UL) 630 baseptr = &hostbase; 631 else 632 baseptr = &pci_emul_membase64; 633 limit = PCI_EMUL_MEMLIMIT64; 634 mask = PCIM_BAR_MEM_BASE; 635 lobits = PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_64 | 636 PCIM_BAR_MEM_PREFETCH; 637 } else { 638 baseptr = &pci_emul_membase32; 639 limit = PCI_EMUL_MEMLIMIT32; 640 mask = PCIM_BAR_MEM_BASE; 641 lobits = PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_64; 642 } 643 enbit = PCIM_CMD_MEMEN; 644 break; 645 case PCIBAR_MEM32: 646 baseptr = &pci_emul_membase32; 647 limit = PCI_EMUL_MEMLIMIT32; 648 mask = PCIM_BAR_MEM_BASE; 649 lobits = PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_32; 650 enbit = PCIM_CMD_MEMEN; 651 break; 652 default: 653 printf("pci_emul_alloc_base: invalid bar type %d\n", type); 654 assert(0); 655 } 656 657 if (baseptr != NULL) { 658 error = pci_emul_alloc_resource(baseptr, limit, size, &addr); 659 if (error != 0) 660 return (error); 661 } 662 663 pdi->pi_bar[idx].type = type; 664 pdi->pi_bar[idx].addr = addr; 665 pdi->pi_bar[idx].size = size; 666 667 /* Initialize the BAR register in config space */ 668 bar = (addr & mask) | lobits; 669 pci_set_cfgdata32(pdi, PCIR_BAR(idx), bar); 670 671 if (type == PCIBAR_MEM64) { 672 assert(idx + 1 <= PCI_BARMAX); 673 pdi->pi_bar[idx + 1].type = PCIBAR_MEMHI64; 674 pci_set_cfgdata32(pdi, PCIR_BAR(idx + 1), bar >> 32); 675 } 676 677 cmd = pci_get_cfgdata16(pdi, PCIR_COMMAND); 678 if ((cmd & enbit) != enbit) 679 pci_set_cfgdata16(pdi, PCIR_COMMAND, cmd | enbit); 680 register_bar(pdi, idx); 681 682 return (0); 683 } 684 685 #define CAP_START_OFFSET 0x40 686 static int 687 pci_emul_add_capability(struct pci_devinst *pi, u_char *capdata, int caplen) 688 { 689 int i, capoff, reallen; 690 uint16_t sts; 691 692 assert(caplen > 0); 693 694 reallen = roundup2(caplen, 4); /* dword aligned */ 695 696 sts = pci_get_cfgdata16(pi, PCIR_STATUS); 697 if ((sts & PCIM_STATUS_CAPPRESENT) == 0) 698 capoff = CAP_START_OFFSET; 699 else 700 capoff = pi->pi_capend + 1; 701 702 /* Check if we have enough space */ 703 if (capoff + reallen > PCI_REGMAX + 1) 704 return (-1); 705 706 /* Set the previous capability pointer */ 707 if ((sts & PCIM_STATUS_CAPPRESENT) == 0) { 708 pci_set_cfgdata8(pi, PCIR_CAP_PTR, capoff); 709 pci_set_cfgdata16(pi, PCIR_STATUS, sts|PCIM_STATUS_CAPPRESENT); 710 } else 711 pci_set_cfgdata8(pi, pi->pi_prevcap + 1, capoff); 712 713 /* Copy the capability */ 714 for (i = 0; i < caplen; i++) 715 pci_set_cfgdata8(pi, capoff + i, capdata[i]); 716 717 /* Set the next capability pointer */ 718 pci_set_cfgdata8(pi, capoff + 1, 0); 719 720 pi->pi_prevcap = capoff; 721 pi->pi_capend = capoff + reallen - 1; 722 return (0); 723 } 724 725 static struct pci_devemu * 726 pci_emul_finddev(char *name) 727 { 728 struct pci_devemu **pdpp, *pdp; 729 730 SET_FOREACH(pdpp, pci_devemu_set) { 731 pdp = *pdpp; 732 if (!strcmp(pdp->pe_emu, name)) { 733 return (pdp); 734 } 735 } 736 737 return (NULL); 738 } 739 740 static int 741 pci_emul_init(struct vmctx *ctx, struct pci_devemu *pde, int bus, int slot, 742 int func, struct funcinfo *fi) 743 { 744 struct pci_devinst *pdi; 745 int err; 746 747 pdi = calloc(1, sizeof(struct pci_devinst)); 748 749 pdi->pi_vmctx = ctx; 750 pdi->pi_bus = bus; 751 pdi->pi_slot = slot; 752 pdi->pi_func = func; 753 pthread_mutex_init(&pdi->pi_lintr.lock, NULL); 754 pdi->pi_lintr.pin = 0; 755 pdi->pi_lintr.state = IDLE; 756 pdi->pi_lintr.pirq_pin = 0; 757 pdi->pi_lintr.ioapic_irq = 0; 758 pdi->pi_d = pde; 759 snprintf(pdi->pi_name, PI_NAMESZ, "%s-pci-%d", pde->pe_emu, slot); 760 761 /* Disable legacy interrupts */ 762 pci_set_cfgdata8(pdi, PCIR_INTLINE, 255); 763 pci_set_cfgdata8(pdi, PCIR_INTPIN, 0); 764 765 pci_set_cfgdata8(pdi, PCIR_COMMAND, PCIM_CMD_BUSMASTEREN); 766 767 err = (*pde->pe_init)(ctx, pdi, fi->fi_param); 768 if (err == 0) 769 fi->fi_devi = pdi; 770 else 771 free(pdi); 772 773 return (err); 774 } 775 776 void 777 pci_populate_msicap(struct msicap *msicap, int msgnum, int nextptr) 778 { 779 int mmc; 780 781 /* Number of msi messages must be a power of 2 between 1 and 32 */ 782 assert((msgnum & (msgnum - 1)) == 0 && msgnum >= 1 && msgnum <= 32); 783 mmc = ffs(msgnum) - 1; 784 785 bzero(msicap, sizeof(struct msicap)); 786 msicap->capid = PCIY_MSI; 787 msicap->nextptr = nextptr; 788 msicap->msgctrl = PCIM_MSICTRL_64BIT | (mmc << 1); 789 } 790 791 int 792 pci_emul_add_msicap(struct pci_devinst *pi, int msgnum) 793 { 794 struct msicap msicap; 795 796 pci_populate_msicap(&msicap, msgnum, 0); 797 798 return (pci_emul_add_capability(pi, (u_char *)&msicap, sizeof(msicap))); 799 } 800 801 static void 802 pci_populate_msixcap(struct msixcap *msixcap, int msgnum, int barnum, 803 uint32_t msix_tab_size) 804 { 805 806 assert(msix_tab_size % 4096 == 0); 807 808 bzero(msixcap, sizeof(struct msixcap)); 809 msixcap->capid = PCIY_MSIX; 810 811 /* 812 * Message Control Register, all fields set to 813 * zero except for the Table Size. 814 * Note: Table size N is encoded as N-1 815 */ 816 msixcap->msgctrl = msgnum - 1; 817 818 /* 819 * MSI-X BAR setup: 820 * - MSI-X table start at offset 0 821 * - PBA table starts at a 4K aligned offset after the MSI-X table 822 */ 823 msixcap->table_info = barnum & PCIM_MSIX_BIR_MASK; 824 msixcap->pba_info = msix_tab_size | (barnum & PCIM_MSIX_BIR_MASK); 825 } 826 827 static void 828 pci_msix_table_init(struct pci_devinst *pi, int table_entries) 829 { 830 int i, table_size; 831 832 assert(table_entries > 0); 833 assert(table_entries <= MAX_MSIX_TABLE_ENTRIES); 834 835 table_size = table_entries * MSIX_TABLE_ENTRY_SIZE; 836 pi->pi_msix.table = calloc(1, table_size); 837 838 /* set mask bit of vector control register */ 839 for (i = 0; i < table_entries; i++) 840 pi->pi_msix.table[i].vector_control |= PCIM_MSIX_VCTRL_MASK; 841 } 842 843 int 844 pci_emul_add_msixcap(struct pci_devinst *pi, int msgnum, int barnum) 845 { 846 uint32_t tab_size; 847 struct msixcap msixcap; 848 849 assert(msgnum >= 1 && msgnum <= MAX_MSIX_TABLE_ENTRIES); 850 assert(barnum >= 0 && barnum <= PCIR_MAX_BAR_0); 851 852 tab_size = msgnum * MSIX_TABLE_ENTRY_SIZE; 853 854 /* Align table size to nearest 4K */ 855 tab_size = roundup2(tab_size, 4096); 856 857 pi->pi_msix.table_bar = barnum; 858 pi->pi_msix.pba_bar = barnum; 859 pi->pi_msix.table_offset = 0; 860 pi->pi_msix.table_count = msgnum; 861 pi->pi_msix.pba_offset = tab_size; 862 pi->pi_msix.pba_size = PBA_SIZE(msgnum); 863 864 pci_msix_table_init(pi, msgnum); 865 866 pci_populate_msixcap(&msixcap, msgnum, barnum, tab_size); 867 868 /* allocate memory for MSI-X Table and PBA */ 869 pci_emul_alloc_bar(pi, barnum, PCIBAR_MEM32, 870 tab_size + pi->pi_msix.pba_size); 871 872 return (pci_emul_add_capability(pi, (u_char *)&msixcap, 873 sizeof(msixcap))); 874 } 875 876 void 877 msixcap_cfgwrite(struct pci_devinst *pi, int capoff, int offset, 878 int bytes, uint32_t val) 879 { 880 uint16_t msgctrl, rwmask; 881 int off; 882 883 off = offset - capoff; 884 /* Message Control Register */ 885 if (off == 2 && bytes == 2) { 886 rwmask = PCIM_MSIXCTRL_MSIX_ENABLE | PCIM_MSIXCTRL_FUNCTION_MASK; 887 msgctrl = pci_get_cfgdata16(pi, offset); 888 msgctrl &= ~rwmask; 889 msgctrl |= val & rwmask; 890 val = msgctrl; 891 892 pi->pi_msix.enabled = val & PCIM_MSIXCTRL_MSIX_ENABLE; 893 pi->pi_msix.function_mask = val & PCIM_MSIXCTRL_FUNCTION_MASK; 894 pci_lintr_update(pi); 895 } 896 897 CFGWRITE(pi, offset, val, bytes); 898 } 899 900 void 901 msicap_cfgwrite(struct pci_devinst *pi, int capoff, int offset, 902 int bytes, uint32_t val) 903 { 904 uint16_t msgctrl, rwmask, msgdata, mme; 905 uint32_t addrlo; 906 907 /* 908 * If guest is writing to the message control register make sure 909 * we do not overwrite read-only fields. 910 */ 911 if ((offset - capoff) == 2 && bytes == 2) { 912 rwmask = PCIM_MSICTRL_MME_MASK | PCIM_MSICTRL_MSI_ENABLE; 913 msgctrl = pci_get_cfgdata16(pi, offset); 914 msgctrl &= ~rwmask; 915 msgctrl |= val & rwmask; 916 val = msgctrl; 917 918 addrlo = pci_get_cfgdata32(pi, capoff + 4); 919 if (msgctrl & PCIM_MSICTRL_64BIT) 920 msgdata = pci_get_cfgdata16(pi, capoff + 12); 921 else 922 msgdata = pci_get_cfgdata16(pi, capoff + 8); 923 924 mme = msgctrl & PCIM_MSICTRL_MME_MASK; 925 pi->pi_msi.enabled = msgctrl & PCIM_MSICTRL_MSI_ENABLE ? 1 : 0; 926 if (pi->pi_msi.enabled) { 927 pi->pi_msi.addr = addrlo; 928 pi->pi_msi.msg_data = msgdata; 929 pi->pi_msi.maxmsgnum = 1 << (mme >> 4); 930 } else { 931 pi->pi_msi.maxmsgnum = 0; 932 } 933 pci_lintr_update(pi); 934 } 935 936 CFGWRITE(pi, offset, val, bytes); 937 } 938 939 void 940 pciecap_cfgwrite(struct pci_devinst *pi, int capoff, int offset, 941 int bytes, uint32_t val) 942 { 943 944 /* XXX don't write to the readonly parts */ 945 CFGWRITE(pi, offset, val, bytes); 946 } 947 948 #define PCIECAP_VERSION 0x2 949 int 950 pci_emul_add_pciecap(struct pci_devinst *pi, int type) 951 { 952 int err; 953 struct pciecap pciecap; 954 955 bzero(&pciecap, sizeof(pciecap)); 956 957 /* 958 * Use the integrated endpoint type for endpoints on a root complex bus. 959 * 960 * NB: bhyve currently only supports a single PCI bus that is the root 961 * complex bus, so all endpoints are integrated. 962 */ 963 if ((type == PCIEM_TYPE_ENDPOINT) && (pi->pi_bus == 0)) 964 type = PCIEM_TYPE_ROOT_INT_EP; 965 966 pciecap.capid = PCIY_EXPRESS; 967 pciecap.pcie_capabilities = PCIECAP_VERSION | type; 968 if (type != PCIEM_TYPE_ROOT_INT_EP) { 969 pciecap.link_capabilities = 0x411; /* gen1, x1 */ 970 pciecap.link_status = 0x11; /* gen1, x1 */ 971 } 972 973 err = pci_emul_add_capability(pi, (u_char *)&pciecap, sizeof(pciecap)); 974 return (err); 975 } 976 977 /* 978 * This function assumes that 'coff' is in the capabilities region of the 979 * config space. 980 */ 981 static void 982 pci_emul_capwrite(struct pci_devinst *pi, int offset, int bytes, uint32_t val) 983 { 984 int capid; 985 uint8_t capoff, nextoff; 986 987 /* Do not allow un-aligned writes */ 988 if ((offset & (bytes - 1)) != 0) 989 return; 990 991 /* Find the capability that we want to update */ 992 capoff = CAP_START_OFFSET; 993 while (1) { 994 nextoff = pci_get_cfgdata8(pi, capoff + 1); 995 if (nextoff == 0) 996 break; 997 if (offset >= capoff && offset < nextoff) 998 break; 999 1000 capoff = nextoff; 1001 } 1002 assert(offset >= capoff); 1003 1004 /* 1005 * Capability ID and Next Capability Pointer are readonly. 1006 * However, some o/s's do 4-byte writes that include these. 1007 * For this case, trim the write back to 2 bytes and adjust 1008 * the data. 1009 */ 1010 if (offset == capoff || offset == capoff + 1) { 1011 if (offset == capoff && bytes == 4) { 1012 bytes = 2; 1013 offset += 2; 1014 val >>= 16; 1015 } else 1016 return; 1017 } 1018 1019 capid = pci_get_cfgdata8(pi, capoff); 1020 switch (capid) { 1021 case PCIY_MSI: 1022 msicap_cfgwrite(pi, capoff, offset, bytes, val); 1023 break; 1024 case PCIY_MSIX: 1025 msixcap_cfgwrite(pi, capoff, offset, bytes, val); 1026 break; 1027 case PCIY_EXPRESS: 1028 pciecap_cfgwrite(pi, capoff, offset, bytes, val); 1029 break; 1030 default: 1031 break; 1032 } 1033 } 1034 1035 static int 1036 pci_emul_iscap(struct pci_devinst *pi, int offset) 1037 { 1038 uint16_t sts; 1039 1040 sts = pci_get_cfgdata16(pi, PCIR_STATUS); 1041 if ((sts & PCIM_STATUS_CAPPRESENT) != 0) { 1042 if (offset >= CAP_START_OFFSET && offset <= pi->pi_capend) 1043 return (1); 1044 } 1045 return (0); 1046 } 1047 1048 static int 1049 pci_emul_fallback_handler(struct vmctx *ctx, int vcpu, int dir, uint64_t addr, 1050 int size, uint64_t *val, void *arg1, long arg2) 1051 { 1052 /* 1053 * Ignore writes; return 0xff's for reads. The mem read code 1054 * will take care of truncating to the correct size. 1055 */ 1056 if (dir == MEM_F_READ) { 1057 *val = 0xffffffffffffffff; 1058 } 1059 1060 return (0); 1061 } 1062 1063 static int 1064 pci_emul_ecfg_handler(struct vmctx *ctx, int vcpu, int dir, uint64_t addr, 1065 int bytes, uint64_t *val, void *arg1, long arg2) 1066 { 1067 int bus, slot, func, coff, in; 1068 1069 coff = addr & 0xfff; 1070 func = (addr >> 12) & 0x7; 1071 slot = (addr >> 15) & 0x1f; 1072 bus = (addr >> 20) & 0xff; 1073 in = (dir == MEM_F_READ); 1074 if (in) 1075 *val = ~0UL; 1076 pci_cfgrw(ctx, vcpu, in, bus, slot, func, coff, bytes, (uint32_t *)val); 1077 return (0); 1078 } 1079 1080 uint64_t 1081 pci_ecfg_base(void) 1082 { 1083 1084 return (PCI_EMUL_ECFG_BASE); 1085 } 1086 1087 #define BUSIO_ROUNDUP 32 1088 #define BUSMEM_ROUNDUP (1024 * 1024) 1089 1090 int 1091 init_pci(struct vmctx *ctx) 1092 { 1093 struct mem_range mr; 1094 struct pci_devemu *pde; 1095 struct businfo *bi; 1096 struct slotinfo *si; 1097 struct funcinfo *fi; 1098 size_t lowmem; 1099 int bus, slot, func; 1100 int error; 1101 1102 pci_emul_iobase = PCI_EMUL_IOBASE; 1103 pci_emul_membase32 = vm_get_lowmem_limit(ctx); 1104 pci_emul_membase64 = PCI_EMUL_MEMBASE64; 1105 1106 for (bus = 0; bus < MAXBUSES; bus++) { 1107 if ((bi = pci_businfo[bus]) == NULL) 1108 continue; 1109 /* 1110 * Keep track of the i/o and memory resources allocated to 1111 * this bus. 1112 */ 1113 bi->iobase = pci_emul_iobase; 1114 bi->membase32 = pci_emul_membase32; 1115 bi->membase64 = pci_emul_membase64; 1116 1117 for (slot = 0; slot < MAXSLOTS; slot++) { 1118 si = &bi->slotinfo[slot]; 1119 for (func = 0; func < MAXFUNCS; func++) { 1120 fi = &si->si_funcs[func]; 1121 if (fi->fi_name == NULL) 1122 continue; 1123 pde = pci_emul_finddev(fi->fi_name); 1124 assert(pde != NULL); 1125 error = pci_emul_init(ctx, pde, bus, slot, 1126 func, fi); 1127 if (error) 1128 return (error); 1129 } 1130 } 1131 1132 /* 1133 * Add some slop to the I/O and memory resources decoded by 1134 * this bus to give a guest some flexibility if it wants to 1135 * reprogram the BARs. 1136 */ 1137 pci_emul_iobase += BUSIO_ROUNDUP; 1138 pci_emul_iobase = roundup2(pci_emul_iobase, BUSIO_ROUNDUP); 1139 bi->iolimit = pci_emul_iobase; 1140 1141 pci_emul_membase32 += BUSMEM_ROUNDUP; 1142 pci_emul_membase32 = roundup2(pci_emul_membase32, 1143 BUSMEM_ROUNDUP); 1144 bi->memlimit32 = pci_emul_membase32; 1145 1146 pci_emul_membase64 += BUSMEM_ROUNDUP; 1147 pci_emul_membase64 = roundup2(pci_emul_membase64, 1148 BUSMEM_ROUNDUP); 1149 bi->memlimit64 = pci_emul_membase64; 1150 } 1151 1152 /* 1153 * PCI backends are initialized before routing INTx interrupts 1154 * so that LPC devices are able to reserve ISA IRQs before 1155 * routing PIRQ pins. 1156 */ 1157 for (bus = 0; bus < MAXBUSES; bus++) { 1158 if ((bi = pci_businfo[bus]) == NULL) 1159 continue; 1160 1161 for (slot = 0; slot < MAXSLOTS; slot++) { 1162 si = &bi->slotinfo[slot]; 1163 for (func = 0; func < MAXFUNCS; func++) { 1164 fi = &si->si_funcs[func]; 1165 if (fi->fi_devi == NULL) 1166 continue; 1167 pci_lintr_route(fi->fi_devi); 1168 } 1169 } 1170 } 1171 lpc_pirq_routed(); 1172 1173 /* 1174 * The guest physical memory map looks like the following: 1175 * [0, lowmem) guest system memory 1176 * [lowmem, lowmem_limit) memory hole (may be absent) 1177 * [lowmem_limit, 0xE0000000) PCI hole (32-bit BAR allocation) 1178 * [0xE0000000, 0xF0000000) PCI extended config window 1179 * [0xF0000000, 4GB) LAPIC, IOAPIC, HPET, firmware 1180 * [4GB, 4GB + highmem) 1181 */ 1182 1183 /* 1184 * Accesses to memory addresses that are not allocated to system 1185 * memory or PCI devices return 0xff's. 1186 */ 1187 lowmem = vm_get_lowmem_size(ctx); 1188 bzero(&mr, sizeof(struct mem_range)); 1189 mr.name = "PCI hole"; 1190 mr.flags = MEM_F_RW | MEM_F_IMMUTABLE; 1191 mr.base = lowmem; 1192 mr.size = (4ULL * 1024 * 1024 * 1024) - lowmem; 1193 mr.handler = pci_emul_fallback_handler; 1194 error = register_mem_fallback(&mr); 1195 assert(error == 0); 1196 1197 /* PCI extended config space */ 1198 bzero(&mr, sizeof(struct mem_range)); 1199 mr.name = "PCI ECFG"; 1200 mr.flags = MEM_F_RW | MEM_F_IMMUTABLE; 1201 mr.base = PCI_EMUL_ECFG_BASE; 1202 mr.size = PCI_EMUL_ECFG_SIZE; 1203 mr.handler = pci_emul_ecfg_handler; 1204 error = register_mem(&mr); 1205 assert(error == 0); 1206 1207 return (0); 1208 } 1209 1210 static void 1211 pci_apic_prt_entry(int bus, int slot, int pin, int pirq_pin, int ioapic_irq, 1212 void *arg) 1213 { 1214 1215 dsdt_line(" Package ()"); 1216 dsdt_line(" {"); 1217 dsdt_line(" 0x%X,", slot << 16 | 0xffff); 1218 dsdt_line(" 0x%02X,", pin - 1); 1219 dsdt_line(" Zero,"); 1220 dsdt_line(" 0x%X", ioapic_irq); 1221 dsdt_line(" },"); 1222 } 1223 1224 static void 1225 pci_pirq_prt_entry(int bus, int slot, int pin, int pirq_pin, int ioapic_irq, 1226 void *arg) 1227 { 1228 char *name; 1229 1230 name = lpc_pirq_name(pirq_pin); 1231 if (name == NULL) 1232 return; 1233 dsdt_line(" Package ()"); 1234 dsdt_line(" {"); 1235 dsdt_line(" 0x%X,", slot << 16 | 0xffff); 1236 dsdt_line(" 0x%02X,", pin - 1); 1237 dsdt_line(" %s,", name); 1238 dsdt_line(" 0x00"); 1239 dsdt_line(" },"); 1240 free(name); 1241 } 1242 1243 /* 1244 * A bhyve virtual machine has a flat PCI hierarchy with a root port 1245 * corresponding to each PCI bus. 1246 */ 1247 static void 1248 pci_bus_write_dsdt(int bus) 1249 { 1250 struct businfo *bi; 1251 struct slotinfo *si; 1252 struct pci_devinst *pi; 1253 int count, func, slot; 1254 1255 /* 1256 * If there are no devices on this 'bus' then just return. 1257 */ 1258 if ((bi = pci_businfo[bus]) == NULL) { 1259 /* 1260 * Bus 0 is special because it decodes the I/O ports used 1261 * for PCI config space access even if there are no devices 1262 * on it. 1263 */ 1264 if (bus != 0) 1265 return; 1266 } 1267 1268 dsdt_line(" Device (PC%02X)", bus); 1269 dsdt_line(" {"); 1270 dsdt_line(" Name (_HID, EisaId (\"PNP0A03\"))"); 1271 1272 dsdt_line(" Method (_BBN, 0, NotSerialized)"); 1273 dsdt_line(" {"); 1274 dsdt_line(" Return (0x%08X)", bus); 1275 dsdt_line(" }"); 1276 dsdt_line(" Name (_CRS, ResourceTemplate ()"); 1277 dsdt_line(" {"); 1278 dsdt_line(" WordBusNumber (ResourceProducer, MinFixed, " 1279 "MaxFixed, PosDecode,"); 1280 dsdt_line(" 0x0000, // Granularity"); 1281 dsdt_line(" 0x%04X, // Range Minimum", bus); 1282 dsdt_line(" 0x%04X, // Range Maximum", bus); 1283 dsdt_line(" 0x0000, // Translation Offset"); 1284 dsdt_line(" 0x0001, // Length"); 1285 dsdt_line(" ,, )"); 1286 1287 if (bus == 0) { 1288 dsdt_indent(3); 1289 dsdt_fixed_ioport(0xCF8, 8); 1290 dsdt_unindent(3); 1291 1292 dsdt_line(" WordIO (ResourceProducer, MinFixed, MaxFixed, " 1293 "PosDecode, EntireRange,"); 1294 dsdt_line(" 0x0000, // Granularity"); 1295 dsdt_line(" 0x0000, // Range Minimum"); 1296 dsdt_line(" 0x0CF7, // Range Maximum"); 1297 dsdt_line(" 0x0000, // Translation Offset"); 1298 dsdt_line(" 0x0CF8, // Length"); 1299 dsdt_line(" ,, , TypeStatic)"); 1300 1301 dsdt_line(" WordIO (ResourceProducer, MinFixed, MaxFixed, " 1302 "PosDecode, EntireRange,"); 1303 dsdt_line(" 0x0000, // Granularity"); 1304 dsdt_line(" 0x0D00, // Range Minimum"); 1305 dsdt_line(" 0x%04X, // Range Maximum", 1306 PCI_EMUL_IOBASE - 1); 1307 dsdt_line(" 0x0000, // Translation Offset"); 1308 dsdt_line(" 0x%04X, // Length", 1309 PCI_EMUL_IOBASE - 0x0D00); 1310 dsdt_line(" ,, , TypeStatic)"); 1311 1312 if (bi == NULL) { 1313 dsdt_line(" })"); 1314 goto done; 1315 } 1316 } 1317 assert(bi != NULL); 1318 1319 /* i/o window */ 1320 dsdt_line(" WordIO (ResourceProducer, MinFixed, MaxFixed, " 1321 "PosDecode, EntireRange,"); 1322 dsdt_line(" 0x0000, // Granularity"); 1323 dsdt_line(" 0x%04X, // Range Minimum", bi->iobase); 1324 dsdt_line(" 0x%04X, // Range Maximum", 1325 bi->iolimit - 1); 1326 dsdt_line(" 0x0000, // Translation Offset"); 1327 dsdt_line(" 0x%04X, // Length", 1328 bi->iolimit - bi->iobase); 1329 dsdt_line(" ,, , TypeStatic)"); 1330 1331 /* mmio window (32-bit) */ 1332 dsdt_line(" DWordMemory (ResourceProducer, PosDecode, " 1333 "MinFixed, MaxFixed, NonCacheable, ReadWrite,"); 1334 dsdt_line(" 0x00000000, // Granularity"); 1335 dsdt_line(" 0x%08X, // Range Minimum\n", bi->membase32); 1336 dsdt_line(" 0x%08X, // Range Maximum\n", 1337 bi->memlimit32 - 1); 1338 dsdt_line(" 0x00000000, // Translation Offset"); 1339 dsdt_line(" 0x%08X, // Length\n", 1340 bi->memlimit32 - bi->membase32); 1341 dsdt_line(" ,, , AddressRangeMemory, TypeStatic)"); 1342 1343 /* mmio window (64-bit) */ 1344 dsdt_line(" QWordMemory (ResourceProducer, PosDecode, " 1345 "MinFixed, MaxFixed, NonCacheable, ReadWrite,"); 1346 dsdt_line(" 0x0000000000000000, // Granularity"); 1347 dsdt_line(" 0x%016lX, // Range Minimum\n", bi->membase64); 1348 dsdt_line(" 0x%016lX, // Range Maximum\n", 1349 bi->memlimit64 - 1); 1350 dsdt_line(" 0x0000000000000000, // Translation Offset"); 1351 dsdt_line(" 0x%016lX, // Length\n", 1352 bi->memlimit64 - bi->membase64); 1353 dsdt_line(" ,, , AddressRangeMemory, TypeStatic)"); 1354 dsdt_line(" })"); 1355 1356 count = pci_count_lintr(bus); 1357 if (count != 0) { 1358 dsdt_indent(2); 1359 dsdt_line("Name (PPRT, Package ()"); 1360 dsdt_line("{"); 1361 pci_walk_lintr(bus, pci_pirq_prt_entry, NULL); 1362 dsdt_line("})"); 1363 dsdt_line("Name (APRT, Package ()"); 1364 dsdt_line("{"); 1365 pci_walk_lintr(bus, pci_apic_prt_entry, NULL); 1366 dsdt_line("})"); 1367 dsdt_line("Method (_PRT, 0, NotSerialized)"); 1368 dsdt_line("{"); 1369 dsdt_line(" If (PICM)"); 1370 dsdt_line(" {"); 1371 dsdt_line(" Return (APRT)"); 1372 dsdt_line(" }"); 1373 dsdt_line(" Else"); 1374 dsdt_line(" {"); 1375 dsdt_line(" Return (PPRT)"); 1376 dsdt_line(" }"); 1377 dsdt_line("}"); 1378 dsdt_unindent(2); 1379 } 1380 1381 dsdt_indent(2); 1382 for (slot = 0; slot < MAXSLOTS; slot++) { 1383 si = &bi->slotinfo[slot]; 1384 for (func = 0; func < MAXFUNCS; func++) { 1385 pi = si->si_funcs[func].fi_devi; 1386 if (pi != NULL && pi->pi_d->pe_write_dsdt != NULL) 1387 pi->pi_d->pe_write_dsdt(pi); 1388 } 1389 } 1390 dsdt_unindent(2); 1391 done: 1392 dsdt_line(" }"); 1393 } 1394 1395 void 1396 pci_write_dsdt(void) 1397 { 1398 int bus; 1399 1400 dsdt_indent(1); 1401 dsdt_line("Name (PICM, 0x00)"); 1402 dsdt_line("Method (_PIC, 1, NotSerialized)"); 1403 dsdt_line("{"); 1404 dsdt_line(" Store (Arg0, PICM)"); 1405 dsdt_line("}"); 1406 dsdt_line(""); 1407 dsdt_line("Scope (_SB)"); 1408 dsdt_line("{"); 1409 for (bus = 0; bus < MAXBUSES; bus++) 1410 pci_bus_write_dsdt(bus); 1411 dsdt_line("}"); 1412 dsdt_unindent(1); 1413 } 1414 1415 int 1416 pci_bus_configured(int bus) 1417 { 1418 assert(bus >= 0 && bus < MAXBUSES); 1419 return (pci_businfo[bus] != NULL); 1420 } 1421 1422 int 1423 pci_msi_enabled(struct pci_devinst *pi) 1424 { 1425 return (pi->pi_msi.enabled); 1426 } 1427 1428 int 1429 pci_msi_maxmsgnum(struct pci_devinst *pi) 1430 { 1431 if (pi->pi_msi.enabled) 1432 return (pi->pi_msi.maxmsgnum); 1433 else 1434 return (0); 1435 } 1436 1437 int 1438 pci_msix_enabled(struct pci_devinst *pi) 1439 { 1440 1441 return (pi->pi_msix.enabled && !pi->pi_msi.enabled); 1442 } 1443 1444 void 1445 pci_generate_msix(struct pci_devinst *pi, int index) 1446 { 1447 struct msix_table_entry *mte; 1448 1449 if (!pci_msix_enabled(pi)) 1450 return; 1451 1452 if (pi->pi_msix.function_mask) 1453 return; 1454 1455 if (index >= pi->pi_msix.table_count) 1456 return; 1457 1458 mte = &pi->pi_msix.table[index]; 1459 if ((mte->vector_control & PCIM_MSIX_VCTRL_MASK) == 0) { 1460 /* XXX Set PBA bit if interrupt is disabled */ 1461 vm_lapic_msi(pi->pi_vmctx, mte->addr, mte->msg_data); 1462 } 1463 } 1464 1465 void 1466 pci_generate_msi(struct pci_devinst *pi, int index) 1467 { 1468 1469 if (pci_msi_enabled(pi) && index < pci_msi_maxmsgnum(pi)) { 1470 vm_lapic_msi(pi->pi_vmctx, pi->pi_msi.addr, 1471 pi->pi_msi.msg_data + index); 1472 } 1473 } 1474 1475 static bool 1476 pci_lintr_permitted(struct pci_devinst *pi) 1477 { 1478 uint16_t cmd; 1479 1480 cmd = pci_get_cfgdata16(pi, PCIR_COMMAND); 1481 return (!(pi->pi_msi.enabled || pi->pi_msix.enabled || 1482 (cmd & PCIM_CMD_INTxDIS))); 1483 } 1484 1485 void 1486 pci_lintr_request(struct pci_devinst *pi) 1487 { 1488 struct businfo *bi; 1489 struct slotinfo *si; 1490 int bestpin, bestcount, pin; 1491 1492 bi = pci_businfo[pi->pi_bus]; 1493 assert(bi != NULL); 1494 1495 /* 1496 * Just allocate a pin from our slot. The pin will be 1497 * assigned IRQs later when interrupts are routed. 1498 */ 1499 si = &bi->slotinfo[pi->pi_slot]; 1500 bestpin = 0; 1501 bestcount = si->si_intpins[0].ii_count; 1502 for (pin = 1; pin < 4; pin++) { 1503 if (si->si_intpins[pin].ii_count < bestcount) { 1504 bestpin = pin; 1505 bestcount = si->si_intpins[pin].ii_count; 1506 } 1507 } 1508 1509 si->si_intpins[bestpin].ii_count++; 1510 pi->pi_lintr.pin = bestpin + 1; 1511 pci_set_cfgdata8(pi, PCIR_INTPIN, bestpin + 1); 1512 } 1513 1514 static void 1515 pci_lintr_route(struct pci_devinst *pi) 1516 { 1517 struct businfo *bi; 1518 struct intxinfo *ii; 1519 1520 if (pi->pi_lintr.pin == 0) 1521 return; 1522 1523 bi = pci_businfo[pi->pi_bus]; 1524 assert(bi != NULL); 1525 ii = &bi->slotinfo[pi->pi_slot].si_intpins[pi->pi_lintr.pin - 1]; 1526 1527 /* 1528 * Attempt to allocate an I/O APIC pin for this intpin if one 1529 * is not yet assigned. 1530 */ 1531 if (ii->ii_ioapic_irq == 0) 1532 ii->ii_ioapic_irq = ioapic_pci_alloc_irq(pi); 1533 assert(ii->ii_ioapic_irq > 0); 1534 1535 /* 1536 * Attempt to allocate a PIRQ pin for this intpin if one is 1537 * not yet assigned. 1538 */ 1539 if (ii->ii_pirq_pin == 0) 1540 ii->ii_pirq_pin = pirq_alloc_pin(pi); 1541 assert(ii->ii_pirq_pin > 0); 1542 1543 pi->pi_lintr.ioapic_irq = ii->ii_ioapic_irq; 1544 pi->pi_lintr.pirq_pin = ii->ii_pirq_pin; 1545 pci_set_cfgdata8(pi, PCIR_INTLINE, pirq_irq(ii->ii_pirq_pin)); 1546 } 1547 1548 void 1549 pci_lintr_assert(struct pci_devinst *pi) 1550 { 1551 1552 assert(pi->pi_lintr.pin > 0); 1553 1554 pthread_mutex_lock(&pi->pi_lintr.lock); 1555 if (pi->pi_lintr.state == IDLE) { 1556 if (pci_lintr_permitted(pi)) { 1557 pi->pi_lintr.state = ASSERTED; 1558 pci_irq_assert(pi); 1559 } else 1560 pi->pi_lintr.state = PENDING; 1561 } 1562 pthread_mutex_unlock(&pi->pi_lintr.lock); 1563 } 1564 1565 void 1566 pci_lintr_deassert(struct pci_devinst *pi) 1567 { 1568 1569 assert(pi->pi_lintr.pin > 0); 1570 1571 pthread_mutex_lock(&pi->pi_lintr.lock); 1572 if (pi->pi_lintr.state == ASSERTED) { 1573 pi->pi_lintr.state = IDLE; 1574 pci_irq_deassert(pi); 1575 } else if (pi->pi_lintr.state == PENDING) 1576 pi->pi_lintr.state = IDLE; 1577 pthread_mutex_unlock(&pi->pi_lintr.lock); 1578 } 1579 1580 static void 1581 pci_lintr_update(struct pci_devinst *pi) 1582 { 1583 1584 pthread_mutex_lock(&pi->pi_lintr.lock); 1585 if (pi->pi_lintr.state == ASSERTED && !pci_lintr_permitted(pi)) { 1586 pci_irq_deassert(pi); 1587 pi->pi_lintr.state = PENDING; 1588 } else if (pi->pi_lintr.state == PENDING && pci_lintr_permitted(pi)) { 1589 pi->pi_lintr.state = ASSERTED; 1590 pci_irq_assert(pi); 1591 } 1592 pthread_mutex_unlock(&pi->pi_lintr.lock); 1593 } 1594 1595 int 1596 pci_count_lintr(int bus) 1597 { 1598 int count, slot, pin; 1599 struct slotinfo *slotinfo; 1600 1601 count = 0; 1602 if (pci_businfo[bus] != NULL) { 1603 for (slot = 0; slot < MAXSLOTS; slot++) { 1604 slotinfo = &pci_businfo[bus]->slotinfo[slot]; 1605 for (pin = 0; pin < 4; pin++) { 1606 if (slotinfo->si_intpins[pin].ii_count != 0) 1607 count++; 1608 } 1609 } 1610 } 1611 return (count); 1612 } 1613 1614 void 1615 pci_walk_lintr(int bus, pci_lintr_cb cb, void *arg) 1616 { 1617 struct businfo *bi; 1618 struct slotinfo *si; 1619 struct intxinfo *ii; 1620 int slot, pin; 1621 1622 if ((bi = pci_businfo[bus]) == NULL) 1623 return; 1624 1625 for (slot = 0; slot < MAXSLOTS; slot++) { 1626 si = &bi->slotinfo[slot]; 1627 for (pin = 0; pin < 4; pin++) { 1628 ii = &si->si_intpins[pin]; 1629 if (ii->ii_count != 0) 1630 cb(bus, slot, pin + 1, ii->ii_pirq_pin, 1631 ii->ii_ioapic_irq, arg); 1632 } 1633 } 1634 } 1635 1636 /* 1637 * Return 1 if the emulated device in 'slot' is a multi-function device. 1638 * Return 0 otherwise. 1639 */ 1640 static int 1641 pci_emul_is_mfdev(int bus, int slot) 1642 { 1643 struct businfo *bi; 1644 struct slotinfo *si; 1645 int f, numfuncs; 1646 1647 numfuncs = 0; 1648 if ((bi = pci_businfo[bus]) != NULL) { 1649 si = &bi->slotinfo[slot]; 1650 for (f = 0; f < MAXFUNCS; f++) { 1651 if (si->si_funcs[f].fi_devi != NULL) { 1652 numfuncs++; 1653 } 1654 } 1655 } 1656 return (numfuncs > 1); 1657 } 1658 1659 /* 1660 * Ensure that the PCIM_MFDEV bit is properly set (or unset) depending on 1661 * whether or not is a multi-function being emulated in the pci 'slot'. 1662 */ 1663 static void 1664 pci_emul_hdrtype_fixup(int bus, int slot, int off, int bytes, uint32_t *rv) 1665 { 1666 int mfdev; 1667 1668 if (off <= PCIR_HDRTYPE && off + bytes > PCIR_HDRTYPE) { 1669 mfdev = pci_emul_is_mfdev(bus, slot); 1670 switch (bytes) { 1671 case 1: 1672 case 2: 1673 *rv &= ~PCIM_MFDEV; 1674 if (mfdev) { 1675 *rv |= PCIM_MFDEV; 1676 } 1677 break; 1678 case 4: 1679 *rv &= ~(PCIM_MFDEV << 16); 1680 if (mfdev) { 1681 *rv |= (PCIM_MFDEV << 16); 1682 } 1683 break; 1684 } 1685 } 1686 } 1687 1688 /* 1689 * Update device state in response to changes to the PCI command 1690 * register. 1691 */ 1692 void 1693 pci_emul_cmd_changed(struct pci_devinst *pi, uint16_t old) 1694 { 1695 int i; 1696 uint16_t changed, new; 1697 1698 new = pci_get_cfgdata16(pi, PCIR_COMMAND); 1699 changed = old ^ new; 1700 1701 /* 1702 * If the MMIO or I/O address space decoding has changed then 1703 * register/unregister all BARs that decode that address space. 1704 */ 1705 for (i = 0; i <= PCI_BARMAX; i++) { 1706 switch (pi->pi_bar[i].type) { 1707 case PCIBAR_NONE: 1708 case PCIBAR_MEMHI64: 1709 break; 1710 case PCIBAR_IO: 1711 /* I/O address space decoding changed? */ 1712 if (changed & PCIM_CMD_PORTEN) { 1713 if (new & PCIM_CMD_PORTEN) 1714 register_bar(pi, i); 1715 else 1716 unregister_bar(pi, i); 1717 } 1718 break; 1719 case PCIBAR_MEM32: 1720 case PCIBAR_MEM64: 1721 /* MMIO address space decoding changed? */ 1722 if (changed & PCIM_CMD_MEMEN) { 1723 if (new & PCIM_CMD_MEMEN) 1724 register_bar(pi, i); 1725 else 1726 unregister_bar(pi, i); 1727 } 1728 break; 1729 default: 1730 assert(0); 1731 } 1732 } 1733 1734 /* 1735 * If INTx has been unmasked and is pending, assert the 1736 * interrupt. 1737 */ 1738 pci_lintr_update(pi); 1739 } 1740 1741 static void 1742 pci_emul_cmdsts_write(struct pci_devinst *pi, int coff, uint32_t new, int bytes) 1743 { 1744 int rshift; 1745 uint32_t cmd, old, readonly; 1746 1747 cmd = pci_get_cfgdata16(pi, PCIR_COMMAND); /* stash old value */ 1748 1749 /* 1750 * From PCI Local Bus Specification 3.0 sections 6.2.2 and 6.2.3. 1751 * 1752 * XXX Bits 8, 11, 12, 13, 14 and 15 in the status register are 1753 * 'write 1 to clear'. However these bits are not set to '1' by 1754 * any device emulation so it is simpler to treat them as readonly. 1755 */ 1756 rshift = (coff & 0x3) * 8; 1757 readonly = 0xFFFFF880 >> rshift; 1758 1759 old = CFGREAD(pi, coff, bytes); 1760 new &= ~readonly; 1761 new |= (old & readonly); 1762 CFGWRITE(pi, coff, new, bytes); /* update config */ 1763 1764 pci_emul_cmd_changed(pi, cmd); 1765 } 1766 1767 static void 1768 pci_cfgrw(struct vmctx *ctx, int vcpu, int in, int bus, int slot, int func, 1769 int coff, int bytes, uint32_t *eax) 1770 { 1771 struct businfo *bi; 1772 struct slotinfo *si; 1773 struct pci_devinst *pi; 1774 struct pci_devemu *pe; 1775 int idx, needcfg; 1776 uint64_t addr, bar, mask; 1777 1778 if ((bi = pci_businfo[bus]) != NULL) { 1779 si = &bi->slotinfo[slot]; 1780 pi = si->si_funcs[func].fi_devi; 1781 } else 1782 pi = NULL; 1783 1784 /* 1785 * Just return if there is no device at this slot:func or if the 1786 * the guest is doing an un-aligned access. 1787 */ 1788 if (pi == NULL || (bytes != 1 && bytes != 2 && bytes != 4) || 1789 (coff & (bytes - 1)) != 0) { 1790 if (in) 1791 *eax = 0xffffffff; 1792 return; 1793 } 1794 1795 /* 1796 * Ignore all writes beyond the standard config space and return all 1797 * ones on reads. 1798 */ 1799 if (coff >= PCI_REGMAX + 1) { 1800 if (in) { 1801 *eax = 0xffffffff; 1802 /* 1803 * Extended capabilities begin at offset 256 in config 1804 * space. Absence of extended capabilities is signaled 1805 * with all 0s in the extended capability header at 1806 * offset 256. 1807 */ 1808 if (coff <= PCI_REGMAX + 4) 1809 *eax = 0x00000000; 1810 } 1811 return; 1812 } 1813 1814 pe = pi->pi_d; 1815 1816 /* 1817 * Config read 1818 */ 1819 if (in) { 1820 /* Let the device emulation override the default handler */ 1821 if (pe->pe_cfgread != NULL) { 1822 needcfg = pe->pe_cfgread(ctx, vcpu, pi, coff, bytes, 1823 eax); 1824 } else { 1825 needcfg = 1; 1826 } 1827 1828 if (needcfg) 1829 *eax = CFGREAD(pi, coff, bytes); 1830 1831 pci_emul_hdrtype_fixup(bus, slot, coff, bytes, eax); 1832 } else { 1833 /* Let the device emulation override the default handler */ 1834 if (pe->pe_cfgwrite != NULL && 1835 (*pe->pe_cfgwrite)(ctx, vcpu, pi, coff, bytes, *eax) == 0) 1836 return; 1837 1838 /* 1839 * Special handling for write to BAR registers 1840 */ 1841 if (coff >= PCIR_BAR(0) && coff < PCIR_BAR(PCI_BARMAX + 1)) { 1842 /* 1843 * Ignore writes to BAR registers that are not 1844 * 4-byte aligned. 1845 */ 1846 if (bytes != 4 || (coff & 0x3) != 0) 1847 return; 1848 idx = (coff - PCIR_BAR(0)) / 4; 1849 mask = ~(pi->pi_bar[idx].size - 1); 1850 switch (pi->pi_bar[idx].type) { 1851 case PCIBAR_NONE: 1852 pi->pi_bar[idx].addr = bar = 0; 1853 break; 1854 case PCIBAR_IO: 1855 addr = *eax & mask; 1856 addr &= 0xffff; 1857 bar = addr | PCIM_BAR_IO_SPACE; 1858 /* 1859 * Register the new BAR value for interception 1860 */ 1861 if (addr != pi->pi_bar[idx].addr) { 1862 update_bar_address(pi, addr, idx, 1863 PCIBAR_IO); 1864 } 1865 break; 1866 case PCIBAR_MEM32: 1867 addr = bar = *eax & mask; 1868 bar |= PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_32; 1869 if (addr != pi->pi_bar[idx].addr) { 1870 update_bar_address(pi, addr, idx, 1871 PCIBAR_MEM32); 1872 } 1873 break; 1874 case PCIBAR_MEM64: 1875 addr = bar = *eax & mask; 1876 bar |= PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_64 | 1877 PCIM_BAR_MEM_PREFETCH; 1878 if (addr != (uint32_t)pi->pi_bar[idx].addr) { 1879 update_bar_address(pi, addr, idx, 1880 PCIBAR_MEM64); 1881 } 1882 break; 1883 case PCIBAR_MEMHI64: 1884 mask = ~(pi->pi_bar[idx - 1].size - 1); 1885 addr = ((uint64_t)*eax << 32) & mask; 1886 bar = addr >> 32; 1887 if (bar != pi->pi_bar[idx - 1].addr >> 32) { 1888 update_bar_address(pi, addr, idx - 1, 1889 PCIBAR_MEMHI64); 1890 } 1891 break; 1892 default: 1893 assert(0); 1894 } 1895 pci_set_cfgdata32(pi, coff, bar); 1896 1897 } else if (pci_emul_iscap(pi, coff)) { 1898 pci_emul_capwrite(pi, coff, bytes, *eax); 1899 } else if (coff >= PCIR_COMMAND && coff < PCIR_REVID) { 1900 pci_emul_cmdsts_write(pi, coff, *eax, bytes); 1901 } else { 1902 CFGWRITE(pi, coff, *eax, bytes); 1903 } 1904 } 1905 } 1906 1907 static int cfgenable, cfgbus, cfgslot, cfgfunc, cfgoff; 1908 1909 static int 1910 pci_emul_cfgaddr(struct vmctx *ctx, int vcpu, int in, int port, int bytes, 1911 uint32_t *eax, void *arg) 1912 { 1913 uint32_t x; 1914 1915 if (bytes != 4) { 1916 if (in) 1917 *eax = (bytes == 2) ? 0xffff : 0xff; 1918 return (0); 1919 } 1920 1921 if (in) { 1922 x = (cfgbus << 16) | (cfgslot << 11) | (cfgfunc << 8) | cfgoff; 1923 if (cfgenable) 1924 x |= CONF1_ENABLE; 1925 *eax = x; 1926 } else { 1927 x = *eax; 1928 cfgenable = (x & CONF1_ENABLE) == CONF1_ENABLE; 1929 cfgoff = x & PCI_REGMAX; 1930 cfgfunc = (x >> 8) & PCI_FUNCMAX; 1931 cfgslot = (x >> 11) & PCI_SLOTMAX; 1932 cfgbus = (x >> 16) & PCI_BUSMAX; 1933 } 1934 1935 return (0); 1936 } 1937 INOUT_PORT(pci_cfgaddr, CONF1_ADDR_PORT, IOPORT_F_INOUT, pci_emul_cfgaddr); 1938 1939 static int 1940 pci_emul_cfgdata(struct vmctx *ctx, int vcpu, int in, int port, int bytes, 1941 uint32_t *eax, void *arg) 1942 { 1943 int coff; 1944 1945 assert(bytes == 1 || bytes == 2 || bytes == 4); 1946 1947 coff = cfgoff + (port - CONF1_DATA_PORT); 1948 if (cfgenable) { 1949 pci_cfgrw(ctx, vcpu, in, cfgbus, cfgslot, cfgfunc, coff, bytes, 1950 eax); 1951 } else { 1952 /* Ignore accesses to cfgdata if not enabled by cfgaddr */ 1953 if (in) 1954 *eax = 0xffffffff; 1955 } 1956 return (0); 1957 } 1958 1959 INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+0, IOPORT_F_INOUT, pci_emul_cfgdata); 1960 INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+1, IOPORT_F_INOUT, pci_emul_cfgdata); 1961 INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+2, IOPORT_F_INOUT, pci_emul_cfgdata); 1962 INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+3, IOPORT_F_INOUT, pci_emul_cfgdata); 1963 1964 #define PCI_EMUL_TEST 1965 #ifdef PCI_EMUL_TEST 1966 /* 1967 * Define a dummy test device 1968 */ 1969 #define DIOSZ 8 1970 #define DMEMSZ 4096 1971 struct pci_emul_dsoftc { 1972 uint8_t ioregs[DIOSZ]; 1973 uint8_t memregs[2][DMEMSZ]; 1974 }; 1975 1976 #define PCI_EMUL_MSI_MSGS 4 1977 #define PCI_EMUL_MSIX_MSGS 16 1978 1979 static int 1980 pci_emul_dinit(struct vmctx *ctx, struct pci_devinst *pi, char *opts) 1981 { 1982 int error; 1983 struct pci_emul_dsoftc *sc; 1984 1985 sc = calloc(1, sizeof(struct pci_emul_dsoftc)); 1986 1987 pi->pi_arg = sc; 1988 1989 pci_set_cfgdata16(pi, PCIR_DEVICE, 0x0001); 1990 pci_set_cfgdata16(pi, PCIR_VENDOR, 0x10DD); 1991 pci_set_cfgdata8(pi, PCIR_CLASS, 0x02); 1992 1993 error = pci_emul_add_msicap(pi, PCI_EMUL_MSI_MSGS); 1994 assert(error == 0); 1995 1996 error = pci_emul_alloc_bar(pi, 0, PCIBAR_IO, DIOSZ); 1997 assert(error == 0); 1998 1999 error = pci_emul_alloc_bar(pi, 1, PCIBAR_MEM32, DMEMSZ); 2000 assert(error == 0); 2001 2002 error = pci_emul_alloc_bar(pi, 2, PCIBAR_MEM32, DMEMSZ); 2003 assert(error == 0); 2004 2005 return (0); 2006 } 2007 2008 static void 2009 pci_emul_diow(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, int baridx, 2010 uint64_t offset, int size, uint64_t value) 2011 { 2012 int i; 2013 struct pci_emul_dsoftc *sc = pi->pi_arg; 2014 2015 if (baridx == 0) { 2016 if (offset + size > DIOSZ) { 2017 printf("diow: iow too large, offset %ld size %d\n", 2018 offset, size); 2019 return; 2020 } 2021 2022 if (size == 1) { 2023 sc->ioregs[offset] = value & 0xff; 2024 } else if (size == 2) { 2025 *(uint16_t *)&sc->ioregs[offset] = value & 0xffff; 2026 } else if (size == 4) { 2027 *(uint32_t *)&sc->ioregs[offset] = value; 2028 } else { 2029 printf("diow: iow unknown size %d\n", size); 2030 } 2031 2032 /* 2033 * Special magic value to generate an interrupt 2034 */ 2035 if (offset == 4 && size == 4 && pci_msi_enabled(pi)) 2036 pci_generate_msi(pi, value % pci_msi_maxmsgnum(pi)); 2037 2038 if (value == 0xabcdef) { 2039 for (i = 0; i < pci_msi_maxmsgnum(pi); i++) 2040 pci_generate_msi(pi, i); 2041 } 2042 } 2043 2044 if (baridx == 1 || baridx == 2) { 2045 if (offset + size > DMEMSZ) { 2046 printf("diow: memw too large, offset %ld size %d\n", 2047 offset, size); 2048 return; 2049 } 2050 2051 i = baridx - 1; /* 'memregs' index */ 2052 2053 if (size == 1) { 2054 sc->memregs[i][offset] = value; 2055 } else if (size == 2) { 2056 *(uint16_t *)&sc->memregs[i][offset] = value; 2057 } else if (size == 4) { 2058 *(uint32_t *)&sc->memregs[i][offset] = value; 2059 } else if (size == 8) { 2060 *(uint64_t *)&sc->memregs[i][offset] = value; 2061 } else { 2062 printf("diow: memw unknown size %d\n", size); 2063 } 2064 2065 /* 2066 * magic interrupt ?? 2067 */ 2068 } 2069 2070 if (baridx > 2 || baridx < 0) { 2071 printf("diow: unknown bar idx %d\n", baridx); 2072 } 2073 } 2074 2075 static uint64_t 2076 pci_emul_dior(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, int baridx, 2077 uint64_t offset, int size) 2078 { 2079 struct pci_emul_dsoftc *sc = pi->pi_arg; 2080 uint32_t value; 2081 int i; 2082 2083 if (baridx == 0) { 2084 if (offset + size > DIOSZ) { 2085 printf("dior: ior too large, offset %ld size %d\n", 2086 offset, size); 2087 return (0); 2088 } 2089 2090 value = 0; 2091 if (size == 1) { 2092 value = sc->ioregs[offset]; 2093 } else if (size == 2) { 2094 value = *(uint16_t *) &sc->ioregs[offset]; 2095 } else if (size == 4) { 2096 value = *(uint32_t *) &sc->ioregs[offset]; 2097 } else { 2098 printf("dior: ior unknown size %d\n", size); 2099 } 2100 } 2101 2102 if (baridx == 1 || baridx == 2) { 2103 if (offset + size > DMEMSZ) { 2104 printf("dior: memr too large, offset %ld size %d\n", 2105 offset, size); 2106 return (0); 2107 } 2108 2109 i = baridx - 1; /* 'memregs' index */ 2110 2111 if (size == 1) { 2112 value = sc->memregs[i][offset]; 2113 } else if (size == 2) { 2114 value = *(uint16_t *) &sc->memregs[i][offset]; 2115 } else if (size == 4) { 2116 value = *(uint32_t *) &sc->memregs[i][offset]; 2117 } else if (size == 8) { 2118 value = *(uint64_t *) &sc->memregs[i][offset]; 2119 } else { 2120 printf("dior: ior unknown size %d\n", size); 2121 } 2122 } 2123 2124 2125 if (baridx > 2 || baridx < 0) { 2126 printf("dior: unknown bar idx %d\n", baridx); 2127 return (0); 2128 } 2129 2130 return (value); 2131 } 2132 2133 struct pci_devemu pci_dummy = { 2134 .pe_emu = "dummy", 2135 .pe_init = pci_emul_dinit, 2136 .pe_barwrite = pci_emul_diow, 2137 .pe_barread = pci_emul_dior 2138 }; 2139 PCI_EMUL_SET(pci_dummy); 2140 2141 #endif /* PCI_EMUL_TEST */ 2142