1 /*- 2 * Copyright (c) 2011 NetApp, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 #include <sys/param.h> 33 #include <sys/linker_set.h> 34 #include <sys/errno.h> 35 36 #include <ctype.h> 37 #include <stdio.h> 38 #include <stdlib.h> 39 #include <string.h> 40 #include <strings.h> 41 #include <assert.h> 42 #include <stdbool.h> 43 44 #include <machine/vmm.h> 45 #include <vmmapi.h> 46 47 #include "bhyverun.h" 48 #include "inout.h" 49 #include "mem.h" 50 #include "pci_emul.h" 51 #include "ioapic.h" 52 53 #define CONF1_ADDR_PORT 0x0cf8 54 #define CONF1_DATA_PORT 0x0cfc 55 56 #define CONF1_ENABLE 0x80000000ul 57 58 #define CFGWRITE(pi,off,val,b) \ 59 do { \ 60 if ((b) == 1) { \ 61 pci_set_cfgdata8((pi),(off),(val)); \ 62 } else if ((b) == 2) { \ 63 pci_set_cfgdata16((pi),(off),(val)); \ 64 } else { \ 65 pci_set_cfgdata32((pi),(off),(val)); \ 66 } \ 67 } while (0) 68 69 #define MAXSLOTS (PCI_SLOTMAX + 1) 70 #define MAXFUNCS (PCI_FUNCMAX + 1) 71 72 static struct slotinfo { 73 char *si_name; 74 char *si_param; 75 struct pci_devinst *si_devi; 76 int si_legacy; 77 } pci_slotinfo[MAXSLOTS][MAXFUNCS]; 78 79 /* 80 * Used to keep track of legacy interrupt owners/requestors 81 */ 82 #define NLIRQ 16 83 84 static struct lirqinfo { 85 int li_generic; 86 int li_acount; 87 struct pci_devinst *li_owner; /* XXX should be a list */ 88 } lirq[NLIRQ]; 89 90 SET_DECLARE(pci_devemu_set, struct pci_devemu); 91 92 static uint64_t pci_emul_iobase; 93 static uint64_t pci_emul_membase32; 94 static uint64_t pci_emul_membase64; 95 96 #define PCI_EMUL_IOBASE 0x2000 97 #define PCI_EMUL_IOLIMIT 0x10000 98 99 #define PCI_EMUL_MEMLIMIT32 0xE0000000 /* 3.5GB */ 100 101 #define PCI_EMUL_MEMBASE64 0xD000000000UL 102 #define PCI_EMUL_MEMLIMIT64 0xFD00000000UL 103 104 static struct pci_devemu *pci_emul_finddev(char *name); 105 106 static int pci_emul_devices; 107 108 /* 109 * I/O access 110 */ 111 112 /* 113 * Slot options are in the form: 114 * 115 * <slot>[:<func>],<emul>[,<config>] 116 * 117 * slot is 0..31 118 * func is 0..7 119 * emul is a string describing the type of PCI device e.g. virtio-net 120 * config is an optional string, depending on the device, that can be 121 * used for configuration. 122 * Examples are: 123 * 1,virtio-net,tap0 124 * 3:0,dummy 125 */ 126 static void 127 pci_parse_slot_usage(char *aopt) 128 { 129 130 fprintf(stderr, "Invalid PCI slot info field \"%s\"\n", aopt); 131 } 132 133 int 134 pci_parse_slot(char *opt, int legacy) 135 { 136 char *slot, *func, *emul, *config; 137 char *str, *cpy; 138 int error, snum, fnum; 139 140 error = -1; 141 str = cpy = strdup(opt); 142 143 slot = strsep(&str, ","); 144 func = NULL; 145 if (strchr(slot, ':') != NULL) { 146 func = cpy; 147 (void) strsep(&func, ":"); 148 } 149 150 emul = strsep(&str, ","); 151 config = str; 152 153 if (emul == NULL) { 154 pci_parse_slot_usage(opt); 155 goto done; 156 } 157 158 snum = atoi(slot); 159 fnum = func ? atoi(func) : 0; 160 161 if (snum < 0 || snum >= MAXSLOTS || fnum < 0 || fnum >= MAXFUNCS) { 162 pci_parse_slot_usage(opt); 163 goto done; 164 } 165 166 if (pci_slotinfo[snum][fnum].si_name != NULL) { 167 fprintf(stderr, "pci slot %d:%d already occupied!\n", 168 snum, fnum); 169 goto done; 170 } 171 172 if (pci_emul_finddev(emul) == NULL) { 173 fprintf(stderr, "pci slot %d:%d: unknown device \"%s\"\n", 174 snum, fnum, emul); 175 goto done; 176 } 177 178 error = 0; 179 pci_slotinfo[snum][fnum].si_name = emul; 180 pci_slotinfo[snum][fnum].si_param = config; 181 pci_slotinfo[snum][fnum].si_legacy = legacy; 182 183 done: 184 if (error) 185 free(cpy); 186 187 return (error); 188 } 189 190 static int 191 pci_valid_pba_offset(struct pci_devinst *pi, uint64_t offset) 192 { 193 194 if (offset < pi->pi_msix.pba_offset) 195 return (0); 196 197 if (offset >= pi->pi_msix.pba_offset + pi->pi_msix.pba_size) { 198 return (0); 199 } 200 201 return (1); 202 } 203 204 int 205 pci_emul_msix_twrite(struct pci_devinst *pi, uint64_t offset, int size, 206 uint64_t value) 207 { 208 int msix_entry_offset; 209 int tab_index; 210 char *dest; 211 212 /* support only 4 or 8 byte writes */ 213 if (size != 4 && size != 8) 214 return (-1); 215 216 /* 217 * Return if table index is beyond what device supports 218 */ 219 tab_index = offset / MSIX_TABLE_ENTRY_SIZE; 220 if (tab_index >= pi->pi_msix.table_count) 221 return (-1); 222 223 msix_entry_offset = offset % MSIX_TABLE_ENTRY_SIZE; 224 225 /* support only aligned writes */ 226 if ((msix_entry_offset % size) != 0) 227 return (-1); 228 229 dest = (char *)(pi->pi_msix.table + tab_index); 230 dest += msix_entry_offset; 231 232 if (size == 4) 233 *((uint32_t *)dest) = value; 234 else 235 *((uint64_t *)dest) = value; 236 237 return (0); 238 } 239 240 uint64_t 241 pci_emul_msix_tread(struct pci_devinst *pi, uint64_t offset, int size) 242 { 243 char *dest; 244 int msix_entry_offset; 245 int tab_index; 246 uint64_t retval = ~0; 247 248 /* 249 * The PCI standard only allows 4 and 8 byte accesses to the MSI-X 250 * table but we also allow 1 byte access to accomodate reads from 251 * ddb. 252 */ 253 if (size != 1 && size != 4 && size != 8) 254 return (retval); 255 256 msix_entry_offset = offset % MSIX_TABLE_ENTRY_SIZE; 257 258 /* support only aligned reads */ 259 if ((msix_entry_offset % size) != 0) { 260 return (retval); 261 } 262 263 tab_index = offset / MSIX_TABLE_ENTRY_SIZE; 264 265 if (tab_index < pi->pi_msix.table_count) { 266 /* valid MSI-X Table access */ 267 dest = (char *)(pi->pi_msix.table + tab_index); 268 dest += msix_entry_offset; 269 270 if (size == 1) 271 retval = *((uint8_t *)dest); 272 else if (size == 4) 273 retval = *((uint32_t *)dest); 274 else 275 retval = *((uint64_t *)dest); 276 } else if (pci_valid_pba_offset(pi, offset)) { 277 /* return 0 for PBA access */ 278 retval = 0; 279 } 280 281 return (retval); 282 } 283 284 int 285 pci_msix_table_bar(struct pci_devinst *pi) 286 { 287 288 if (pi->pi_msix.table != NULL) 289 return (pi->pi_msix.table_bar); 290 else 291 return (-1); 292 } 293 294 int 295 pci_msix_pba_bar(struct pci_devinst *pi) 296 { 297 298 if (pi->pi_msix.table != NULL) 299 return (pi->pi_msix.pba_bar); 300 else 301 return (-1); 302 } 303 304 static int 305 pci_emul_io_handler(struct vmctx *ctx, int vcpu, int in, int port, int bytes, 306 uint32_t *eax, void *arg) 307 { 308 struct pci_devinst *pdi = arg; 309 struct pci_devemu *pe = pdi->pi_d; 310 uint64_t offset; 311 int i; 312 313 for (i = 0; i <= PCI_BARMAX; i++) { 314 if (pdi->pi_bar[i].type == PCIBAR_IO && 315 port >= pdi->pi_bar[i].addr && 316 port + bytes <= pdi->pi_bar[i].addr + pdi->pi_bar[i].size) { 317 offset = port - pdi->pi_bar[i].addr; 318 if (in) 319 *eax = (*pe->pe_barread)(ctx, vcpu, pdi, i, 320 offset, bytes); 321 else 322 (*pe->pe_barwrite)(ctx, vcpu, pdi, i, offset, 323 bytes, *eax); 324 return (0); 325 } 326 } 327 return (-1); 328 } 329 330 static int 331 pci_emul_mem_handler(struct vmctx *ctx, int vcpu, int dir, uint64_t addr, 332 int size, uint64_t *val, void *arg1, long arg2) 333 { 334 struct pci_devinst *pdi = arg1; 335 struct pci_devemu *pe = pdi->pi_d; 336 uint64_t offset; 337 int bidx = (int) arg2; 338 339 assert(bidx <= PCI_BARMAX); 340 assert(pdi->pi_bar[bidx].type == PCIBAR_MEM32 || 341 pdi->pi_bar[bidx].type == PCIBAR_MEM64); 342 assert(addr >= pdi->pi_bar[bidx].addr && 343 addr + size <= pdi->pi_bar[bidx].addr + pdi->pi_bar[bidx].size); 344 345 offset = addr - pdi->pi_bar[bidx].addr; 346 347 if (dir == MEM_F_WRITE) 348 (*pe->pe_barwrite)(ctx, vcpu, pdi, bidx, offset, size, *val); 349 else 350 *val = (*pe->pe_barread)(ctx, vcpu, pdi, bidx, offset, size); 351 352 return (0); 353 } 354 355 356 static int 357 pci_emul_alloc_resource(uint64_t *baseptr, uint64_t limit, uint64_t size, 358 uint64_t *addr) 359 { 360 uint64_t base; 361 362 assert((size & (size - 1)) == 0); /* must be a power of 2 */ 363 364 base = roundup2(*baseptr, size); 365 366 if (base + size <= limit) { 367 *addr = base; 368 *baseptr = base + size; 369 return (0); 370 } else 371 return (-1); 372 } 373 374 int 375 pci_emul_alloc_bar(struct pci_devinst *pdi, int idx, enum pcibar_type type, 376 uint64_t size) 377 { 378 379 return (pci_emul_alloc_pbar(pdi, idx, 0, type, size)); 380 } 381 382 /* 383 * Register (or unregister) the MMIO or I/O region associated with the BAR 384 * register 'idx' of an emulated pci device. 385 */ 386 static void 387 modify_bar_registration(struct pci_devinst *pi, int idx, int registration) 388 { 389 int error; 390 struct inout_port iop; 391 struct mem_range mr; 392 393 switch (pi->pi_bar[idx].type) { 394 case PCIBAR_IO: 395 bzero(&iop, sizeof(struct inout_port)); 396 iop.name = pi->pi_name; 397 iop.port = pi->pi_bar[idx].addr; 398 iop.size = pi->pi_bar[idx].size; 399 if (registration) { 400 iop.flags = IOPORT_F_INOUT; 401 iop.handler = pci_emul_io_handler; 402 iop.arg = pi; 403 error = register_inout(&iop); 404 } else 405 error = unregister_inout(&iop); 406 break; 407 case PCIBAR_MEM32: 408 case PCIBAR_MEM64: 409 bzero(&mr, sizeof(struct mem_range)); 410 mr.name = pi->pi_name; 411 mr.base = pi->pi_bar[idx].addr; 412 mr.size = pi->pi_bar[idx].size; 413 if (registration) { 414 mr.flags = MEM_F_RW; 415 mr.handler = pci_emul_mem_handler; 416 mr.arg1 = pi; 417 mr.arg2 = idx; 418 error = register_mem(&mr); 419 } else 420 error = unregister_mem(&mr); 421 break; 422 default: 423 error = EINVAL; 424 break; 425 } 426 assert(error == 0); 427 } 428 429 static void 430 unregister_bar(struct pci_devinst *pi, int idx) 431 { 432 433 modify_bar_registration(pi, idx, 0); 434 } 435 436 static void 437 register_bar(struct pci_devinst *pi, int idx) 438 { 439 440 modify_bar_registration(pi, idx, 1); 441 } 442 443 /* Are we decoding i/o port accesses for the emulated pci device? */ 444 static int 445 porten(struct pci_devinst *pi) 446 { 447 uint16_t cmd; 448 449 cmd = pci_get_cfgdata16(pi, PCIR_COMMAND); 450 451 return (cmd & PCIM_CMD_PORTEN); 452 } 453 454 /* Are we decoding memory accesses for the emulated pci device? */ 455 static int 456 memen(struct pci_devinst *pi) 457 { 458 uint16_t cmd; 459 460 cmd = pci_get_cfgdata16(pi, PCIR_COMMAND); 461 462 return (cmd & PCIM_CMD_MEMEN); 463 } 464 465 /* 466 * Update the MMIO or I/O address that is decoded by the BAR register. 467 * 468 * If the pci device has enabled the address space decoding then intercept 469 * the address range decoded by the BAR register. 470 */ 471 static void 472 update_bar_address(struct pci_devinst *pi, uint64_t addr, int idx, int type) 473 { 474 int decode; 475 476 if (pi->pi_bar[idx].type == PCIBAR_IO) 477 decode = porten(pi); 478 else 479 decode = memen(pi); 480 481 if (decode) 482 unregister_bar(pi, idx); 483 484 switch (type) { 485 case PCIBAR_IO: 486 case PCIBAR_MEM32: 487 pi->pi_bar[idx].addr = addr; 488 break; 489 case PCIBAR_MEM64: 490 pi->pi_bar[idx].addr &= ~0xffffffffUL; 491 pi->pi_bar[idx].addr |= addr; 492 break; 493 case PCIBAR_MEMHI64: 494 pi->pi_bar[idx].addr &= 0xffffffff; 495 pi->pi_bar[idx].addr |= addr; 496 break; 497 default: 498 assert(0); 499 } 500 501 if (decode) 502 register_bar(pi, idx); 503 } 504 505 int 506 pci_emul_alloc_pbar(struct pci_devinst *pdi, int idx, uint64_t hostbase, 507 enum pcibar_type type, uint64_t size) 508 { 509 int error; 510 uint64_t *baseptr, limit, addr, mask, lobits, bar; 511 512 assert(idx >= 0 && idx <= PCI_BARMAX); 513 514 if ((size & (size - 1)) != 0) 515 size = 1UL << flsl(size); /* round up to a power of 2 */ 516 517 /* Enforce minimum BAR sizes required by the PCI standard */ 518 if (type == PCIBAR_IO) { 519 if (size < 4) 520 size = 4; 521 } else { 522 if (size < 16) 523 size = 16; 524 } 525 526 switch (type) { 527 case PCIBAR_NONE: 528 baseptr = NULL; 529 addr = mask = lobits = 0; 530 break; 531 case PCIBAR_IO: 532 if (hostbase && 533 pci_slotinfo[pdi->pi_slot][pdi->pi_func].si_legacy) { 534 assert(hostbase < PCI_EMUL_IOBASE); 535 baseptr = &hostbase; 536 } else { 537 baseptr = &pci_emul_iobase; 538 } 539 limit = PCI_EMUL_IOLIMIT; 540 mask = PCIM_BAR_IO_BASE; 541 lobits = PCIM_BAR_IO_SPACE; 542 break; 543 case PCIBAR_MEM64: 544 /* 545 * XXX 546 * Some drivers do not work well if the 64-bit BAR is allocated 547 * above 4GB. Allow for this by allocating small requests under 548 * 4GB unless then allocation size is larger than some arbitrary 549 * number (32MB currently). 550 */ 551 if (size > 32 * 1024 * 1024) { 552 /* 553 * XXX special case for device requiring peer-peer DMA 554 */ 555 if (size == 0x100000000UL) 556 baseptr = &hostbase; 557 else 558 baseptr = &pci_emul_membase64; 559 limit = PCI_EMUL_MEMLIMIT64; 560 mask = PCIM_BAR_MEM_BASE; 561 lobits = PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_64 | 562 PCIM_BAR_MEM_PREFETCH; 563 break; 564 } else { 565 baseptr = &pci_emul_membase32; 566 limit = PCI_EMUL_MEMLIMIT32; 567 mask = PCIM_BAR_MEM_BASE; 568 lobits = PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_64; 569 } 570 break; 571 case PCIBAR_MEM32: 572 baseptr = &pci_emul_membase32; 573 limit = PCI_EMUL_MEMLIMIT32; 574 mask = PCIM_BAR_MEM_BASE; 575 lobits = PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_32; 576 break; 577 default: 578 printf("pci_emul_alloc_base: invalid bar type %d\n", type); 579 assert(0); 580 } 581 582 if (baseptr != NULL) { 583 error = pci_emul_alloc_resource(baseptr, limit, size, &addr); 584 if (error != 0) 585 return (error); 586 } 587 588 pdi->pi_bar[idx].type = type; 589 pdi->pi_bar[idx].addr = addr; 590 pdi->pi_bar[idx].size = size; 591 592 /* Initialize the BAR register in config space */ 593 bar = (addr & mask) | lobits; 594 pci_set_cfgdata32(pdi, PCIR_BAR(idx), bar); 595 596 if (type == PCIBAR_MEM64) { 597 assert(idx + 1 <= PCI_BARMAX); 598 pdi->pi_bar[idx + 1].type = PCIBAR_MEMHI64; 599 pci_set_cfgdata32(pdi, PCIR_BAR(idx + 1), bar >> 32); 600 } 601 602 register_bar(pdi, idx); 603 604 return (0); 605 } 606 607 #define CAP_START_OFFSET 0x40 608 static int 609 pci_emul_add_capability(struct pci_devinst *pi, u_char *capdata, int caplen) 610 { 611 int i, capoff, capid, reallen; 612 uint16_t sts; 613 614 static u_char endofcap[4] = { 615 PCIY_RESERVED, 0, 0, 0 616 }; 617 618 assert(caplen > 0 && capdata[0] != PCIY_RESERVED); 619 620 reallen = roundup2(caplen, 4); /* dword aligned */ 621 622 sts = pci_get_cfgdata16(pi, PCIR_STATUS); 623 if ((sts & PCIM_STATUS_CAPPRESENT) == 0) { 624 capoff = CAP_START_OFFSET; 625 pci_set_cfgdata8(pi, PCIR_CAP_PTR, capoff); 626 pci_set_cfgdata16(pi, PCIR_STATUS, sts|PCIM_STATUS_CAPPRESENT); 627 } else { 628 capoff = pci_get_cfgdata8(pi, PCIR_CAP_PTR); 629 while (1) { 630 assert((capoff & 0x3) == 0); 631 capid = pci_get_cfgdata8(pi, capoff); 632 if (capid == PCIY_RESERVED) 633 break; 634 capoff = pci_get_cfgdata8(pi, capoff + 1); 635 } 636 } 637 638 /* Check if we have enough space */ 639 if (capoff + reallen + sizeof(endofcap) > PCI_REGMAX + 1) 640 return (-1); 641 642 /* Copy the capability */ 643 for (i = 0; i < caplen; i++) 644 pci_set_cfgdata8(pi, capoff + i, capdata[i]); 645 646 /* Set the next capability pointer */ 647 pci_set_cfgdata8(pi, capoff + 1, capoff + reallen); 648 649 /* Copy of the reserved capability which serves as the end marker */ 650 for (i = 0; i < sizeof(endofcap); i++) 651 pci_set_cfgdata8(pi, capoff + reallen + i, endofcap[i]); 652 653 return (0); 654 } 655 656 static struct pci_devemu * 657 pci_emul_finddev(char *name) 658 { 659 struct pci_devemu **pdpp, *pdp; 660 661 SET_FOREACH(pdpp, pci_devemu_set) { 662 pdp = *pdpp; 663 if (!strcmp(pdp->pe_emu, name)) { 664 return (pdp); 665 } 666 } 667 668 return (NULL); 669 } 670 671 static int 672 pci_emul_init(struct vmctx *ctx, struct pci_devemu *pde, int slot, int func, 673 char *params) 674 { 675 struct pci_devinst *pdi; 676 int err; 677 678 pdi = malloc(sizeof(struct pci_devinst)); 679 bzero(pdi, sizeof(*pdi)); 680 681 pdi->pi_vmctx = ctx; 682 pdi->pi_bus = 0; 683 pdi->pi_slot = slot; 684 pdi->pi_func = func; 685 pdi->pi_d = pde; 686 snprintf(pdi->pi_name, PI_NAMESZ, "%s-pci-%d", pde->pe_emu, slot); 687 688 /* Disable legacy interrupts */ 689 pci_set_cfgdata8(pdi, PCIR_INTLINE, 255); 690 pci_set_cfgdata8(pdi, PCIR_INTPIN, 0); 691 692 pci_set_cfgdata8(pdi, PCIR_COMMAND, 693 PCIM_CMD_PORTEN | PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN); 694 695 err = (*pde->pe_init)(ctx, pdi, params); 696 if (err != 0) { 697 free(pdi); 698 } else { 699 pci_emul_devices++; 700 pci_slotinfo[slot][func].si_devi = pdi; 701 } 702 703 return (err); 704 } 705 706 void 707 pci_populate_msicap(struct msicap *msicap, int msgnum, int nextptr) 708 { 709 int mmc; 710 711 CTASSERT(sizeof(struct msicap) == 14); 712 713 /* Number of msi messages must be a power of 2 between 1 and 32 */ 714 assert((msgnum & (msgnum - 1)) == 0 && msgnum >= 1 && msgnum <= 32); 715 mmc = ffs(msgnum) - 1; 716 717 bzero(msicap, sizeof(struct msicap)); 718 msicap->capid = PCIY_MSI; 719 msicap->nextptr = nextptr; 720 msicap->msgctrl = PCIM_MSICTRL_64BIT | (mmc << 1); 721 } 722 723 int 724 pci_emul_add_msicap(struct pci_devinst *pi, int msgnum) 725 { 726 struct msicap msicap; 727 728 pci_populate_msicap(&msicap, msgnum, 0); 729 730 return (pci_emul_add_capability(pi, (u_char *)&msicap, sizeof(msicap))); 731 } 732 733 static void 734 pci_populate_msixcap(struct msixcap *msixcap, int msgnum, int barnum, 735 uint32_t msix_tab_size, int nextptr) 736 { 737 CTASSERT(sizeof(struct msixcap) == 12); 738 739 assert(msix_tab_size % 4096 == 0); 740 741 bzero(msixcap, sizeof(struct msixcap)); 742 msixcap->capid = PCIY_MSIX; 743 msixcap->nextptr = nextptr; 744 745 /* 746 * Message Control Register, all fields set to 747 * zero except for the Table Size. 748 * Note: Table size N is encoded as N-1 749 */ 750 msixcap->msgctrl = msgnum - 1; 751 752 /* 753 * MSI-X BAR setup: 754 * - MSI-X table start at offset 0 755 * - PBA table starts at a 4K aligned offset after the MSI-X table 756 */ 757 msixcap->table_info = barnum & PCIM_MSIX_BIR_MASK; 758 msixcap->pba_info = msix_tab_size | (barnum & PCIM_MSIX_BIR_MASK); 759 } 760 761 static void 762 pci_msix_table_init(struct pci_devinst *pi, int table_entries) 763 { 764 int i, table_size; 765 766 assert(table_entries > 0); 767 assert(table_entries <= MAX_MSIX_TABLE_ENTRIES); 768 769 table_size = table_entries * MSIX_TABLE_ENTRY_SIZE; 770 pi->pi_msix.table = malloc(table_size); 771 bzero(pi->pi_msix.table, table_size); 772 773 /* set mask bit of vector control register */ 774 for (i = 0; i < table_entries; i++) 775 pi->pi_msix.table[i].vector_control |= PCIM_MSIX_VCTRL_MASK; 776 } 777 778 int 779 pci_emul_add_msixcap(struct pci_devinst *pi, int msgnum, int barnum) 780 { 781 uint16_t pba_index; 782 uint32_t tab_size; 783 struct msixcap msixcap; 784 785 assert(msgnum >= 1 && msgnum <= MAX_MSIX_TABLE_ENTRIES); 786 assert(barnum >= 0 && barnum <= PCIR_MAX_BAR_0); 787 788 tab_size = msgnum * MSIX_TABLE_ENTRY_SIZE; 789 790 /* Align table size to nearest 4K */ 791 tab_size = roundup2(tab_size, 4096); 792 793 pi->pi_msix.table_bar = barnum; 794 pi->pi_msix.pba_bar = barnum; 795 pi->pi_msix.table_offset = 0; 796 pi->pi_msix.table_count = msgnum; 797 pi->pi_msix.pba_offset = tab_size; 798 799 /* calculate the MMIO size required for MSI-X PBA */ 800 pba_index = (msgnum - 1) / (PBA_TABLE_ENTRY_SIZE * 8); 801 pi->pi_msix.pba_size = (pba_index + 1) * PBA_TABLE_ENTRY_SIZE; 802 803 pci_msix_table_init(pi, msgnum); 804 805 pci_populate_msixcap(&msixcap, msgnum, barnum, tab_size, 0); 806 807 /* allocate memory for MSI-X Table and PBA */ 808 pci_emul_alloc_bar(pi, barnum, PCIBAR_MEM32, 809 tab_size + pi->pi_msix.pba_size); 810 811 return (pci_emul_add_capability(pi, (u_char *)&msixcap, 812 sizeof(msixcap))); 813 } 814 815 void 816 msixcap_cfgwrite(struct pci_devinst *pi, int capoff, int offset, 817 int bytes, uint32_t val) 818 { 819 uint16_t msgctrl, rwmask; 820 int off, table_bar; 821 822 off = offset - capoff; 823 table_bar = pi->pi_msix.table_bar; 824 /* Message Control Register */ 825 if (off == 2 && bytes == 2) { 826 rwmask = PCIM_MSIXCTRL_MSIX_ENABLE | PCIM_MSIXCTRL_FUNCTION_MASK; 827 msgctrl = pci_get_cfgdata16(pi, offset); 828 msgctrl &= ~rwmask; 829 msgctrl |= val & rwmask; 830 val = msgctrl; 831 832 pi->pi_msix.enabled = val & PCIM_MSIXCTRL_MSIX_ENABLE; 833 pi->pi_msix.function_mask = val & PCIM_MSIXCTRL_FUNCTION_MASK; 834 } 835 836 CFGWRITE(pi, offset, val, bytes); 837 } 838 839 void 840 msicap_cfgwrite(struct pci_devinst *pi, int capoff, int offset, 841 int bytes, uint32_t val) 842 { 843 uint16_t msgctrl, rwmask, msgdata, mme; 844 uint32_t addrlo; 845 846 /* 847 * If guest is writing to the message control register make sure 848 * we do not overwrite read-only fields. 849 */ 850 if ((offset - capoff) == 2 && bytes == 2) { 851 rwmask = PCIM_MSICTRL_MME_MASK | PCIM_MSICTRL_MSI_ENABLE; 852 msgctrl = pci_get_cfgdata16(pi, offset); 853 msgctrl &= ~rwmask; 854 msgctrl |= val & rwmask; 855 val = msgctrl; 856 857 addrlo = pci_get_cfgdata32(pi, capoff + 4); 858 if (msgctrl & PCIM_MSICTRL_64BIT) 859 msgdata = pci_get_cfgdata16(pi, capoff + 12); 860 else 861 msgdata = pci_get_cfgdata16(pi, capoff + 8); 862 863 /* 864 * XXX check delivery mode, destination mode etc 865 */ 866 mme = msgctrl & PCIM_MSICTRL_MME_MASK; 867 pi->pi_msi.enabled = msgctrl & PCIM_MSICTRL_MSI_ENABLE ? 1 : 0; 868 if (pi->pi_msi.enabled) { 869 pi->pi_msi.cpu = (addrlo >> 12) & 0xff; 870 pi->pi_msi.vector = msgdata & 0xff; 871 pi->pi_msi.msgnum = 1 << (mme >> 4); 872 } else { 873 pi->pi_msi.cpu = 0; 874 pi->pi_msi.vector = 0; 875 pi->pi_msi.msgnum = 0; 876 } 877 } 878 879 CFGWRITE(pi, offset, val, bytes); 880 } 881 882 void 883 pciecap_cfgwrite(struct pci_devinst *pi, int capoff, int offset, 884 int bytes, uint32_t val) 885 { 886 887 /* XXX don't write to the readonly parts */ 888 CFGWRITE(pi, offset, val, bytes); 889 } 890 891 #define PCIECAP_VERSION 0x2 892 int 893 pci_emul_add_pciecap(struct pci_devinst *pi, int type) 894 { 895 int err; 896 struct pciecap pciecap; 897 898 CTASSERT(sizeof(struct pciecap) == 60); 899 900 if (type != PCIEM_TYPE_ROOT_PORT) 901 return (-1); 902 903 bzero(&pciecap, sizeof(pciecap)); 904 905 pciecap.capid = PCIY_EXPRESS; 906 pciecap.pcie_capabilities = PCIECAP_VERSION | PCIEM_TYPE_ROOT_PORT; 907 pciecap.link_capabilities = 0x411; /* gen1, x1 */ 908 pciecap.link_status = 0x11; /* gen1, x1 */ 909 910 err = pci_emul_add_capability(pi, (u_char *)&pciecap, sizeof(pciecap)); 911 return (err); 912 } 913 914 /* 915 * This function assumes that 'coff' is in the capabilities region of the 916 * config space. 917 */ 918 static void 919 pci_emul_capwrite(struct pci_devinst *pi, int offset, int bytes, uint32_t val) 920 { 921 int capid; 922 uint8_t capoff, nextoff; 923 924 /* Do not allow un-aligned writes */ 925 if ((offset & (bytes - 1)) != 0) 926 return; 927 928 /* Find the capability that we want to update */ 929 capoff = CAP_START_OFFSET; 930 while (1) { 931 capid = pci_get_cfgdata8(pi, capoff); 932 if (capid == PCIY_RESERVED) 933 break; 934 935 nextoff = pci_get_cfgdata8(pi, capoff + 1); 936 if (offset >= capoff && offset < nextoff) 937 break; 938 939 capoff = nextoff; 940 } 941 assert(offset >= capoff); 942 943 /* 944 * Capability ID and Next Capability Pointer are readonly 945 */ 946 if (offset == capoff || offset == capoff + 1) 947 return; 948 949 switch (capid) { 950 case PCIY_MSI: 951 msicap_cfgwrite(pi, capoff, offset, bytes, val); 952 break; 953 case PCIY_MSIX: 954 msixcap_cfgwrite(pi, capoff, offset, bytes, val); 955 break; 956 case PCIY_EXPRESS: 957 pciecap_cfgwrite(pi, capoff, offset, bytes, val); 958 break; 959 default: 960 break; 961 } 962 } 963 964 static int 965 pci_emul_iscap(struct pci_devinst *pi, int offset) 966 { 967 int found; 968 uint16_t sts; 969 uint8_t capid, lastoff; 970 971 found = 0; 972 sts = pci_get_cfgdata16(pi, PCIR_STATUS); 973 if ((sts & PCIM_STATUS_CAPPRESENT) != 0) { 974 lastoff = pci_get_cfgdata8(pi, PCIR_CAP_PTR); 975 while (1) { 976 assert((lastoff & 0x3) == 0); 977 capid = pci_get_cfgdata8(pi, lastoff); 978 if (capid == PCIY_RESERVED) 979 break; 980 lastoff = pci_get_cfgdata8(pi, lastoff + 1); 981 } 982 if (offset >= CAP_START_OFFSET && offset <= lastoff) 983 found = 1; 984 } 985 return (found); 986 } 987 988 static int 989 pci_emul_fallback_handler(struct vmctx *ctx, int vcpu, int dir, uint64_t addr, 990 int size, uint64_t *val, void *arg1, long arg2) 991 { 992 /* 993 * Ignore writes; return 0xff's for reads. The mem read code 994 * will take care of truncating to the correct size. 995 */ 996 if (dir == MEM_F_READ) { 997 *val = 0xffffffffffffffff; 998 } 999 1000 return (0); 1001 } 1002 1003 int 1004 init_pci(struct vmctx *ctx) 1005 { 1006 struct mem_range memp; 1007 struct pci_devemu *pde; 1008 struct slotinfo *si; 1009 size_t lowmem; 1010 int slot, func; 1011 int error; 1012 1013 pci_emul_iobase = PCI_EMUL_IOBASE; 1014 pci_emul_membase32 = vm_get_lowmem_limit(ctx); 1015 pci_emul_membase64 = PCI_EMUL_MEMBASE64; 1016 1017 /* 1018 * Allow ISA IRQs 5,10,11,12, and 15 to be available for 1019 * generic use 1020 */ 1021 lirq[5].li_generic = 1; 1022 lirq[10].li_generic = 1; 1023 lirq[11].li_generic = 1; 1024 lirq[12].li_generic = 1; 1025 lirq[15].li_generic = 1; 1026 1027 for (slot = 0; slot < MAXSLOTS; slot++) { 1028 for (func = 0; func < MAXFUNCS; func++) { 1029 si = &pci_slotinfo[slot][func]; 1030 if (si->si_name != NULL) { 1031 pde = pci_emul_finddev(si->si_name); 1032 assert(pde != NULL); 1033 error = pci_emul_init(ctx, pde, slot, func, 1034 si->si_param); 1035 if (error) 1036 return (error); 1037 } 1038 } 1039 } 1040 1041 /* 1042 * The guest physical memory map looks like the following: 1043 * [0, lowmem) guest system memory 1044 * [lowmem, lowmem_limit) memory hole (may be absent) 1045 * [lowmem_limit, 4GB) PCI hole (32-bit BAR allocation) 1046 * [4GB, 4GB + highmem) 1047 * 1048 * Accesses to memory addresses that are not allocated to system 1049 * memory or PCI devices return 0xff's. 1050 */ 1051 error = vm_get_memory_seg(ctx, 0, &lowmem); 1052 assert(error == 0); 1053 1054 memset(&memp, 0, sizeof(struct mem_range)); 1055 memp.name = "PCI hole"; 1056 memp.flags = MEM_F_RW; 1057 memp.base = lowmem; 1058 memp.size = (4ULL * 1024 * 1024 * 1024) - lowmem; 1059 memp.handler = pci_emul_fallback_handler; 1060 1061 error = register_mem_fallback(&memp); 1062 assert(error == 0); 1063 1064 return (0); 1065 } 1066 1067 int 1068 pci_msi_enabled(struct pci_devinst *pi) 1069 { 1070 return (pi->pi_msi.enabled); 1071 } 1072 1073 int 1074 pci_msi_msgnum(struct pci_devinst *pi) 1075 { 1076 if (pi->pi_msi.enabled) 1077 return (pi->pi_msi.msgnum); 1078 else 1079 return (0); 1080 } 1081 1082 int 1083 pci_msix_enabled(struct pci_devinst *pi) 1084 { 1085 1086 return (pi->pi_msix.enabled && !pi->pi_msi.enabled); 1087 } 1088 1089 void 1090 pci_generate_msix(struct pci_devinst *pi, int index) 1091 { 1092 struct msix_table_entry *mte; 1093 1094 if (!pci_msix_enabled(pi)) 1095 return; 1096 1097 if (pi->pi_msix.function_mask) 1098 return; 1099 1100 if (index >= pi->pi_msix.table_count) 1101 return; 1102 1103 mte = &pi->pi_msix.table[index]; 1104 if ((mte->vector_control & PCIM_MSIX_VCTRL_MASK) == 0) { 1105 /* XXX Set PBA bit if interrupt is disabled */ 1106 vm_lapic_irq(pi->pi_vmctx, 1107 (mte->addr >> 12) & 0xff, mte->msg_data & 0xff); 1108 } 1109 } 1110 1111 void 1112 pci_generate_msi(struct pci_devinst *pi, int msg) 1113 { 1114 1115 if (pci_msi_enabled(pi) && msg < pci_msi_msgnum(pi)) { 1116 vm_lapic_irq(pi->pi_vmctx, 1117 pi->pi_msi.cpu, 1118 pi->pi_msi.vector + msg); 1119 } 1120 } 1121 1122 int 1123 pci_is_legacy(struct pci_devinst *pi) 1124 { 1125 1126 return (pci_slotinfo[pi->pi_slot][pi->pi_func].si_legacy); 1127 } 1128 1129 static int 1130 pci_lintr_alloc(struct pci_devinst *pi, int vec) 1131 { 1132 int i; 1133 1134 assert(vec < NLIRQ); 1135 1136 if (vec == -1) { 1137 for (i = 0; i < NLIRQ; i++) { 1138 if (lirq[i].li_generic && 1139 lirq[i].li_owner == NULL) { 1140 vec = i; 1141 break; 1142 } 1143 } 1144 } else { 1145 if (lirq[vec].li_owner != NULL) { 1146 vec = -1; 1147 } 1148 } 1149 assert(vec != -1); 1150 1151 lirq[vec].li_owner = pi; 1152 pi->pi_lintr_pin = vec; 1153 1154 return (vec); 1155 } 1156 1157 int 1158 pci_lintr_request(struct pci_devinst *pi, int vec) 1159 { 1160 1161 vec = pci_lintr_alloc(pi, vec); 1162 pci_set_cfgdata8(pi, PCIR_INTLINE, vec); 1163 pci_set_cfgdata8(pi, PCIR_INTPIN, 1); 1164 return (0); 1165 } 1166 1167 void 1168 pci_lintr_assert(struct pci_devinst *pi) 1169 { 1170 1171 assert(pi->pi_lintr_pin); 1172 ioapic_assert_pin(pi->pi_vmctx, pi->pi_lintr_pin); 1173 } 1174 1175 void 1176 pci_lintr_deassert(struct pci_devinst *pi) 1177 { 1178 1179 assert(pi->pi_lintr_pin); 1180 ioapic_deassert_pin(pi->pi_vmctx, pi->pi_lintr_pin); 1181 } 1182 1183 /* 1184 * Return 1 if the emulated device in 'slot' is a multi-function device. 1185 * Return 0 otherwise. 1186 */ 1187 static int 1188 pci_emul_is_mfdev(int slot) 1189 { 1190 int f, numfuncs; 1191 1192 numfuncs = 0; 1193 for (f = 0; f < MAXFUNCS; f++) { 1194 if (pci_slotinfo[slot][f].si_devi != NULL) { 1195 numfuncs++; 1196 } 1197 } 1198 return (numfuncs > 1); 1199 } 1200 1201 /* 1202 * Ensure that the PCIM_MFDEV bit is properly set (or unset) depending on 1203 * whether or not is a multi-function being emulated in the pci 'slot'. 1204 */ 1205 static void 1206 pci_emul_hdrtype_fixup(int slot, int off, int bytes, uint32_t *rv) 1207 { 1208 int mfdev; 1209 1210 if (off <= PCIR_HDRTYPE && off + bytes > PCIR_HDRTYPE) { 1211 mfdev = pci_emul_is_mfdev(slot); 1212 switch (bytes) { 1213 case 1: 1214 case 2: 1215 *rv &= ~PCIM_MFDEV; 1216 if (mfdev) { 1217 *rv |= PCIM_MFDEV; 1218 } 1219 break; 1220 case 4: 1221 *rv &= ~(PCIM_MFDEV << 16); 1222 if (mfdev) { 1223 *rv |= (PCIM_MFDEV << 16); 1224 } 1225 break; 1226 } 1227 } 1228 } 1229 1230 static int cfgbus, cfgslot, cfgfunc, cfgoff; 1231 1232 static int 1233 pci_emul_cfgaddr(struct vmctx *ctx, int vcpu, int in, int port, int bytes, 1234 uint32_t *eax, void *arg) 1235 { 1236 uint32_t x; 1237 1238 if (bytes != 4) { 1239 if (in) 1240 *eax = (bytes == 2) ? 0xffff : 0xff; 1241 return (0); 1242 } 1243 1244 if (in) { 1245 x = (cfgbus << 16) | 1246 (cfgslot << 11) | 1247 (cfgfunc << 8) | 1248 cfgoff; 1249 *eax = x | CONF1_ENABLE; 1250 } else { 1251 x = *eax; 1252 cfgoff = x & PCI_REGMAX; 1253 cfgfunc = (x >> 8) & PCI_FUNCMAX; 1254 cfgslot = (x >> 11) & PCI_SLOTMAX; 1255 cfgbus = (x >> 16) & PCI_BUSMAX; 1256 } 1257 1258 return (0); 1259 } 1260 INOUT_PORT(pci_cfgaddr, CONF1_ADDR_PORT, IOPORT_F_INOUT, pci_emul_cfgaddr); 1261 1262 static uint32_t 1263 bits_changed(uint32_t old, uint32_t new, uint32_t mask) 1264 { 1265 1266 return ((old ^ new) & mask); 1267 } 1268 1269 static void 1270 pci_emul_cmdwrite(struct pci_devinst *pi, uint32_t new, int bytes) 1271 { 1272 int i; 1273 uint16_t old; 1274 1275 /* 1276 * The command register is at an offset of 4 bytes and thus the 1277 * guest could write 1, 2 or 4 bytes starting at this offset. 1278 */ 1279 1280 old = pci_get_cfgdata16(pi, PCIR_COMMAND); /* stash old value */ 1281 CFGWRITE(pi, PCIR_COMMAND, new, bytes); /* update config */ 1282 new = pci_get_cfgdata16(pi, PCIR_COMMAND); /* get updated value */ 1283 1284 /* 1285 * If the MMIO or I/O address space decoding has changed then 1286 * register/unregister all BARs that decode that address space. 1287 */ 1288 for (i = 0; i < PCI_BARMAX; i++) { 1289 switch (pi->pi_bar[i].type) { 1290 case PCIBAR_NONE: 1291 case PCIBAR_MEMHI64: 1292 break; 1293 case PCIBAR_IO: 1294 /* I/O address space decoding changed? */ 1295 if (bits_changed(old, new, PCIM_CMD_PORTEN)) { 1296 if (porten(pi)) 1297 register_bar(pi, i); 1298 else 1299 unregister_bar(pi, i); 1300 } 1301 break; 1302 case PCIBAR_MEM32: 1303 case PCIBAR_MEM64: 1304 /* MMIO address space decoding changed? */ 1305 if (bits_changed(old, new, PCIM_CMD_MEMEN)) { 1306 if (memen(pi)) 1307 register_bar(pi, i); 1308 else 1309 unregister_bar(pi, i); 1310 } 1311 break; 1312 default: 1313 assert(0); 1314 } 1315 } 1316 } 1317 1318 static int 1319 pci_emul_cfgdata(struct vmctx *ctx, int vcpu, int in, int port, int bytes, 1320 uint32_t *eax, void *arg) 1321 { 1322 struct pci_devinst *pi; 1323 struct pci_devemu *pe; 1324 int coff, idx, needcfg; 1325 uint64_t addr, bar, mask; 1326 1327 assert(bytes == 1 || bytes == 2 || bytes == 4); 1328 1329 if (cfgbus == 0) 1330 pi = pci_slotinfo[cfgslot][cfgfunc].si_devi; 1331 else 1332 pi = NULL; 1333 1334 coff = cfgoff + (port - CONF1_DATA_PORT); 1335 1336 #if 0 1337 printf("pcicfg-%s from 0x%0x of %d bytes (%d/%d/%d)\n\r", 1338 in ? "read" : "write", coff, bytes, cfgbus, cfgslot, cfgfunc); 1339 #endif 1340 1341 /* 1342 * Just return if there is no device at this cfgslot:cfgfunc or 1343 * if the guest is doing an un-aligned access 1344 */ 1345 if (pi == NULL || (coff & (bytes - 1)) != 0) { 1346 if (in) 1347 *eax = 0xffffffff; 1348 return (0); 1349 } 1350 1351 pe = pi->pi_d; 1352 1353 /* 1354 * Config read 1355 */ 1356 if (in) { 1357 /* Let the device emulation override the default handler */ 1358 if (pe->pe_cfgread != NULL) { 1359 needcfg = pe->pe_cfgread(ctx, vcpu, pi, 1360 coff, bytes, eax); 1361 } else { 1362 needcfg = 1; 1363 } 1364 1365 if (needcfg) { 1366 if (bytes == 1) 1367 *eax = pci_get_cfgdata8(pi, coff); 1368 else if (bytes == 2) 1369 *eax = pci_get_cfgdata16(pi, coff); 1370 else 1371 *eax = pci_get_cfgdata32(pi, coff); 1372 } 1373 1374 pci_emul_hdrtype_fixup(cfgslot, coff, bytes, eax); 1375 } else { 1376 /* Let the device emulation override the default handler */ 1377 if (pe->pe_cfgwrite != NULL && 1378 (*pe->pe_cfgwrite)(ctx, vcpu, pi, coff, bytes, *eax) == 0) 1379 return (0); 1380 1381 /* 1382 * Special handling for write to BAR registers 1383 */ 1384 if (coff >= PCIR_BAR(0) && coff < PCIR_BAR(PCI_BARMAX + 1)) { 1385 /* 1386 * Ignore writes to BAR registers that are not 1387 * 4-byte aligned. 1388 */ 1389 if (bytes != 4 || (coff & 0x3) != 0) 1390 return (0); 1391 idx = (coff - PCIR_BAR(0)) / 4; 1392 mask = ~(pi->pi_bar[idx].size - 1); 1393 switch (pi->pi_bar[idx].type) { 1394 case PCIBAR_NONE: 1395 pi->pi_bar[idx].addr = bar = 0; 1396 break; 1397 case PCIBAR_IO: 1398 addr = *eax & mask; 1399 addr &= 0xffff; 1400 bar = addr | PCIM_BAR_IO_SPACE; 1401 /* 1402 * Register the new BAR value for interception 1403 */ 1404 if (addr != pi->pi_bar[idx].addr) { 1405 update_bar_address(pi, addr, idx, 1406 PCIBAR_IO); 1407 } 1408 break; 1409 case PCIBAR_MEM32: 1410 addr = bar = *eax & mask; 1411 bar |= PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_32; 1412 if (addr != pi->pi_bar[idx].addr) { 1413 update_bar_address(pi, addr, idx, 1414 PCIBAR_MEM32); 1415 } 1416 break; 1417 case PCIBAR_MEM64: 1418 addr = bar = *eax & mask; 1419 bar |= PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_64 | 1420 PCIM_BAR_MEM_PREFETCH; 1421 if (addr != (uint32_t)pi->pi_bar[idx].addr) { 1422 update_bar_address(pi, addr, idx, 1423 PCIBAR_MEM64); 1424 } 1425 break; 1426 case PCIBAR_MEMHI64: 1427 mask = ~(pi->pi_bar[idx - 1].size - 1); 1428 addr = ((uint64_t)*eax << 32) & mask; 1429 bar = addr >> 32; 1430 if (bar != pi->pi_bar[idx - 1].addr >> 32) { 1431 update_bar_address(pi, addr, idx - 1, 1432 PCIBAR_MEMHI64); 1433 } 1434 break; 1435 default: 1436 assert(0); 1437 } 1438 pci_set_cfgdata32(pi, coff, bar); 1439 1440 } else if (pci_emul_iscap(pi, coff)) { 1441 pci_emul_capwrite(pi, coff, bytes, *eax); 1442 } else if (coff == PCIR_COMMAND) { 1443 pci_emul_cmdwrite(pi, *eax, bytes); 1444 } else { 1445 CFGWRITE(pi, coff, *eax, bytes); 1446 } 1447 } 1448 1449 return (0); 1450 } 1451 1452 INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+0, IOPORT_F_INOUT, pci_emul_cfgdata); 1453 INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+1, IOPORT_F_INOUT, pci_emul_cfgdata); 1454 INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+2, IOPORT_F_INOUT, pci_emul_cfgdata); 1455 INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+3, IOPORT_F_INOUT, pci_emul_cfgdata); 1456 1457 /* 1458 * I/O ports to configure PCI IRQ routing. We ignore all writes to it. 1459 */ 1460 static int 1461 pci_irq_port_handler(struct vmctx *ctx, int vcpu, int in, int port, int bytes, 1462 uint32_t *eax, void *arg) 1463 { 1464 assert(in == 0); 1465 return (0); 1466 } 1467 INOUT_PORT(pci_irq, 0xC00, IOPORT_F_OUT, pci_irq_port_handler); 1468 INOUT_PORT(pci_irq, 0xC01, IOPORT_F_OUT, pci_irq_port_handler); 1469 1470 #define PCI_EMUL_TEST 1471 #ifdef PCI_EMUL_TEST 1472 /* 1473 * Define a dummy test device 1474 */ 1475 #define DIOSZ 20 1476 #define DMEMSZ 4096 1477 struct pci_emul_dsoftc { 1478 uint8_t ioregs[DIOSZ]; 1479 uint8_t memregs[DMEMSZ]; 1480 }; 1481 1482 #define PCI_EMUL_MSI_MSGS 4 1483 #define PCI_EMUL_MSIX_MSGS 16 1484 1485 static int 1486 pci_emul_dinit(struct vmctx *ctx, struct pci_devinst *pi, char *opts) 1487 { 1488 int error; 1489 struct pci_emul_dsoftc *sc; 1490 1491 sc = malloc(sizeof(struct pci_emul_dsoftc)); 1492 memset(sc, 0, sizeof(struct pci_emul_dsoftc)); 1493 1494 pi->pi_arg = sc; 1495 1496 pci_set_cfgdata16(pi, PCIR_DEVICE, 0x0001); 1497 pci_set_cfgdata16(pi, PCIR_VENDOR, 0x10DD); 1498 pci_set_cfgdata8(pi, PCIR_CLASS, 0x02); 1499 1500 error = pci_emul_add_msicap(pi, PCI_EMUL_MSI_MSGS); 1501 assert(error == 0); 1502 1503 error = pci_emul_alloc_bar(pi, 0, PCIBAR_IO, DIOSZ); 1504 assert(error == 0); 1505 1506 error = pci_emul_alloc_bar(pi, 1, PCIBAR_MEM32, DMEMSZ); 1507 assert(error == 0); 1508 1509 return (0); 1510 } 1511 1512 static void 1513 pci_emul_diow(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, int baridx, 1514 uint64_t offset, int size, uint64_t value) 1515 { 1516 int i; 1517 struct pci_emul_dsoftc *sc = pi->pi_arg; 1518 1519 if (baridx == 0) { 1520 if (offset + size > DIOSZ) { 1521 printf("diow: iow too large, offset %ld size %d\n", 1522 offset, size); 1523 return; 1524 } 1525 1526 if (size == 1) { 1527 sc->ioregs[offset] = value & 0xff; 1528 } else if (size == 2) { 1529 *(uint16_t *)&sc->ioregs[offset] = value & 0xffff; 1530 } else if (size == 4) { 1531 *(uint32_t *)&sc->ioregs[offset] = value; 1532 } else { 1533 printf("diow: iow unknown size %d\n", size); 1534 } 1535 1536 /* 1537 * Special magic value to generate an interrupt 1538 */ 1539 if (offset == 4 && size == 4 && pci_msi_enabled(pi)) 1540 pci_generate_msi(pi, value % pci_msi_msgnum(pi)); 1541 1542 if (value == 0xabcdef) { 1543 for (i = 0; i < pci_msi_msgnum(pi); i++) 1544 pci_generate_msi(pi, i); 1545 } 1546 } 1547 1548 if (baridx == 1) { 1549 if (offset + size > DMEMSZ) { 1550 printf("diow: memw too large, offset %ld size %d\n", 1551 offset, size); 1552 return; 1553 } 1554 1555 if (size == 1) { 1556 sc->memregs[offset] = value; 1557 } else if (size == 2) { 1558 *(uint16_t *)&sc->memregs[offset] = value; 1559 } else if (size == 4) { 1560 *(uint32_t *)&sc->memregs[offset] = value; 1561 } else if (size == 8) { 1562 *(uint64_t *)&sc->memregs[offset] = value; 1563 } else { 1564 printf("diow: memw unknown size %d\n", size); 1565 } 1566 1567 /* 1568 * magic interrupt ?? 1569 */ 1570 } 1571 1572 if (baridx > 1) { 1573 printf("diow: unknown bar idx %d\n", baridx); 1574 } 1575 } 1576 1577 static uint64_t 1578 pci_emul_dior(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, int baridx, 1579 uint64_t offset, int size) 1580 { 1581 struct pci_emul_dsoftc *sc = pi->pi_arg; 1582 uint32_t value; 1583 1584 if (baridx == 0) { 1585 if (offset + size > DIOSZ) { 1586 printf("dior: ior too large, offset %ld size %d\n", 1587 offset, size); 1588 return (0); 1589 } 1590 1591 if (size == 1) { 1592 value = sc->ioregs[offset]; 1593 } else if (size == 2) { 1594 value = *(uint16_t *) &sc->ioregs[offset]; 1595 } else if (size == 4) { 1596 value = *(uint32_t *) &sc->ioregs[offset]; 1597 } else { 1598 printf("dior: ior unknown size %d\n", size); 1599 } 1600 } 1601 1602 if (baridx == 1) { 1603 if (offset + size > DMEMSZ) { 1604 printf("dior: memr too large, offset %ld size %d\n", 1605 offset, size); 1606 return (0); 1607 } 1608 1609 if (size == 1) { 1610 value = sc->memregs[offset]; 1611 } else if (size == 2) { 1612 value = *(uint16_t *) &sc->memregs[offset]; 1613 } else if (size == 4) { 1614 value = *(uint32_t *) &sc->memregs[offset]; 1615 } else if (size == 8) { 1616 value = *(uint64_t *) &sc->memregs[offset]; 1617 } else { 1618 printf("dior: ior unknown size %d\n", size); 1619 } 1620 } 1621 1622 1623 if (baridx > 1) { 1624 printf("dior: unknown bar idx %d\n", baridx); 1625 return (0); 1626 } 1627 1628 return (value); 1629 } 1630 1631 struct pci_devemu pci_dummy = { 1632 .pe_emu = "dummy", 1633 .pe_init = pci_emul_dinit, 1634 .pe_barwrite = pci_emul_diow, 1635 .pe_barread = pci_emul_dior 1636 }; 1637 PCI_EMUL_SET(pci_dummy); 1638 1639 #endif /* PCI_EMUL_TEST */ 1640