1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2011 NetApp, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 */ 30 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD$"); 33 34 #include <sys/param.h> 35 #include <sys/linker_set.h> 36 #include <sys/mman.h> 37 38 #include <ctype.h> 39 #include <err.h> 40 #include <errno.h> 41 #include <pthread.h> 42 #include <stdio.h> 43 #include <stdlib.h> 44 #include <string.h> 45 #include <strings.h> 46 #include <assert.h> 47 #include <stdbool.h> 48 #include <sysexits.h> 49 50 #include <machine/vmm.h> 51 #include <machine/vmm_snapshot.h> 52 #include <vmmapi.h> 53 54 #include "acpi.h" 55 #include "bhyverun.h" 56 #include "config.h" 57 #include "debug.h" 58 #include "inout.h" 59 #include "ioapic.h" 60 #include "mem.h" 61 #include "pci_emul.h" 62 #include "pci_irq.h" 63 #include "pci_lpc.h" 64 #include "pci_passthru.h" 65 66 #define CONF1_ADDR_PORT 0x0cf8 67 #define CONF1_DATA_PORT 0x0cfc 68 69 #define CONF1_ENABLE 0x80000000ul 70 71 #define MAXBUSES (PCI_BUSMAX + 1) 72 #define MAXSLOTS (PCI_SLOTMAX + 1) 73 #define MAXFUNCS (PCI_FUNCMAX + 1) 74 75 #define GB (1024 * 1024 * 1024UL) 76 77 struct funcinfo { 78 nvlist_t *fi_config; 79 struct pci_devemu *fi_pde; 80 struct pci_devinst *fi_devi; 81 }; 82 83 struct intxinfo { 84 int ii_count; 85 int ii_pirq_pin; 86 int ii_ioapic_irq; 87 }; 88 89 struct slotinfo { 90 struct intxinfo si_intpins[4]; 91 struct funcinfo si_funcs[MAXFUNCS]; 92 }; 93 94 struct businfo { 95 uint16_t iobase, iolimit; /* I/O window */ 96 uint32_t membase32, memlimit32; /* mmio window below 4GB */ 97 uint64_t membase64, memlimit64; /* mmio window above 4GB */ 98 struct slotinfo slotinfo[MAXSLOTS]; 99 }; 100 101 static struct businfo *pci_businfo[MAXBUSES]; 102 103 SET_DECLARE(pci_devemu_set, struct pci_devemu); 104 105 static uint64_t pci_emul_iobase; 106 static uint8_t *pci_emul_rombase; 107 static uint64_t pci_emul_romoffset; 108 static uint8_t *pci_emul_romlim; 109 static uint64_t pci_emul_membase32; 110 static uint64_t pci_emul_membase64; 111 static uint64_t pci_emul_memlim64; 112 113 struct pci_bar_allocation { 114 TAILQ_ENTRY(pci_bar_allocation) chain; 115 struct pci_devinst *pdi; 116 int idx; 117 enum pcibar_type type; 118 uint64_t size; 119 }; 120 121 static TAILQ_HEAD(pci_bar_list, pci_bar_allocation) pci_bars = 122 TAILQ_HEAD_INITIALIZER(pci_bars); 123 124 #define PCI_EMUL_IOBASE 0x2000 125 #define PCI_EMUL_IOLIMIT 0x10000 126 127 #define PCI_EMUL_ROMSIZE 0x10000000 128 129 #define PCI_EMUL_ECFG_BASE 0xE0000000 /* 3.5GB */ 130 #define PCI_EMUL_ECFG_SIZE (MAXBUSES * 1024 * 1024) /* 1MB per bus */ 131 SYSRES_MEM(PCI_EMUL_ECFG_BASE, PCI_EMUL_ECFG_SIZE); 132 133 /* 134 * OVMF always uses 0xC0000000 as base address for 32 bit PCI MMIO. Don't 135 * change this address without changing it in OVMF. 136 */ 137 #define PCI_EMUL_MEMBASE32 0xC0000000 138 #define PCI_EMUL_MEMLIMIT32 PCI_EMUL_ECFG_BASE 139 #define PCI_EMUL_MEMSIZE64 (32*GB) 140 141 static struct pci_devemu *pci_emul_finddev(const char *name); 142 static void pci_lintr_route(struct pci_devinst *pi); 143 static void pci_lintr_update(struct pci_devinst *pi); 144 static void pci_cfgrw(int in, int bus, int slot, int func, int coff, 145 int bytes, uint32_t *val); 146 147 static __inline void 148 CFGWRITE(struct pci_devinst *pi, int coff, uint32_t val, int bytes) 149 { 150 151 if (bytes == 1) 152 pci_set_cfgdata8(pi, coff, val); 153 else if (bytes == 2) 154 pci_set_cfgdata16(pi, coff, val); 155 else 156 pci_set_cfgdata32(pi, coff, val); 157 } 158 159 static __inline uint32_t 160 CFGREAD(struct pci_devinst *pi, int coff, int bytes) 161 { 162 163 if (bytes == 1) 164 return (pci_get_cfgdata8(pi, coff)); 165 else if (bytes == 2) 166 return (pci_get_cfgdata16(pi, coff)); 167 else 168 return (pci_get_cfgdata32(pi, coff)); 169 } 170 171 static int 172 is_pcir_bar(int coff) 173 { 174 return (coff >= PCIR_BAR(0) && coff < PCIR_BAR(PCI_BARMAX + 1)); 175 } 176 177 static int 178 is_pcir_bios(int coff) 179 { 180 return (coff >= PCIR_BIOS && coff < PCIR_BIOS + 4); 181 } 182 183 /* 184 * I/O access 185 */ 186 187 /* 188 * Slot options are in the form: 189 * 190 * <bus>:<slot>:<func>,<emul>[,<config>] 191 * <slot>[:<func>],<emul>[,<config>] 192 * 193 * slot is 0..31 194 * func is 0..7 195 * emul is a string describing the type of PCI device e.g. virtio-net 196 * config is an optional string, depending on the device, that can be 197 * used for configuration. 198 * Examples are: 199 * 1,virtio-net,tap0 200 * 3:0,dummy 201 */ 202 static void 203 pci_parse_slot_usage(char *aopt) 204 { 205 206 EPRINTLN("Invalid PCI slot info field \"%s\"", aopt); 207 } 208 209 /* 210 * Helper function to parse a list of comma-separated options where 211 * each option is formatted as "name[=value]". If no value is 212 * provided, the option is treated as a boolean and is given a value 213 * of true. 214 */ 215 int 216 pci_parse_legacy_config(nvlist_t *nvl, const char *opt) 217 { 218 char *config, *name, *tofree, *value; 219 220 if (opt == NULL) 221 return (0); 222 223 config = tofree = strdup(opt); 224 while ((name = strsep(&config, ",")) != NULL) { 225 value = strchr(name, '='); 226 if (value != NULL) { 227 *value = '\0'; 228 value++; 229 set_config_value_node(nvl, name, value); 230 } else 231 set_config_bool_node(nvl, name, true); 232 } 233 free(tofree); 234 return (0); 235 } 236 237 /* 238 * PCI device configuration is stored in MIBs that encode the device's 239 * location: 240 * 241 * pci.<bus>.<slot>.<func> 242 * 243 * Where "bus", "slot", and "func" are all decimal values without 244 * leading zeroes. Each valid device must have a "device" node which 245 * identifies the driver model of the device. 246 * 247 * Device backends can provide a parser for the "config" string. If 248 * a custom parser is not provided, pci_parse_legacy_config() is used 249 * to parse the string. 250 */ 251 int 252 pci_parse_slot(char *opt) 253 { 254 char node_name[sizeof("pci.XXX.XX.X")]; 255 struct pci_devemu *pde; 256 char *emul, *config, *str, *cp; 257 int error, bnum, snum, fnum; 258 nvlist_t *nvl; 259 260 error = -1; 261 str = strdup(opt); 262 263 emul = config = NULL; 264 if ((cp = strchr(str, ',')) != NULL) { 265 *cp = '\0'; 266 emul = cp + 1; 267 if ((cp = strchr(emul, ',')) != NULL) { 268 *cp = '\0'; 269 config = cp + 1; 270 } 271 } else { 272 pci_parse_slot_usage(opt); 273 goto done; 274 } 275 276 /* <bus>:<slot>:<func> */ 277 if (sscanf(str, "%d:%d:%d", &bnum, &snum, &fnum) != 3) { 278 bnum = 0; 279 /* <slot>:<func> */ 280 if (sscanf(str, "%d:%d", &snum, &fnum) != 2) { 281 fnum = 0; 282 /* <slot> */ 283 if (sscanf(str, "%d", &snum) != 1) { 284 snum = -1; 285 } 286 } 287 } 288 289 if (bnum < 0 || bnum >= MAXBUSES || snum < 0 || snum >= MAXSLOTS || 290 fnum < 0 || fnum >= MAXFUNCS) { 291 pci_parse_slot_usage(opt); 292 goto done; 293 } 294 295 pde = pci_emul_finddev(emul); 296 if (pde == NULL) { 297 EPRINTLN("pci slot %d:%d:%d: unknown device \"%s\"", bnum, snum, 298 fnum, emul); 299 goto done; 300 } 301 302 snprintf(node_name, sizeof(node_name), "pci.%d.%d.%d", bnum, snum, 303 fnum); 304 nvl = find_config_node(node_name); 305 if (nvl != NULL) { 306 EPRINTLN("pci slot %d:%d:%d already occupied!", bnum, snum, 307 fnum); 308 goto done; 309 } 310 nvl = create_config_node(node_name); 311 if (pde->pe_alias != NULL) 312 set_config_value_node(nvl, "device", pde->pe_alias); 313 else 314 set_config_value_node(nvl, "device", pde->pe_emu); 315 316 if (pde->pe_legacy_config != NULL) 317 error = pde->pe_legacy_config(nvl, config); 318 else 319 error = pci_parse_legacy_config(nvl, config); 320 done: 321 free(str); 322 return (error); 323 } 324 325 void 326 pci_print_supported_devices(void) 327 { 328 struct pci_devemu **pdpp, *pdp; 329 330 SET_FOREACH(pdpp, pci_devemu_set) { 331 pdp = *pdpp; 332 printf("%s\n", pdp->pe_emu); 333 } 334 } 335 336 uint32_t 337 pci_config_read_reg(const struct pcisel *const host_sel, nvlist_t *nvl, 338 const uint32_t reg, const uint8_t size, const uint32_t def) 339 { 340 const char *config; 341 const nvlist_t *pci_regs; 342 343 assert(size == 1 || size == 2 || size == 4); 344 345 pci_regs = find_relative_config_node(nvl, "pcireg"); 346 if (pci_regs == NULL) { 347 return def; 348 } 349 350 switch (reg) { 351 case PCIR_DEVICE: 352 config = get_config_value_node(pci_regs, "device"); 353 break; 354 case PCIR_VENDOR: 355 config = get_config_value_node(pci_regs, "vendor"); 356 break; 357 case PCIR_REVID: 358 config = get_config_value_node(pci_regs, "revid"); 359 break; 360 case PCIR_SUBVEND_0: 361 config = get_config_value_node(pci_regs, "subvendor"); 362 break; 363 case PCIR_SUBDEV_0: 364 config = get_config_value_node(pci_regs, "subdevice"); 365 break; 366 default: 367 return (-1); 368 } 369 370 if (config == NULL) { 371 return def; 372 } else if (host_sel != NULL && strcmp(config, "host") == 0) { 373 return read_config(host_sel, reg, size); 374 } else { 375 return strtol(config, NULL, 16); 376 } 377 } 378 379 static int 380 pci_valid_pba_offset(struct pci_devinst *pi, uint64_t offset) 381 { 382 383 if (offset < pi->pi_msix.pba_offset) 384 return (0); 385 386 if (offset >= pi->pi_msix.pba_offset + pi->pi_msix.pba_size) { 387 return (0); 388 } 389 390 return (1); 391 } 392 393 int 394 pci_emul_msix_twrite(struct pci_devinst *pi, uint64_t offset, int size, 395 uint64_t value) 396 { 397 int msix_entry_offset; 398 int tab_index; 399 char *dest; 400 401 /* support only 4 or 8 byte writes */ 402 if (size != 4 && size != 8) 403 return (-1); 404 405 /* 406 * Return if table index is beyond what device supports 407 */ 408 tab_index = offset / MSIX_TABLE_ENTRY_SIZE; 409 if (tab_index >= pi->pi_msix.table_count) 410 return (-1); 411 412 msix_entry_offset = offset % MSIX_TABLE_ENTRY_SIZE; 413 414 /* support only aligned writes */ 415 if ((msix_entry_offset % size) != 0) 416 return (-1); 417 418 dest = (char *)(pi->pi_msix.table + tab_index); 419 dest += msix_entry_offset; 420 421 if (size == 4) 422 *((uint32_t *)dest) = value; 423 else 424 *((uint64_t *)dest) = value; 425 426 return (0); 427 } 428 429 uint64_t 430 pci_emul_msix_tread(struct pci_devinst *pi, uint64_t offset, int size) 431 { 432 char *dest; 433 int msix_entry_offset; 434 int tab_index; 435 uint64_t retval = ~0; 436 437 /* 438 * The PCI standard only allows 4 and 8 byte accesses to the MSI-X 439 * table but we also allow 1 byte access to accommodate reads from 440 * ddb. 441 */ 442 if (size != 1 && size != 4 && size != 8) 443 return (retval); 444 445 msix_entry_offset = offset % MSIX_TABLE_ENTRY_SIZE; 446 447 /* support only aligned reads */ 448 if ((msix_entry_offset % size) != 0) { 449 return (retval); 450 } 451 452 tab_index = offset / MSIX_TABLE_ENTRY_SIZE; 453 454 if (tab_index < pi->pi_msix.table_count) { 455 /* valid MSI-X Table access */ 456 dest = (char *)(pi->pi_msix.table + tab_index); 457 dest += msix_entry_offset; 458 459 if (size == 1) 460 retval = *((uint8_t *)dest); 461 else if (size == 4) 462 retval = *((uint32_t *)dest); 463 else 464 retval = *((uint64_t *)dest); 465 } else if (pci_valid_pba_offset(pi, offset)) { 466 /* return 0 for PBA access */ 467 retval = 0; 468 } 469 470 return (retval); 471 } 472 473 int 474 pci_msix_table_bar(struct pci_devinst *pi) 475 { 476 477 if (pi->pi_msix.table != NULL) 478 return (pi->pi_msix.table_bar); 479 else 480 return (-1); 481 } 482 483 int 484 pci_msix_pba_bar(struct pci_devinst *pi) 485 { 486 487 if (pi->pi_msix.table != NULL) 488 return (pi->pi_msix.pba_bar); 489 else 490 return (-1); 491 } 492 493 static int 494 pci_emul_io_handler(struct vmctx *ctx __unused, int in, int port, 495 int bytes, uint32_t *eax, void *arg) 496 { 497 struct pci_devinst *pdi = arg; 498 struct pci_devemu *pe = pdi->pi_d; 499 uint64_t offset; 500 int i; 501 502 assert(port >= 0); 503 504 for (i = 0; i <= PCI_BARMAX; i++) { 505 if (pdi->pi_bar[i].type == PCIBAR_IO && 506 (uint64_t)port >= pdi->pi_bar[i].addr && 507 (uint64_t)port + bytes <= 508 pdi->pi_bar[i].addr + pdi->pi_bar[i].size) { 509 offset = port - pdi->pi_bar[i].addr; 510 if (in) 511 *eax = (*pe->pe_barread)(pdi, i, 512 offset, bytes); 513 else 514 (*pe->pe_barwrite)(pdi, i, offset, 515 bytes, *eax); 516 return (0); 517 } 518 } 519 return (-1); 520 } 521 522 static int 523 pci_emul_mem_handler(struct vcpu *vcpu __unused, int dir, 524 uint64_t addr, int size, uint64_t *val, void *arg1, long arg2) 525 { 526 struct pci_devinst *pdi = arg1; 527 struct pci_devemu *pe = pdi->pi_d; 528 uint64_t offset; 529 int bidx = (int) arg2; 530 531 assert(bidx <= PCI_BARMAX); 532 assert(pdi->pi_bar[bidx].type == PCIBAR_MEM32 || 533 pdi->pi_bar[bidx].type == PCIBAR_MEM64); 534 assert(addr >= pdi->pi_bar[bidx].addr && 535 addr + size <= pdi->pi_bar[bidx].addr + pdi->pi_bar[bidx].size); 536 537 offset = addr - pdi->pi_bar[bidx].addr; 538 539 if (dir == MEM_F_WRITE) { 540 if (size == 8) { 541 (*pe->pe_barwrite)(pdi, bidx, offset, 542 4, *val & 0xffffffff); 543 (*pe->pe_barwrite)(pdi, bidx, offset + 4, 544 4, *val >> 32); 545 } else { 546 (*pe->pe_barwrite)(pdi, bidx, offset, 547 size, *val); 548 } 549 } else { 550 if (size == 8) { 551 *val = (*pe->pe_barread)(pdi, bidx, 552 offset, 4); 553 *val |= (*pe->pe_barread)(pdi, bidx, 554 offset + 4, 4) << 32; 555 } else { 556 *val = (*pe->pe_barread)(pdi, bidx, 557 offset, size); 558 } 559 } 560 561 return (0); 562 } 563 564 565 static int 566 pci_emul_alloc_resource(uint64_t *baseptr, uint64_t limit, uint64_t size, 567 uint64_t *addr) 568 { 569 uint64_t base; 570 571 assert((size & (size - 1)) == 0); /* must be a power of 2 */ 572 573 base = roundup2(*baseptr, size); 574 575 if (base + size <= limit) { 576 *addr = base; 577 *baseptr = base + size; 578 return (0); 579 } else 580 return (-1); 581 } 582 583 /* 584 * Register (or unregister) the MMIO or I/O region associated with the BAR 585 * register 'idx' of an emulated pci device. 586 */ 587 static void 588 modify_bar_registration(struct pci_devinst *pi, int idx, int registration) 589 { 590 struct pci_devemu *pe; 591 int error; 592 struct inout_port iop; 593 struct mem_range mr; 594 595 pe = pi->pi_d; 596 switch (pi->pi_bar[idx].type) { 597 case PCIBAR_IO: 598 bzero(&iop, sizeof(struct inout_port)); 599 iop.name = pi->pi_name; 600 iop.port = pi->pi_bar[idx].addr; 601 iop.size = pi->pi_bar[idx].size; 602 if (registration) { 603 iop.flags = IOPORT_F_INOUT; 604 iop.handler = pci_emul_io_handler; 605 iop.arg = pi; 606 error = register_inout(&iop); 607 } else 608 error = unregister_inout(&iop); 609 if (pe->pe_baraddr != NULL) 610 (*pe->pe_baraddr)(pi, idx, registration, 611 pi->pi_bar[idx].addr); 612 break; 613 case PCIBAR_MEM32: 614 case PCIBAR_MEM64: 615 bzero(&mr, sizeof(struct mem_range)); 616 mr.name = pi->pi_name; 617 mr.base = pi->pi_bar[idx].addr; 618 mr.size = pi->pi_bar[idx].size; 619 if (registration) { 620 mr.flags = MEM_F_RW; 621 mr.handler = pci_emul_mem_handler; 622 mr.arg1 = pi; 623 mr.arg2 = idx; 624 error = register_mem(&mr); 625 } else 626 error = unregister_mem(&mr); 627 if (pe->pe_baraddr != NULL) 628 (*pe->pe_baraddr)(pi, idx, registration, 629 pi->pi_bar[idx].addr); 630 break; 631 case PCIBAR_ROM: 632 error = 0; 633 if (pe->pe_baraddr != NULL) 634 (*pe->pe_baraddr)(pi, idx, registration, 635 pi->pi_bar[idx].addr); 636 break; 637 default: 638 error = EINVAL; 639 break; 640 } 641 assert(error == 0); 642 } 643 644 static void 645 unregister_bar(struct pci_devinst *pi, int idx) 646 { 647 648 modify_bar_registration(pi, idx, 0); 649 } 650 651 static void 652 register_bar(struct pci_devinst *pi, int idx) 653 { 654 655 modify_bar_registration(pi, idx, 1); 656 } 657 658 /* Is the ROM enabled for the emulated pci device? */ 659 static int 660 romen(struct pci_devinst *pi) 661 { 662 return (pi->pi_bar[PCI_ROM_IDX].lobits & PCIM_BIOS_ENABLE) == 663 PCIM_BIOS_ENABLE; 664 } 665 666 /* Are we decoding i/o port accesses for the emulated pci device? */ 667 static int 668 porten(struct pci_devinst *pi) 669 { 670 uint16_t cmd; 671 672 cmd = pci_get_cfgdata16(pi, PCIR_COMMAND); 673 674 return (cmd & PCIM_CMD_PORTEN); 675 } 676 677 /* Are we decoding memory accesses for the emulated pci device? */ 678 static int 679 memen(struct pci_devinst *pi) 680 { 681 uint16_t cmd; 682 683 cmd = pci_get_cfgdata16(pi, PCIR_COMMAND); 684 685 return (cmd & PCIM_CMD_MEMEN); 686 } 687 688 /* 689 * Update the MMIO or I/O address that is decoded by the BAR register. 690 * 691 * If the pci device has enabled the address space decoding then intercept 692 * the address range decoded by the BAR register. 693 */ 694 static void 695 update_bar_address(struct pci_devinst *pi, uint64_t addr, int idx, int type) 696 { 697 int decode; 698 699 if (pi->pi_bar[idx].type == PCIBAR_IO) 700 decode = porten(pi); 701 else 702 decode = memen(pi); 703 704 if (decode) 705 unregister_bar(pi, idx); 706 707 switch (type) { 708 case PCIBAR_IO: 709 case PCIBAR_MEM32: 710 pi->pi_bar[idx].addr = addr; 711 break; 712 case PCIBAR_MEM64: 713 pi->pi_bar[idx].addr &= ~0xffffffffUL; 714 pi->pi_bar[idx].addr |= addr; 715 break; 716 case PCIBAR_MEMHI64: 717 pi->pi_bar[idx].addr &= 0xffffffff; 718 pi->pi_bar[idx].addr |= addr; 719 break; 720 default: 721 assert(0); 722 } 723 724 if (decode) 725 register_bar(pi, idx); 726 } 727 728 int 729 pci_emul_alloc_bar(struct pci_devinst *pdi, int idx, enum pcibar_type type, 730 uint64_t size) 731 { 732 assert((type == PCIBAR_ROM) || (idx >= 0 && idx <= PCI_BARMAX)); 733 assert((type != PCIBAR_ROM) || (idx == PCI_ROM_IDX)); 734 735 if ((size & (size - 1)) != 0) 736 size = 1UL << flsl(size); /* round up to a power of 2 */ 737 738 /* Enforce minimum BAR sizes required by the PCI standard */ 739 if (type == PCIBAR_IO) { 740 if (size < 4) 741 size = 4; 742 } else if (type == PCIBAR_ROM) { 743 if (size < ~PCIM_BIOS_ADDR_MASK + 1) 744 size = ~PCIM_BIOS_ADDR_MASK + 1; 745 } else { 746 if (size < 16) 747 size = 16; 748 } 749 750 /* 751 * To reduce fragmentation of the MMIO space, we allocate the BARs by 752 * size. Therefore, don't allocate the BAR yet. We create a list of all 753 * BAR allocation which is sorted by BAR size. When all PCI devices are 754 * initialized, we will assign an address to the BARs. 755 */ 756 757 /* create a new list entry */ 758 struct pci_bar_allocation *const new_bar = malloc(sizeof(*new_bar)); 759 memset(new_bar, 0, sizeof(*new_bar)); 760 new_bar->pdi = pdi; 761 new_bar->idx = idx; 762 new_bar->type = type; 763 new_bar->size = size; 764 765 /* 766 * Search for a BAR which size is lower than the size of our newly 767 * allocated BAR. 768 */ 769 struct pci_bar_allocation *bar = NULL; 770 TAILQ_FOREACH(bar, &pci_bars, chain) { 771 if (bar->size < size) { 772 break; 773 } 774 } 775 776 if (bar == NULL) { 777 /* 778 * Either the list is empty or new BAR is the smallest BAR of 779 * the list. Append it to the end of our list. 780 */ 781 TAILQ_INSERT_TAIL(&pci_bars, new_bar, chain); 782 } else { 783 /* 784 * The found BAR is smaller than our new BAR. For that reason, 785 * insert our new BAR before the found BAR. 786 */ 787 TAILQ_INSERT_BEFORE(bar, new_bar, chain); 788 } 789 790 /* 791 * pci_passthru devices synchronize their physical and virtual command 792 * register on init. For that reason, the virtual cmd reg should be 793 * updated as early as possible. 794 */ 795 uint16_t enbit = 0; 796 switch (type) { 797 case PCIBAR_IO: 798 enbit = PCIM_CMD_PORTEN; 799 break; 800 case PCIBAR_MEM64: 801 case PCIBAR_MEM32: 802 enbit = PCIM_CMD_MEMEN; 803 break; 804 default: 805 enbit = 0; 806 break; 807 } 808 809 const uint16_t cmd = pci_get_cfgdata16(pdi, PCIR_COMMAND); 810 pci_set_cfgdata16(pdi, PCIR_COMMAND, cmd | enbit); 811 812 return (0); 813 } 814 815 static int 816 pci_emul_assign_bar(struct pci_devinst *const pdi, const int idx, 817 const enum pcibar_type type, const uint64_t size) 818 { 819 int error; 820 uint64_t *baseptr, limit, addr, mask, lobits, bar; 821 822 switch (type) { 823 case PCIBAR_NONE: 824 baseptr = NULL; 825 addr = mask = lobits = 0; 826 break; 827 case PCIBAR_IO: 828 baseptr = &pci_emul_iobase; 829 limit = PCI_EMUL_IOLIMIT; 830 mask = PCIM_BAR_IO_BASE; 831 lobits = PCIM_BAR_IO_SPACE; 832 break; 833 case PCIBAR_MEM64: 834 /* 835 * XXX 836 * Some drivers do not work well if the 64-bit BAR is allocated 837 * above 4GB. Allow for this by allocating small requests under 838 * 4GB unless then allocation size is larger than some arbitrary 839 * number (128MB currently). 840 */ 841 if (size > 128 * 1024 * 1024) { 842 baseptr = &pci_emul_membase64; 843 limit = pci_emul_memlim64; 844 mask = PCIM_BAR_MEM_BASE; 845 lobits = PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_64 | 846 PCIM_BAR_MEM_PREFETCH; 847 } else { 848 baseptr = &pci_emul_membase32; 849 limit = PCI_EMUL_MEMLIMIT32; 850 mask = PCIM_BAR_MEM_BASE; 851 lobits = PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_64; 852 } 853 break; 854 case PCIBAR_MEM32: 855 baseptr = &pci_emul_membase32; 856 limit = PCI_EMUL_MEMLIMIT32; 857 mask = PCIM_BAR_MEM_BASE; 858 lobits = PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_32; 859 break; 860 case PCIBAR_ROM: 861 /* do not claim memory for ROM. OVMF will do it for us. */ 862 baseptr = NULL; 863 limit = 0; 864 mask = PCIM_BIOS_ADDR_MASK; 865 lobits = 0; 866 break; 867 default: 868 printf("pci_emul_alloc_base: invalid bar type %d\n", type); 869 assert(0); 870 } 871 872 if (baseptr != NULL) { 873 error = pci_emul_alloc_resource(baseptr, limit, size, &addr); 874 if (error != 0) 875 return (error); 876 } else { 877 addr = 0; 878 } 879 880 pdi->pi_bar[idx].type = type; 881 pdi->pi_bar[idx].addr = addr; 882 pdi->pi_bar[idx].size = size; 883 /* 884 * passthru devices are using same lobits as physical device they set 885 * this property 886 */ 887 if (pdi->pi_bar[idx].lobits != 0) { 888 lobits = pdi->pi_bar[idx].lobits; 889 } else { 890 pdi->pi_bar[idx].lobits = lobits; 891 } 892 893 /* Initialize the BAR register in config space */ 894 bar = (addr & mask) | lobits; 895 pci_set_cfgdata32(pdi, PCIR_BAR(idx), bar); 896 897 if (type == PCIBAR_MEM64) { 898 assert(idx + 1 <= PCI_BARMAX); 899 pdi->pi_bar[idx + 1].type = PCIBAR_MEMHI64; 900 pci_set_cfgdata32(pdi, PCIR_BAR(idx + 1), bar >> 32); 901 } 902 903 if (type != PCIBAR_ROM) { 904 register_bar(pdi, idx); 905 } 906 907 return (0); 908 } 909 910 int 911 pci_emul_alloc_rom(struct pci_devinst *const pdi, const uint64_t size, 912 void **const addr) 913 { 914 /* allocate ROM space once on first call */ 915 if (pci_emul_rombase == 0) { 916 pci_emul_rombase = vm_create_devmem(pdi->pi_vmctx, VM_PCIROM, 917 "pcirom", PCI_EMUL_ROMSIZE); 918 if (pci_emul_rombase == MAP_FAILED) { 919 warnx("%s: failed to create rom segment", __func__); 920 return (-1); 921 } 922 pci_emul_romlim = pci_emul_rombase + PCI_EMUL_ROMSIZE; 923 pci_emul_romoffset = 0; 924 } 925 926 /* ROM size should be a power of 2 and greater than 2 KB */ 927 const uint64_t rom_size = MAX(1UL << flsl(size), 928 ~PCIM_BIOS_ADDR_MASK + 1); 929 930 /* check if ROM fits into ROM space */ 931 if (pci_emul_romoffset + rom_size > PCI_EMUL_ROMSIZE) { 932 warnx("%s: no space left in rom segment:", __func__); 933 warnx("%16lu bytes left", 934 PCI_EMUL_ROMSIZE - pci_emul_romoffset); 935 warnx("%16lu bytes required by %d/%d/%d", rom_size, pdi->pi_bus, 936 pdi->pi_slot, pdi->pi_func); 937 return (-1); 938 } 939 940 /* allocate ROM BAR */ 941 const int error = pci_emul_alloc_bar(pdi, PCI_ROM_IDX, PCIBAR_ROM, 942 rom_size); 943 if (error) 944 return error; 945 946 /* return address */ 947 *addr = pci_emul_rombase + pci_emul_romoffset; 948 949 /* save offset into ROM Space */ 950 pdi->pi_romoffset = pci_emul_romoffset; 951 952 /* increase offset for next ROM */ 953 pci_emul_romoffset += rom_size; 954 955 return (0); 956 } 957 958 #define CAP_START_OFFSET 0x40 959 static int 960 pci_emul_add_capability(struct pci_devinst *pi, u_char *capdata, int caplen) 961 { 962 int i, capoff, reallen; 963 uint16_t sts; 964 965 assert(caplen > 0); 966 967 reallen = roundup2(caplen, 4); /* dword aligned */ 968 969 sts = pci_get_cfgdata16(pi, PCIR_STATUS); 970 if ((sts & PCIM_STATUS_CAPPRESENT) == 0) 971 capoff = CAP_START_OFFSET; 972 else 973 capoff = pi->pi_capend + 1; 974 975 /* Check if we have enough space */ 976 if (capoff + reallen > PCI_REGMAX + 1) 977 return (-1); 978 979 /* Set the previous capability pointer */ 980 if ((sts & PCIM_STATUS_CAPPRESENT) == 0) { 981 pci_set_cfgdata8(pi, PCIR_CAP_PTR, capoff); 982 pci_set_cfgdata16(pi, PCIR_STATUS, sts|PCIM_STATUS_CAPPRESENT); 983 } else 984 pci_set_cfgdata8(pi, pi->pi_prevcap + 1, capoff); 985 986 /* Copy the capability */ 987 for (i = 0; i < caplen; i++) 988 pci_set_cfgdata8(pi, capoff + i, capdata[i]); 989 990 /* Set the next capability pointer */ 991 pci_set_cfgdata8(pi, capoff + 1, 0); 992 993 pi->pi_prevcap = capoff; 994 pi->pi_capend = capoff + reallen - 1; 995 return (0); 996 } 997 998 static struct pci_devemu * 999 pci_emul_finddev(const char *name) 1000 { 1001 struct pci_devemu **pdpp, *pdp; 1002 1003 SET_FOREACH(pdpp, pci_devemu_set) { 1004 pdp = *pdpp; 1005 if (!strcmp(pdp->pe_emu, name)) { 1006 return (pdp); 1007 } 1008 } 1009 1010 return (NULL); 1011 } 1012 1013 static int 1014 pci_emul_init(struct vmctx *ctx, struct pci_devemu *pde, int bus, int slot, 1015 int func, struct funcinfo *fi) 1016 { 1017 struct pci_devinst *pdi; 1018 int err; 1019 1020 pdi = calloc(1, sizeof(struct pci_devinst)); 1021 1022 pdi->pi_vmctx = ctx; 1023 pdi->pi_bus = bus; 1024 pdi->pi_slot = slot; 1025 pdi->pi_func = func; 1026 pthread_mutex_init(&pdi->pi_lintr.lock, NULL); 1027 pdi->pi_lintr.pin = 0; 1028 pdi->pi_lintr.state = IDLE; 1029 pdi->pi_lintr.pirq_pin = 0; 1030 pdi->pi_lintr.ioapic_irq = 0; 1031 pdi->pi_d = pde; 1032 snprintf(pdi->pi_name, PI_NAMESZ, "%s@pci.%d.%d.%d", pde->pe_emu, bus, 1033 slot, func); 1034 1035 /* Disable legacy interrupts */ 1036 pci_set_cfgdata8(pdi, PCIR_INTLINE, 255); 1037 pci_set_cfgdata8(pdi, PCIR_INTPIN, 0); 1038 1039 pci_set_cfgdata8(pdi, PCIR_COMMAND, PCIM_CMD_BUSMASTEREN); 1040 1041 err = (*pde->pe_init)(pdi, fi->fi_config); 1042 if (err == 0) 1043 fi->fi_devi = pdi; 1044 else 1045 free(pdi); 1046 1047 return (err); 1048 } 1049 1050 void 1051 pci_populate_msicap(struct msicap *msicap, int msgnum, int nextptr) 1052 { 1053 int mmc; 1054 1055 /* Number of msi messages must be a power of 2 between 1 and 32 */ 1056 assert((msgnum & (msgnum - 1)) == 0 && msgnum >= 1 && msgnum <= 32); 1057 mmc = ffs(msgnum) - 1; 1058 1059 bzero(msicap, sizeof(struct msicap)); 1060 msicap->capid = PCIY_MSI; 1061 msicap->nextptr = nextptr; 1062 msicap->msgctrl = PCIM_MSICTRL_64BIT | (mmc << 1); 1063 } 1064 1065 int 1066 pci_emul_add_msicap(struct pci_devinst *pi, int msgnum) 1067 { 1068 struct msicap msicap; 1069 1070 pci_populate_msicap(&msicap, msgnum, 0); 1071 1072 return (pci_emul_add_capability(pi, (u_char *)&msicap, sizeof(msicap))); 1073 } 1074 1075 static void 1076 pci_populate_msixcap(struct msixcap *msixcap, int msgnum, int barnum, 1077 uint32_t msix_tab_size) 1078 { 1079 1080 assert(msix_tab_size % 4096 == 0); 1081 1082 bzero(msixcap, sizeof(struct msixcap)); 1083 msixcap->capid = PCIY_MSIX; 1084 1085 /* 1086 * Message Control Register, all fields set to 1087 * zero except for the Table Size. 1088 * Note: Table size N is encoded as N-1 1089 */ 1090 msixcap->msgctrl = msgnum - 1; 1091 1092 /* 1093 * MSI-X BAR setup: 1094 * - MSI-X table start at offset 0 1095 * - PBA table starts at a 4K aligned offset after the MSI-X table 1096 */ 1097 msixcap->table_info = barnum & PCIM_MSIX_BIR_MASK; 1098 msixcap->pba_info = msix_tab_size | (barnum & PCIM_MSIX_BIR_MASK); 1099 } 1100 1101 static void 1102 pci_msix_table_init(struct pci_devinst *pi, int table_entries) 1103 { 1104 int i, table_size; 1105 1106 assert(table_entries > 0); 1107 assert(table_entries <= MAX_MSIX_TABLE_ENTRIES); 1108 1109 table_size = table_entries * MSIX_TABLE_ENTRY_SIZE; 1110 pi->pi_msix.table = calloc(1, table_size); 1111 1112 /* set mask bit of vector control register */ 1113 for (i = 0; i < table_entries; i++) 1114 pi->pi_msix.table[i].vector_control |= PCIM_MSIX_VCTRL_MASK; 1115 } 1116 1117 int 1118 pci_emul_add_msixcap(struct pci_devinst *pi, int msgnum, int barnum) 1119 { 1120 uint32_t tab_size; 1121 struct msixcap msixcap; 1122 1123 assert(msgnum >= 1 && msgnum <= MAX_MSIX_TABLE_ENTRIES); 1124 assert(barnum >= 0 && barnum <= PCIR_MAX_BAR_0); 1125 1126 tab_size = msgnum * MSIX_TABLE_ENTRY_SIZE; 1127 1128 /* Align table size to nearest 4K */ 1129 tab_size = roundup2(tab_size, 4096); 1130 1131 pi->pi_msix.table_bar = barnum; 1132 pi->pi_msix.pba_bar = barnum; 1133 pi->pi_msix.table_offset = 0; 1134 pi->pi_msix.table_count = msgnum; 1135 pi->pi_msix.pba_offset = tab_size; 1136 pi->pi_msix.pba_size = PBA_SIZE(msgnum); 1137 1138 pci_msix_table_init(pi, msgnum); 1139 1140 pci_populate_msixcap(&msixcap, msgnum, barnum, tab_size); 1141 1142 /* allocate memory for MSI-X Table and PBA */ 1143 pci_emul_alloc_bar(pi, barnum, PCIBAR_MEM32, 1144 tab_size + pi->pi_msix.pba_size); 1145 1146 return (pci_emul_add_capability(pi, (u_char *)&msixcap, 1147 sizeof(msixcap))); 1148 } 1149 1150 static void 1151 msixcap_cfgwrite(struct pci_devinst *pi, int capoff, int offset, 1152 int bytes, uint32_t val) 1153 { 1154 uint16_t msgctrl, rwmask; 1155 int off; 1156 1157 off = offset - capoff; 1158 /* Message Control Register */ 1159 if (off == 2 && bytes == 2) { 1160 rwmask = PCIM_MSIXCTRL_MSIX_ENABLE | PCIM_MSIXCTRL_FUNCTION_MASK; 1161 msgctrl = pci_get_cfgdata16(pi, offset); 1162 msgctrl &= ~rwmask; 1163 msgctrl |= val & rwmask; 1164 val = msgctrl; 1165 1166 pi->pi_msix.enabled = val & PCIM_MSIXCTRL_MSIX_ENABLE; 1167 pi->pi_msix.function_mask = val & PCIM_MSIXCTRL_FUNCTION_MASK; 1168 pci_lintr_update(pi); 1169 } 1170 1171 CFGWRITE(pi, offset, val, bytes); 1172 } 1173 1174 static void 1175 msicap_cfgwrite(struct pci_devinst *pi, int capoff, int offset, 1176 int bytes, uint32_t val) 1177 { 1178 uint16_t msgctrl, rwmask, msgdata, mme; 1179 uint32_t addrlo; 1180 1181 /* 1182 * If guest is writing to the message control register make sure 1183 * we do not overwrite read-only fields. 1184 */ 1185 if ((offset - capoff) == 2 && bytes == 2) { 1186 rwmask = PCIM_MSICTRL_MME_MASK | PCIM_MSICTRL_MSI_ENABLE; 1187 msgctrl = pci_get_cfgdata16(pi, offset); 1188 msgctrl &= ~rwmask; 1189 msgctrl |= val & rwmask; 1190 val = msgctrl; 1191 } 1192 CFGWRITE(pi, offset, val, bytes); 1193 1194 msgctrl = pci_get_cfgdata16(pi, capoff + 2); 1195 addrlo = pci_get_cfgdata32(pi, capoff + 4); 1196 if (msgctrl & PCIM_MSICTRL_64BIT) 1197 msgdata = pci_get_cfgdata16(pi, capoff + 12); 1198 else 1199 msgdata = pci_get_cfgdata16(pi, capoff + 8); 1200 1201 mme = msgctrl & PCIM_MSICTRL_MME_MASK; 1202 pi->pi_msi.enabled = msgctrl & PCIM_MSICTRL_MSI_ENABLE ? 1 : 0; 1203 if (pi->pi_msi.enabled) { 1204 pi->pi_msi.addr = addrlo; 1205 pi->pi_msi.msg_data = msgdata; 1206 pi->pi_msi.maxmsgnum = 1 << (mme >> 4); 1207 } else { 1208 pi->pi_msi.maxmsgnum = 0; 1209 } 1210 pci_lintr_update(pi); 1211 } 1212 1213 static void 1214 pciecap_cfgwrite(struct pci_devinst *pi, int capoff __unused, int offset, 1215 int bytes, uint32_t val) 1216 { 1217 1218 /* XXX don't write to the readonly parts */ 1219 CFGWRITE(pi, offset, val, bytes); 1220 } 1221 1222 #define PCIECAP_VERSION 0x2 1223 int 1224 pci_emul_add_pciecap(struct pci_devinst *pi, int type) 1225 { 1226 int err; 1227 struct pciecap pciecap; 1228 1229 bzero(&pciecap, sizeof(pciecap)); 1230 1231 /* 1232 * Use the integrated endpoint type for endpoints on a root complex bus. 1233 * 1234 * NB: bhyve currently only supports a single PCI bus that is the root 1235 * complex bus, so all endpoints are integrated. 1236 */ 1237 if ((type == PCIEM_TYPE_ENDPOINT) && (pi->pi_bus == 0)) 1238 type = PCIEM_TYPE_ROOT_INT_EP; 1239 1240 pciecap.capid = PCIY_EXPRESS; 1241 pciecap.pcie_capabilities = PCIECAP_VERSION | type; 1242 if (type != PCIEM_TYPE_ROOT_INT_EP) { 1243 pciecap.link_capabilities = 0x411; /* gen1, x1 */ 1244 pciecap.link_status = 0x11; /* gen1, x1 */ 1245 } 1246 1247 err = pci_emul_add_capability(pi, (u_char *)&pciecap, sizeof(pciecap)); 1248 return (err); 1249 } 1250 1251 /* 1252 * This function assumes that 'coff' is in the capabilities region of the 1253 * config space. A capoff parameter of zero will force a search for the 1254 * offset and type. 1255 */ 1256 void 1257 pci_emul_capwrite(struct pci_devinst *pi, int offset, int bytes, uint32_t val, 1258 uint8_t capoff, int capid) 1259 { 1260 uint8_t nextoff; 1261 1262 /* Do not allow un-aligned writes */ 1263 if ((offset & (bytes - 1)) != 0) 1264 return; 1265 1266 if (capoff == 0) { 1267 /* Find the capability that we want to update */ 1268 capoff = CAP_START_OFFSET; 1269 while (1) { 1270 nextoff = pci_get_cfgdata8(pi, capoff + 1); 1271 if (nextoff == 0) 1272 break; 1273 if (offset >= capoff && offset < nextoff) 1274 break; 1275 1276 capoff = nextoff; 1277 } 1278 assert(offset >= capoff); 1279 capid = pci_get_cfgdata8(pi, capoff); 1280 } 1281 1282 /* 1283 * Capability ID and Next Capability Pointer are readonly. 1284 * However, some o/s's do 4-byte writes that include these. 1285 * For this case, trim the write back to 2 bytes and adjust 1286 * the data. 1287 */ 1288 if (offset == capoff || offset == capoff + 1) { 1289 if (offset == capoff && bytes == 4) { 1290 bytes = 2; 1291 offset += 2; 1292 val >>= 16; 1293 } else 1294 return; 1295 } 1296 1297 switch (capid) { 1298 case PCIY_MSI: 1299 msicap_cfgwrite(pi, capoff, offset, bytes, val); 1300 break; 1301 case PCIY_MSIX: 1302 msixcap_cfgwrite(pi, capoff, offset, bytes, val); 1303 break; 1304 case PCIY_EXPRESS: 1305 pciecap_cfgwrite(pi, capoff, offset, bytes, val); 1306 break; 1307 default: 1308 break; 1309 } 1310 } 1311 1312 static int 1313 pci_emul_iscap(struct pci_devinst *pi, int offset) 1314 { 1315 uint16_t sts; 1316 1317 sts = pci_get_cfgdata16(pi, PCIR_STATUS); 1318 if ((sts & PCIM_STATUS_CAPPRESENT) != 0) { 1319 if (offset >= CAP_START_OFFSET && offset <= pi->pi_capend) 1320 return (1); 1321 } 1322 return (0); 1323 } 1324 1325 static int 1326 pci_emul_fallback_handler(struct vcpu *vcpu __unused, int dir, 1327 uint64_t addr __unused, int size __unused, uint64_t *val, 1328 void *arg1 __unused, long arg2 __unused) 1329 { 1330 /* 1331 * Ignore writes; return 0xff's for reads. The mem read code 1332 * will take care of truncating to the correct size. 1333 */ 1334 if (dir == MEM_F_READ) { 1335 *val = 0xffffffffffffffff; 1336 } 1337 1338 return (0); 1339 } 1340 1341 static int 1342 pci_emul_ecfg_handler(struct vcpu *vcpu __unused, int dir, uint64_t addr, 1343 int bytes, uint64_t *val, void *arg1 __unused, long arg2 __unused) 1344 { 1345 int bus, slot, func, coff, in; 1346 1347 coff = addr & 0xfff; 1348 func = (addr >> 12) & 0x7; 1349 slot = (addr >> 15) & 0x1f; 1350 bus = (addr >> 20) & 0xff; 1351 in = (dir == MEM_F_READ); 1352 if (in) 1353 *val = ~0UL; 1354 pci_cfgrw(in, bus, slot, func, coff, bytes, (uint32_t *)val); 1355 return (0); 1356 } 1357 1358 uint64_t 1359 pci_ecfg_base(void) 1360 { 1361 1362 return (PCI_EMUL_ECFG_BASE); 1363 } 1364 1365 #define BUSIO_ROUNDUP 32 1366 #define BUSMEM32_ROUNDUP (1024 * 1024) 1367 #define BUSMEM64_ROUNDUP (512 * 1024 * 1024) 1368 1369 int 1370 init_pci(struct vmctx *ctx) 1371 { 1372 char node_name[sizeof("pci.XXX.XX.X")]; 1373 struct mem_range mr; 1374 struct pci_devemu *pde; 1375 struct businfo *bi; 1376 struct slotinfo *si; 1377 struct funcinfo *fi; 1378 nvlist_t *nvl; 1379 const char *emul; 1380 size_t lowmem; 1381 int bus, slot, func; 1382 int error; 1383 1384 if (vm_get_lowmem_limit(ctx) > PCI_EMUL_MEMBASE32) 1385 errx(EX_OSERR, "Invalid lowmem limit"); 1386 1387 pci_emul_iobase = PCI_EMUL_IOBASE; 1388 pci_emul_membase32 = PCI_EMUL_MEMBASE32; 1389 1390 pci_emul_membase64 = 4*GB + vm_get_highmem_size(ctx); 1391 pci_emul_membase64 = roundup2(pci_emul_membase64, PCI_EMUL_MEMSIZE64); 1392 pci_emul_memlim64 = pci_emul_membase64 + PCI_EMUL_MEMSIZE64; 1393 1394 for (bus = 0; bus < MAXBUSES; bus++) { 1395 snprintf(node_name, sizeof(node_name), "pci.%d", bus); 1396 nvl = find_config_node(node_name); 1397 if (nvl == NULL) 1398 continue; 1399 pci_businfo[bus] = calloc(1, sizeof(struct businfo)); 1400 bi = pci_businfo[bus]; 1401 1402 /* 1403 * Keep track of the i/o and memory resources allocated to 1404 * this bus. 1405 */ 1406 bi->iobase = pci_emul_iobase; 1407 bi->membase32 = pci_emul_membase32; 1408 bi->membase64 = pci_emul_membase64; 1409 1410 /* first run: init devices */ 1411 for (slot = 0; slot < MAXSLOTS; slot++) { 1412 si = &bi->slotinfo[slot]; 1413 for (func = 0; func < MAXFUNCS; func++) { 1414 fi = &si->si_funcs[func]; 1415 snprintf(node_name, sizeof(node_name), 1416 "pci.%d.%d.%d", bus, slot, func); 1417 nvl = find_config_node(node_name); 1418 if (nvl == NULL) 1419 continue; 1420 1421 fi->fi_config = nvl; 1422 emul = get_config_value_node(nvl, "device"); 1423 if (emul == NULL) { 1424 EPRINTLN("pci slot %d:%d:%d: missing " 1425 "\"device\" value", bus, slot, func); 1426 return (EINVAL); 1427 } 1428 pde = pci_emul_finddev(emul); 1429 if (pde == NULL) { 1430 EPRINTLN("pci slot %d:%d:%d: unknown " 1431 "device \"%s\"", bus, slot, func, 1432 emul); 1433 return (EINVAL); 1434 } 1435 if (pde->pe_alias != NULL) { 1436 EPRINTLN("pci slot %d:%d:%d: legacy " 1437 "device \"%s\", use \"%s\" instead", 1438 bus, slot, func, emul, 1439 pde->pe_alias); 1440 return (EINVAL); 1441 } 1442 fi->fi_pde = pde; 1443 error = pci_emul_init(ctx, pde, bus, slot, 1444 func, fi); 1445 if (error) 1446 return (error); 1447 } 1448 } 1449 1450 /* second run: assign BARs and free list */ 1451 struct pci_bar_allocation *bar; 1452 struct pci_bar_allocation *bar_tmp; 1453 TAILQ_FOREACH_SAFE(bar, &pci_bars, chain, bar_tmp) { 1454 pci_emul_assign_bar(bar->pdi, bar->idx, bar->type, 1455 bar->size); 1456 free(bar); 1457 } 1458 TAILQ_INIT(&pci_bars); 1459 1460 /* 1461 * Add some slop to the I/O and memory resources decoded by 1462 * this bus to give a guest some flexibility if it wants to 1463 * reprogram the BARs. 1464 */ 1465 pci_emul_iobase += BUSIO_ROUNDUP; 1466 pci_emul_iobase = roundup2(pci_emul_iobase, BUSIO_ROUNDUP); 1467 bi->iolimit = pci_emul_iobase; 1468 1469 pci_emul_membase32 += BUSMEM32_ROUNDUP; 1470 pci_emul_membase32 = roundup2(pci_emul_membase32, 1471 BUSMEM32_ROUNDUP); 1472 bi->memlimit32 = pci_emul_membase32; 1473 1474 pci_emul_membase64 += BUSMEM64_ROUNDUP; 1475 pci_emul_membase64 = roundup2(pci_emul_membase64, 1476 BUSMEM64_ROUNDUP); 1477 bi->memlimit64 = pci_emul_membase64; 1478 } 1479 1480 /* 1481 * PCI backends are initialized before routing INTx interrupts 1482 * so that LPC devices are able to reserve ISA IRQs before 1483 * routing PIRQ pins. 1484 */ 1485 for (bus = 0; bus < MAXBUSES; bus++) { 1486 if ((bi = pci_businfo[bus]) == NULL) 1487 continue; 1488 1489 for (slot = 0; slot < MAXSLOTS; slot++) { 1490 si = &bi->slotinfo[slot]; 1491 for (func = 0; func < MAXFUNCS; func++) { 1492 fi = &si->si_funcs[func]; 1493 if (fi->fi_devi == NULL) 1494 continue; 1495 pci_lintr_route(fi->fi_devi); 1496 } 1497 } 1498 } 1499 lpc_pirq_routed(); 1500 1501 /* 1502 * The guest physical memory map looks like the following: 1503 * [0, lowmem) guest system memory 1504 * [lowmem, 0xC0000000) memory hole (may be absent) 1505 * [0xC0000000, 0xE0000000) PCI hole (32-bit BAR allocation) 1506 * [0xE0000000, 0xF0000000) PCI extended config window 1507 * [0xF0000000, 4GB) LAPIC, IOAPIC, HPET, firmware 1508 * [4GB, 4GB + highmem) 1509 */ 1510 1511 /* 1512 * Accesses to memory addresses that are not allocated to system 1513 * memory or PCI devices return 0xff's. 1514 */ 1515 lowmem = vm_get_lowmem_size(ctx); 1516 bzero(&mr, sizeof(struct mem_range)); 1517 mr.name = "PCI hole"; 1518 mr.flags = MEM_F_RW | MEM_F_IMMUTABLE; 1519 mr.base = lowmem; 1520 mr.size = (4ULL * 1024 * 1024 * 1024) - lowmem; 1521 mr.handler = pci_emul_fallback_handler; 1522 error = register_mem_fallback(&mr); 1523 assert(error == 0); 1524 1525 /* PCI extended config space */ 1526 bzero(&mr, sizeof(struct mem_range)); 1527 mr.name = "PCI ECFG"; 1528 mr.flags = MEM_F_RW | MEM_F_IMMUTABLE; 1529 mr.base = PCI_EMUL_ECFG_BASE; 1530 mr.size = PCI_EMUL_ECFG_SIZE; 1531 mr.handler = pci_emul_ecfg_handler; 1532 error = register_mem(&mr); 1533 assert(error == 0); 1534 1535 return (0); 1536 } 1537 1538 static void 1539 pci_apic_prt_entry(int bus __unused, int slot, int pin, int pirq_pin __unused, 1540 int ioapic_irq, void *arg __unused) 1541 { 1542 1543 dsdt_line(" Package ()"); 1544 dsdt_line(" {"); 1545 dsdt_line(" 0x%X,", slot << 16 | 0xffff); 1546 dsdt_line(" 0x%02X,", pin - 1); 1547 dsdt_line(" Zero,"); 1548 dsdt_line(" 0x%X", ioapic_irq); 1549 dsdt_line(" },"); 1550 } 1551 1552 static void 1553 pci_pirq_prt_entry(int bus __unused, int slot, int pin, int pirq_pin, 1554 int ioapic_irq __unused, void *arg __unused) 1555 { 1556 char *name; 1557 1558 name = lpc_pirq_name(pirq_pin); 1559 if (name == NULL) 1560 return; 1561 dsdt_line(" Package ()"); 1562 dsdt_line(" {"); 1563 dsdt_line(" 0x%X,", slot << 16 | 0xffff); 1564 dsdt_line(" 0x%02X,", pin - 1); 1565 dsdt_line(" %s,", name); 1566 dsdt_line(" 0x00"); 1567 dsdt_line(" },"); 1568 free(name); 1569 } 1570 1571 /* 1572 * A bhyve virtual machine has a flat PCI hierarchy with a root port 1573 * corresponding to each PCI bus. 1574 */ 1575 static void 1576 pci_bus_write_dsdt(int bus) 1577 { 1578 struct businfo *bi; 1579 struct slotinfo *si; 1580 struct pci_devinst *pi; 1581 int count, func, slot; 1582 1583 /* 1584 * If there are no devices on this 'bus' then just return. 1585 */ 1586 if ((bi = pci_businfo[bus]) == NULL) { 1587 /* 1588 * Bus 0 is special because it decodes the I/O ports used 1589 * for PCI config space access even if there are no devices 1590 * on it. 1591 */ 1592 if (bus != 0) 1593 return; 1594 } 1595 1596 dsdt_line(" Device (PC%02X)", bus); 1597 dsdt_line(" {"); 1598 dsdt_line(" Name (_HID, EisaId (\"PNP0A03\"))"); 1599 1600 dsdt_line(" Method (_BBN, 0, NotSerialized)"); 1601 dsdt_line(" {"); 1602 dsdt_line(" Return (0x%08X)", bus); 1603 dsdt_line(" }"); 1604 dsdt_line(" Name (_CRS, ResourceTemplate ()"); 1605 dsdt_line(" {"); 1606 dsdt_line(" WordBusNumber (ResourceProducer, MinFixed, " 1607 "MaxFixed, PosDecode,"); 1608 dsdt_line(" 0x0000, // Granularity"); 1609 dsdt_line(" 0x%04X, // Range Minimum", bus); 1610 dsdt_line(" 0x%04X, // Range Maximum", bus); 1611 dsdt_line(" 0x0000, // Translation Offset"); 1612 dsdt_line(" 0x0001, // Length"); 1613 dsdt_line(" ,, )"); 1614 1615 if (bus == 0) { 1616 dsdt_indent(3); 1617 dsdt_fixed_ioport(0xCF8, 8); 1618 dsdt_unindent(3); 1619 1620 dsdt_line(" WordIO (ResourceProducer, MinFixed, MaxFixed, " 1621 "PosDecode, EntireRange,"); 1622 dsdt_line(" 0x0000, // Granularity"); 1623 dsdt_line(" 0x0000, // Range Minimum"); 1624 dsdt_line(" 0x0CF7, // Range Maximum"); 1625 dsdt_line(" 0x0000, // Translation Offset"); 1626 dsdt_line(" 0x0CF8, // Length"); 1627 dsdt_line(" ,, , TypeStatic)"); 1628 1629 dsdt_line(" WordIO (ResourceProducer, MinFixed, MaxFixed, " 1630 "PosDecode, EntireRange,"); 1631 dsdt_line(" 0x0000, // Granularity"); 1632 dsdt_line(" 0x0D00, // Range Minimum"); 1633 dsdt_line(" 0x%04X, // Range Maximum", 1634 PCI_EMUL_IOBASE - 1); 1635 dsdt_line(" 0x0000, // Translation Offset"); 1636 dsdt_line(" 0x%04X, // Length", 1637 PCI_EMUL_IOBASE - 0x0D00); 1638 dsdt_line(" ,, , TypeStatic)"); 1639 1640 if (bi == NULL) { 1641 dsdt_line(" })"); 1642 goto done; 1643 } 1644 } 1645 assert(bi != NULL); 1646 1647 /* i/o window */ 1648 dsdt_line(" WordIO (ResourceProducer, MinFixed, MaxFixed, " 1649 "PosDecode, EntireRange,"); 1650 dsdt_line(" 0x0000, // Granularity"); 1651 dsdt_line(" 0x%04X, // Range Minimum", bi->iobase); 1652 dsdt_line(" 0x%04X, // Range Maximum", 1653 bi->iolimit - 1); 1654 dsdt_line(" 0x0000, // Translation Offset"); 1655 dsdt_line(" 0x%04X, // Length", 1656 bi->iolimit - bi->iobase); 1657 dsdt_line(" ,, , TypeStatic)"); 1658 1659 /* mmio window (32-bit) */ 1660 dsdt_line(" DWordMemory (ResourceProducer, PosDecode, " 1661 "MinFixed, MaxFixed, NonCacheable, ReadWrite,"); 1662 dsdt_line(" 0x00000000, // Granularity"); 1663 dsdt_line(" 0x%08X, // Range Minimum\n", bi->membase32); 1664 dsdt_line(" 0x%08X, // Range Maximum\n", 1665 bi->memlimit32 - 1); 1666 dsdt_line(" 0x00000000, // Translation Offset"); 1667 dsdt_line(" 0x%08X, // Length\n", 1668 bi->memlimit32 - bi->membase32); 1669 dsdt_line(" ,, , AddressRangeMemory, TypeStatic)"); 1670 1671 /* mmio window (64-bit) */ 1672 dsdt_line(" QWordMemory (ResourceProducer, PosDecode, " 1673 "MinFixed, MaxFixed, NonCacheable, ReadWrite,"); 1674 dsdt_line(" 0x0000000000000000, // Granularity"); 1675 dsdt_line(" 0x%016lX, // Range Minimum\n", bi->membase64); 1676 dsdt_line(" 0x%016lX, // Range Maximum\n", 1677 bi->memlimit64 - 1); 1678 dsdt_line(" 0x0000000000000000, // Translation Offset"); 1679 dsdt_line(" 0x%016lX, // Length\n", 1680 bi->memlimit64 - bi->membase64); 1681 dsdt_line(" ,, , AddressRangeMemory, TypeStatic)"); 1682 dsdt_line(" })"); 1683 1684 count = pci_count_lintr(bus); 1685 if (count != 0) { 1686 dsdt_indent(2); 1687 dsdt_line("Name (PPRT, Package ()"); 1688 dsdt_line("{"); 1689 pci_walk_lintr(bus, pci_pirq_prt_entry, NULL); 1690 dsdt_line("})"); 1691 dsdt_line("Name (APRT, Package ()"); 1692 dsdt_line("{"); 1693 pci_walk_lintr(bus, pci_apic_prt_entry, NULL); 1694 dsdt_line("})"); 1695 dsdt_line("Method (_PRT, 0, NotSerialized)"); 1696 dsdt_line("{"); 1697 dsdt_line(" If (PICM)"); 1698 dsdt_line(" {"); 1699 dsdt_line(" Return (APRT)"); 1700 dsdt_line(" }"); 1701 dsdt_line(" Else"); 1702 dsdt_line(" {"); 1703 dsdt_line(" Return (PPRT)"); 1704 dsdt_line(" }"); 1705 dsdt_line("}"); 1706 dsdt_unindent(2); 1707 } 1708 1709 dsdt_indent(2); 1710 for (slot = 0; slot < MAXSLOTS; slot++) { 1711 si = &bi->slotinfo[slot]; 1712 for (func = 0; func < MAXFUNCS; func++) { 1713 pi = si->si_funcs[func].fi_devi; 1714 if (pi != NULL && pi->pi_d->pe_write_dsdt != NULL) 1715 pi->pi_d->pe_write_dsdt(pi); 1716 } 1717 } 1718 dsdt_unindent(2); 1719 done: 1720 dsdt_line(" }"); 1721 } 1722 1723 void 1724 pci_write_dsdt(void) 1725 { 1726 int bus; 1727 1728 dsdt_indent(1); 1729 dsdt_line("Name (PICM, 0x00)"); 1730 dsdt_line("Method (_PIC, 1, NotSerialized)"); 1731 dsdt_line("{"); 1732 dsdt_line(" Store (Arg0, PICM)"); 1733 dsdt_line("}"); 1734 dsdt_line(""); 1735 dsdt_line("Scope (_SB)"); 1736 dsdt_line("{"); 1737 for (bus = 0; bus < MAXBUSES; bus++) 1738 pci_bus_write_dsdt(bus); 1739 dsdt_line("}"); 1740 dsdt_unindent(1); 1741 } 1742 1743 int 1744 pci_bus_configured(int bus) 1745 { 1746 assert(bus >= 0 && bus < MAXBUSES); 1747 return (pci_businfo[bus] != NULL); 1748 } 1749 1750 int 1751 pci_msi_enabled(struct pci_devinst *pi) 1752 { 1753 return (pi->pi_msi.enabled); 1754 } 1755 1756 int 1757 pci_msi_maxmsgnum(struct pci_devinst *pi) 1758 { 1759 if (pi->pi_msi.enabled) 1760 return (pi->pi_msi.maxmsgnum); 1761 else 1762 return (0); 1763 } 1764 1765 int 1766 pci_msix_enabled(struct pci_devinst *pi) 1767 { 1768 1769 return (pi->pi_msix.enabled && !pi->pi_msi.enabled); 1770 } 1771 1772 void 1773 pci_generate_msix(struct pci_devinst *pi, int index) 1774 { 1775 struct msix_table_entry *mte; 1776 1777 if (!pci_msix_enabled(pi)) 1778 return; 1779 1780 if (pi->pi_msix.function_mask) 1781 return; 1782 1783 if (index >= pi->pi_msix.table_count) 1784 return; 1785 1786 mte = &pi->pi_msix.table[index]; 1787 if ((mte->vector_control & PCIM_MSIX_VCTRL_MASK) == 0) { 1788 /* XXX Set PBA bit if interrupt is disabled */ 1789 vm_lapic_msi(pi->pi_vmctx, mte->addr, mte->msg_data); 1790 } 1791 } 1792 1793 void 1794 pci_generate_msi(struct pci_devinst *pi, int index) 1795 { 1796 1797 if (pci_msi_enabled(pi) && index < pci_msi_maxmsgnum(pi)) { 1798 vm_lapic_msi(pi->pi_vmctx, pi->pi_msi.addr, 1799 pi->pi_msi.msg_data + index); 1800 } 1801 } 1802 1803 static bool 1804 pci_lintr_permitted(struct pci_devinst *pi) 1805 { 1806 uint16_t cmd; 1807 1808 cmd = pci_get_cfgdata16(pi, PCIR_COMMAND); 1809 return (!(pi->pi_msi.enabled || pi->pi_msix.enabled || 1810 (cmd & PCIM_CMD_INTxDIS))); 1811 } 1812 1813 void 1814 pci_lintr_request(struct pci_devinst *pi) 1815 { 1816 struct businfo *bi; 1817 struct slotinfo *si; 1818 int bestpin, bestcount, pin; 1819 1820 bi = pci_businfo[pi->pi_bus]; 1821 assert(bi != NULL); 1822 1823 /* 1824 * Just allocate a pin from our slot. The pin will be 1825 * assigned IRQs later when interrupts are routed. 1826 */ 1827 si = &bi->slotinfo[pi->pi_slot]; 1828 bestpin = 0; 1829 bestcount = si->si_intpins[0].ii_count; 1830 for (pin = 1; pin < 4; pin++) { 1831 if (si->si_intpins[pin].ii_count < bestcount) { 1832 bestpin = pin; 1833 bestcount = si->si_intpins[pin].ii_count; 1834 } 1835 } 1836 1837 si->si_intpins[bestpin].ii_count++; 1838 pi->pi_lintr.pin = bestpin + 1; 1839 pci_set_cfgdata8(pi, PCIR_INTPIN, bestpin + 1); 1840 } 1841 1842 static void 1843 pci_lintr_route(struct pci_devinst *pi) 1844 { 1845 struct businfo *bi; 1846 struct intxinfo *ii; 1847 1848 if (pi->pi_lintr.pin == 0) 1849 return; 1850 1851 bi = pci_businfo[pi->pi_bus]; 1852 assert(bi != NULL); 1853 ii = &bi->slotinfo[pi->pi_slot].si_intpins[pi->pi_lintr.pin - 1]; 1854 1855 /* 1856 * Attempt to allocate an I/O APIC pin for this intpin if one 1857 * is not yet assigned. 1858 */ 1859 if (ii->ii_ioapic_irq == 0) 1860 ii->ii_ioapic_irq = ioapic_pci_alloc_irq(pi); 1861 assert(ii->ii_ioapic_irq > 0); 1862 1863 /* 1864 * Attempt to allocate a PIRQ pin for this intpin if one is 1865 * not yet assigned. 1866 */ 1867 if (ii->ii_pirq_pin == 0) 1868 ii->ii_pirq_pin = pirq_alloc_pin(pi); 1869 assert(ii->ii_pirq_pin > 0); 1870 1871 pi->pi_lintr.ioapic_irq = ii->ii_ioapic_irq; 1872 pi->pi_lintr.pirq_pin = ii->ii_pirq_pin; 1873 pci_set_cfgdata8(pi, PCIR_INTLINE, pirq_irq(ii->ii_pirq_pin)); 1874 } 1875 1876 void 1877 pci_lintr_assert(struct pci_devinst *pi) 1878 { 1879 1880 assert(pi->pi_lintr.pin > 0); 1881 1882 pthread_mutex_lock(&pi->pi_lintr.lock); 1883 if (pi->pi_lintr.state == IDLE) { 1884 if (pci_lintr_permitted(pi)) { 1885 pi->pi_lintr.state = ASSERTED; 1886 pci_irq_assert(pi); 1887 } else 1888 pi->pi_lintr.state = PENDING; 1889 } 1890 pthread_mutex_unlock(&pi->pi_lintr.lock); 1891 } 1892 1893 void 1894 pci_lintr_deassert(struct pci_devinst *pi) 1895 { 1896 1897 assert(pi->pi_lintr.pin > 0); 1898 1899 pthread_mutex_lock(&pi->pi_lintr.lock); 1900 if (pi->pi_lintr.state == ASSERTED) { 1901 pi->pi_lintr.state = IDLE; 1902 pci_irq_deassert(pi); 1903 } else if (pi->pi_lintr.state == PENDING) 1904 pi->pi_lintr.state = IDLE; 1905 pthread_mutex_unlock(&pi->pi_lintr.lock); 1906 } 1907 1908 static void 1909 pci_lintr_update(struct pci_devinst *pi) 1910 { 1911 1912 pthread_mutex_lock(&pi->pi_lintr.lock); 1913 if (pi->pi_lintr.state == ASSERTED && !pci_lintr_permitted(pi)) { 1914 pci_irq_deassert(pi); 1915 pi->pi_lintr.state = PENDING; 1916 } else if (pi->pi_lintr.state == PENDING && pci_lintr_permitted(pi)) { 1917 pi->pi_lintr.state = ASSERTED; 1918 pci_irq_assert(pi); 1919 } 1920 pthread_mutex_unlock(&pi->pi_lintr.lock); 1921 } 1922 1923 int 1924 pci_count_lintr(int bus) 1925 { 1926 int count, slot, pin; 1927 struct slotinfo *slotinfo; 1928 1929 count = 0; 1930 if (pci_businfo[bus] != NULL) { 1931 for (slot = 0; slot < MAXSLOTS; slot++) { 1932 slotinfo = &pci_businfo[bus]->slotinfo[slot]; 1933 for (pin = 0; pin < 4; pin++) { 1934 if (slotinfo->si_intpins[pin].ii_count != 0) 1935 count++; 1936 } 1937 } 1938 } 1939 return (count); 1940 } 1941 1942 void 1943 pci_walk_lintr(int bus, pci_lintr_cb cb, void *arg) 1944 { 1945 struct businfo *bi; 1946 struct slotinfo *si; 1947 struct intxinfo *ii; 1948 int slot, pin; 1949 1950 if ((bi = pci_businfo[bus]) == NULL) 1951 return; 1952 1953 for (slot = 0; slot < MAXSLOTS; slot++) { 1954 si = &bi->slotinfo[slot]; 1955 for (pin = 0; pin < 4; pin++) { 1956 ii = &si->si_intpins[pin]; 1957 if (ii->ii_count != 0) 1958 cb(bus, slot, pin + 1, ii->ii_pirq_pin, 1959 ii->ii_ioapic_irq, arg); 1960 } 1961 } 1962 } 1963 1964 /* 1965 * Return 1 if the emulated device in 'slot' is a multi-function device. 1966 * Return 0 otherwise. 1967 */ 1968 static int 1969 pci_emul_is_mfdev(int bus, int slot) 1970 { 1971 struct businfo *bi; 1972 struct slotinfo *si; 1973 int f, numfuncs; 1974 1975 numfuncs = 0; 1976 if ((bi = pci_businfo[bus]) != NULL) { 1977 si = &bi->slotinfo[slot]; 1978 for (f = 0; f < MAXFUNCS; f++) { 1979 if (si->si_funcs[f].fi_devi != NULL) { 1980 numfuncs++; 1981 } 1982 } 1983 } 1984 return (numfuncs > 1); 1985 } 1986 1987 /* 1988 * Ensure that the PCIM_MFDEV bit is properly set (or unset) depending on 1989 * whether or not is a multi-function being emulated in the pci 'slot'. 1990 */ 1991 static void 1992 pci_emul_hdrtype_fixup(int bus, int slot, int off, int bytes, uint32_t *rv) 1993 { 1994 int mfdev; 1995 1996 if (off <= PCIR_HDRTYPE && off + bytes > PCIR_HDRTYPE) { 1997 mfdev = pci_emul_is_mfdev(bus, slot); 1998 switch (bytes) { 1999 case 1: 2000 case 2: 2001 *rv &= ~PCIM_MFDEV; 2002 if (mfdev) { 2003 *rv |= PCIM_MFDEV; 2004 } 2005 break; 2006 case 4: 2007 *rv &= ~(PCIM_MFDEV << 16); 2008 if (mfdev) { 2009 *rv |= (PCIM_MFDEV << 16); 2010 } 2011 break; 2012 } 2013 } 2014 } 2015 2016 /* 2017 * Update device state in response to changes to the PCI command 2018 * register. 2019 */ 2020 void 2021 pci_emul_cmd_changed(struct pci_devinst *pi, uint16_t old) 2022 { 2023 int i; 2024 uint16_t changed, new; 2025 2026 new = pci_get_cfgdata16(pi, PCIR_COMMAND); 2027 changed = old ^ new; 2028 2029 /* 2030 * If the MMIO or I/O address space decoding has changed then 2031 * register/unregister all BARs that decode that address space. 2032 */ 2033 for (i = 0; i <= PCI_BARMAX_WITH_ROM; i++) { 2034 switch (pi->pi_bar[i].type) { 2035 case PCIBAR_NONE: 2036 case PCIBAR_MEMHI64: 2037 break; 2038 case PCIBAR_IO: 2039 /* I/O address space decoding changed? */ 2040 if (changed & PCIM_CMD_PORTEN) { 2041 if (new & PCIM_CMD_PORTEN) 2042 register_bar(pi, i); 2043 else 2044 unregister_bar(pi, i); 2045 } 2046 break; 2047 case PCIBAR_ROM: 2048 /* skip (un-)register of ROM if it disabled */ 2049 if (!romen(pi)) 2050 break; 2051 /* fallthrough */ 2052 case PCIBAR_MEM32: 2053 case PCIBAR_MEM64: 2054 /* MMIO address space decoding changed? */ 2055 if (changed & PCIM_CMD_MEMEN) { 2056 if (new & PCIM_CMD_MEMEN) 2057 register_bar(pi, i); 2058 else 2059 unregister_bar(pi, i); 2060 } 2061 break; 2062 default: 2063 assert(0); 2064 } 2065 } 2066 2067 /* 2068 * If INTx has been unmasked and is pending, assert the 2069 * interrupt. 2070 */ 2071 pci_lintr_update(pi); 2072 } 2073 2074 static void 2075 pci_emul_cmdsts_write(struct pci_devinst *pi, int coff, uint32_t new, int bytes) 2076 { 2077 int rshift; 2078 uint32_t cmd, old, readonly; 2079 2080 cmd = pci_get_cfgdata16(pi, PCIR_COMMAND); /* stash old value */ 2081 2082 /* 2083 * From PCI Local Bus Specification 3.0 sections 6.2.2 and 6.2.3. 2084 * 2085 * XXX Bits 8, 11, 12, 13, 14 and 15 in the status register are 2086 * 'write 1 to clear'. However these bits are not set to '1' by 2087 * any device emulation so it is simpler to treat them as readonly. 2088 */ 2089 rshift = (coff & 0x3) * 8; 2090 readonly = 0xFFFFF880 >> rshift; 2091 2092 old = CFGREAD(pi, coff, bytes); 2093 new &= ~readonly; 2094 new |= (old & readonly); 2095 CFGWRITE(pi, coff, new, bytes); /* update config */ 2096 2097 pci_emul_cmd_changed(pi, cmd); 2098 } 2099 2100 static void 2101 pci_cfgrw(int in, int bus, int slot, int func, int coff, int bytes, 2102 uint32_t *eax) 2103 { 2104 struct businfo *bi; 2105 struct slotinfo *si; 2106 struct pci_devinst *pi; 2107 struct pci_devemu *pe; 2108 int idx, needcfg; 2109 uint64_t addr, bar, mask; 2110 2111 if ((bi = pci_businfo[bus]) != NULL) { 2112 si = &bi->slotinfo[slot]; 2113 pi = si->si_funcs[func].fi_devi; 2114 } else 2115 pi = NULL; 2116 2117 /* 2118 * Just return if there is no device at this slot:func or if the 2119 * the guest is doing an un-aligned access. 2120 */ 2121 if (pi == NULL || (bytes != 1 && bytes != 2 && bytes != 4) || 2122 (coff & (bytes - 1)) != 0) { 2123 if (in) 2124 *eax = 0xffffffff; 2125 return; 2126 } 2127 2128 /* 2129 * Ignore all writes beyond the standard config space and return all 2130 * ones on reads. 2131 */ 2132 if (coff >= PCI_REGMAX + 1) { 2133 if (in) { 2134 *eax = 0xffffffff; 2135 /* 2136 * Extended capabilities begin at offset 256 in config 2137 * space. Absence of extended capabilities is signaled 2138 * with all 0s in the extended capability header at 2139 * offset 256. 2140 */ 2141 if (coff <= PCI_REGMAX + 4) 2142 *eax = 0x00000000; 2143 } 2144 return; 2145 } 2146 2147 pe = pi->pi_d; 2148 2149 /* 2150 * Config read 2151 */ 2152 if (in) { 2153 /* Let the device emulation override the default handler */ 2154 if (pe->pe_cfgread != NULL) { 2155 needcfg = pe->pe_cfgread(pi, coff, bytes, eax); 2156 } else { 2157 needcfg = 1; 2158 } 2159 2160 if (needcfg) 2161 *eax = CFGREAD(pi, coff, bytes); 2162 2163 pci_emul_hdrtype_fixup(bus, slot, coff, bytes, eax); 2164 } else { 2165 /* Let the device emulation override the default handler */ 2166 if (pe->pe_cfgwrite != NULL && 2167 (*pe->pe_cfgwrite)(pi, coff, bytes, *eax) == 0) 2168 return; 2169 2170 /* 2171 * Special handling for write to BAR and ROM registers 2172 */ 2173 if (is_pcir_bar(coff) || is_pcir_bios(coff)) { 2174 /* 2175 * Ignore writes to BAR registers that are not 2176 * 4-byte aligned. 2177 */ 2178 if (bytes != 4 || (coff & 0x3) != 0) 2179 return; 2180 2181 if (is_pcir_bar(coff)) { 2182 idx = (coff - PCIR_BAR(0)) / 4; 2183 } else if (is_pcir_bios(coff)) { 2184 idx = PCI_ROM_IDX; 2185 } else { 2186 errx(4, "%s: invalid BAR offset %d", __func__, 2187 coff); 2188 } 2189 2190 mask = ~(pi->pi_bar[idx].size - 1); 2191 switch (pi->pi_bar[idx].type) { 2192 case PCIBAR_NONE: 2193 pi->pi_bar[idx].addr = bar = 0; 2194 break; 2195 case PCIBAR_IO: 2196 addr = *eax & mask; 2197 addr &= 0xffff; 2198 bar = addr | pi->pi_bar[idx].lobits; 2199 /* 2200 * Register the new BAR value for interception 2201 */ 2202 if (addr != pi->pi_bar[idx].addr) { 2203 update_bar_address(pi, addr, idx, 2204 PCIBAR_IO); 2205 } 2206 break; 2207 case PCIBAR_MEM32: 2208 addr = bar = *eax & mask; 2209 bar |= pi->pi_bar[idx].lobits; 2210 if (addr != pi->pi_bar[idx].addr) { 2211 update_bar_address(pi, addr, idx, 2212 PCIBAR_MEM32); 2213 } 2214 break; 2215 case PCIBAR_MEM64: 2216 addr = bar = *eax & mask; 2217 bar |= pi->pi_bar[idx].lobits; 2218 if (addr != (uint32_t)pi->pi_bar[idx].addr) { 2219 update_bar_address(pi, addr, idx, 2220 PCIBAR_MEM64); 2221 } 2222 break; 2223 case PCIBAR_MEMHI64: 2224 mask = ~(pi->pi_bar[idx - 1].size - 1); 2225 addr = ((uint64_t)*eax << 32) & mask; 2226 bar = addr >> 32; 2227 if (bar != pi->pi_bar[idx - 1].addr >> 32) { 2228 update_bar_address(pi, addr, idx - 1, 2229 PCIBAR_MEMHI64); 2230 } 2231 break; 2232 case PCIBAR_ROM: 2233 addr = bar = *eax & mask; 2234 if (memen(pi) && romen(pi)) { 2235 unregister_bar(pi, idx); 2236 } 2237 pi->pi_bar[idx].addr = addr; 2238 pi->pi_bar[idx].lobits = *eax & 2239 PCIM_BIOS_ENABLE; 2240 /* romen could have changed it value */ 2241 if (memen(pi) && romen(pi)) { 2242 register_bar(pi, idx); 2243 } 2244 bar |= pi->pi_bar[idx].lobits; 2245 break; 2246 default: 2247 assert(0); 2248 } 2249 pci_set_cfgdata32(pi, coff, bar); 2250 2251 } else if (pci_emul_iscap(pi, coff)) { 2252 pci_emul_capwrite(pi, coff, bytes, *eax, 0, 0); 2253 } else if (coff >= PCIR_COMMAND && coff < PCIR_REVID) { 2254 pci_emul_cmdsts_write(pi, coff, *eax, bytes); 2255 } else { 2256 CFGWRITE(pi, coff, *eax, bytes); 2257 } 2258 } 2259 } 2260 2261 static int cfgenable, cfgbus, cfgslot, cfgfunc, cfgoff; 2262 2263 static int 2264 pci_emul_cfgaddr(struct vmctx *ctx __unused, int in, 2265 int port __unused, int bytes, uint32_t *eax, void *arg __unused) 2266 { 2267 uint32_t x; 2268 2269 if (bytes != 4) { 2270 if (in) 2271 *eax = (bytes == 2) ? 0xffff : 0xff; 2272 return (0); 2273 } 2274 2275 if (in) { 2276 x = (cfgbus << 16) | (cfgslot << 11) | (cfgfunc << 8) | cfgoff; 2277 if (cfgenable) 2278 x |= CONF1_ENABLE; 2279 *eax = x; 2280 } else { 2281 x = *eax; 2282 cfgenable = (x & CONF1_ENABLE) == CONF1_ENABLE; 2283 cfgoff = (x & PCI_REGMAX) & ~0x03; 2284 cfgfunc = (x >> 8) & PCI_FUNCMAX; 2285 cfgslot = (x >> 11) & PCI_SLOTMAX; 2286 cfgbus = (x >> 16) & PCI_BUSMAX; 2287 } 2288 2289 return (0); 2290 } 2291 INOUT_PORT(pci_cfgaddr, CONF1_ADDR_PORT, IOPORT_F_INOUT, pci_emul_cfgaddr); 2292 2293 static int 2294 pci_emul_cfgdata(struct vmctx *ctx __unused, int in, int port, 2295 int bytes, uint32_t *eax, void *arg __unused) 2296 { 2297 int coff; 2298 2299 assert(bytes == 1 || bytes == 2 || bytes == 4); 2300 2301 coff = cfgoff + (port - CONF1_DATA_PORT); 2302 if (cfgenable) { 2303 pci_cfgrw(in, cfgbus, cfgslot, cfgfunc, coff, bytes, eax); 2304 } else { 2305 /* Ignore accesses to cfgdata if not enabled by cfgaddr */ 2306 if (in) 2307 *eax = 0xffffffff; 2308 } 2309 return (0); 2310 } 2311 2312 INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+0, IOPORT_F_INOUT, pci_emul_cfgdata); 2313 INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+1, IOPORT_F_INOUT, pci_emul_cfgdata); 2314 INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+2, IOPORT_F_INOUT, pci_emul_cfgdata); 2315 INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+3, IOPORT_F_INOUT, pci_emul_cfgdata); 2316 2317 #ifdef BHYVE_SNAPSHOT 2318 /* 2319 * Saves/restores PCI device emulated state. Returns 0 on success. 2320 */ 2321 static int 2322 pci_snapshot_pci_dev(struct vm_snapshot_meta *meta) 2323 { 2324 struct pci_devinst *pi; 2325 int i; 2326 int ret; 2327 2328 pi = meta->dev_data; 2329 2330 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msi.enabled, meta, ret, done); 2331 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msi.addr, meta, ret, done); 2332 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msi.msg_data, meta, ret, done); 2333 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msi.maxmsgnum, meta, ret, done); 2334 2335 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.enabled, meta, ret, done); 2336 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.table_bar, meta, ret, done); 2337 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.pba_bar, meta, ret, done); 2338 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.table_offset, meta, ret, done); 2339 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.table_count, meta, ret, done); 2340 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.pba_offset, meta, ret, done); 2341 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.pba_size, meta, ret, done); 2342 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.function_mask, meta, ret, done); 2343 2344 SNAPSHOT_BUF_OR_LEAVE(pi->pi_cfgdata, sizeof(pi->pi_cfgdata), 2345 meta, ret, done); 2346 2347 for (i = 0; i < (int)nitems(pi->pi_bar); i++) { 2348 SNAPSHOT_VAR_OR_LEAVE(pi->pi_bar[i].type, meta, ret, done); 2349 SNAPSHOT_VAR_OR_LEAVE(pi->pi_bar[i].size, meta, ret, done); 2350 SNAPSHOT_VAR_OR_LEAVE(pi->pi_bar[i].addr, meta, ret, done); 2351 } 2352 2353 /* Restore MSI-X table. */ 2354 for (i = 0; i < pi->pi_msix.table_count; i++) { 2355 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.table[i].addr, 2356 meta, ret, done); 2357 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.table[i].msg_data, 2358 meta, ret, done); 2359 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.table[i].vector_control, 2360 meta, ret, done); 2361 } 2362 2363 done: 2364 return (ret); 2365 } 2366 2367 static int 2368 pci_find_slotted_dev(const char *dev_name, struct pci_devemu **pde, 2369 struct pci_devinst **pdi) 2370 { 2371 struct businfo *bi; 2372 struct slotinfo *si; 2373 struct funcinfo *fi; 2374 int bus, slot, func; 2375 2376 assert(dev_name != NULL); 2377 assert(pde != NULL); 2378 assert(pdi != NULL); 2379 2380 for (bus = 0; bus < MAXBUSES; bus++) { 2381 if ((bi = pci_businfo[bus]) == NULL) 2382 continue; 2383 2384 for (slot = 0; slot < MAXSLOTS; slot++) { 2385 si = &bi->slotinfo[slot]; 2386 for (func = 0; func < MAXFUNCS; func++) { 2387 fi = &si->si_funcs[func]; 2388 if (fi->fi_pde == NULL) 2389 continue; 2390 if (strcmp(dev_name, fi->fi_pde->pe_emu) != 0) 2391 continue; 2392 2393 *pde = fi->fi_pde; 2394 *pdi = fi->fi_devi; 2395 return (0); 2396 } 2397 } 2398 } 2399 2400 return (EINVAL); 2401 } 2402 2403 int 2404 pci_snapshot(struct vm_snapshot_meta *meta) 2405 { 2406 struct pci_devemu *pde; 2407 struct pci_devinst *pdi; 2408 int ret; 2409 2410 assert(meta->dev_name != NULL); 2411 2412 ret = pci_find_slotted_dev(meta->dev_name, &pde, &pdi); 2413 if (ret != 0) { 2414 fprintf(stderr, "%s: no such name: %s\r\n", 2415 __func__, meta->dev_name); 2416 memset(meta->buffer.buf_start, 0, meta->buffer.buf_size); 2417 return (0); 2418 } 2419 2420 meta->dev_data = pdi; 2421 2422 if (pde->pe_snapshot == NULL) { 2423 fprintf(stderr, "%s: not implemented yet for: %s\r\n", 2424 __func__, meta->dev_name); 2425 return (-1); 2426 } 2427 2428 ret = pci_snapshot_pci_dev(meta); 2429 if (ret != 0) { 2430 fprintf(stderr, "%s: failed to snapshot pci dev\r\n", 2431 __func__); 2432 return (-1); 2433 } 2434 2435 ret = (*pde->pe_snapshot)(meta); 2436 2437 return (ret); 2438 } 2439 2440 int 2441 pci_pause(const char *dev_name) 2442 { 2443 struct pci_devemu *pde; 2444 struct pci_devinst *pdi; 2445 int ret; 2446 2447 assert(dev_name != NULL); 2448 2449 ret = pci_find_slotted_dev(dev_name, &pde, &pdi); 2450 if (ret != 0) { 2451 /* 2452 * It is possible to call this function without 2453 * checking that the device is inserted first. 2454 */ 2455 fprintf(stderr, "%s: no such name: %s\n", __func__, dev_name); 2456 return (0); 2457 } 2458 2459 if (pde->pe_pause == NULL) { 2460 /* The pause/resume functionality is optional. */ 2461 fprintf(stderr, "%s: not implemented for: %s\n", 2462 __func__, dev_name); 2463 return (0); 2464 } 2465 2466 return (*pde->pe_pause)(pdi); 2467 } 2468 2469 int 2470 pci_resume(const char *dev_name) 2471 { 2472 struct pci_devemu *pde; 2473 struct pci_devinst *pdi; 2474 int ret; 2475 2476 assert(dev_name != NULL); 2477 2478 ret = pci_find_slotted_dev(dev_name, &pde, &pdi); 2479 if (ret != 0) { 2480 /* 2481 * It is possible to call this function without 2482 * checking that the device is inserted first. 2483 */ 2484 fprintf(stderr, "%s: no such name: %s\n", __func__, dev_name); 2485 return (0); 2486 } 2487 2488 if (pde->pe_resume == NULL) { 2489 /* The pause/resume functionality is optional. */ 2490 fprintf(stderr, "%s: not implemented for: %s\n", 2491 __func__, dev_name); 2492 return (0); 2493 } 2494 2495 return (*pde->pe_resume)(pdi); 2496 } 2497 #endif 2498 2499 #define PCI_EMUL_TEST 2500 #ifdef PCI_EMUL_TEST 2501 /* 2502 * Define a dummy test device 2503 */ 2504 #define DIOSZ 8 2505 #define DMEMSZ 4096 2506 struct pci_emul_dsoftc { 2507 uint8_t ioregs[DIOSZ]; 2508 uint8_t memregs[2][DMEMSZ]; 2509 }; 2510 2511 #define PCI_EMUL_MSI_MSGS 4 2512 #define PCI_EMUL_MSIX_MSGS 16 2513 2514 static int 2515 pci_emul_dinit(struct pci_devinst *pi, nvlist_t *nvl __unused) 2516 { 2517 int error; 2518 struct pci_emul_dsoftc *sc; 2519 2520 sc = calloc(1, sizeof(struct pci_emul_dsoftc)); 2521 2522 pi->pi_arg = sc; 2523 2524 pci_set_cfgdata16(pi, PCIR_DEVICE, 0x0001); 2525 pci_set_cfgdata16(pi, PCIR_VENDOR, 0x10DD); 2526 pci_set_cfgdata8(pi, PCIR_CLASS, 0x02); 2527 2528 error = pci_emul_add_msicap(pi, PCI_EMUL_MSI_MSGS); 2529 assert(error == 0); 2530 2531 error = pci_emul_alloc_bar(pi, 0, PCIBAR_IO, DIOSZ); 2532 assert(error == 0); 2533 2534 error = pci_emul_alloc_bar(pi, 1, PCIBAR_MEM32, DMEMSZ); 2535 assert(error == 0); 2536 2537 error = pci_emul_alloc_bar(pi, 2, PCIBAR_MEM32, DMEMSZ); 2538 assert(error == 0); 2539 2540 return (0); 2541 } 2542 2543 static void 2544 pci_emul_diow(struct pci_devinst *pi, int baridx, uint64_t offset, int size, 2545 uint64_t value) 2546 { 2547 int i; 2548 struct pci_emul_dsoftc *sc = pi->pi_arg; 2549 2550 if (baridx == 0) { 2551 if (offset + size > DIOSZ) { 2552 printf("diow: iow too large, offset %ld size %d\n", 2553 offset, size); 2554 return; 2555 } 2556 2557 if (size == 1) { 2558 sc->ioregs[offset] = value & 0xff; 2559 } else if (size == 2) { 2560 *(uint16_t *)&sc->ioregs[offset] = value & 0xffff; 2561 } else if (size == 4) { 2562 *(uint32_t *)&sc->ioregs[offset] = value; 2563 } else { 2564 printf("diow: iow unknown size %d\n", size); 2565 } 2566 2567 /* 2568 * Special magic value to generate an interrupt 2569 */ 2570 if (offset == 4 && size == 4 && pci_msi_enabled(pi)) 2571 pci_generate_msi(pi, value % pci_msi_maxmsgnum(pi)); 2572 2573 if (value == 0xabcdef) { 2574 for (i = 0; i < pci_msi_maxmsgnum(pi); i++) 2575 pci_generate_msi(pi, i); 2576 } 2577 } 2578 2579 if (baridx == 1 || baridx == 2) { 2580 if (offset + size > DMEMSZ) { 2581 printf("diow: memw too large, offset %ld size %d\n", 2582 offset, size); 2583 return; 2584 } 2585 2586 i = baridx - 1; /* 'memregs' index */ 2587 2588 if (size == 1) { 2589 sc->memregs[i][offset] = value; 2590 } else if (size == 2) { 2591 *(uint16_t *)&sc->memregs[i][offset] = value; 2592 } else if (size == 4) { 2593 *(uint32_t *)&sc->memregs[i][offset] = value; 2594 } else if (size == 8) { 2595 *(uint64_t *)&sc->memregs[i][offset] = value; 2596 } else { 2597 printf("diow: memw unknown size %d\n", size); 2598 } 2599 2600 /* 2601 * magic interrupt ?? 2602 */ 2603 } 2604 2605 if (baridx > 2 || baridx < 0) { 2606 printf("diow: unknown bar idx %d\n", baridx); 2607 } 2608 } 2609 2610 static uint64_t 2611 pci_emul_dior(struct pci_devinst *pi, int baridx, uint64_t offset, int size) 2612 { 2613 struct pci_emul_dsoftc *sc = pi->pi_arg; 2614 uint32_t value; 2615 int i; 2616 2617 if (baridx == 0) { 2618 if (offset + size > DIOSZ) { 2619 printf("dior: ior too large, offset %ld size %d\n", 2620 offset, size); 2621 return (0); 2622 } 2623 2624 value = 0; 2625 if (size == 1) { 2626 value = sc->ioregs[offset]; 2627 } else if (size == 2) { 2628 value = *(uint16_t *) &sc->ioregs[offset]; 2629 } else if (size == 4) { 2630 value = *(uint32_t *) &sc->ioregs[offset]; 2631 } else { 2632 printf("dior: ior unknown size %d\n", size); 2633 } 2634 } 2635 2636 if (baridx == 1 || baridx == 2) { 2637 if (offset + size > DMEMSZ) { 2638 printf("dior: memr too large, offset %ld size %d\n", 2639 offset, size); 2640 return (0); 2641 } 2642 2643 i = baridx - 1; /* 'memregs' index */ 2644 2645 if (size == 1) { 2646 value = sc->memregs[i][offset]; 2647 } else if (size == 2) { 2648 value = *(uint16_t *) &sc->memregs[i][offset]; 2649 } else if (size == 4) { 2650 value = *(uint32_t *) &sc->memregs[i][offset]; 2651 } else if (size == 8) { 2652 value = *(uint64_t *) &sc->memregs[i][offset]; 2653 } else { 2654 printf("dior: ior unknown size %d\n", size); 2655 } 2656 } 2657 2658 2659 if (baridx > 2 || baridx < 0) { 2660 printf("dior: unknown bar idx %d\n", baridx); 2661 return (0); 2662 } 2663 2664 return (value); 2665 } 2666 2667 #ifdef BHYVE_SNAPSHOT 2668 static int 2669 pci_emul_snapshot(struct vm_snapshot_meta *meta __unused) 2670 { 2671 return (0); 2672 } 2673 #endif 2674 2675 static const struct pci_devemu pci_dummy = { 2676 .pe_emu = "dummy", 2677 .pe_init = pci_emul_dinit, 2678 .pe_barwrite = pci_emul_diow, 2679 .pe_barread = pci_emul_dior, 2680 #ifdef BHYVE_SNAPSHOT 2681 .pe_snapshot = pci_emul_snapshot, 2682 #endif 2683 }; 2684 PCI_EMUL_SET(pci_dummy); 2685 2686 #endif /* PCI_EMUL_TEST */ 2687