1 /*- 2 * Copyright (c) 2011 NetApp, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 #include <sys/param.h> 33 #include <sys/linker_set.h> 34 #include <sys/errno.h> 35 36 #include <ctype.h> 37 #include <pthread.h> 38 #include <stdio.h> 39 #include <stdlib.h> 40 #include <string.h> 41 #include <strings.h> 42 #include <assert.h> 43 #include <stdbool.h> 44 45 #include <machine/vmm.h> 46 #include <vmmapi.h> 47 48 #include "acpi.h" 49 #include "bhyverun.h" 50 #include "inout.h" 51 #include "ioapic.h" 52 #include "mem.h" 53 #include "pci_emul.h" 54 #include "pci_irq.h" 55 #include "pci_lpc.h" 56 57 #define CONF1_ADDR_PORT 0x0cf8 58 #define CONF1_DATA_PORT 0x0cfc 59 60 #define CONF1_ENABLE 0x80000000ul 61 62 #define CFGWRITE(pi,off,val,b) \ 63 do { \ 64 if ((b) == 1) { \ 65 pci_set_cfgdata8((pi),(off),(val)); \ 66 } else if ((b) == 2) { \ 67 pci_set_cfgdata16((pi),(off),(val)); \ 68 } else { \ 69 pci_set_cfgdata32((pi),(off),(val)); \ 70 } \ 71 } while (0) 72 73 #define MAXBUSES (PCI_BUSMAX + 1) 74 #define MAXSLOTS (PCI_SLOTMAX + 1) 75 #define MAXFUNCS (PCI_FUNCMAX + 1) 76 77 struct funcinfo { 78 char *fi_name; 79 char *fi_param; 80 struct pci_devinst *fi_devi; 81 }; 82 83 struct intxinfo { 84 int ii_count; 85 int ii_pirq_pin; 86 int ii_ioapic_irq; 87 }; 88 89 struct slotinfo { 90 struct intxinfo si_intpins[4]; 91 struct funcinfo si_funcs[MAXFUNCS]; 92 }; 93 94 struct businfo { 95 uint16_t iobase, iolimit; /* I/O window */ 96 uint32_t membase32, memlimit32; /* mmio window below 4GB */ 97 uint64_t membase64, memlimit64; /* mmio window above 4GB */ 98 struct slotinfo slotinfo[MAXSLOTS]; 99 }; 100 101 static struct businfo *pci_businfo[MAXBUSES]; 102 103 SET_DECLARE(pci_devemu_set, struct pci_devemu); 104 105 static uint64_t pci_emul_iobase; 106 static uint64_t pci_emul_membase32; 107 static uint64_t pci_emul_membase64; 108 109 #define PCI_EMUL_IOBASE 0x2000 110 #define PCI_EMUL_IOLIMIT 0x10000 111 112 #define PCI_EMUL_MEMLIMIT32 0xE0000000 /* 3.5GB */ 113 114 #define PCI_EMUL_MEMBASE64 0xD000000000UL 115 #define PCI_EMUL_MEMLIMIT64 0xFD00000000UL 116 117 static struct pci_devemu *pci_emul_finddev(char *name); 118 static void pci_lintr_route(struct pci_devinst *pi); 119 static void pci_lintr_update(struct pci_devinst *pi); 120 121 static struct mem_range pci_mem_hole; 122 123 /* 124 * I/O access 125 */ 126 127 /* 128 * Slot options are in the form: 129 * 130 * <bus>:<slot>:<func>,<emul>[,<config>] 131 * <slot>[:<func>],<emul>[,<config>] 132 * 133 * slot is 0..31 134 * func is 0..7 135 * emul is a string describing the type of PCI device e.g. virtio-net 136 * config is an optional string, depending on the device, that can be 137 * used for configuration. 138 * Examples are: 139 * 1,virtio-net,tap0 140 * 3:0,dummy 141 */ 142 static void 143 pci_parse_slot_usage(char *aopt) 144 { 145 146 fprintf(stderr, "Invalid PCI slot info field \"%s\"\n", aopt); 147 } 148 149 int 150 pci_parse_slot(char *opt) 151 { 152 struct businfo *bi; 153 struct slotinfo *si; 154 char *emul, *config, *str, *cp; 155 int error, bnum, snum, fnum; 156 157 error = -1; 158 str = strdup(opt); 159 160 emul = config = NULL; 161 if ((cp = strchr(str, ',')) != NULL) { 162 *cp = '\0'; 163 emul = cp + 1; 164 if ((cp = strchr(emul, ',')) != NULL) { 165 *cp = '\0'; 166 config = cp + 1; 167 } 168 } else { 169 pci_parse_slot_usage(opt); 170 goto done; 171 } 172 173 /* <bus>:<slot>:<func> */ 174 if (sscanf(str, "%d:%d:%d", &bnum, &snum, &fnum) != 3) { 175 bnum = 0; 176 /* <slot>:<func> */ 177 if (sscanf(str, "%d:%d", &snum, &fnum) != 2) { 178 fnum = 0; 179 /* <slot> */ 180 if (sscanf(str, "%d", &snum) != 1) { 181 snum = -1; 182 } 183 } 184 } 185 186 if (bnum < 0 || bnum >= MAXBUSES || snum < 0 || snum >= MAXSLOTS || 187 fnum < 0 || fnum >= MAXFUNCS) { 188 pci_parse_slot_usage(opt); 189 goto done; 190 } 191 192 if (pci_businfo[bnum] == NULL) 193 pci_businfo[bnum] = calloc(1, sizeof(struct businfo)); 194 195 bi = pci_businfo[bnum]; 196 si = &bi->slotinfo[snum]; 197 198 if (si->si_funcs[fnum].fi_name != NULL) { 199 fprintf(stderr, "pci slot %d:%d already occupied!\n", 200 snum, fnum); 201 goto done; 202 } 203 204 if (pci_emul_finddev(emul) == NULL) { 205 fprintf(stderr, "pci slot %d:%d: unknown device \"%s\"\n", 206 snum, fnum, emul); 207 goto done; 208 } 209 210 error = 0; 211 si->si_funcs[fnum].fi_name = emul; 212 si->si_funcs[fnum].fi_param = config; 213 214 done: 215 if (error) 216 free(str); 217 218 return (error); 219 } 220 221 static int 222 pci_valid_pba_offset(struct pci_devinst *pi, uint64_t offset) 223 { 224 225 if (offset < pi->pi_msix.pba_offset) 226 return (0); 227 228 if (offset >= pi->pi_msix.pba_offset + pi->pi_msix.pba_size) { 229 return (0); 230 } 231 232 return (1); 233 } 234 235 int 236 pci_emul_msix_twrite(struct pci_devinst *pi, uint64_t offset, int size, 237 uint64_t value) 238 { 239 int msix_entry_offset; 240 int tab_index; 241 char *dest; 242 243 /* support only 4 or 8 byte writes */ 244 if (size != 4 && size != 8) 245 return (-1); 246 247 /* 248 * Return if table index is beyond what device supports 249 */ 250 tab_index = offset / MSIX_TABLE_ENTRY_SIZE; 251 if (tab_index >= pi->pi_msix.table_count) 252 return (-1); 253 254 msix_entry_offset = offset % MSIX_TABLE_ENTRY_SIZE; 255 256 /* support only aligned writes */ 257 if ((msix_entry_offset % size) != 0) 258 return (-1); 259 260 dest = (char *)(pi->pi_msix.table + tab_index); 261 dest += msix_entry_offset; 262 263 if (size == 4) 264 *((uint32_t *)dest) = value; 265 else 266 *((uint64_t *)dest) = value; 267 268 return (0); 269 } 270 271 uint64_t 272 pci_emul_msix_tread(struct pci_devinst *pi, uint64_t offset, int size) 273 { 274 char *dest; 275 int msix_entry_offset; 276 int tab_index; 277 uint64_t retval = ~0; 278 279 /* 280 * The PCI standard only allows 4 and 8 byte accesses to the MSI-X 281 * table but we also allow 1 byte access to accomodate reads from 282 * ddb. 283 */ 284 if (size != 1 && size != 4 && size != 8) 285 return (retval); 286 287 msix_entry_offset = offset % MSIX_TABLE_ENTRY_SIZE; 288 289 /* support only aligned reads */ 290 if ((msix_entry_offset % size) != 0) { 291 return (retval); 292 } 293 294 tab_index = offset / MSIX_TABLE_ENTRY_SIZE; 295 296 if (tab_index < pi->pi_msix.table_count) { 297 /* valid MSI-X Table access */ 298 dest = (char *)(pi->pi_msix.table + tab_index); 299 dest += msix_entry_offset; 300 301 if (size == 1) 302 retval = *((uint8_t *)dest); 303 else if (size == 4) 304 retval = *((uint32_t *)dest); 305 else 306 retval = *((uint64_t *)dest); 307 } else if (pci_valid_pba_offset(pi, offset)) { 308 /* return 0 for PBA access */ 309 retval = 0; 310 } 311 312 return (retval); 313 } 314 315 int 316 pci_msix_table_bar(struct pci_devinst *pi) 317 { 318 319 if (pi->pi_msix.table != NULL) 320 return (pi->pi_msix.table_bar); 321 else 322 return (-1); 323 } 324 325 int 326 pci_msix_pba_bar(struct pci_devinst *pi) 327 { 328 329 if (pi->pi_msix.table != NULL) 330 return (pi->pi_msix.pba_bar); 331 else 332 return (-1); 333 } 334 335 static int 336 pci_emul_io_handler(struct vmctx *ctx, int vcpu, int in, int port, int bytes, 337 uint32_t *eax, void *arg) 338 { 339 struct pci_devinst *pdi = arg; 340 struct pci_devemu *pe = pdi->pi_d; 341 uint64_t offset; 342 int i; 343 344 for (i = 0; i <= PCI_BARMAX; i++) { 345 if (pdi->pi_bar[i].type == PCIBAR_IO && 346 port >= pdi->pi_bar[i].addr && 347 port + bytes <= pdi->pi_bar[i].addr + pdi->pi_bar[i].size) { 348 offset = port - pdi->pi_bar[i].addr; 349 if (in) 350 *eax = (*pe->pe_barread)(ctx, vcpu, pdi, i, 351 offset, bytes); 352 else 353 (*pe->pe_barwrite)(ctx, vcpu, pdi, i, offset, 354 bytes, *eax); 355 return (0); 356 } 357 } 358 return (-1); 359 } 360 361 static int 362 pci_emul_mem_handler(struct vmctx *ctx, int vcpu, int dir, uint64_t addr, 363 int size, uint64_t *val, void *arg1, long arg2) 364 { 365 struct pci_devinst *pdi = arg1; 366 struct pci_devemu *pe = pdi->pi_d; 367 uint64_t offset; 368 int bidx = (int) arg2; 369 370 assert(bidx <= PCI_BARMAX); 371 assert(pdi->pi_bar[bidx].type == PCIBAR_MEM32 || 372 pdi->pi_bar[bidx].type == PCIBAR_MEM64); 373 assert(addr >= pdi->pi_bar[bidx].addr && 374 addr + size <= pdi->pi_bar[bidx].addr + pdi->pi_bar[bidx].size); 375 376 offset = addr - pdi->pi_bar[bidx].addr; 377 378 if (dir == MEM_F_WRITE) 379 (*pe->pe_barwrite)(ctx, vcpu, pdi, bidx, offset, size, *val); 380 else 381 *val = (*pe->pe_barread)(ctx, vcpu, pdi, bidx, offset, size); 382 383 return (0); 384 } 385 386 387 static int 388 pci_emul_alloc_resource(uint64_t *baseptr, uint64_t limit, uint64_t size, 389 uint64_t *addr) 390 { 391 uint64_t base; 392 393 assert((size & (size - 1)) == 0); /* must be a power of 2 */ 394 395 base = roundup2(*baseptr, size); 396 397 if (base + size <= limit) { 398 *addr = base; 399 *baseptr = base + size; 400 return (0); 401 } else 402 return (-1); 403 } 404 405 int 406 pci_emul_alloc_bar(struct pci_devinst *pdi, int idx, enum pcibar_type type, 407 uint64_t size) 408 { 409 410 return (pci_emul_alloc_pbar(pdi, idx, 0, type, size)); 411 } 412 413 /* 414 * Register (or unregister) the MMIO or I/O region associated with the BAR 415 * register 'idx' of an emulated pci device. 416 */ 417 static void 418 modify_bar_registration(struct pci_devinst *pi, int idx, int registration) 419 { 420 int error; 421 struct inout_port iop; 422 struct mem_range mr; 423 424 switch (pi->pi_bar[idx].type) { 425 case PCIBAR_IO: 426 bzero(&iop, sizeof(struct inout_port)); 427 iop.name = pi->pi_name; 428 iop.port = pi->pi_bar[idx].addr; 429 iop.size = pi->pi_bar[idx].size; 430 if (registration) { 431 iop.flags = IOPORT_F_INOUT; 432 iop.handler = pci_emul_io_handler; 433 iop.arg = pi; 434 error = register_inout(&iop); 435 } else 436 error = unregister_inout(&iop); 437 break; 438 case PCIBAR_MEM32: 439 case PCIBAR_MEM64: 440 bzero(&mr, sizeof(struct mem_range)); 441 mr.name = pi->pi_name; 442 mr.base = pi->pi_bar[idx].addr; 443 mr.size = pi->pi_bar[idx].size; 444 if (registration) { 445 mr.flags = MEM_F_RW; 446 mr.handler = pci_emul_mem_handler; 447 mr.arg1 = pi; 448 mr.arg2 = idx; 449 error = register_mem(&mr); 450 } else 451 error = unregister_mem(&mr); 452 break; 453 default: 454 error = EINVAL; 455 break; 456 } 457 assert(error == 0); 458 } 459 460 static void 461 unregister_bar(struct pci_devinst *pi, int idx) 462 { 463 464 modify_bar_registration(pi, idx, 0); 465 } 466 467 static void 468 register_bar(struct pci_devinst *pi, int idx) 469 { 470 471 modify_bar_registration(pi, idx, 1); 472 } 473 474 /* Are we decoding i/o port accesses for the emulated pci device? */ 475 static int 476 porten(struct pci_devinst *pi) 477 { 478 uint16_t cmd; 479 480 cmd = pci_get_cfgdata16(pi, PCIR_COMMAND); 481 482 return (cmd & PCIM_CMD_PORTEN); 483 } 484 485 /* Are we decoding memory accesses for the emulated pci device? */ 486 static int 487 memen(struct pci_devinst *pi) 488 { 489 uint16_t cmd; 490 491 cmd = pci_get_cfgdata16(pi, PCIR_COMMAND); 492 493 return (cmd & PCIM_CMD_MEMEN); 494 } 495 496 /* 497 * Update the MMIO or I/O address that is decoded by the BAR register. 498 * 499 * If the pci device has enabled the address space decoding then intercept 500 * the address range decoded by the BAR register. 501 */ 502 static void 503 update_bar_address(struct pci_devinst *pi, uint64_t addr, int idx, int type) 504 { 505 int decode; 506 507 if (pi->pi_bar[idx].type == PCIBAR_IO) 508 decode = porten(pi); 509 else 510 decode = memen(pi); 511 512 if (decode) 513 unregister_bar(pi, idx); 514 515 switch (type) { 516 case PCIBAR_IO: 517 case PCIBAR_MEM32: 518 pi->pi_bar[idx].addr = addr; 519 break; 520 case PCIBAR_MEM64: 521 pi->pi_bar[idx].addr &= ~0xffffffffUL; 522 pi->pi_bar[idx].addr |= addr; 523 break; 524 case PCIBAR_MEMHI64: 525 pi->pi_bar[idx].addr &= 0xffffffff; 526 pi->pi_bar[idx].addr |= addr; 527 break; 528 default: 529 assert(0); 530 } 531 532 if (decode) 533 register_bar(pi, idx); 534 } 535 536 int 537 pci_emul_alloc_pbar(struct pci_devinst *pdi, int idx, uint64_t hostbase, 538 enum pcibar_type type, uint64_t size) 539 { 540 int error; 541 uint64_t *baseptr, limit, addr, mask, lobits, bar; 542 543 assert(idx >= 0 && idx <= PCI_BARMAX); 544 545 if ((size & (size - 1)) != 0) 546 size = 1UL << flsl(size); /* round up to a power of 2 */ 547 548 /* Enforce minimum BAR sizes required by the PCI standard */ 549 if (type == PCIBAR_IO) { 550 if (size < 4) 551 size = 4; 552 } else { 553 if (size < 16) 554 size = 16; 555 } 556 557 switch (type) { 558 case PCIBAR_NONE: 559 baseptr = NULL; 560 addr = mask = lobits = 0; 561 break; 562 case PCIBAR_IO: 563 baseptr = &pci_emul_iobase; 564 limit = PCI_EMUL_IOLIMIT; 565 mask = PCIM_BAR_IO_BASE; 566 lobits = PCIM_BAR_IO_SPACE; 567 break; 568 case PCIBAR_MEM64: 569 /* 570 * XXX 571 * Some drivers do not work well if the 64-bit BAR is allocated 572 * above 4GB. Allow for this by allocating small requests under 573 * 4GB unless then allocation size is larger than some arbitrary 574 * number (32MB currently). 575 */ 576 if (size > 32 * 1024 * 1024) { 577 /* 578 * XXX special case for device requiring peer-peer DMA 579 */ 580 if (size == 0x100000000UL) 581 baseptr = &hostbase; 582 else 583 baseptr = &pci_emul_membase64; 584 limit = PCI_EMUL_MEMLIMIT64; 585 mask = PCIM_BAR_MEM_BASE; 586 lobits = PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_64 | 587 PCIM_BAR_MEM_PREFETCH; 588 break; 589 } else { 590 baseptr = &pci_emul_membase32; 591 limit = PCI_EMUL_MEMLIMIT32; 592 mask = PCIM_BAR_MEM_BASE; 593 lobits = PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_64; 594 } 595 break; 596 case PCIBAR_MEM32: 597 baseptr = &pci_emul_membase32; 598 limit = PCI_EMUL_MEMLIMIT32; 599 mask = PCIM_BAR_MEM_BASE; 600 lobits = PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_32; 601 break; 602 default: 603 printf("pci_emul_alloc_base: invalid bar type %d\n", type); 604 assert(0); 605 } 606 607 if (baseptr != NULL) { 608 error = pci_emul_alloc_resource(baseptr, limit, size, &addr); 609 if (error != 0) 610 return (error); 611 } 612 613 pdi->pi_bar[idx].type = type; 614 pdi->pi_bar[idx].addr = addr; 615 pdi->pi_bar[idx].size = size; 616 617 /* Initialize the BAR register in config space */ 618 bar = (addr & mask) | lobits; 619 pci_set_cfgdata32(pdi, PCIR_BAR(idx), bar); 620 621 if (type == PCIBAR_MEM64) { 622 assert(idx + 1 <= PCI_BARMAX); 623 pdi->pi_bar[idx + 1].type = PCIBAR_MEMHI64; 624 pci_set_cfgdata32(pdi, PCIR_BAR(idx + 1), bar >> 32); 625 } 626 627 register_bar(pdi, idx); 628 629 return (0); 630 } 631 632 #define CAP_START_OFFSET 0x40 633 static int 634 pci_emul_add_capability(struct pci_devinst *pi, u_char *capdata, int caplen) 635 { 636 int i, capoff, reallen; 637 uint16_t sts; 638 639 assert(caplen > 0); 640 641 reallen = roundup2(caplen, 4); /* dword aligned */ 642 643 sts = pci_get_cfgdata16(pi, PCIR_STATUS); 644 if ((sts & PCIM_STATUS_CAPPRESENT) == 0) 645 capoff = CAP_START_OFFSET; 646 else 647 capoff = pi->pi_capend + 1; 648 649 /* Check if we have enough space */ 650 if (capoff + reallen > PCI_REGMAX + 1) 651 return (-1); 652 653 /* Set the previous capability pointer */ 654 if ((sts & PCIM_STATUS_CAPPRESENT) == 0) { 655 pci_set_cfgdata8(pi, PCIR_CAP_PTR, capoff); 656 pci_set_cfgdata16(pi, PCIR_STATUS, sts|PCIM_STATUS_CAPPRESENT); 657 } else 658 pci_set_cfgdata8(pi, pi->pi_prevcap + 1, capoff); 659 660 /* Copy the capability */ 661 for (i = 0; i < caplen; i++) 662 pci_set_cfgdata8(pi, capoff + i, capdata[i]); 663 664 /* Set the next capability pointer */ 665 pci_set_cfgdata8(pi, capoff + 1, 0); 666 667 pi->pi_prevcap = capoff; 668 pi->pi_capend = capoff + reallen - 1; 669 return (0); 670 } 671 672 static struct pci_devemu * 673 pci_emul_finddev(char *name) 674 { 675 struct pci_devemu **pdpp, *pdp; 676 677 SET_FOREACH(pdpp, pci_devemu_set) { 678 pdp = *pdpp; 679 if (!strcmp(pdp->pe_emu, name)) { 680 return (pdp); 681 } 682 } 683 684 return (NULL); 685 } 686 687 static int 688 pci_emul_init(struct vmctx *ctx, struct pci_devemu *pde, int bus, int slot, 689 int func, struct funcinfo *fi) 690 { 691 struct pci_devinst *pdi; 692 int err; 693 694 pdi = calloc(1, sizeof(struct pci_devinst)); 695 696 pdi->pi_vmctx = ctx; 697 pdi->pi_bus = bus; 698 pdi->pi_slot = slot; 699 pdi->pi_func = func; 700 pthread_mutex_init(&pdi->pi_lintr.lock, NULL); 701 pdi->pi_lintr.pin = 0; 702 pdi->pi_lintr.state = IDLE; 703 pdi->pi_lintr.pirq_pin = 0; 704 pdi->pi_lintr.ioapic_irq = 0; 705 pdi->pi_d = pde; 706 snprintf(pdi->pi_name, PI_NAMESZ, "%s-pci-%d", pde->pe_emu, slot); 707 708 /* Disable legacy interrupts */ 709 pci_set_cfgdata8(pdi, PCIR_INTLINE, 255); 710 pci_set_cfgdata8(pdi, PCIR_INTPIN, 0); 711 712 pci_set_cfgdata8(pdi, PCIR_COMMAND, 713 PCIM_CMD_PORTEN | PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN); 714 715 err = (*pde->pe_init)(ctx, pdi, fi->fi_param); 716 if (err == 0) 717 fi->fi_devi = pdi; 718 else 719 free(pdi); 720 721 return (err); 722 } 723 724 void 725 pci_populate_msicap(struct msicap *msicap, int msgnum, int nextptr) 726 { 727 int mmc; 728 729 CTASSERT(sizeof(struct msicap) == 14); 730 731 /* Number of msi messages must be a power of 2 between 1 and 32 */ 732 assert((msgnum & (msgnum - 1)) == 0 && msgnum >= 1 && msgnum <= 32); 733 mmc = ffs(msgnum) - 1; 734 735 bzero(msicap, sizeof(struct msicap)); 736 msicap->capid = PCIY_MSI; 737 msicap->nextptr = nextptr; 738 msicap->msgctrl = PCIM_MSICTRL_64BIT | (mmc << 1); 739 } 740 741 int 742 pci_emul_add_msicap(struct pci_devinst *pi, int msgnum) 743 { 744 struct msicap msicap; 745 746 pci_populate_msicap(&msicap, msgnum, 0); 747 748 return (pci_emul_add_capability(pi, (u_char *)&msicap, sizeof(msicap))); 749 } 750 751 static void 752 pci_populate_msixcap(struct msixcap *msixcap, int msgnum, int barnum, 753 uint32_t msix_tab_size) 754 { 755 CTASSERT(sizeof(struct msixcap) == 12); 756 757 assert(msix_tab_size % 4096 == 0); 758 759 bzero(msixcap, sizeof(struct msixcap)); 760 msixcap->capid = PCIY_MSIX; 761 762 /* 763 * Message Control Register, all fields set to 764 * zero except for the Table Size. 765 * Note: Table size N is encoded as N-1 766 */ 767 msixcap->msgctrl = msgnum - 1; 768 769 /* 770 * MSI-X BAR setup: 771 * - MSI-X table start at offset 0 772 * - PBA table starts at a 4K aligned offset after the MSI-X table 773 */ 774 msixcap->table_info = barnum & PCIM_MSIX_BIR_MASK; 775 msixcap->pba_info = msix_tab_size | (barnum & PCIM_MSIX_BIR_MASK); 776 } 777 778 static void 779 pci_msix_table_init(struct pci_devinst *pi, int table_entries) 780 { 781 int i, table_size; 782 783 assert(table_entries > 0); 784 assert(table_entries <= MAX_MSIX_TABLE_ENTRIES); 785 786 table_size = table_entries * MSIX_TABLE_ENTRY_SIZE; 787 pi->pi_msix.table = calloc(1, table_size); 788 789 /* set mask bit of vector control register */ 790 for (i = 0; i < table_entries; i++) 791 pi->pi_msix.table[i].vector_control |= PCIM_MSIX_VCTRL_MASK; 792 } 793 794 int 795 pci_emul_add_msixcap(struct pci_devinst *pi, int msgnum, int barnum) 796 { 797 uint32_t tab_size; 798 struct msixcap msixcap; 799 800 assert(msgnum >= 1 && msgnum <= MAX_MSIX_TABLE_ENTRIES); 801 assert(barnum >= 0 && barnum <= PCIR_MAX_BAR_0); 802 803 tab_size = msgnum * MSIX_TABLE_ENTRY_SIZE; 804 805 /* Align table size to nearest 4K */ 806 tab_size = roundup2(tab_size, 4096); 807 808 pi->pi_msix.table_bar = barnum; 809 pi->pi_msix.pba_bar = barnum; 810 pi->pi_msix.table_offset = 0; 811 pi->pi_msix.table_count = msgnum; 812 pi->pi_msix.pba_offset = tab_size; 813 pi->pi_msix.pba_size = PBA_SIZE(msgnum); 814 815 pci_msix_table_init(pi, msgnum); 816 817 pci_populate_msixcap(&msixcap, msgnum, barnum, tab_size); 818 819 /* allocate memory for MSI-X Table and PBA */ 820 pci_emul_alloc_bar(pi, barnum, PCIBAR_MEM32, 821 tab_size + pi->pi_msix.pba_size); 822 823 return (pci_emul_add_capability(pi, (u_char *)&msixcap, 824 sizeof(msixcap))); 825 } 826 827 void 828 msixcap_cfgwrite(struct pci_devinst *pi, int capoff, int offset, 829 int bytes, uint32_t val) 830 { 831 uint16_t msgctrl, rwmask; 832 int off, table_bar; 833 834 off = offset - capoff; 835 table_bar = pi->pi_msix.table_bar; 836 /* Message Control Register */ 837 if (off == 2 && bytes == 2) { 838 rwmask = PCIM_MSIXCTRL_MSIX_ENABLE | PCIM_MSIXCTRL_FUNCTION_MASK; 839 msgctrl = pci_get_cfgdata16(pi, offset); 840 msgctrl &= ~rwmask; 841 msgctrl |= val & rwmask; 842 val = msgctrl; 843 844 pi->pi_msix.enabled = val & PCIM_MSIXCTRL_MSIX_ENABLE; 845 pi->pi_msix.function_mask = val & PCIM_MSIXCTRL_FUNCTION_MASK; 846 pci_lintr_update(pi); 847 } 848 849 CFGWRITE(pi, offset, val, bytes); 850 } 851 852 void 853 msicap_cfgwrite(struct pci_devinst *pi, int capoff, int offset, 854 int bytes, uint32_t val) 855 { 856 uint16_t msgctrl, rwmask, msgdata, mme; 857 uint32_t addrlo; 858 859 /* 860 * If guest is writing to the message control register make sure 861 * we do not overwrite read-only fields. 862 */ 863 if ((offset - capoff) == 2 && bytes == 2) { 864 rwmask = PCIM_MSICTRL_MME_MASK | PCIM_MSICTRL_MSI_ENABLE; 865 msgctrl = pci_get_cfgdata16(pi, offset); 866 msgctrl &= ~rwmask; 867 msgctrl |= val & rwmask; 868 val = msgctrl; 869 870 addrlo = pci_get_cfgdata32(pi, capoff + 4); 871 if (msgctrl & PCIM_MSICTRL_64BIT) 872 msgdata = pci_get_cfgdata16(pi, capoff + 12); 873 else 874 msgdata = pci_get_cfgdata16(pi, capoff + 8); 875 876 mme = msgctrl & PCIM_MSICTRL_MME_MASK; 877 pi->pi_msi.enabled = msgctrl & PCIM_MSICTRL_MSI_ENABLE ? 1 : 0; 878 if (pi->pi_msi.enabled) { 879 pi->pi_msi.addr = addrlo; 880 pi->pi_msi.msg_data = msgdata; 881 pi->pi_msi.maxmsgnum = 1 << (mme >> 4); 882 } else { 883 pi->pi_msi.maxmsgnum = 0; 884 } 885 pci_lintr_update(pi); 886 } 887 888 CFGWRITE(pi, offset, val, bytes); 889 } 890 891 void 892 pciecap_cfgwrite(struct pci_devinst *pi, int capoff, int offset, 893 int bytes, uint32_t val) 894 { 895 896 /* XXX don't write to the readonly parts */ 897 CFGWRITE(pi, offset, val, bytes); 898 } 899 900 #define PCIECAP_VERSION 0x2 901 int 902 pci_emul_add_pciecap(struct pci_devinst *pi, int type) 903 { 904 int err; 905 struct pciecap pciecap; 906 907 CTASSERT(sizeof(struct pciecap) == 60); 908 909 if (type != PCIEM_TYPE_ROOT_PORT) 910 return (-1); 911 912 bzero(&pciecap, sizeof(pciecap)); 913 914 pciecap.capid = PCIY_EXPRESS; 915 pciecap.pcie_capabilities = PCIECAP_VERSION | PCIEM_TYPE_ROOT_PORT; 916 pciecap.link_capabilities = 0x411; /* gen1, x1 */ 917 pciecap.link_status = 0x11; /* gen1, x1 */ 918 919 err = pci_emul_add_capability(pi, (u_char *)&pciecap, sizeof(pciecap)); 920 return (err); 921 } 922 923 /* 924 * This function assumes that 'coff' is in the capabilities region of the 925 * config space. 926 */ 927 static void 928 pci_emul_capwrite(struct pci_devinst *pi, int offset, int bytes, uint32_t val) 929 { 930 int capid; 931 uint8_t capoff, nextoff; 932 933 /* Do not allow un-aligned writes */ 934 if ((offset & (bytes - 1)) != 0) 935 return; 936 937 /* Find the capability that we want to update */ 938 capoff = CAP_START_OFFSET; 939 while (1) { 940 nextoff = pci_get_cfgdata8(pi, capoff + 1); 941 if (nextoff == 0) 942 break; 943 if (offset >= capoff && offset < nextoff) 944 break; 945 946 capoff = nextoff; 947 } 948 assert(offset >= capoff); 949 950 /* 951 * Capability ID and Next Capability Pointer are readonly. 952 * However, some o/s's do 4-byte writes that include these. 953 * For this case, trim the write back to 2 bytes and adjust 954 * the data. 955 */ 956 if (offset == capoff || offset == capoff + 1) { 957 if (offset == capoff && bytes == 4) { 958 bytes = 2; 959 offset += 2; 960 val >>= 16; 961 } else 962 return; 963 } 964 965 capid = pci_get_cfgdata8(pi, capoff); 966 switch (capid) { 967 case PCIY_MSI: 968 msicap_cfgwrite(pi, capoff, offset, bytes, val); 969 break; 970 case PCIY_MSIX: 971 msixcap_cfgwrite(pi, capoff, offset, bytes, val); 972 break; 973 case PCIY_EXPRESS: 974 pciecap_cfgwrite(pi, capoff, offset, bytes, val); 975 break; 976 default: 977 break; 978 } 979 } 980 981 static int 982 pci_emul_iscap(struct pci_devinst *pi, int offset) 983 { 984 uint16_t sts; 985 986 sts = pci_get_cfgdata16(pi, PCIR_STATUS); 987 if ((sts & PCIM_STATUS_CAPPRESENT) != 0) { 988 if (offset >= CAP_START_OFFSET && offset <= pi->pi_capend) 989 return (1); 990 } 991 return (0); 992 } 993 994 static int 995 pci_emul_fallback_handler(struct vmctx *ctx, int vcpu, int dir, uint64_t addr, 996 int size, uint64_t *val, void *arg1, long arg2) 997 { 998 /* 999 * Ignore writes; return 0xff's for reads. The mem read code 1000 * will take care of truncating to the correct size. 1001 */ 1002 if (dir == MEM_F_READ) { 1003 *val = 0xffffffffffffffff; 1004 } 1005 1006 return (0); 1007 } 1008 1009 #define BUSIO_ROUNDUP 32 1010 #define BUSMEM_ROUNDUP (1024 * 1024) 1011 1012 int 1013 init_pci(struct vmctx *ctx) 1014 { 1015 struct pci_devemu *pde; 1016 struct businfo *bi; 1017 struct slotinfo *si; 1018 struct funcinfo *fi; 1019 size_t lowmem; 1020 int bus, slot, func; 1021 int error; 1022 1023 pci_emul_iobase = PCI_EMUL_IOBASE; 1024 pci_emul_membase32 = vm_get_lowmem_limit(ctx); 1025 pci_emul_membase64 = PCI_EMUL_MEMBASE64; 1026 1027 for (bus = 0; bus < MAXBUSES; bus++) { 1028 if ((bi = pci_businfo[bus]) == NULL) 1029 continue; 1030 /* 1031 * Keep track of the i/o and memory resources allocated to 1032 * this bus. 1033 */ 1034 bi->iobase = pci_emul_iobase; 1035 bi->membase32 = pci_emul_membase32; 1036 bi->membase64 = pci_emul_membase64; 1037 1038 for (slot = 0; slot < MAXSLOTS; slot++) { 1039 si = &bi->slotinfo[slot]; 1040 for (func = 0; func < MAXFUNCS; func++) { 1041 fi = &si->si_funcs[func]; 1042 if (fi->fi_name == NULL) 1043 continue; 1044 pde = pci_emul_finddev(fi->fi_name); 1045 assert(pde != NULL); 1046 error = pci_emul_init(ctx, pde, bus, slot, 1047 func, fi); 1048 if (error) 1049 return (error); 1050 } 1051 } 1052 1053 /* 1054 * Add some slop to the I/O and memory resources decoded by 1055 * this bus to give a guest some flexibility if it wants to 1056 * reprogram the BARs. 1057 */ 1058 pci_emul_iobase += BUSIO_ROUNDUP; 1059 pci_emul_iobase = roundup2(pci_emul_iobase, BUSIO_ROUNDUP); 1060 bi->iolimit = pci_emul_iobase; 1061 1062 pci_emul_membase32 += BUSMEM_ROUNDUP; 1063 pci_emul_membase32 = roundup2(pci_emul_membase32, 1064 BUSMEM_ROUNDUP); 1065 bi->memlimit32 = pci_emul_membase32; 1066 1067 pci_emul_membase64 += BUSMEM_ROUNDUP; 1068 pci_emul_membase64 = roundup2(pci_emul_membase64, 1069 BUSMEM_ROUNDUP); 1070 bi->memlimit64 = pci_emul_membase64; 1071 } 1072 1073 /* 1074 * PCI backends are initialized before routing INTx interrupts 1075 * so that LPC devices are able to reserve ISA IRQs before 1076 * routing PIRQ pins. 1077 */ 1078 for (bus = 0; bus < MAXBUSES; bus++) { 1079 if ((bi = pci_businfo[bus]) == NULL) 1080 continue; 1081 1082 for (slot = 0; slot < MAXSLOTS; slot++) { 1083 si = &bi->slotinfo[slot]; 1084 for (func = 0; func < MAXFUNCS; func++) { 1085 fi = &si->si_funcs[func]; 1086 if (fi->fi_devi == NULL) 1087 continue; 1088 pci_lintr_route(fi->fi_devi); 1089 } 1090 } 1091 } 1092 lpc_pirq_routed(); 1093 1094 /* 1095 * The guest physical memory map looks like the following: 1096 * [0, lowmem) guest system memory 1097 * [lowmem, lowmem_limit) memory hole (may be absent) 1098 * [lowmem_limit, 4GB) PCI hole (32-bit BAR allocation) 1099 * [4GB, 4GB + highmem) 1100 * 1101 * Accesses to memory addresses that are not allocated to system 1102 * memory or PCI devices return 0xff's. 1103 */ 1104 error = vm_get_memory_seg(ctx, 0, &lowmem, NULL); 1105 assert(error == 0); 1106 1107 memset(&pci_mem_hole, 0, sizeof(struct mem_range)); 1108 pci_mem_hole.name = "PCI hole"; 1109 pci_mem_hole.flags = MEM_F_RW; 1110 pci_mem_hole.base = lowmem; 1111 pci_mem_hole.size = (4ULL * 1024 * 1024 * 1024) - lowmem; 1112 pci_mem_hole.handler = pci_emul_fallback_handler; 1113 1114 error = register_mem_fallback(&pci_mem_hole); 1115 assert(error == 0); 1116 1117 return (0); 1118 } 1119 1120 static void 1121 pci_apic_prt_entry(int bus, int slot, int pin, int pirq_pin, int ioapic_irq, 1122 void *arg) 1123 { 1124 1125 dsdt_line(" Package ()"); 1126 dsdt_line(" {"); 1127 dsdt_line(" 0x%X,", slot << 16 | 0xffff); 1128 dsdt_line(" 0x%02X,", pin - 1); 1129 dsdt_line(" Zero,"); 1130 dsdt_line(" 0x%X", ioapic_irq); 1131 dsdt_line(" },"); 1132 } 1133 1134 static void 1135 pci_pirq_prt_entry(int bus, int slot, int pin, int pirq_pin, int ioapic_irq, 1136 void *arg) 1137 { 1138 char *name; 1139 1140 name = lpc_pirq_name(pirq_pin); 1141 if (name == NULL) 1142 return; 1143 dsdt_line(" Package ()"); 1144 dsdt_line(" {"); 1145 dsdt_line(" 0x%X,", slot << 16 | 0xffff); 1146 dsdt_line(" 0x%02X,", pin - 1); 1147 dsdt_line(" %s,", name); 1148 dsdt_line(" 0x00"); 1149 dsdt_line(" },"); 1150 free(name); 1151 } 1152 1153 /* 1154 * A bhyve virtual machine has a flat PCI hierarchy with a root port 1155 * corresponding to each PCI bus. 1156 */ 1157 static void 1158 pci_bus_write_dsdt(int bus) 1159 { 1160 struct businfo *bi; 1161 struct slotinfo *si; 1162 struct pci_devinst *pi; 1163 int count, func, slot; 1164 1165 /* 1166 * If there are no devices on this 'bus' then just return. 1167 */ 1168 if ((bi = pci_businfo[bus]) == NULL) { 1169 /* 1170 * Bus 0 is special because it decodes the I/O ports used 1171 * for PCI config space access even if there are no devices 1172 * on it. 1173 */ 1174 if (bus != 0) 1175 return; 1176 } 1177 1178 dsdt_line(" Device (PC%02X)", bus); 1179 dsdt_line(" {"); 1180 dsdt_line(" Name (_HID, EisaId (\"PNP0A03\"))"); 1181 dsdt_line(" Name (_ADR, Zero)"); 1182 1183 dsdt_line(" Method (_BBN, 0, NotSerialized)"); 1184 dsdt_line(" {"); 1185 dsdt_line(" Return (0x%08X)", bus); 1186 dsdt_line(" }"); 1187 dsdt_line(" Name (_CRS, ResourceTemplate ()"); 1188 dsdt_line(" {"); 1189 dsdt_line(" WordBusNumber (ResourceProducer, MinFixed, " 1190 "MaxFixed, PosDecode,"); 1191 dsdt_line(" 0x0000, // Granularity"); 1192 dsdt_line(" 0x%04X, // Range Minimum", bus); 1193 dsdt_line(" 0x%04X, // Range Maximum", bus); 1194 dsdt_line(" 0x0000, // Translation Offset"); 1195 dsdt_line(" 0x0001, // Length"); 1196 dsdt_line(" ,, )"); 1197 1198 if (bus == 0) { 1199 dsdt_indent(3); 1200 dsdt_fixed_ioport(0xCF8, 8); 1201 dsdt_unindent(3); 1202 1203 dsdt_line(" WordIO (ResourceProducer, MinFixed, MaxFixed, " 1204 "PosDecode, EntireRange,"); 1205 dsdt_line(" 0x0000, // Granularity"); 1206 dsdt_line(" 0x0000, // Range Minimum"); 1207 dsdt_line(" 0x0CF7, // Range Maximum"); 1208 dsdt_line(" 0x0000, // Translation Offset"); 1209 dsdt_line(" 0x0CF8, // Length"); 1210 dsdt_line(" ,, , TypeStatic)"); 1211 1212 dsdt_line(" WordIO (ResourceProducer, MinFixed, MaxFixed, " 1213 "PosDecode, EntireRange,"); 1214 dsdt_line(" 0x0000, // Granularity"); 1215 dsdt_line(" 0x0D00, // Range Minimum"); 1216 dsdt_line(" 0x%04X, // Range Maximum", 1217 PCI_EMUL_IOBASE - 1); 1218 dsdt_line(" 0x0000, // Translation Offset"); 1219 dsdt_line(" 0x%04X, // Length", 1220 PCI_EMUL_IOBASE - 0x0D00); 1221 dsdt_line(" ,, , TypeStatic)"); 1222 1223 if (bi == NULL) { 1224 dsdt_line(" })"); 1225 goto done; 1226 } 1227 } 1228 assert(bi != NULL); 1229 1230 /* i/o window */ 1231 dsdt_line(" WordIO (ResourceProducer, MinFixed, MaxFixed, " 1232 "PosDecode, EntireRange,"); 1233 dsdt_line(" 0x0000, // Granularity"); 1234 dsdt_line(" 0x%04X, // Range Minimum", bi->iobase); 1235 dsdt_line(" 0x%04X, // Range Maximum", 1236 bi->iolimit - 1); 1237 dsdt_line(" 0x0000, // Translation Offset"); 1238 dsdt_line(" 0x%04X, // Length", 1239 bi->iolimit - bi->iobase); 1240 dsdt_line(" ,, , TypeStatic)"); 1241 1242 /* mmio window (32-bit) */ 1243 dsdt_line(" DWordMemory (ResourceProducer, PosDecode, " 1244 "MinFixed, MaxFixed, NonCacheable, ReadWrite,"); 1245 dsdt_line(" 0x00000000, // Granularity"); 1246 dsdt_line(" 0x%08X, // Range Minimum\n", bi->membase32); 1247 dsdt_line(" 0x%08X, // Range Maximum\n", 1248 bi->memlimit32 - 1); 1249 dsdt_line(" 0x00000000, // Translation Offset"); 1250 dsdt_line(" 0x%08X, // Length\n", 1251 bi->memlimit32 - bi->membase32); 1252 dsdt_line(" ,, , AddressRangeMemory, TypeStatic)"); 1253 1254 /* mmio window (64-bit) */ 1255 dsdt_line(" QWordMemory (ResourceProducer, PosDecode, " 1256 "MinFixed, MaxFixed, NonCacheable, ReadWrite,"); 1257 dsdt_line(" 0x0000000000000000, // Granularity"); 1258 dsdt_line(" 0x%016lX, // Range Minimum\n", bi->membase64); 1259 dsdt_line(" 0x%016lX, // Range Maximum\n", 1260 bi->memlimit64 - 1); 1261 dsdt_line(" 0x0000000000000000, // Translation Offset"); 1262 dsdt_line(" 0x%016lX, // Length\n", 1263 bi->memlimit64 - bi->membase64); 1264 dsdt_line(" ,, , AddressRangeMemory, TypeStatic)"); 1265 dsdt_line(" })"); 1266 1267 count = pci_count_lintr(bus); 1268 if (count != 0) { 1269 dsdt_indent(2); 1270 dsdt_line("Name (PPRT, Package ()"); 1271 dsdt_line("{"); 1272 pci_walk_lintr(bus, pci_pirq_prt_entry, NULL); 1273 dsdt_line("})"); 1274 dsdt_line("Name (APRT, Package ()"); 1275 dsdt_line("{"); 1276 pci_walk_lintr(bus, pci_apic_prt_entry, NULL); 1277 dsdt_line("})"); 1278 dsdt_line("Method (_PRT, 0, NotSerialized)"); 1279 dsdt_line("{"); 1280 dsdt_line(" If (PICM)"); 1281 dsdt_line(" {"); 1282 dsdt_line(" Return (APRT)"); 1283 dsdt_line(" }"); 1284 dsdt_line(" Else"); 1285 dsdt_line(" {"); 1286 dsdt_line(" Return (PPRT)"); 1287 dsdt_line(" }"); 1288 dsdt_line("}"); 1289 dsdt_unindent(2); 1290 } 1291 1292 dsdt_indent(2); 1293 for (slot = 0; slot < MAXSLOTS; slot++) { 1294 si = &bi->slotinfo[slot]; 1295 for (func = 0; func < MAXFUNCS; func++) { 1296 pi = si->si_funcs[func].fi_devi; 1297 if (pi != NULL && pi->pi_d->pe_write_dsdt != NULL) 1298 pi->pi_d->pe_write_dsdt(pi); 1299 } 1300 } 1301 dsdt_unindent(2); 1302 done: 1303 dsdt_line(" }"); 1304 } 1305 1306 void 1307 pci_write_dsdt(void) 1308 { 1309 int bus; 1310 1311 dsdt_indent(1); 1312 dsdt_line("Name (PICM, 0x00)"); 1313 dsdt_line("Method (_PIC, 1, NotSerialized)"); 1314 dsdt_line("{"); 1315 dsdt_line(" Store (Arg0, PICM)"); 1316 dsdt_line("}"); 1317 dsdt_line(""); 1318 dsdt_line("Scope (_SB)"); 1319 dsdt_line("{"); 1320 for (bus = 0; bus < MAXBUSES; bus++) 1321 pci_bus_write_dsdt(bus); 1322 dsdt_line("}"); 1323 dsdt_unindent(1); 1324 } 1325 1326 int 1327 pci_bus_configured(int bus) 1328 { 1329 assert(bus >= 0 && bus < MAXBUSES); 1330 return (pci_businfo[bus] != NULL); 1331 } 1332 1333 int 1334 pci_msi_enabled(struct pci_devinst *pi) 1335 { 1336 return (pi->pi_msi.enabled); 1337 } 1338 1339 int 1340 pci_msi_maxmsgnum(struct pci_devinst *pi) 1341 { 1342 if (pi->pi_msi.enabled) 1343 return (pi->pi_msi.maxmsgnum); 1344 else 1345 return (0); 1346 } 1347 1348 int 1349 pci_msix_enabled(struct pci_devinst *pi) 1350 { 1351 1352 return (pi->pi_msix.enabled && !pi->pi_msi.enabled); 1353 } 1354 1355 void 1356 pci_generate_msix(struct pci_devinst *pi, int index) 1357 { 1358 struct msix_table_entry *mte; 1359 1360 if (!pci_msix_enabled(pi)) 1361 return; 1362 1363 if (pi->pi_msix.function_mask) 1364 return; 1365 1366 if (index >= pi->pi_msix.table_count) 1367 return; 1368 1369 mte = &pi->pi_msix.table[index]; 1370 if ((mte->vector_control & PCIM_MSIX_VCTRL_MASK) == 0) { 1371 /* XXX Set PBA bit if interrupt is disabled */ 1372 vm_lapic_msi(pi->pi_vmctx, mte->addr, mte->msg_data); 1373 } 1374 } 1375 1376 void 1377 pci_generate_msi(struct pci_devinst *pi, int index) 1378 { 1379 1380 if (pci_msi_enabled(pi) && index < pci_msi_maxmsgnum(pi)) { 1381 vm_lapic_msi(pi->pi_vmctx, pi->pi_msi.addr, 1382 pi->pi_msi.msg_data + index); 1383 } 1384 } 1385 1386 static bool 1387 pci_lintr_permitted(struct pci_devinst *pi) 1388 { 1389 uint16_t cmd; 1390 1391 cmd = pci_get_cfgdata16(pi, PCIR_COMMAND); 1392 return (!(pi->pi_msi.enabled || pi->pi_msix.enabled || 1393 (cmd & PCIM_CMD_INTxDIS))); 1394 } 1395 1396 void 1397 pci_lintr_request(struct pci_devinst *pi) 1398 { 1399 struct businfo *bi; 1400 struct slotinfo *si; 1401 int bestpin, bestcount, pin; 1402 1403 bi = pci_businfo[pi->pi_bus]; 1404 assert(bi != NULL); 1405 1406 /* 1407 * Just allocate a pin from our slot. The pin will be 1408 * assigned IRQs later when interrupts are routed. 1409 */ 1410 si = &bi->slotinfo[pi->pi_slot]; 1411 bestpin = 0; 1412 bestcount = si->si_intpins[0].ii_count; 1413 for (pin = 1; pin < 4; pin++) { 1414 if (si->si_intpins[pin].ii_count < bestcount) { 1415 bestpin = pin; 1416 bestcount = si->si_intpins[pin].ii_count; 1417 } 1418 } 1419 1420 si->si_intpins[bestpin].ii_count++; 1421 pi->pi_lintr.pin = bestpin + 1; 1422 pci_set_cfgdata8(pi, PCIR_INTPIN, bestpin + 1); 1423 } 1424 1425 static void 1426 pci_lintr_route(struct pci_devinst *pi) 1427 { 1428 struct businfo *bi; 1429 struct intxinfo *ii; 1430 1431 if (pi->pi_lintr.pin == 0) 1432 return; 1433 1434 bi = pci_businfo[pi->pi_bus]; 1435 assert(bi != NULL); 1436 ii = &bi->slotinfo[pi->pi_slot].si_intpins[pi->pi_lintr.pin - 1]; 1437 1438 /* 1439 * Attempt to allocate an I/O APIC pin for this intpin if one 1440 * is not yet assigned. 1441 */ 1442 if (ii->ii_ioapic_irq == 0) 1443 ii->ii_ioapic_irq = ioapic_pci_alloc_irq(); 1444 assert(ii->ii_ioapic_irq > 0); 1445 1446 /* 1447 * Attempt to allocate a PIRQ pin for this intpin if one is 1448 * not yet assigned. 1449 */ 1450 if (ii->ii_pirq_pin == 0) 1451 ii->ii_pirq_pin = pirq_alloc_pin(pi->pi_vmctx); 1452 assert(ii->ii_pirq_pin > 0); 1453 1454 pi->pi_lintr.ioapic_irq = ii->ii_ioapic_irq; 1455 pi->pi_lintr.pirq_pin = ii->ii_pirq_pin; 1456 pci_set_cfgdata8(pi, PCIR_INTLINE, pirq_irq(ii->ii_pirq_pin)); 1457 } 1458 1459 void 1460 pci_lintr_assert(struct pci_devinst *pi) 1461 { 1462 1463 assert(pi->pi_lintr.pin > 0); 1464 1465 pthread_mutex_lock(&pi->pi_lintr.lock); 1466 if (pi->pi_lintr.state == IDLE) { 1467 if (pci_lintr_permitted(pi)) { 1468 pi->pi_lintr.state = ASSERTED; 1469 pci_irq_assert(pi); 1470 } else 1471 pi->pi_lintr.state = PENDING; 1472 } 1473 pthread_mutex_unlock(&pi->pi_lintr.lock); 1474 } 1475 1476 void 1477 pci_lintr_deassert(struct pci_devinst *pi) 1478 { 1479 1480 assert(pi->pi_lintr.pin > 0); 1481 1482 pthread_mutex_lock(&pi->pi_lintr.lock); 1483 if (pi->pi_lintr.state == ASSERTED) { 1484 pi->pi_lintr.state = IDLE; 1485 pci_irq_deassert(pi); 1486 } else if (pi->pi_lintr.state == PENDING) 1487 pi->pi_lintr.state = IDLE; 1488 pthread_mutex_unlock(&pi->pi_lintr.lock); 1489 } 1490 1491 static void 1492 pci_lintr_update(struct pci_devinst *pi) 1493 { 1494 1495 pthread_mutex_lock(&pi->pi_lintr.lock); 1496 if (pi->pi_lintr.state == ASSERTED && !pci_lintr_permitted(pi)) { 1497 pci_irq_deassert(pi); 1498 pi->pi_lintr.state = PENDING; 1499 } else if (pi->pi_lintr.state == PENDING && pci_lintr_permitted(pi)) { 1500 pi->pi_lintr.state = ASSERTED; 1501 pci_irq_assert(pi); 1502 } 1503 pthread_mutex_unlock(&pi->pi_lintr.lock); 1504 } 1505 1506 int 1507 pci_count_lintr(int bus) 1508 { 1509 int count, slot, pin; 1510 struct slotinfo *slotinfo; 1511 1512 count = 0; 1513 if (pci_businfo[bus] != NULL) { 1514 for (slot = 0; slot < MAXSLOTS; slot++) { 1515 slotinfo = &pci_businfo[bus]->slotinfo[slot]; 1516 for (pin = 0; pin < 4; pin++) { 1517 if (slotinfo->si_intpins[pin].ii_count != 0) 1518 count++; 1519 } 1520 } 1521 } 1522 return (count); 1523 } 1524 1525 void 1526 pci_walk_lintr(int bus, pci_lintr_cb cb, void *arg) 1527 { 1528 struct businfo *bi; 1529 struct slotinfo *si; 1530 struct intxinfo *ii; 1531 int slot, pin; 1532 1533 if ((bi = pci_businfo[bus]) == NULL) 1534 return; 1535 1536 for (slot = 0; slot < MAXSLOTS; slot++) { 1537 si = &bi->slotinfo[slot]; 1538 for (pin = 0; pin < 4; pin++) { 1539 ii = &si->si_intpins[pin]; 1540 if (ii->ii_count != 0) 1541 cb(bus, slot, pin + 1, ii->ii_pirq_pin, 1542 ii->ii_ioapic_irq, arg); 1543 } 1544 } 1545 } 1546 1547 /* 1548 * Return 1 if the emulated device in 'slot' is a multi-function device. 1549 * Return 0 otherwise. 1550 */ 1551 static int 1552 pci_emul_is_mfdev(int bus, int slot) 1553 { 1554 struct businfo *bi; 1555 struct slotinfo *si; 1556 int f, numfuncs; 1557 1558 numfuncs = 0; 1559 if ((bi = pci_businfo[bus]) != NULL) { 1560 si = &bi->slotinfo[slot]; 1561 for (f = 0; f < MAXFUNCS; f++) { 1562 if (si->si_funcs[f].fi_devi != NULL) { 1563 numfuncs++; 1564 } 1565 } 1566 } 1567 return (numfuncs > 1); 1568 } 1569 1570 /* 1571 * Ensure that the PCIM_MFDEV bit is properly set (or unset) depending on 1572 * whether or not is a multi-function being emulated in the pci 'slot'. 1573 */ 1574 static void 1575 pci_emul_hdrtype_fixup(int bus, int slot, int off, int bytes, uint32_t *rv) 1576 { 1577 int mfdev; 1578 1579 if (off <= PCIR_HDRTYPE && off + bytes > PCIR_HDRTYPE) { 1580 mfdev = pci_emul_is_mfdev(bus, slot); 1581 switch (bytes) { 1582 case 1: 1583 case 2: 1584 *rv &= ~PCIM_MFDEV; 1585 if (mfdev) { 1586 *rv |= PCIM_MFDEV; 1587 } 1588 break; 1589 case 4: 1590 *rv &= ~(PCIM_MFDEV << 16); 1591 if (mfdev) { 1592 *rv |= (PCIM_MFDEV << 16); 1593 } 1594 break; 1595 } 1596 } 1597 } 1598 1599 static int cfgenable, cfgbus, cfgslot, cfgfunc, cfgoff; 1600 1601 static int 1602 pci_emul_cfgaddr(struct vmctx *ctx, int vcpu, int in, int port, int bytes, 1603 uint32_t *eax, void *arg) 1604 { 1605 uint32_t x; 1606 1607 if (bytes != 4) { 1608 if (in) 1609 *eax = (bytes == 2) ? 0xffff : 0xff; 1610 return (0); 1611 } 1612 1613 if (in) { 1614 x = (cfgbus << 16) | 1615 (cfgslot << 11) | 1616 (cfgfunc << 8) | 1617 cfgoff; 1618 if (cfgenable) 1619 x |= CONF1_ENABLE; 1620 *eax = x; 1621 } else { 1622 x = *eax; 1623 cfgenable = (x & CONF1_ENABLE) == CONF1_ENABLE; 1624 cfgoff = x & PCI_REGMAX; 1625 cfgfunc = (x >> 8) & PCI_FUNCMAX; 1626 cfgslot = (x >> 11) & PCI_SLOTMAX; 1627 cfgbus = (x >> 16) & PCI_BUSMAX; 1628 } 1629 1630 return (0); 1631 } 1632 INOUT_PORT(pci_cfgaddr, CONF1_ADDR_PORT, IOPORT_F_INOUT, pci_emul_cfgaddr); 1633 1634 static uint32_t 1635 bits_changed(uint32_t old, uint32_t new, uint32_t mask) 1636 { 1637 1638 return ((old ^ new) & mask); 1639 } 1640 1641 static void 1642 pci_emul_cmdwrite(struct pci_devinst *pi, uint32_t new, int bytes) 1643 { 1644 int i; 1645 uint16_t old; 1646 1647 /* 1648 * The command register is at an offset of 4 bytes and thus the 1649 * guest could write 1, 2 or 4 bytes starting at this offset. 1650 */ 1651 1652 old = pci_get_cfgdata16(pi, PCIR_COMMAND); /* stash old value */ 1653 CFGWRITE(pi, PCIR_COMMAND, new, bytes); /* update config */ 1654 new = pci_get_cfgdata16(pi, PCIR_COMMAND); /* get updated value */ 1655 1656 /* 1657 * If the MMIO or I/O address space decoding has changed then 1658 * register/unregister all BARs that decode that address space. 1659 */ 1660 for (i = 0; i <= PCI_BARMAX; i++) { 1661 switch (pi->pi_bar[i].type) { 1662 case PCIBAR_NONE: 1663 case PCIBAR_MEMHI64: 1664 break; 1665 case PCIBAR_IO: 1666 /* I/O address space decoding changed? */ 1667 if (bits_changed(old, new, PCIM_CMD_PORTEN)) { 1668 if (porten(pi)) 1669 register_bar(pi, i); 1670 else 1671 unregister_bar(pi, i); 1672 } 1673 break; 1674 case PCIBAR_MEM32: 1675 case PCIBAR_MEM64: 1676 /* MMIO address space decoding changed? */ 1677 if (bits_changed(old, new, PCIM_CMD_MEMEN)) { 1678 if (memen(pi)) 1679 register_bar(pi, i); 1680 else 1681 unregister_bar(pi, i); 1682 } 1683 break; 1684 default: 1685 assert(0); 1686 } 1687 } 1688 1689 /* 1690 * If INTx has been unmasked and is pending, assert the 1691 * interrupt. 1692 */ 1693 pci_lintr_update(pi); 1694 } 1695 1696 static int 1697 pci_emul_cfgdata(struct vmctx *ctx, int vcpu, int in, int port, int bytes, 1698 uint32_t *eax, void *arg) 1699 { 1700 struct businfo *bi; 1701 struct slotinfo *si; 1702 struct pci_devinst *pi; 1703 struct pci_devemu *pe; 1704 int coff, idx, needcfg; 1705 uint64_t addr, bar, mask; 1706 1707 assert(bytes == 1 || bytes == 2 || bytes == 4); 1708 1709 if ((bi = pci_businfo[cfgbus]) != NULL) { 1710 si = &bi->slotinfo[cfgslot]; 1711 pi = si->si_funcs[cfgfunc].fi_devi; 1712 } else 1713 pi = NULL; 1714 1715 coff = cfgoff + (port - CONF1_DATA_PORT); 1716 1717 #if 0 1718 printf("pcicfg-%s from 0x%0x of %d bytes (%d/%d/%d)\n\r", 1719 in ? "read" : "write", coff, bytes, cfgbus, cfgslot, cfgfunc); 1720 #endif 1721 1722 /* 1723 * Just return if there is no device at this cfgslot:cfgfunc, 1724 * if the guest is doing an un-aligned access, or if the config 1725 * address word isn't enabled. 1726 */ 1727 if (!cfgenable || pi == NULL || (coff & (bytes - 1)) != 0) { 1728 if (in) 1729 *eax = 0xffffffff; 1730 return (0); 1731 } 1732 1733 pe = pi->pi_d; 1734 1735 /* 1736 * Config read 1737 */ 1738 if (in) { 1739 /* Let the device emulation override the default handler */ 1740 if (pe->pe_cfgread != NULL) { 1741 needcfg = pe->pe_cfgread(ctx, vcpu, pi, 1742 coff, bytes, eax); 1743 } else { 1744 needcfg = 1; 1745 } 1746 1747 if (needcfg) { 1748 if (bytes == 1) 1749 *eax = pci_get_cfgdata8(pi, coff); 1750 else if (bytes == 2) 1751 *eax = pci_get_cfgdata16(pi, coff); 1752 else 1753 *eax = pci_get_cfgdata32(pi, coff); 1754 } 1755 1756 pci_emul_hdrtype_fixup(cfgbus, cfgslot, coff, bytes, eax); 1757 } else { 1758 /* Let the device emulation override the default handler */ 1759 if (pe->pe_cfgwrite != NULL && 1760 (*pe->pe_cfgwrite)(ctx, vcpu, pi, coff, bytes, *eax) == 0) 1761 return (0); 1762 1763 /* 1764 * Special handling for write to BAR registers 1765 */ 1766 if (coff >= PCIR_BAR(0) && coff < PCIR_BAR(PCI_BARMAX + 1)) { 1767 /* 1768 * Ignore writes to BAR registers that are not 1769 * 4-byte aligned. 1770 */ 1771 if (bytes != 4 || (coff & 0x3) != 0) 1772 return (0); 1773 idx = (coff - PCIR_BAR(0)) / 4; 1774 mask = ~(pi->pi_bar[idx].size - 1); 1775 switch (pi->pi_bar[idx].type) { 1776 case PCIBAR_NONE: 1777 pi->pi_bar[idx].addr = bar = 0; 1778 break; 1779 case PCIBAR_IO: 1780 addr = *eax & mask; 1781 addr &= 0xffff; 1782 bar = addr | PCIM_BAR_IO_SPACE; 1783 /* 1784 * Register the new BAR value for interception 1785 */ 1786 if (addr != pi->pi_bar[idx].addr) { 1787 update_bar_address(pi, addr, idx, 1788 PCIBAR_IO); 1789 } 1790 break; 1791 case PCIBAR_MEM32: 1792 addr = bar = *eax & mask; 1793 bar |= PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_32; 1794 if (addr != pi->pi_bar[idx].addr) { 1795 update_bar_address(pi, addr, idx, 1796 PCIBAR_MEM32); 1797 } 1798 break; 1799 case PCIBAR_MEM64: 1800 addr = bar = *eax & mask; 1801 bar |= PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_64 | 1802 PCIM_BAR_MEM_PREFETCH; 1803 if (addr != (uint32_t)pi->pi_bar[idx].addr) { 1804 update_bar_address(pi, addr, idx, 1805 PCIBAR_MEM64); 1806 } 1807 break; 1808 case PCIBAR_MEMHI64: 1809 mask = ~(pi->pi_bar[idx - 1].size - 1); 1810 addr = ((uint64_t)*eax << 32) & mask; 1811 bar = addr >> 32; 1812 if (bar != pi->pi_bar[idx - 1].addr >> 32) { 1813 update_bar_address(pi, addr, idx - 1, 1814 PCIBAR_MEMHI64); 1815 } 1816 break; 1817 default: 1818 assert(0); 1819 } 1820 pci_set_cfgdata32(pi, coff, bar); 1821 1822 } else if (pci_emul_iscap(pi, coff)) { 1823 pci_emul_capwrite(pi, coff, bytes, *eax); 1824 } else if (coff == PCIR_COMMAND) { 1825 pci_emul_cmdwrite(pi, *eax, bytes); 1826 } else { 1827 CFGWRITE(pi, coff, *eax, bytes); 1828 } 1829 } 1830 1831 return (0); 1832 } 1833 1834 INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+0, IOPORT_F_INOUT, pci_emul_cfgdata); 1835 INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+1, IOPORT_F_INOUT, pci_emul_cfgdata); 1836 INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+2, IOPORT_F_INOUT, pci_emul_cfgdata); 1837 INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+3, IOPORT_F_INOUT, pci_emul_cfgdata); 1838 1839 #define PCI_EMUL_TEST 1840 #ifdef PCI_EMUL_TEST 1841 /* 1842 * Define a dummy test device 1843 */ 1844 #define DIOSZ 8 1845 #define DMEMSZ 4096 1846 struct pci_emul_dsoftc { 1847 uint8_t ioregs[DIOSZ]; 1848 uint8_t memregs[DMEMSZ]; 1849 }; 1850 1851 #define PCI_EMUL_MSI_MSGS 4 1852 #define PCI_EMUL_MSIX_MSGS 16 1853 1854 static int 1855 pci_emul_dinit(struct vmctx *ctx, struct pci_devinst *pi, char *opts) 1856 { 1857 int error; 1858 struct pci_emul_dsoftc *sc; 1859 1860 sc = calloc(1, sizeof(struct pci_emul_dsoftc)); 1861 1862 pi->pi_arg = sc; 1863 1864 pci_set_cfgdata16(pi, PCIR_DEVICE, 0x0001); 1865 pci_set_cfgdata16(pi, PCIR_VENDOR, 0x10DD); 1866 pci_set_cfgdata8(pi, PCIR_CLASS, 0x02); 1867 1868 error = pci_emul_add_msicap(pi, PCI_EMUL_MSI_MSGS); 1869 assert(error == 0); 1870 1871 error = pci_emul_alloc_bar(pi, 0, PCIBAR_IO, DIOSZ); 1872 assert(error == 0); 1873 1874 error = pci_emul_alloc_bar(pi, 1, PCIBAR_MEM32, DMEMSZ); 1875 assert(error == 0); 1876 1877 return (0); 1878 } 1879 1880 static void 1881 pci_emul_diow(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, int baridx, 1882 uint64_t offset, int size, uint64_t value) 1883 { 1884 int i; 1885 struct pci_emul_dsoftc *sc = pi->pi_arg; 1886 1887 if (baridx == 0) { 1888 if (offset + size > DIOSZ) { 1889 printf("diow: iow too large, offset %ld size %d\n", 1890 offset, size); 1891 return; 1892 } 1893 1894 if (size == 1) { 1895 sc->ioregs[offset] = value & 0xff; 1896 } else if (size == 2) { 1897 *(uint16_t *)&sc->ioregs[offset] = value & 0xffff; 1898 } else if (size == 4) { 1899 *(uint32_t *)&sc->ioregs[offset] = value; 1900 } else { 1901 printf("diow: iow unknown size %d\n", size); 1902 } 1903 1904 /* 1905 * Special magic value to generate an interrupt 1906 */ 1907 if (offset == 4 && size == 4 && pci_msi_enabled(pi)) 1908 pci_generate_msi(pi, value % pci_msi_maxmsgnum(pi)); 1909 1910 if (value == 0xabcdef) { 1911 for (i = 0; i < pci_msi_maxmsgnum(pi); i++) 1912 pci_generate_msi(pi, i); 1913 } 1914 } 1915 1916 if (baridx == 1) { 1917 if (offset + size > DMEMSZ) { 1918 printf("diow: memw too large, offset %ld size %d\n", 1919 offset, size); 1920 return; 1921 } 1922 1923 if (size == 1) { 1924 sc->memregs[offset] = value; 1925 } else if (size == 2) { 1926 *(uint16_t *)&sc->memregs[offset] = value; 1927 } else if (size == 4) { 1928 *(uint32_t *)&sc->memregs[offset] = value; 1929 } else if (size == 8) { 1930 *(uint64_t *)&sc->memregs[offset] = value; 1931 } else { 1932 printf("diow: memw unknown size %d\n", size); 1933 } 1934 1935 /* 1936 * magic interrupt ?? 1937 */ 1938 } 1939 1940 if (baridx > 1) { 1941 printf("diow: unknown bar idx %d\n", baridx); 1942 } 1943 } 1944 1945 static uint64_t 1946 pci_emul_dior(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, int baridx, 1947 uint64_t offset, int size) 1948 { 1949 struct pci_emul_dsoftc *sc = pi->pi_arg; 1950 uint32_t value; 1951 1952 if (baridx == 0) { 1953 if (offset + size > DIOSZ) { 1954 printf("dior: ior too large, offset %ld size %d\n", 1955 offset, size); 1956 return (0); 1957 } 1958 1959 if (size == 1) { 1960 value = sc->ioregs[offset]; 1961 } else if (size == 2) { 1962 value = *(uint16_t *) &sc->ioregs[offset]; 1963 } else if (size == 4) { 1964 value = *(uint32_t *) &sc->ioregs[offset]; 1965 } else { 1966 printf("dior: ior unknown size %d\n", size); 1967 } 1968 } 1969 1970 if (baridx == 1) { 1971 if (offset + size > DMEMSZ) { 1972 printf("dior: memr too large, offset %ld size %d\n", 1973 offset, size); 1974 return (0); 1975 } 1976 1977 if (size == 1) { 1978 value = sc->memregs[offset]; 1979 } else if (size == 2) { 1980 value = *(uint16_t *) &sc->memregs[offset]; 1981 } else if (size == 4) { 1982 value = *(uint32_t *) &sc->memregs[offset]; 1983 } else if (size == 8) { 1984 value = *(uint64_t *) &sc->memregs[offset]; 1985 } else { 1986 printf("dior: ior unknown size %d\n", size); 1987 } 1988 } 1989 1990 1991 if (baridx > 1) { 1992 printf("dior: unknown bar idx %d\n", baridx); 1993 return (0); 1994 } 1995 1996 return (value); 1997 } 1998 1999 struct pci_devemu pci_dummy = { 2000 .pe_emu = "dummy", 2001 .pe_init = pci_emul_dinit, 2002 .pe_barwrite = pci_emul_diow, 2003 .pe_barread = pci_emul_dior 2004 }; 2005 PCI_EMUL_SET(pci_dummy); 2006 2007 #endif /* PCI_EMUL_TEST */ 2008