1 /* 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2016 Alexander Motin <mav@FreeBSD.org> 5 * Copyright (c) 2015 Peter Grehan <grehan@freebsd.org> 6 * Copyright (c) 2013 Jeremiah Lott, Avere Systems 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer 14 * in this position and unchanged. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __FBSDID("$FreeBSD$"); 34 35 #include <sys/types.h> 36 #ifndef WITHOUT_CAPSICUM 37 #include <sys/capsicum.h> 38 #endif 39 #include <sys/limits.h> 40 #include <sys/ioctl.h> 41 #include <sys/uio.h> 42 #include <net/ethernet.h> 43 #include <netinet/in.h> 44 #include <netinet/tcp.h> 45 46 #ifndef WITHOUT_CAPSICUM 47 #include <capsicum_helpers.h> 48 #endif 49 #include <err.h> 50 #include <errno.h> 51 #include <fcntl.h> 52 #include <md5.h> 53 #include <stdio.h> 54 #include <stdlib.h> 55 #include <string.h> 56 #include <sysexits.h> 57 #include <unistd.h> 58 #include <pthread.h> 59 #include <pthread_np.h> 60 61 #include "e1000_regs.h" 62 #include "e1000_defines.h" 63 #include "mii.h" 64 65 #include "bhyverun.h" 66 #include "pci_emul.h" 67 #include "mevent.h" 68 #include "net_utils.h" 69 #include "net_backends.h" 70 71 /* Hardware/register definitions XXX: move some to common code. */ 72 #define E82545_VENDOR_ID_INTEL 0x8086 73 #define E82545_DEV_ID_82545EM_COPPER 0x100F 74 #define E82545_SUBDEV_ID 0x1008 75 76 #define E82545_REVISION_4 4 77 78 #define E82545_MDIC_DATA_MASK 0x0000FFFF 79 #define E82545_MDIC_OP_MASK 0x0c000000 80 #define E82545_MDIC_IE 0x20000000 81 82 #define E82545_EECD_FWE_DIS 0x00000010 /* Flash writes disabled */ 83 #define E82545_EECD_FWE_EN 0x00000020 /* Flash writes enabled */ 84 #define E82545_EECD_FWE_MASK 0x00000030 /* Flash writes mask */ 85 86 #define E82545_BAR_REGISTER 0 87 #define E82545_BAR_REGISTER_LEN (128*1024) 88 #define E82545_BAR_FLASH 1 89 #define E82545_BAR_FLASH_LEN (64*1024) 90 #define E82545_BAR_IO 2 91 #define E82545_BAR_IO_LEN 8 92 93 #define E82545_IOADDR 0x00000000 94 #define E82545_IODATA 0x00000004 95 #define E82545_IO_REGISTER_MAX 0x0001FFFF 96 #define E82545_IO_FLASH_BASE 0x00080000 97 #define E82545_IO_FLASH_MAX 0x000FFFFF 98 99 #define E82545_ARRAY_ENTRY(reg, offset) (reg + (offset<<2)) 100 #define E82545_RAR_MAX 15 101 #define E82545_MTA_MAX 127 102 #define E82545_VFTA_MAX 127 103 104 /* Slightly modified from the driver versions, hardcoded for 3 opcode bits, 105 * followed by 6 address bits. 106 * TODO: make opcode bits and addr bits configurable? 107 * NVM Commands - Microwire */ 108 #define E82545_NVM_OPCODE_BITS 3 109 #define E82545_NVM_ADDR_BITS 6 110 #define E82545_NVM_DATA_BITS 16 111 #define E82545_NVM_OPADDR_BITS (E82545_NVM_OPCODE_BITS + E82545_NVM_ADDR_BITS) 112 #define E82545_NVM_ADDR_MASK ((1 << E82545_NVM_ADDR_BITS)-1) 113 #define E82545_NVM_OPCODE_MASK \ 114 (((1 << E82545_NVM_OPCODE_BITS) - 1) << E82545_NVM_ADDR_BITS) 115 #define E82545_NVM_OPCODE_READ (0x6 << E82545_NVM_ADDR_BITS) /* read */ 116 #define E82545_NVM_OPCODE_WRITE (0x5 << E82545_NVM_ADDR_BITS) /* write */ 117 #define E82545_NVM_OPCODE_ERASE (0x7 << E82545_NVM_ADDR_BITS) /* erase */ 118 #define E82545_NVM_OPCODE_EWEN (0x4 << E82545_NVM_ADDR_BITS) /* wr-enable */ 119 120 #define E82545_NVM_EEPROM_SIZE 64 /* 64 * 16-bit values == 128K */ 121 122 #define E1000_ICR_SRPD 0x00010000 123 124 /* This is an arbitrary number. There is no hard limit on the chip. */ 125 #define I82545_MAX_TXSEGS 64 126 127 /* Legacy receive descriptor */ 128 struct e1000_rx_desc { 129 uint64_t buffer_addr; /* Address of the descriptor's data buffer */ 130 uint16_t length; /* Length of data DMAed into data buffer */ 131 uint16_t csum; /* Packet checksum */ 132 uint8_t status; /* Descriptor status */ 133 uint8_t errors; /* Descriptor Errors */ 134 uint16_t special; 135 }; 136 137 /* Transmit descriptor types */ 138 #define E1000_TXD_MASK (E1000_TXD_CMD_DEXT | 0x00F00000) 139 #define E1000_TXD_TYP_L (0) 140 #define E1000_TXD_TYP_C (E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_C) 141 #define E1000_TXD_TYP_D (E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D) 142 143 /* Legacy transmit descriptor */ 144 struct e1000_tx_desc { 145 uint64_t buffer_addr; /* Address of the descriptor's data buffer */ 146 union { 147 uint32_t data; 148 struct { 149 uint16_t length; /* Data buffer length */ 150 uint8_t cso; /* Checksum offset */ 151 uint8_t cmd; /* Descriptor control */ 152 } flags; 153 } lower; 154 union { 155 uint32_t data; 156 struct { 157 uint8_t status; /* Descriptor status */ 158 uint8_t css; /* Checksum start */ 159 uint16_t special; 160 } fields; 161 } upper; 162 }; 163 164 /* Context descriptor */ 165 struct e1000_context_desc { 166 union { 167 uint32_t ip_config; 168 struct { 169 uint8_t ipcss; /* IP checksum start */ 170 uint8_t ipcso; /* IP checksum offset */ 171 uint16_t ipcse; /* IP checksum end */ 172 } ip_fields; 173 } lower_setup; 174 union { 175 uint32_t tcp_config; 176 struct { 177 uint8_t tucss; /* TCP checksum start */ 178 uint8_t tucso; /* TCP checksum offset */ 179 uint16_t tucse; /* TCP checksum end */ 180 } tcp_fields; 181 } upper_setup; 182 uint32_t cmd_and_length; 183 union { 184 uint32_t data; 185 struct { 186 uint8_t status; /* Descriptor status */ 187 uint8_t hdr_len; /* Header length */ 188 uint16_t mss; /* Maximum segment size */ 189 } fields; 190 } tcp_seg_setup; 191 }; 192 193 /* Data descriptor */ 194 struct e1000_data_desc { 195 uint64_t buffer_addr; /* Address of the descriptor's buffer address */ 196 union { 197 uint32_t data; 198 struct { 199 uint16_t length; /* Data buffer length */ 200 uint8_t typ_len_ext; 201 uint8_t cmd; 202 } flags; 203 } lower; 204 union { 205 uint32_t data; 206 struct { 207 uint8_t status; /* Descriptor status */ 208 uint8_t popts; /* Packet Options */ 209 uint16_t special; 210 } fields; 211 } upper; 212 }; 213 214 union e1000_tx_udesc { 215 struct e1000_tx_desc td; 216 struct e1000_context_desc cd; 217 struct e1000_data_desc dd; 218 }; 219 220 /* Tx checksum info for a packet. */ 221 struct ck_info { 222 int ck_valid; /* ck_info is valid */ 223 uint8_t ck_start; /* start byte of cksum calcuation */ 224 uint8_t ck_off; /* offset of cksum insertion */ 225 uint16_t ck_len; /* length of cksum calc: 0 is to packet-end */ 226 }; 227 228 /* 229 * Debug printf 230 */ 231 static int e82545_debug = 0; 232 #define DPRINTF(msg,params...) if (e82545_debug) fprintf(stderr, "e82545: " msg, params) 233 #define WPRINTF(msg,params...) fprintf(stderr, "e82545: " msg, params) 234 235 #define MIN(a,b) (((a)<(b))?(a):(b)) 236 #define MAX(a,b) (((a)>(b))?(a):(b)) 237 238 /* s/w representation of the RAL/RAH regs */ 239 struct eth_uni { 240 int eu_valid; 241 int eu_addrsel; 242 struct ether_addr eu_eth; 243 }; 244 245 246 struct e82545_softc { 247 struct pci_devinst *esc_pi; 248 struct vmctx *esc_ctx; 249 struct mevent *esc_mevpitr; 250 pthread_mutex_t esc_mtx; 251 struct ether_addr esc_mac; 252 net_backend_t *esc_be; 253 254 /* General */ 255 uint32_t esc_CTRL; /* x0000 device ctl */ 256 uint32_t esc_FCAL; /* x0028 flow ctl addr lo */ 257 uint32_t esc_FCAH; /* x002C flow ctl addr hi */ 258 uint32_t esc_FCT; /* x0030 flow ctl type */ 259 uint32_t esc_VET; /* x0038 VLAN eth type */ 260 uint32_t esc_FCTTV; /* x0170 flow ctl tx timer */ 261 uint32_t esc_LEDCTL; /* x0E00 LED control */ 262 uint32_t esc_PBA; /* x1000 pkt buffer allocation */ 263 264 /* Interrupt control */ 265 int esc_irq_asserted; 266 uint32_t esc_ICR; /* x00C0 cause read/clear */ 267 uint32_t esc_ITR; /* x00C4 intr throttling */ 268 uint32_t esc_ICS; /* x00C8 cause set */ 269 uint32_t esc_IMS; /* x00D0 mask set/read */ 270 uint32_t esc_IMC; /* x00D8 mask clear */ 271 272 /* Transmit */ 273 union e1000_tx_udesc *esc_txdesc; 274 struct e1000_context_desc esc_txctx; 275 pthread_t esc_tx_tid; 276 pthread_cond_t esc_tx_cond; 277 int esc_tx_enabled; 278 int esc_tx_active; 279 uint32_t esc_TXCW; /* x0178 transmit config */ 280 uint32_t esc_TCTL; /* x0400 transmit ctl */ 281 uint32_t esc_TIPG; /* x0410 inter-packet gap */ 282 uint16_t esc_AIT; /* x0458 Adaptive Interframe Throttle */ 283 uint64_t esc_tdba; /* verified 64-bit desc table addr */ 284 uint32_t esc_TDBAL; /* x3800 desc table addr, low bits */ 285 uint32_t esc_TDBAH; /* x3804 desc table addr, hi 32-bits */ 286 uint32_t esc_TDLEN; /* x3808 # descriptors in bytes */ 287 uint16_t esc_TDH; /* x3810 desc table head idx */ 288 uint16_t esc_TDHr; /* internal read version of TDH */ 289 uint16_t esc_TDT; /* x3818 desc table tail idx */ 290 uint32_t esc_TIDV; /* x3820 intr delay */ 291 uint32_t esc_TXDCTL; /* x3828 desc control */ 292 uint32_t esc_TADV; /* x382C intr absolute delay */ 293 294 /* L2 frame acceptance */ 295 struct eth_uni esc_uni[16]; /* 16 x unicast MAC addresses */ 296 uint32_t esc_fmcast[128]; /* Multicast filter bit-match */ 297 uint32_t esc_fvlan[128]; /* VLAN 4096-bit filter */ 298 299 /* Receive */ 300 struct e1000_rx_desc *esc_rxdesc; 301 pthread_cond_t esc_rx_cond; 302 int esc_rx_enabled; 303 int esc_rx_active; 304 int esc_rx_loopback; 305 uint32_t esc_RCTL; /* x0100 receive ctl */ 306 uint32_t esc_FCRTL; /* x2160 flow cntl thresh, low */ 307 uint32_t esc_FCRTH; /* x2168 flow cntl thresh, hi */ 308 uint64_t esc_rdba; /* verified 64-bit desc table addr */ 309 uint32_t esc_RDBAL; /* x2800 desc table addr, low bits */ 310 uint32_t esc_RDBAH; /* x2804 desc table addr, hi 32-bits*/ 311 uint32_t esc_RDLEN; /* x2808 #descriptors */ 312 uint16_t esc_RDH; /* x2810 desc table head idx */ 313 uint16_t esc_RDT; /* x2818 desc table tail idx */ 314 uint32_t esc_RDTR; /* x2820 intr delay */ 315 uint32_t esc_RXDCTL; /* x2828 desc control */ 316 uint32_t esc_RADV; /* x282C intr absolute delay */ 317 uint32_t esc_RSRPD; /* x2C00 recv small packet detect */ 318 uint32_t esc_RXCSUM; /* x5000 receive cksum ctl */ 319 320 /* IO Port register access */ 321 uint32_t io_addr; 322 323 /* Shadow copy of MDIC */ 324 uint32_t mdi_control; 325 /* Shadow copy of EECD */ 326 uint32_t eeprom_control; 327 /* Latest NVM in/out */ 328 uint16_t nvm_data; 329 uint16_t nvm_opaddr; 330 /* stats */ 331 uint32_t missed_pkt_count; /* dropped for no room in rx queue */ 332 uint32_t pkt_rx_by_size[6]; 333 uint32_t pkt_tx_by_size[6]; 334 uint32_t good_pkt_rx_count; 335 uint32_t bcast_pkt_rx_count; 336 uint32_t mcast_pkt_rx_count; 337 uint32_t good_pkt_tx_count; 338 uint32_t bcast_pkt_tx_count; 339 uint32_t mcast_pkt_tx_count; 340 uint32_t oversize_rx_count; 341 uint32_t tso_tx_count; 342 uint64_t good_octets_rx; 343 uint64_t good_octets_tx; 344 uint64_t missed_octets; /* counts missed and oversized */ 345 346 uint8_t nvm_bits:6; /* number of bits remaining in/out */ 347 uint8_t nvm_mode:2; 348 #define E82545_NVM_MODE_OPADDR 0x0 349 #define E82545_NVM_MODE_DATAIN 0x1 350 #define E82545_NVM_MODE_DATAOUT 0x2 351 /* EEPROM data */ 352 uint16_t eeprom_data[E82545_NVM_EEPROM_SIZE]; 353 }; 354 355 static void e82545_reset(struct e82545_softc *sc, int dev); 356 static void e82545_rx_enable(struct e82545_softc *sc); 357 static void e82545_rx_disable(struct e82545_softc *sc); 358 static void e82545_rx_callback(int fd, enum ev_type type, void *param); 359 static void e82545_tx_start(struct e82545_softc *sc); 360 static void e82545_tx_enable(struct e82545_softc *sc); 361 static void e82545_tx_disable(struct e82545_softc *sc); 362 363 static inline int 364 e82545_size_stat_index(uint32_t size) 365 { 366 if (size <= 64) { 367 return 0; 368 } else if (size >= 1024) { 369 return 5; 370 } else { 371 /* should be 1-4 */ 372 return (ffs(size) - 6); 373 } 374 } 375 376 static void 377 e82545_init_eeprom(struct e82545_softc *sc) 378 { 379 uint16_t checksum, i; 380 381 /* mac addr */ 382 sc->eeprom_data[NVM_MAC_ADDR] = ((uint16_t)sc->esc_mac.octet[0]) | 383 (((uint16_t)sc->esc_mac.octet[1]) << 8); 384 sc->eeprom_data[NVM_MAC_ADDR+1] = ((uint16_t)sc->esc_mac.octet[2]) | 385 (((uint16_t)sc->esc_mac.octet[3]) << 8); 386 sc->eeprom_data[NVM_MAC_ADDR+2] = ((uint16_t)sc->esc_mac.octet[4]) | 387 (((uint16_t)sc->esc_mac.octet[5]) << 8); 388 389 /* pci ids */ 390 sc->eeprom_data[NVM_SUB_DEV_ID] = E82545_SUBDEV_ID; 391 sc->eeprom_data[NVM_SUB_VEN_ID] = E82545_VENDOR_ID_INTEL; 392 sc->eeprom_data[NVM_DEV_ID] = E82545_DEV_ID_82545EM_COPPER; 393 sc->eeprom_data[NVM_VEN_ID] = E82545_VENDOR_ID_INTEL; 394 395 /* fill in the checksum */ 396 checksum = 0; 397 for (i = 0; i < NVM_CHECKSUM_REG; i++) { 398 checksum += sc->eeprom_data[i]; 399 } 400 checksum = NVM_SUM - checksum; 401 sc->eeprom_data[NVM_CHECKSUM_REG] = checksum; 402 DPRINTF("eeprom checksum: 0x%x\r\n", checksum); 403 } 404 405 static void 406 e82545_write_mdi(struct e82545_softc *sc, uint8_t reg_addr, 407 uint8_t phy_addr, uint32_t data) 408 { 409 DPRINTF("Write mdi reg:0x%x phy:0x%x data: 0x%x\r\n", reg_addr, phy_addr, data); 410 } 411 412 static uint32_t 413 e82545_read_mdi(struct e82545_softc *sc, uint8_t reg_addr, 414 uint8_t phy_addr) 415 { 416 //DPRINTF("Read mdi reg:0x%x phy:0x%x\r\n", reg_addr, phy_addr); 417 switch (reg_addr) { 418 case PHY_STATUS: 419 return (MII_SR_LINK_STATUS | MII_SR_AUTONEG_CAPS | 420 MII_SR_AUTONEG_COMPLETE); 421 case PHY_AUTONEG_ADV: 422 return NWAY_AR_SELECTOR_FIELD; 423 case PHY_LP_ABILITY: 424 return 0; 425 case PHY_1000T_STATUS: 426 return (SR_1000T_LP_FD_CAPS | SR_1000T_REMOTE_RX_STATUS | 427 SR_1000T_LOCAL_RX_STATUS); 428 case PHY_ID1: 429 return (M88E1011_I_PHY_ID >> 16) & 0xFFFF; 430 case PHY_ID2: 431 return (M88E1011_I_PHY_ID | E82545_REVISION_4) & 0xFFFF; 432 default: 433 DPRINTF("Unknown mdi read reg:0x%x phy:0x%x\r\n", reg_addr, phy_addr); 434 return 0; 435 } 436 /* not reached */ 437 } 438 439 static void 440 e82545_eecd_strobe(struct e82545_softc *sc) 441 { 442 /* Microwire state machine */ 443 /* 444 DPRINTF("eeprom state machine srtobe " 445 "0x%x 0x%x 0x%x 0x%x\r\n", 446 sc->nvm_mode, sc->nvm_bits, 447 sc->nvm_opaddr, sc->nvm_data);*/ 448 449 if (sc->nvm_bits == 0) { 450 DPRINTF("eeprom state machine not expecting data! " 451 "0x%x 0x%x 0x%x 0x%x\r\n", 452 sc->nvm_mode, sc->nvm_bits, 453 sc->nvm_opaddr, sc->nvm_data); 454 return; 455 } 456 sc->nvm_bits--; 457 if (sc->nvm_mode == E82545_NVM_MODE_DATAOUT) { 458 /* shifting out */ 459 if (sc->nvm_data & 0x8000) { 460 sc->eeprom_control |= E1000_EECD_DO; 461 } else { 462 sc->eeprom_control &= ~E1000_EECD_DO; 463 } 464 sc->nvm_data <<= 1; 465 if (sc->nvm_bits == 0) { 466 /* read done, back to opcode mode. */ 467 sc->nvm_opaddr = 0; 468 sc->nvm_mode = E82545_NVM_MODE_OPADDR; 469 sc->nvm_bits = E82545_NVM_OPADDR_BITS; 470 } 471 } else if (sc->nvm_mode == E82545_NVM_MODE_DATAIN) { 472 /* shifting in */ 473 sc->nvm_data <<= 1; 474 if (sc->eeprom_control & E1000_EECD_DI) { 475 sc->nvm_data |= 1; 476 } 477 if (sc->nvm_bits == 0) { 478 /* eeprom write */ 479 uint16_t op = sc->nvm_opaddr & E82545_NVM_OPCODE_MASK; 480 uint16_t addr = sc->nvm_opaddr & E82545_NVM_ADDR_MASK; 481 if (op != E82545_NVM_OPCODE_WRITE) { 482 DPRINTF("Illegal eeprom write op 0x%x\r\n", 483 sc->nvm_opaddr); 484 } else if (addr >= E82545_NVM_EEPROM_SIZE) { 485 DPRINTF("Illegal eeprom write addr 0x%x\r\n", 486 sc->nvm_opaddr); 487 } else { 488 DPRINTF("eeprom write eeprom[0x%x] = 0x%x\r\n", 489 addr, sc->nvm_data); 490 sc->eeprom_data[addr] = sc->nvm_data; 491 } 492 /* back to opcode mode */ 493 sc->nvm_opaddr = 0; 494 sc->nvm_mode = E82545_NVM_MODE_OPADDR; 495 sc->nvm_bits = E82545_NVM_OPADDR_BITS; 496 } 497 } else if (sc->nvm_mode == E82545_NVM_MODE_OPADDR) { 498 sc->nvm_opaddr <<= 1; 499 if (sc->eeprom_control & E1000_EECD_DI) { 500 sc->nvm_opaddr |= 1; 501 } 502 if (sc->nvm_bits == 0) { 503 uint16_t op = sc->nvm_opaddr & E82545_NVM_OPCODE_MASK; 504 switch (op) { 505 case E82545_NVM_OPCODE_EWEN: 506 DPRINTF("eeprom write enable: 0x%x\r\n", 507 sc->nvm_opaddr); 508 /* back to opcode mode */ 509 sc->nvm_opaddr = 0; 510 sc->nvm_mode = E82545_NVM_MODE_OPADDR; 511 sc->nvm_bits = E82545_NVM_OPADDR_BITS; 512 break; 513 case E82545_NVM_OPCODE_READ: 514 { 515 uint16_t addr = sc->nvm_opaddr & 516 E82545_NVM_ADDR_MASK; 517 sc->nvm_mode = E82545_NVM_MODE_DATAOUT; 518 sc->nvm_bits = E82545_NVM_DATA_BITS; 519 if (addr < E82545_NVM_EEPROM_SIZE) { 520 sc->nvm_data = sc->eeprom_data[addr]; 521 DPRINTF("eeprom read: eeprom[0x%x] = 0x%x\r\n", 522 addr, sc->nvm_data); 523 } else { 524 DPRINTF("eeprom illegal read: 0x%x\r\n", 525 sc->nvm_opaddr); 526 sc->nvm_data = 0; 527 } 528 break; 529 } 530 case E82545_NVM_OPCODE_WRITE: 531 sc->nvm_mode = E82545_NVM_MODE_DATAIN; 532 sc->nvm_bits = E82545_NVM_DATA_BITS; 533 sc->nvm_data = 0; 534 break; 535 default: 536 DPRINTF("eeprom unknown op: 0x%x\r\r", 537 sc->nvm_opaddr); 538 /* back to opcode mode */ 539 sc->nvm_opaddr = 0; 540 sc->nvm_mode = E82545_NVM_MODE_OPADDR; 541 sc->nvm_bits = E82545_NVM_OPADDR_BITS; 542 } 543 } 544 } else { 545 DPRINTF("eeprom state machine wrong state! " 546 "0x%x 0x%x 0x%x 0x%x\r\n", 547 sc->nvm_mode, sc->nvm_bits, 548 sc->nvm_opaddr, sc->nvm_data); 549 } 550 } 551 552 static void 553 e82545_itr_callback(int fd, enum ev_type type, void *param) 554 { 555 uint32_t new; 556 struct e82545_softc *sc = param; 557 558 pthread_mutex_lock(&sc->esc_mtx); 559 new = sc->esc_ICR & sc->esc_IMS; 560 if (new && !sc->esc_irq_asserted) { 561 DPRINTF("itr callback: lintr assert %x\r\n", new); 562 sc->esc_irq_asserted = 1; 563 pci_lintr_assert(sc->esc_pi); 564 } else { 565 mevent_delete(sc->esc_mevpitr); 566 sc->esc_mevpitr = NULL; 567 } 568 pthread_mutex_unlock(&sc->esc_mtx); 569 } 570 571 static void 572 e82545_icr_assert(struct e82545_softc *sc, uint32_t bits) 573 { 574 uint32_t new; 575 576 DPRINTF("icr assert: 0x%x\r\n", bits); 577 578 /* 579 * An interrupt is only generated if bits are set that 580 * aren't already in the ICR, these bits are unmasked, 581 * and there isn't an interrupt already pending. 582 */ 583 new = bits & ~sc->esc_ICR & sc->esc_IMS; 584 sc->esc_ICR |= bits; 585 586 if (new == 0) { 587 DPRINTF("icr assert: masked %x, ims %x\r\n", new, sc->esc_IMS); 588 } else if (sc->esc_mevpitr != NULL) { 589 DPRINTF("icr assert: throttled %x, ims %x\r\n", new, sc->esc_IMS); 590 } else if (!sc->esc_irq_asserted) { 591 DPRINTF("icr assert: lintr assert %x\r\n", new); 592 sc->esc_irq_asserted = 1; 593 pci_lintr_assert(sc->esc_pi); 594 if (sc->esc_ITR != 0) { 595 sc->esc_mevpitr = mevent_add( 596 (sc->esc_ITR + 3905) / 3906, /* 256ns -> 1ms */ 597 EVF_TIMER, e82545_itr_callback, sc); 598 } 599 } 600 } 601 602 static void 603 e82545_ims_change(struct e82545_softc *sc, uint32_t bits) 604 { 605 uint32_t new; 606 607 /* 608 * Changing the mask may allow previously asserted 609 * but masked interrupt requests to generate an interrupt. 610 */ 611 new = bits & sc->esc_ICR & ~sc->esc_IMS; 612 sc->esc_IMS |= bits; 613 614 if (new == 0) { 615 DPRINTF("ims change: masked %x, ims %x\r\n", new, sc->esc_IMS); 616 } else if (sc->esc_mevpitr != NULL) { 617 DPRINTF("ims change: throttled %x, ims %x\r\n", new, sc->esc_IMS); 618 } else if (!sc->esc_irq_asserted) { 619 DPRINTF("ims change: lintr assert %x\n\r", new); 620 sc->esc_irq_asserted = 1; 621 pci_lintr_assert(sc->esc_pi); 622 if (sc->esc_ITR != 0) { 623 sc->esc_mevpitr = mevent_add( 624 (sc->esc_ITR + 3905) / 3906, /* 256ns -> 1ms */ 625 EVF_TIMER, e82545_itr_callback, sc); 626 } 627 } 628 } 629 630 static void 631 e82545_icr_deassert(struct e82545_softc *sc, uint32_t bits) 632 { 633 634 DPRINTF("icr deassert: 0x%x\r\n", bits); 635 sc->esc_ICR &= ~bits; 636 637 /* 638 * If there are no longer any interrupt sources and there 639 * was an asserted interrupt, clear it 640 */ 641 if (sc->esc_irq_asserted && !(sc->esc_ICR & sc->esc_IMS)) { 642 DPRINTF("icr deassert: lintr deassert %x\r\n", bits); 643 pci_lintr_deassert(sc->esc_pi); 644 sc->esc_irq_asserted = 0; 645 } 646 } 647 648 static void 649 e82545_intr_write(struct e82545_softc *sc, uint32_t offset, uint32_t value) 650 { 651 652 DPRINTF("intr_write: off %x, val %x\n\r", offset, value); 653 654 switch (offset) { 655 case E1000_ICR: 656 e82545_icr_deassert(sc, value); 657 break; 658 case E1000_ITR: 659 sc->esc_ITR = value; 660 break; 661 case E1000_ICS: 662 sc->esc_ICS = value; /* not used: store for debug */ 663 e82545_icr_assert(sc, value); 664 break; 665 case E1000_IMS: 666 e82545_ims_change(sc, value); 667 break; 668 case E1000_IMC: 669 sc->esc_IMC = value; /* for debug */ 670 sc->esc_IMS &= ~value; 671 // XXX clear interrupts if all ICR bits now masked 672 // and interrupt was pending ? 673 break; 674 default: 675 break; 676 } 677 } 678 679 static uint32_t 680 e82545_intr_read(struct e82545_softc *sc, uint32_t offset) 681 { 682 uint32_t retval; 683 684 retval = 0; 685 686 DPRINTF("intr_read: off %x\n\r", offset); 687 688 switch (offset) { 689 case E1000_ICR: 690 retval = sc->esc_ICR; 691 sc->esc_ICR = 0; 692 e82545_icr_deassert(sc, ~0); 693 break; 694 case E1000_ITR: 695 retval = sc->esc_ITR; 696 break; 697 case E1000_ICS: 698 /* write-only register */ 699 break; 700 case E1000_IMS: 701 retval = sc->esc_IMS; 702 break; 703 case E1000_IMC: 704 /* write-only register */ 705 break; 706 default: 707 break; 708 } 709 710 return (retval); 711 } 712 713 static void 714 e82545_devctl(struct e82545_softc *sc, uint32_t val) 715 { 716 717 sc->esc_CTRL = val & ~E1000_CTRL_RST; 718 719 if (val & E1000_CTRL_RST) { 720 DPRINTF("e1k: s/w reset, ctl %x\n", val); 721 e82545_reset(sc, 1); 722 } 723 /* XXX check for phy reset ? */ 724 } 725 726 static void 727 e82545_rx_update_rdba(struct e82545_softc *sc) 728 { 729 730 /* XXX verify desc base/len within phys mem range */ 731 sc->esc_rdba = (uint64_t)sc->esc_RDBAH << 32 | 732 sc->esc_RDBAL; 733 734 /* Cache host mapping of guest descriptor array */ 735 sc->esc_rxdesc = paddr_guest2host(sc->esc_ctx, 736 sc->esc_rdba, sc->esc_RDLEN); 737 } 738 739 static void 740 e82545_rx_ctl(struct e82545_softc *sc, uint32_t val) 741 { 742 int on; 743 744 on = ((val & E1000_RCTL_EN) == E1000_RCTL_EN); 745 746 /* Save RCTL after stripping reserved bits 31:27,24,21,14,11:10,0 */ 747 sc->esc_RCTL = val & ~0xF9204c01; 748 749 DPRINTF("rx_ctl - %s RCTL %x, val %x\n", 750 on ? "on" : "off", sc->esc_RCTL, val); 751 752 /* state change requested */ 753 if (on != sc->esc_rx_enabled) { 754 if (on) { 755 /* Catch disallowed/unimplemented settings */ 756 //assert(!(val & E1000_RCTL_LBM_TCVR)); 757 758 if (sc->esc_RCTL & E1000_RCTL_LBM_TCVR) { 759 sc->esc_rx_loopback = 1; 760 } else { 761 sc->esc_rx_loopback = 0; 762 } 763 764 e82545_rx_update_rdba(sc); 765 e82545_rx_enable(sc); 766 } else { 767 e82545_rx_disable(sc); 768 sc->esc_rx_loopback = 0; 769 sc->esc_rdba = 0; 770 sc->esc_rxdesc = NULL; 771 } 772 } 773 } 774 775 static void 776 e82545_tx_update_tdba(struct e82545_softc *sc) 777 { 778 779 /* XXX verify desc base/len within phys mem range */ 780 sc->esc_tdba = (uint64_t)sc->esc_TDBAH << 32 | sc->esc_TDBAL; 781 782 /* Cache host mapping of guest descriptor array */ 783 sc->esc_txdesc = paddr_guest2host(sc->esc_ctx, sc->esc_tdba, 784 sc->esc_TDLEN); 785 } 786 787 static void 788 e82545_tx_ctl(struct e82545_softc *sc, uint32_t val) 789 { 790 int on; 791 792 on = ((val & E1000_TCTL_EN) == E1000_TCTL_EN); 793 794 /* ignore TCTL_EN settings that don't change state */ 795 if (on == sc->esc_tx_enabled) 796 return; 797 798 if (on) { 799 e82545_tx_update_tdba(sc); 800 e82545_tx_enable(sc); 801 } else { 802 e82545_tx_disable(sc); 803 sc->esc_tdba = 0; 804 sc->esc_txdesc = NULL; 805 } 806 807 /* Save TCTL value after stripping reserved bits 31:25,23,2,0 */ 808 sc->esc_TCTL = val & ~0xFE800005; 809 } 810 811 int 812 e82545_bufsz(uint32_t rctl) 813 { 814 815 switch (rctl & (E1000_RCTL_BSEX | E1000_RCTL_SZ_256)) { 816 case (E1000_RCTL_SZ_2048): return (2048); 817 case (E1000_RCTL_SZ_1024): return (1024); 818 case (E1000_RCTL_SZ_512): return (512); 819 case (E1000_RCTL_SZ_256): return (256); 820 case (E1000_RCTL_BSEX|E1000_RCTL_SZ_16384): return (16384); 821 case (E1000_RCTL_BSEX|E1000_RCTL_SZ_8192): return (8192); 822 case (E1000_RCTL_BSEX|E1000_RCTL_SZ_4096): return (4096); 823 } 824 return (256); /* Forbidden value. */ 825 } 826 827 /* XXX one packet at a time until this is debugged */ 828 static void 829 e82545_rx_callback(int fd, enum ev_type type, void *param) 830 { 831 struct e82545_softc *sc = param; 832 struct e1000_rx_desc *rxd; 833 struct iovec vec[64]; 834 int left, len, lim, maxpktsz, maxpktdesc, bufsz, i, n, size; 835 uint32_t cause = 0; 836 uint16_t *tp, tag, head; 837 838 pthread_mutex_lock(&sc->esc_mtx); 839 DPRINTF("rx_run: head %x, tail %x\r\n", sc->esc_RDH, sc->esc_RDT); 840 841 if (!sc->esc_rx_enabled || sc->esc_rx_loopback) { 842 DPRINTF("rx disabled (!%d || %d) -- packet(s) dropped\r\n", 843 sc->esc_rx_enabled, sc->esc_rx_loopback); 844 while (netbe_rx_discard(sc->esc_be) > 0) { 845 } 846 goto done1; 847 } 848 bufsz = e82545_bufsz(sc->esc_RCTL); 849 maxpktsz = (sc->esc_RCTL & E1000_RCTL_LPE) ? 16384 : 1522; 850 maxpktdesc = (maxpktsz + bufsz - 1) / bufsz; 851 size = sc->esc_RDLEN / 16; 852 head = sc->esc_RDH; 853 left = (size + sc->esc_RDT - head) % size; 854 if (left < maxpktdesc) { 855 DPRINTF("rx overflow (%d < %d) -- packet(s) dropped\r\n", 856 left, maxpktdesc); 857 while (netbe_rx_discard(sc->esc_be) > 0) { 858 } 859 goto done1; 860 } 861 862 sc->esc_rx_active = 1; 863 pthread_mutex_unlock(&sc->esc_mtx); 864 865 for (lim = size / 4; lim > 0 && left >= maxpktdesc; lim -= n) { 866 867 /* Grab rx descriptor pointed to by the head pointer */ 868 for (i = 0; i < maxpktdesc; i++) { 869 rxd = &sc->esc_rxdesc[(head + i) % size]; 870 vec[i].iov_base = paddr_guest2host(sc->esc_ctx, 871 rxd->buffer_addr, bufsz); 872 vec[i].iov_len = bufsz; 873 } 874 len = netbe_recv(sc->esc_be, vec, maxpktdesc); 875 if (len <= 0) { 876 DPRINTF("netbe_recv() returned %d\n", len); 877 goto done; 878 } 879 880 /* 881 * Adjust the packet length based on whether the CRC needs 882 * to be stripped or if the packet is less than the minimum 883 * eth packet size. 884 */ 885 if (len < ETHER_MIN_LEN - ETHER_CRC_LEN) 886 len = ETHER_MIN_LEN - ETHER_CRC_LEN; 887 if (!(sc->esc_RCTL & E1000_RCTL_SECRC)) 888 len += ETHER_CRC_LEN; 889 n = (len + bufsz - 1) / bufsz; 890 891 DPRINTF("packet read %d bytes, %d segs, head %d\r\n", 892 len, n, head); 893 894 /* Apply VLAN filter. */ 895 tp = (uint16_t *)vec[0].iov_base + 6; 896 if ((sc->esc_RCTL & E1000_RCTL_VFE) && 897 (ntohs(tp[0]) == sc->esc_VET)) { 898 tag = ntohs(tp[1]) & 0x0fff; 899 if ((sc->esc_fvlan[tag >> 5] & 900 (1 << (tag & 0x1f))) != 0) { 901 DPRINTF("known VLAN %d\r\n", tag); 902 } else { 903 DPRINTF("unknown VLAN %d\r\n", tag); 904 n = 0; 905 continue; 906 } 907 } 908 909 /* Update all consumed descriptors. */ 910 for (i = 0; i < n - 1; i++) { 911 rxd = &sc->esc_rxdesc[(head + i) % size]; 912 rxd->length = bufsz; 913 rxd->csum = 0; 914 rxd->errors = 0; 915 rxd->special = 0; 916 rxd->status = E1000_RXD_STAT_DD; 917 } 918 rxd = &sc->esc_rxdesc[(head + i) % size]; 919 rxd->length = len % bufsz; 920 rxd->csum = 0; 921 rxd->errors = 0; 922 rxd->special = 0; 923 /* XXX signal no checksum for now */ 924 rxd->status = E1000_RXD_STAT_PIF | E1000_RXD_STAT_IXSM | 925 E1000_RXD_STAT_EOP | E1000_RXD_STAT_DD; 926 927 /* Schedule receive interrupts. */ 928 if (len <= sc->esc_RSRPD) { 929 cause |= E1000_ICR_SRPD | E1000_ICR_RXT0; 930 } else { 931 /* XXX: RDRT and RADV timers should be here. */ 932 cause |= E1000_ICR_RXT0; 933 } 934 935 head = (head + n) % size; 936 left -= n; 937 } 938 939 done: 940 pthread_mutex_lock(&sc->esc_mtx); 941 sc->esc_rx_active = 0; 942 if (sc->esc_rx_enabled == 0) 943 pthread_cond_signal(&sc->esc_rx_cond); 944 945 sc->esc_RDH = head; 946 /* Respect E1000_RCTL_RDMTS */ 947 left = (size + sc->esc_RDT - head) % size; 948 if (left < (size >> (((sc->esc_RCTL >> 8) & 3) + 1))) 949 cause |= E1000_ICR_RXDMT0; 950 /* Assert all accumulated interrupts. */ 951 if (cause != 0) 952 e82545_icr_assert(sc, cause); 953 done1: 954 DPRINTF("rx_run done: head %x, tail %x\r\n", sc->esc_RDH, sc->esc_RDT); 955 pthread_mutex_unlock(&sc->esc_mtx); 956 } 957 958 static uint16_t 959 e82545_carry(uint32_t sum) 960 { 961 962 sum = (sum & 0xFFFF) + (sum >> 16); 963 if (sum > 0xFFFF) 964 sum -= 0xFFFF; 965 return (sum); 966 } 967 968 static uint16_t 969 e82545_buf_checksum(uint8_t *buf, int len) 970 { 971 int i; 972 uint32_t sum = 0; 973 974 /* Checksum all the pairs of bytes first... */ 975 for (i = 0; i < (len & ~1U); i += 2) 976 sum += *((u_int16_t *)(buf + i)); 977 978 /* 979 * If there's a single byte left over, checksum it, too. 980 * Network byte order is big-endian, so the remaining byte is 981 * the high byte. 982 */ 983 if (i < len) 984 sum += htons(buf[i] << 8); 985 986 return (e82545_carry(sum)); 987 } 988 989 static uint16_t 990 e82545_iov_checksum(struct iovec *iov, int iovcnt, int off, int len) 991 { 992 int now, odd; 993 uint32_t sum = 0, s; 994 995 /* Skip completely unneeded vectors. */ 996 while (iovcnt > 0 && iov->iov_len <= off && off > 0) { 997 off -= iov->iov_len; 998 iov++; 999 iovcnt--; 1000 } 1001 1002 /* Calculate checksum of requested range. */ 1003 odd = 0; 1004 while (len > 0 && iovcnt > 0) { 1005 now = MIN(len, iov->iov_len - off); 1006 s = e82545_buf_checksum(iov->iov_base + off, now); 1007 sum += odd ? (s << 8) : s; 1008 odd ^= (now & 1); 1009 len -= now; 1010 off = 0; 1011 iov++; 1012 iovcnt--; 1013 } 1014 1015 return (e82545_carry(sum)); 1016 } 1017 1018 /* 1019 * Return the transmit descriptor type. 1020 */ 1021 int 1022 e82545_txdesc_type(uint32_t lower) 1023 { 1024 int type; 1025 1026 type = 0; 1027 1028 if (lower & E1000_TXD_CMD_DEXT) 1029 type = lower & E1000_TXD_MASK; 1030 1031 return (type); 1032 } 1033 1034 static void 1035 e82545_transmit_checksum(struct iovec *iov, int iovcnt, struct ck_info *ck) 1036 { 1037 uint16_t cksum; 1038 int cklen; 1039 1040 DPRINTF("tx cksum: iovcnt/s/off/len %d/%d/%d/%d\r\n", 1041 iovcnt, ck->ck_start, ck->ck_off, ck->ck_len); 1042 cklen = ck->ck_len ? ck->ck_len - ck->ck_start + 1 : INT_MAX; 1043 cksum = e82545_iov_checksum(iov, iovcnt, ck->ck_start, cklen); 1044 *(uint16_t *)((uint8_t *)iov[0].iov_base + ck->ck_off) = ~cksum; 1045 } 1046 1047 static void 1048 e82545_transmit_backend(struct e82545_softc *sc, struct iovec *iov, int iovcnt) 1049 { 1050 1051 if (sc->esc_be == NULL) 1052 return; 1053 1054 (void) netbe_send(sc->esc_be, iov, iovcnt); 1055 } 1056 1057 static void 1058 e82545_transmit_done(struct e82545_softc *sc, uint16_t head, uint16_t tail, 1059 uint16_t dsize, int *tdwb) 1060 { 1061 union e1000_tx_udesc *dsc; 1062 1063 for ( ; head != tail; head = (head + 1) % dsize) { 1064 dsc = &sc->esc_txdesc[head]; 1065 if (dsc->td.lower.data & E1000_TXD_CMD_RS) { 1066 dsc->td.upper.data |= E1000_TXD_STAT_DD; 1067 *tdwb = 1; 1068 } 1069 } 1070 } 1071 1072 static int 1073 e82545_transmit(struct e82545_softc *sc, uint16_t head, uint16_t tail, 1074 uint16_t dsize, uint16_t *rhead, int *tdwb) 1075 { 1076 uint8_t *hdr, *hdrp; 1077 struct iovec iovb[I82545_MAX_TXSEGS + 2]; 1078 struct iovec tiov[I82545_MAX_TXSEGS + 2]; 1079 struct e1000_context_desc *cd; 1080 struct ck_info ckinfo[2]; 1081 struct iovec *iov; 1082 union e1000_tx_udesc *dsc; 1083 int desc, dtype, len, ntype, iovcnt, tlen, tcp, tso; 1084 int mss, paylen, seg, tiovcnt, left, now, nleft, nnow, pv, pvoff; 1085 unsigned hdrlen, vlen; 1086 uint32_t tcpsum, tcpseq; 1087 uint16_t ipcs, tcpcs, ipid, ohead; 1088 1089 ckinfo[0].ck_valid = ckinfo[1].ck_valid = 0; 1090 iovcnt = 0; 1091 tlen = 0; 1092 ntype = 0; 1093 tso = 0; 1094 ohead = head; 1095 1096 /* iovb[0/1] may be used for writable copy of headers. */ 1097 iov = &iovb[2]; 1098 1099 for (desc = 0; ; desc++, head = (head + 1) % dsize) { 1100 if (head == tail) { 1101 *rhead = head; 1102 return (0); 1103 } 1104 dsc = &sc->esc_txdesc[head]; 1105 dtype = e82545_txdesc_type(dsc->td.lower.data); 1106 1107 if (desc == 0) { 1108 switch (dtype) { 1109 case E1000_TXD_TYP_C: 1110 DPRINTF("tx ctxt desc idx %d: %016jx " 1111 "%08x%08x\r\n", 1112 head, dsc->td.buffer_addr, 1113 dsc->td.upper.data, dsc->td.lower.data); 1114 /* Save context and return */ 1115 sc->esc_txctx = dsc->cd; 1116 goto done; 1117 case E1000_TXD_TYP_L: 1118 DPRINTF("tx legacy desc idx %d: %08x%08x\r\n", 1119 head, dsc->td.upper.data, dsc->td.lower.data); 1120 /* 1121 * legacy cksum start valid in first descriptor 1122 */ 1123 ntype = dtype; 1124 ckinfo[0].ck_start = dsc->td.upper.fields.css; 1125 break; 1126 case E1000_TXD_TYP_D: 1127 DPRINTF("tx data desc idx %d: %08x%08x\r\n", 1128 head, dsc->td.upper.data, dsc->td.lower.data); 1129 ntype = dtype; 1130 break; 1131 default: 1132 break; 1133 } 1134 } else { 1135 /* Descriptor type must be consistent */ 1136 assert(dtype == ntype); 1137 DPRINTF("tx next desc idx %d: %08x%08x\r\n", 1138 head, dsc->td.upper.data, dsc->td.lower.data); 1139 } 1140 1141 len = (dtype == E1000_TXD_TYP_L) ? dsc->td.lower.flags.length : 1142 dsc->dd.lower.data & 0xFFFFF; 1143 1144 if (len > 0) { 1145 /* Strip checksum supplied by guest. */ 1146 if ((dsc->td.lower.data & E1000_TXD_CMD_EOP) != 0 && 1147 (dsc->td.lower.data & E1000_TXD_CMD_IFCS) == 0) 1148 len -= 2; 1149 tlen += len; 1150 if (iovcnt < I82545_MAX_TXSEGS) { 1151 iov[iovcnt].iov_base = paddr_guest2host( 1152 sc->esc_ctx, dsc->td.buffer_addr, len); 1153 iov[iovcnt].iov_len = len; 1154 } 1155 iovcnt++; 1156 } 1157 1158 /* 1159 * Pull out info that is valid in the final descriptor 1160 * and exit descriptor loop. 1161 */ 1162 if (dsc->td.lower.data & E1000_TXD_CMD_EOP) { 1163 if (dtype == E1000_TXD_TYP_L) { 1164 if (dsc->td.lower.data & E1000_TXD_CMD_IC) { 1165 ckinfo[0].ck_valid = 1; 1166 ckinfo[0].ck_off = 1167 dsc->td.lower.flags.cso; 1168 ckinfo[0].ck_len = 0; 1169 } 1170 } else { 1171 cd = &sc->esc_txctx; 1172 if (dsc->dd.lower.data & E1000_TXD_CMD_TSE) 1173 tso = 1; 1174 if (dsc->dd.upper.fields.popts & 1175 E1000_TXD_POPTS_IXSM) 1176 ckinfo[0].ck_valid = 1; 1177 if (dsc->dd.upper.fields.popts & 1178 E1000_TXD_POPTS_IXSM || tso) { 1179 ckinfo[0].ck_start = 1180 cd->lower_setup.ip_fields.ipcss; 1181 ckinfo[0].ck_off = 1182 cd->lower_setup.ip_fields.ipcso; 1183 ckinfo[0].ck_len = 1184 cd->lower_setup.ip_fields.ipcse; 1185 } 1186 if (dsc->dd.upper.fields.popts & 1187 E1000_TXD_POPTS_TXSM) 1188 ckinfo[1].ck_valid = 1; 1189 if (dsc->dd.upper.fields.popts & 1190 E1000_TXD_POPTS_TXSM || tso) { 1191 ckinfo[1].ck_start = 1192 cd->upper_setup.tcp_fields.tucss; 1193 ckinfo[1].ck_off = 1194 cd->upper_setup.tcp_fields.tucso; 1195 ckinfo[1].ck_len = 1196 cd->upper_setup.tcp_fields.tucse; 1197 } 1198 } 1199 break; 1200 } 1201 } 1202 1203 if (iovcnt > I82545_MAX_TXSEGS) { 1204 WPRINTF("tx too many descriptors (%d > %d) -- dropped\r\n", 1205 iovcnt, I82545_MAX_TXSEGS); 1206 goto done; 1207 } 1208 1209 hdrlen = vlen = 0; 1210 /* Estimate writable space for VLAN header insertion. */ 1211 if ((sc->esc_CTRL & E1000_CTRL_VME) && 1212 (dsc->td.lower.data & E1000_TXD_CMD_VLE)) { 1213 hdrlen = ETHER_ADDR_LEN*2; 1214 vlen = ETHER_VLAN_ENCAP_LEN; 1215 } 1216 if (!tso) { 1217 /* Estimate required writable space for checksums. */ 1218 if (ckinfo[0].ck_valid) 1219 hdrlen = MAX(hdrlen, ckinfo[0].ck_off + 2); 1220 if (ckinfo[1].ck_valid) 1221 hdrlen = MAX(hdrlen, ckinfo[1].ck_off + 2); 1222 /* Round up writable space to the first vector. */ 1223 if (hdrlen != 0 && iov[0].iov_len > hdrlen && 1224 iov[0].iov_len < hdrlen + 100) 1225 hdrlen = iov[0].iov_len; 1226 } else { 1227 /* In case of TSO header length provided by software. */ 1228 hdrlen = sc->esc_txctx.tcp_seg_setup.fields.hdr_len; 1229 1230 /* 1231 * Cap the header length at 240 based on 7.2.4.5 of 1232 * the Intel 82576EB (Rev 2.63) datasheet. 1233 */ 1234 if (hdrlen > 240) { 1235 WPRINTF("TSO hdrlen too large: %d\r\n", hdrlen); 1236 goto done; 1237 } 1238 1239 /* 1240 * If VLAN insertion is requested, ensure the header 1241 * at least holds the amount of data copied during 1242 * VLAN insertion below. 1243 * 1244 * XXX: Realistic packets will include a full Ethernet 1245 * header before the IP header at ckinfo[0].ck_start, 1246 * but this check is sufficient to prevent 1247 * out-of-bounds access below. 1248 */ 1249 if (vlen != 0 && hdrlen < ETHER_ADDR_LEN*2) { 1250 WPRINTF("TSO hdrlen too small for vlan insertion " 1251 "(%d vs %d) -- dropped\r\n", hdrlen, 1252 ETHER_ADDR_LEN*2); 1253 goto done; 1254 } 1255 1256 /* 1257 * Ensure that the header length covers the used fields 1258 * in the IP and TCP headers as well as the IP and TCP 1259 * checksums. The following fields are accessed below: 1260 * 1261 * Header | Field | Offset | Length 1262 * -------+-------+--------+------- 1263 * IPv4 | len | 2 | 2 1264 * IPv4 | ID | 4 | 2 1265 * IPv6 | len | 4 | 2 1266 * TCP | seq # | 4 | 4 1267 * TCP | flags | 13 | 1 1268 * UDP | len | 4 | 4 1269 */ 1270 if (hdrlen < ckinfo[0].ck_start + 6 || 1271 hdrlen < ckinfo[0].ck_off + 2) { 1272 WPRINTF("TSO hdrlen too small for IP fields (%d) " 1273 "-- dropped\r\n", hdrlen); 1274 goto done; 1275 } 1276 if (sc->esc_txctx.cmd_and_length & E1000_TXD_CMD_TCP) { 1277 if (hdrlen < ckinfo[1].ck_start + 14 || 1278 (ckinfo[1].ck_valid && 1279 hdrlen < ckinfo[1].ck_off + 2)) { 1280 WPRINTF("TSO hdrlen too small for TCP fields " 1281 "(%d) -- dropped\r\n", hdrlen); 1282 goto done; 1283 } 1284 } else { 1285 if (hdrlen < ckinfo[1].ck_start + 8) { 1286 WPRINTF("TSO hdrlen too small for UDP fields " 1287 "(%d) -- dropped\r\n", hdrlen); 1288 goto done; 1289 } 1290 } 1291 } 1292 1293 /* Allocate, fill and prepend writable header vector. */ 1294 if (hdrlen != 0) { 1295 hdr = __builtin_alloca(hdrlen + vlen); 1296 hdr += vlen; 1297 for (left = hdrlen, hdrp = hdr; left > 0; 1298 left -= now, hdrp += now) { 1299 now = MIN(left, iov->iov_len); 1300 memcpy(hdrp, iov->iov_base, now); 1301 iov->iov_base += now; 1302 iov->iov_len -= now; 1303 if (iov->iov_len == 0) { 1304 iov++; 1305 iovcnt--; 1306 } 1307 } 1308 iov--; 1309 iovcnt++; 1310 iov->iov_base = hdr; 1311 iov->iov_len = hdrlen; 1312 } else 1313 hdr = NULL; 1314 1315 /* Insert VLAN tag. */ 1316 if (vlen != 0) { 1317 hdr -= ETHER_VLAN_ENCAP_LEN; 1318 memmove(hdr, hdr + ETHER_VLAN_ENCAP_LEN, ETHER_ADDR_LEN*2); 1319 hdrlen += ETHER_VLAN_ENCAP_LEN; 1320 hdr[ETHER_ADDR_LEN*2 + 0] = sc->esc_VET >> 8; 1321 hdr[ETHER_ADDR_LEN*2 + 1] = sc->esc_VET & 0xff; 1322 hdr[ETHER_ADDR_LEN*2 + 2] = dsc->td.upper.fields.special >> 8; 1323 hdr[ETHER_ADDR_LEN*2 + 3] = dsc->td.upper.fields.special & 0xff; 1324 iov->iov_base = hdr; 1325 iov->iov_len += ETHER_VLAN_ENCAP_LEN; 1326 /* Correct checksum offsets after VLAN tag insertion. */ 1327 ckinfo[0].ck_start += ETHER_VLAN_ENCAP_LEN; 1328 ckinfo[0].ck_off += ETHER_VLAN_ENCAP_LEN; 1329 if (ckinfo[0].ck_len != 0) 1330 ckinfo[0].ck_len += ETHER_VLAN_ENCAP_LEN; 1331 ckinfo[1].ck_start += ETHER_VLAN_ENCAP_LEN; 1332 ckinfo[1].ck_off += ETHER_VLAN_ENCAP_LEN; 1333 if (ckinfo[1].ck_len != 0) 1334 ckinfo[1].ck_len += ETHER_VLAN_ENCAP_LEN; 1335 } 1336 1337 /* Simple non-TSO case. */ 1338 if (!tso) { 1339 /* Calculate checksums and transmit. */ 1340 if (ckinfo[0].ck_valid) 1341 e82545_transmit_checksum(iov, iovcnt, &ckinfo[0]); 1342 if (ckinfo[1].ck_valid) 1343 e82545_transmit_checksum(iov, iovcnt, &ckinfo[1]); 1344 e82545_transmit_backend(sc, iov, iovcnt); 1345 goto done; 1346 } 1347 1348 /* Doing TSO. */ 1349 tcp = (sc->esc_txctx.cmd_and_length & E1000_TXD_CMD_TCP) != 0; 1350 mss = sc->esc_txctx.tcp_seg_setup.fields.mss; 1351 paylen = (sc->esc_txctx.cmd_and_length & 0x000fffff); 1352 DPRINTF("tx %s segmentation offload %d+%d/%d bytes %d iovs\r\n", 1353 tcp ? "TCP" : "UDP", hdrlen, paylen, mss, iovcnt); 1354 ipid = ntohs(*(uint16_t *)&hdr[ckinfo[0].ck_start + 4]); 1355 tcpseq = 0; 1356 if (tcp) 1357 tcpseq = ntohl(*(uint32_t *)&hdr[ckinfo[1].ck_start + 4]); 1358 ipcs = *(uint16_t *)&hdr[ckinfo[0].ck_off]; 1359 tcpcs = 0; 1360 if (ckinfo[1].ck_valid) /* Save partial pseudo-header checksum. */ 1361 tcpcs = *(uint16_t *)&hdr[ckinfo[1].ck_off]; 1362 pv = 1; 1363 pvoff = 0; 1364 for (seg = 0, left = paylen; left > 0; seg++, left -= now) { 1365 now = MIN(left, mss); 1366 1367 /* Construct IOVs for the segment. */ 1368 /* Include whole original header. */ 1369 tiov[0].iov_base = hdr; 1370 tiov[0].iov_len = hdrlen; 1371 tiovcnt = 1; 1372 /* Include respective part of payload IOV. */ 1373 for (nleft = now; pv < iovcnt && nleft > 0; nleft -= nnow) { 1374 nnow = MIN(nleft, iov[pv].iov_len - pvoff); 1375 tiov[tiovcnt].iov_base = iov[pv].iov_base + pvoff; 1376 tiov[tiovcnt++].iov_len = nnow; 1377 if (pvoff + nnow == iov[pv].iov_len) { 1378 pv++; 1379 pvoff = 0; 1380 } else 1381 pvoff += nnow; 1382 } 1383 DPRINTF("tx segment %d %d+%d bytes %d iovs\r\n", 1384 seg, hdrlen, now, tiovcnt); 1385 1386 /* Update IP header. */ 1387 if (sc->esc_txctx.cmd_and_length & E1000_TXD_CMD_IP) { 1388 /* IPv4 -- set length and ID */ 1389 *(uint16_t *)&hdr[ckinfo[0].ck_start + 2] = 1390 htons(hdrlen - ckinfo[0].ck_start + now); 1391 *(uint16_t *)&hdr[ckinfo[0].ck_start + 4] = 1392 htons(ipid + seg); 1393 } else { 1394 /* IPv6 -- set length */ 1395 *(uint16_t *)&hdr[ckinfo[0].ck_start + 4] = 1396 htons(hdrlen - ckinfo[0].ck_start - 40 + 1397 now); 1398 } 1399 1400 /* Update pseudo-header checksum. */ 1401 tcpsum = tcpcs; 1402 tcpsum += htons(hdrlen - ckinfo[1].ck_start + now); 1403 1404 /* Update TCP/UDP headers. */ 1405 if (tcp) { 1406 /* Update sequence number and FIN/PUSH flags. */ 1407 *(uint32_t *)&hdr[ckinfo[1].ck_start + 4] = 1408 htonl(tcpseq + paylen - left); 1409 if (now < left) { 1410 hdr[ckinfo[1].ck_start + 13] &= 1411 ~(TH_FIN | TH_PUSH); 1412 } 1413 } else { 1414 /* Update payload length. */ 1415 *(uint32_t *)&hdr[ckinfo[1].ck_start + 4] = 1416 hdrlen - ckinfo[1].ck_start + now; 1417 } 1418 1419 /* Calculate checksums and transmit. */ 1420 if (ckinfo[0].ck_valid) { 1421 *(uint16_t *)&hdr[ckinfo[0].ck_off] = ipcs; 1422 e82545_transmit_checksum(tiov, tiovcnt, &ckinfo[0]); 1423 } 1424 if (ckinfo[1].ck_valid) { 1425 *(uint16_t *)&hdr[ckinfo[1].ck_off] = 1426 e82545_carry(tcpsum); 1427 e82545_transmit_checksum(tiov, tiovcnt, &ckinfo[1]); 1428 } 1429 e82545_transmit_backend(sc, tiov, tiovcnt); 1430 } 1431 1432 done: 1433 head = (head + 1) % dsize; 1434 e82545_transmit_done(sc, ohead, head, dsize, tdwb); 1435 1436 *rhead = head; 1437 return (desc + 1); 1438 } 1439 1440 static void 1441 e82545_tx_run(struct e82545_softc *sc) 1442 { 1443 uint32_t cause; 1444 uint16_t head, rhead, tail, size; 1445 int lim, tdwb, sent; 1446 1447 head = sc->esc_TDH; 1448 tail = sc->esc_TDT; 1449 size = sc->esc_TDLEN / 16; 1450 DPRINTF("tx_run: head %x, rhead %x, tail %x\r\n", 1451 sc->esc_TDH, sc->esc_TDHr, sc->esc_TDT); 1452 1453 pthread_mutex_unlock(&sc->esc_mtx); 1454 rhead = head; 1455 tdwb = 0; 1456 for (lim = size / 4; sc->esc_tx_enabled && lim > 0; lim -= sent) { 1457 sent = e82545_transmit(sc, head, tail, size, &rhead, &tdwb); 1458 if (sent == 0) 1459 break; 1460 head = rhead; 1461 } 1462 pthread_mutex_lock(&sc->esc_mtx); 1463 1464 sc->esc_TDH = head; 1465 sc->esc_TDHr = rhead; 1466 cause = 0; 1467 if (tdwb) 1468 cause |= E1000_ICR_TXDW; 1469 if (lim != size / 4 && sc->esc_TDH == sc->esc_TDT) 1470 cause |= E1000_ICR_TXQE; 1471 if (cause) 1472 e82545_icr_assert(sc, cause); 1473 1474 DPRINTF("tx_run done: head %x, rhead %x, tail %x\r\n", 1475 sc->esc_TDH, sc->esc_TDHr, sc->esc_TDT); 1476 } 1477 1478 static _Noreturn void * 1479 e82545_tx_thread(void *param) 1480 { 1481 struct e82545_softc *sc = param; 1482 1483 pthread_mutex_lock(&sc->esc_mtx); 1484 for (;;) { 1485 while (!sc->esc_tx_enabled || sc->esc_TDHr == sc->esc_TDT) { 1486 if (sc->esc_tx_enabled && sc->esc_TDHr != sc->esc_TDT) 1487 break; 1488 sc->esc_tx_active = 0; 1489 if (sc->esc_tx_enabled == 0) 1490 pthread_cond_signal(&sc->esc_tx_cond); 1491 pthread_cond_wait(&sc->esc_tx_cond, &sc->esc_mtx); 1492 } 1493 sc->esc_tx_active = 1; 1494 1495 /* Process some tx descriptors. Lock dropped inside. */ 1496 e82545_tx_run(sc); 1497 } 1498 } 1499 1500 static void 1501 e82545_tx_start(struct e82545_softc *sc) 1502 { 1503 1504 if (sc->esc_tx_active == 0) 1505 pthread_cond_signal(&sc->esc_tx_cond); 1506 } 1507 1508 static void 1509 e82545_tx_enable(struct e82545_softc *sc) 1510 { 1511 1512 sc->esc_tx_enabled = 1; 1513 } 1514 1515 static void 1516 e82545_tx_disable(struct e82545_softc *sc) 1517 { 1518 1519 sc->esc_tx_enabled = 0; 1520 while (sc->esc_tx_active) 1521 pthread_cond_wait(&sc->esc_tx_cond, &sc->esc_mtx); 1522 } 1523 1524 static void 1525 e82545_rx_enable(struct e82545_softc *sc) 1526 { 1527 1528 sc->esc_rx_enabled = 1; 1529 } 1530 1531 static void 1532 e82545_rx_disable(struct e82545_softc *sc) 1533 { 1534 1535 sc->esc_rx_enabled = 0; 1536 while (sc->esc_rx_active) 1537 pthread_cond_wait(&sc->esc_rx_cond, &sc->esc_mtx); 1538 } 1539 1540 static void 1541 e82545_write_ra(struct e82545_softc *sc, int reg, uint32_t wval) 1542 { 1543 struct eth_uni *eu; 1544 int idx; 1545 1546 idx = reg >> 1; 1547 assert(idx < 15); 1548 1549 eu = &sc->esc_uni[idx]; 1550 1551 if (reg & 0x1) { 1552 /* RAH */ 1553 eu->eu_valid = ((wval & E1000_RAH_AV) == E1000_RAH_AV); 1554 eu->eu_addrsel = (wval >> 16) & 0x3; 1555 eu->eu_eth.octet[5] = wval >> 8; 1556 eu->eu_eth.octet[4] = wval; 1557 } else { 1558 /* RAL */ 1559 eu->eu_eth.octet[3] = wval >> 24; 1560 eu->eu_eth.octet[2] = wval >> 16; 1561 eu->eu_eth.octet[1] = wval >> 8; 1562 eu->eu_eth.octet[0] = wval; 1563 } 1564 } 1565 1566 static uint32_t 1567 e82545_read_ra(struct e82545_softc *sc, int reg) 1568 { 1569 struct eth_uni *eu; 1570 uint32_t retval; 1571 int idx; 1572 1573 idx = reg >> 1; 1574 assert(idx < 15); 1575 1576 eu = &sc->esc_uni[idx]; 1577 1578 if (reg & 0x1) { 1579 /* RAH */ 1580 retval = (eu->eu_valid << 31) | 1581 (eu->eu_addrsel << 16) | 1582 (eu->eu_eth.octet[5] << 8) | 1583 eu->eu_eth.octet[4]; 1584 } else { 1585 /* RAL */ 1586 retval = (eu->eu_eth.octet[3] << 24) | 1587 (eu->eu_eth.octet[2] << 16) | 1588 (eu->eu_eth.octet[1] << 8) | 1589 eu->eu_eth.octet[0]; 1590 } 1591 1592 return (retval); 1593 } 1594 1595 static void 1596 e82545_write_register(struct e82545_softc *sc, uint32_t offset, uint32_t value) 1597 { 1598 int ridx; 1599 1600 if (offset & 0x3) { 1601 DPRINTF("Unaligned register write offset:0x%x value:0x%x\r\n", offset, value); 1602 return; 1603 } 1604 DPRINTF("Register write: 0x%x value: 0x%x\r\n", offset, value); 1605 1606 switch (offset) { 1607 case E1000_CTRL: 1608 case E1000_CTRL_DUP: 1609 e82545_devctl(sc, value); 1610 break; 1611 case E1000_FCAL: 1612 sc->esc_FCAL = value; 1613 break; 1614 case E1000_FCAH: 1615 sc->esc_FCAH = value & ~0xFFFF0000; 1616 break; 1617 case E1000_FCT: 1618 sc->esc_FCT = value & ~0xFFFF0000; 1619 break; 1620 case E1000_VET: 1621 sc->esc_VET = value & ~0xFFFF0000; 1622 break; 1623 case E1000_FCTTV: 1624 sc->esc_FCTTV = value & ~0xFFFF0000; 1625 break; 1626 case E1000_LEDCTL: 1627 sc->esc_LEDCTL = value & ~0x30303000; 1628 break; 1629 case E1000_PBA: 1630 sc->esc_PBA = value & 0x0000FF80; 1631 break; 1632 case E1000_ICR: 1633 case E1000_ITR: 1634 case E1000_ICS: 1635 case E1000_IMS: 1636 case E1000_IMC: 1637 e82545_intr_write(sc, offset, value); 1638 break; 1639 case E1000_RCTL: 1640 e82545_rx_ctl(sc, value); 1641 break; 1642 case E1000_FCRTL: 1643 sc->esc_FCRTL = value & ~0xFFFF0007; 1644 break; 1645 case E1000_FCRTH: 1646 sc->esc_FCRTH = value & ~0xFFFF0007; 1647 break; 1648 case E1000_RDBAL(0): 1649 sc->esc_RDBAL = value & ~0xF; 1650 if (sc->esc_rx_enabled) { 1651 /* Apparently legal: update cached address */ 1652 e82545_rx_update_rdba(sc); 1653 } 1654 break; 1655 case E1000_RDBAH(0): 1656 assert(!sc->esc_rx_enabled); 1657 sc->esc_RDBAH = value; 1658 break; 1659 case E1000_RDLEN(0): 1660 assert(!sc->esc_rx_enabled); 1661 sc->esc_RDLEN = value & ~0xFFF0007F; 1662 break; 1663 case E1000_RDH(0): 1664 /* XXX should only ever be zero ? Range check ? */ 1665 sc->esc_RDH = value; 1666 break; 1667 case E1000_RDT(0): 1668 /* XXX if this opens up the rx ring, do something ? */ 1669 sc->esc_RDT = value; 1670 break; 1671 case E1000_RDTR: 1672 /* ignore FPD bit 31 */ 1673 sc->esc_RDTR = value & ~0xFFFF0000; 1674 break; 1675 case E1000_RXDCTL(0): 1676 sc->esc_RXDCTL = value & ~0xFEC0C0C0; 1677 break; 1678 case E1000_RADV: 1679 sc->esc_RADV = value & ~0xFFFF0000; 1680 break; 1681 case E1000_RSRPD: 1682 sc->esc_RSRPD = value & ~0xFFFFF000; 1683 break; 1684 case E1000_RXCSUM: 1685 sc->esc_RXCSUM = value & ~0xFFFFF800; 1686 break; 1687 case E1000_TXCW: 1688 sc->esc_TXCW = value & ~0x3FFF0000; 1689 break; 1690 case E1000_TCTL: 1691 e82545_tx_ctl(sc, value); 1692 break; 1693 case E1000_TIPG: 1694 sc->esc_TIPG = value; 1695 break; 1696 case E1000_AIT: 1697 sc->esc_AIT = value; 1698 break; 1699 case E1000_TDBAL(0): 1700 sc->esc_TDBAL = value & ~0xF; 1701 if (sc->esc_tx_enabled) { 1702 /* Apparently legal */ 1703 e82545_tx_update_tdba(sc); 1704 } 1705 break; 1706 case E1000_TDBAH(0): 1707 //assert(!sc->esc_tx_enabled); 1708 sc->esc_TDBAH = value; 1709 break; 1710 case E1000_TDLEN(0): 1711 //assert(!sc->esc_tx_enabled); 1712 sc->esc_TDLEN = value & ~0xFFF0007F; 1713 break; 1714 case E1000_TDH(0): 1715 //assert(!sc->esc_tx_enabled); 1716 /* XXX should only ever be zero ? Range check ? */ 1717 sc->esc_TDHr = sc->esc_TDH = value; 1718 break; 1719 case E1000_TDT(0): 1720 /* XXX range check ? */ 1721 sc->esc_TDT = value; 1722 if (sc->esc_tx_enabled) 1723 e82545_tx_start(sc); 1724 break; 1725 case E1000_TIDV: 1726 sc->esc_TIDV = value & ~0xFFFF0000; 1727 break; 1728 case E1000_TXDCTL(0): 1729 //assert(!sc->esc_tx_enabled); 1730 sc->esc_TXDCTL = value & ~0xC0C0C0; 1731 break; 1732 case E1000_TADV: 1733 sc->esc_TADV = value & ~0xFFFF0000; 1734 break; 1735 case E1000_RAL(0) ... E1000_RAH(15): 1736 /* convert to u32 offset */ 1737 ridx = (offset - E1000_RAL(0)) >> 2; 1738 e82545_write_ra(sc, ridx, value); 1739 break; 1740 case E1000_MTA ... (E1000_MTA + (127*4)): 1741 sc->esc_fmcast[(offset - E1000_MTA) >> 2] = value; 1742 break; 1743 case E1000_VFTA ... (E1000_VFTA + (127*4)): 1744 sc->esc_fvlan[(offset - E1000_VFTA) >> 2] = value; 1745 break; 1746 case E1000_EECD: 1747 { 1748 //DPRINTF("EECD write 0x%x -> 0x%x\r\n", sc->eeprom_control, value); 1749 /* edge triggered low->high */ 1750 uint32_t eecd_strobe = ((sc->eeprom_control & E1000_EECD_SK) ? 1751 0 : (value & E1000_EECD_SK)); 1752 uint32_t eecd_mask = (E1000_EECD_SK|E1000_EECD_CS| 1753 E1000_EECD_DI|E1000_EECD_REQ); 1754 sc->eeprom_control &= ~eecd_mask; 1755 sc->eeprom_control |= (value & eecd_mask); 1756 /* grant/revoke immediately */ 1757 if (value & E1000_EECD_REQ) { 1758 sc->eeprom_control |= E1000_EECD_GNT; 1759 } else { 1760 sc->eeprom_control &= ~E1000_EECD_GNT; 1761 } 1762 if (eecd_strobe && (sc->eeprom_control & E1000_EECD_CS)) { 1763 e82545_eecd_strobe(sc); 1764 } 1765 return; 1766 } 1767 case E1000_MDIC: 1768 { 1769 uint8_t reg_addr = (uint8_t)((value & E1000_MDIC_REG_MASK) >> 1770 E1000_MDIC_REG_SHIFT); 1771 uint8_t phy_addr = (uint8_t)((value & E1000_MDIC_PHY_MASK) >> 1772 E1000_MDIC_PHY_SHIFT); 1773 sc->mdi_control = 1774 (value & ~(E1000_MDIC_ERROR|E1000_MDIC_DEST)); 1775 if ((value & E1000_MDIC_READY) != 0) { 1776 DPRINTF("Incorrect MDIC ready bit: 0x%x\r\n", value); 1777 return; 1778 } 1779 switch (value & E82545_MDIC_OP_MASK) { 1780 case E1000_MDIC_OP_READ: 1781 sc->mdi_control &= ~E82545_MDIC_DATA_MASK; 1782 sc->mdi_control |= e82545_read_mdi(sc, reg_addr, phy_addr); 1783 break; 1784 case E1000_MDIC_OP_WRITE: 1785 e82545_write_mdi(sc, reg_addr, phy_addr, 1786 value & E82545_MDIC_DATA_MASK); 1787 break; 1788 default: 1789 DPRINTF("Unknown MDIC op: 0x%x\r\n", value); 1790 return; 1791 } 1792 /* TODO: barrier? */ 1793 sc->mdi_control |= E1000_MDIC_READY; 1794 if (value & E82545_MDIC_IE) { 1795 // TODO: generate interrupt 1796 } 1797 return; 1798 } 1799 case E1000_MANC: 1800 case E1000_STATUS: 1801 return; 1802 default: 1803 DPRINTF("Unknown write register: 0x%x value:%x\r\n", offset, value); 1804 return; 1805 } 1806 } 1807 1808 static uint32_t 1809 e82545_read_register(struct e82545_softc *sc, uint32_t offset) 1810 { 1811 uint32_t retval; 1812 int ridx; 1813 1814 if (offset & 0x3) { 1815 DPRINTF("Unaligned register read offset:0x%x\r\n", offset); 1816 return 0; 1817 } 1818 1819 DPRINTF("Register read: 0x%x\r\n", offset); 1820 1821 switch (offset) { 1822 case E1000_CTRL: 1823 retval = sc->esc_CTRL; 1824 break; 1825 case E1000_STATUS: 1826 retval = E1000_STATUS_FD | E1000_STATUS_LU | 1827 E1000_STATUS_SPEED_1000; 1828 break; 1829 case E1000_FCAL: 1830 retval = sc->esc_FCAL; 1831 break; 1832 case E1000_FCAH: 1833 retval = sc->esc_FCAH; 1834 break; 1835 case E1000_FCT: 1836 retval = sc->esc_FCT; 1837 break; 1838 case E1000_VET: 1839 retval = sc->esc_VET; 1840 break; 1841 case E1000_FCTTV: 1842 retval = sc->esc_FCTTV; 1843 break; 1844 case E1000_LEDCTL: 1845 retval = sc->esc_LEDCTL; 1846 break; 1847 case E1000_PBA: 1848 retval = sc->esc_PBA; 1849 break; 1850 case E1000_ICR: 1851 case E1000_ITR: 1852 case E1000_ICS: 1853 case E1000_IMS: 1854 case E1000_IMC: 1855 retval = e82545_intr_read(sc, offset); 1856 break; 1857 case E1000_RCTL: 1858 retval = sc->esc_RCTL; 1859 break; 1860 case E1000_FCRTL: 1861 retval = sc->esc_FCRTL; 1862 break; 1863 case E1000_FCRTH: 1864 retval = sc->esc_FCRTH; 1865 break; 1866 case E1000_RDBAL(0): 1867 retval = sc->esc_RDBAL; 1868 break; 1869 case E1000_RDBAH(0): 1870 retval = sc->esc_RDBAH; 1871 break; 1872 case E1000_RDLEN(0): 1873 retval = sc->esc_RDLEN; 1874 break; 1875 case E1000_RDH(0): 1876 retval = sc->esc_RDH; 1877 break; 1878 case E1000_RDT(0): 1879 retval = sc->esc_RDT; 1880 break; 1881 case E1000_RDTR: 1882 retval = sc->esc_RDTR; 1883 break; 1884 case E1000_RXDCTL(0): 1885 retval = sc->esc_RXDCTL; 1886 break; 1887 case E1000_RADV: 1888 retval = sc->esc_RADV; 1889 break; 1890 case E1000_RSRPD: 1891 retval = sc->esc_RSRPD; 1892 break; 1893 case E1000_RXCSUM: 1894 retval = sc->esc_RXCSUM; 1895 break; 1896 case E1000_TXCW: 1897 retval = sc->esc_TXCW; 1898 break; 1899 case E1000_TCTL: 1900 retval = sc->esc_TCTL; 1901 break; 1902 case E1000_TIPG: 1903 retval = sc->esc_TIPG; 1904 break; 1905 case E1000_AIT: 1906 retval = sc->esc_AIT; 1907 break; 1908 case E1000_TDBAL(0): 1909 retval = sc->esc_TDBAL; 1910 break; 1911 case E1000_TDBAH(0): 1912 retval = sc->esc_TDBAH; 1913 break; 1914 case E1000_TDLEN(0): 1915 retval = sc->esc_TDLEN; 1916 break; 1917 case E1000_TDH(0): 1918 retval = sc->esc_TDH; 1919 break; 1920 case E1000_TDT(0): 1921 retval = sc->esc_TDT; 1922 break; 1923 case E1000_TIDV: 1924 retval = sc->esc_TIDV; 1925 break; 1926 case E1000_TXDCTL(0): 1927 retval = sc->esc_TXDCTL; 1928 break; 1929 case E1000_TADV: 1930 retval = sc->esc_TADV; 1931 break; 1932 case E1000_RAL(0) ... E1000_RAH(15): 1933 /* convert to u32 offset */ 1934 ridx = (offset - E1000_RAL(0)) >> 2; 1935 retval = e82545_read_ra(sc, ridx); 1936 break; 1937 case E1000_MTA ... (E1000_MTA + (127*4)): 1938 retval = sc->esc_fmcast[(offset - E1000_MTA) >> 2]; 1939 break; 1940 case E1000_VFTA ... (E1000_VFTA + (127*4)): 1941 retval = sc->esc_fvlan[(offset - E1000_VFTA) >> 2]; 1942 break; 1943 case E1000_EECD: 1944 //DPRINTF("EECD read %x\r\n", sc->eeprom_control); 1945 retval = sc->eeprom_control; 1946 break; 1947 case E1000_MDIC: 1948 retval = sc->mdi_control; 1949 break; 1950 case E1000_MANC: 1951 retval = 0; 1952 break; 1953 /* stats that we emulate. */ 1954 case E1000_MPC: 1955 retval = sc->missed_pkt_count; 1956 break; 1957 case E1000_PRC64: 1958 retval = sc->pkt_rx_by_size[0]; 1959 break; 1960 case E1000_PRC127: 1961 retval = sc->pkt_rx_by_size[1]; 1962 break; 1963 case E1000_PRC255: 1964 retval = sc->pkt_rx_by_size[2]; 1965 break; 1966 case E1000_PRC511: 1967 retval = sc->pkt_rx_by_size[3]; 1968 break; 1969 case E1000_PRC1023: 1970 retval = sc->pkt_rx_by_size[4]; 1971 break; 1972 case E1000_PRC1522: 1973 retval = sc->pkt_rx_by_size[5]; 1974 break; 1975 case E1000_GPRC: 1976 retval = sc->good_pkt_rx_count; 1977 break; 1978 case E1000_BPRC: 1979 retval = sc->bcast_pkt_rx_count; 1980 break; 1981 case E1000_MPRC: 1982 retval = sc->mcast_pkt_rx_count; 1983 break; 1984 case E1000_GPTC: 1985 case E1000_TPT: 1986 retval = sc->good_pkt_tx_count; 1987 break; 1988 case E1000_GORCL: 1989 retval = (uint32_t)sc->good_octets_rx; 1990 break; 1991 case E1000_GORCH: 1992 retval = (uint32_t)(sc->good_octets_rx >> 32); 1993 break; 1994 case E1000_TOTL: 1995 case E1000_GOTCL: 1996 retval = (uint32_t)sc->good_octets_tx; 1997 break; 1998 case E1000_TOTH: 1999 case E1000_GOTCH: 2000 retval = (uint32_t)(sc->good_octets_tx >> 32); 2001 break; 2002 case E1000_ROC: 2003 retval = sc->oversize_rx_count; 2004 break; 2005 case E1000_TORL: 2006 retval = (uint32_t)(sc->good_octets_rx + sc->missed_octets); 2007 break; 2008 case E1000_TORH: 2009 retval = (uint32_t)((sc->good_octets_rx + 2010 sc->missed_octets) >> 32); 2011 break; 2012 case E1000_TPR: 2013 retval = sc->good_pkt_rx_count + sc->missed_pkt_count + 2014 sc->oversize_rx_count; 2015 break; 2016 case E1000_PTC64: 2017 retval = sc->pkt_tx_by_size[0]; 2018 break; 2019 case E1000_PTC127: 2020 retval = sc->pkt_tx_by_size[1]; 2021 break; 2022 case E1000_PTC255: 2023 retval = sc->pkt_tx_by_size[2]; 2024 break; 2025 case E1000_PTC511: 2026 retval = sc->pkt_tx_by_size[3]; 2027 break; 2028 case E1000_PTC1023: 2029 retval = sc->pkt_tx_by_size[4]; 2030 break; 2031 case E1000_PTC1522: 2032 retval = sc->pkt_tx_by_size[5]; 2033 break; 2034 case E1000_MPTC: 2035 retval = sc->mcast_pkt_tx_count; 2036 break; 2037 case E1000_BPTC: 2038 retval = sc->bcast_pkt_tx_count; 2039 break; 2040 case E1000_TSCTC: 2041 retval = sc->tso_tx_count; 2042 break; 2043 /* stats that are always 0. */ 2044 case E1000_CRCERRS: 2045 case E1000_ALGNERRC: 2046 case E1000_SYMERRS: 2047 case E1000_RXERRC: 2048 case E1000_SCC: 2049 case E1000_ECOL: 2050 case E1000_MCC: 2051 case E1000_LATECOL: 2052 case E1000_COLC: 2053 case E1000_DC: 2054 case E1000_TNCRS: 2055 case E1000_SEC: 2056 case E1000_CEXTERR: 2057 case E1000_RLEC: 2058 case E1000_XONRXC: 2059 case E1000_XONTXC: 2060 case E1000_XOFFRXC: 2061 case E1000_XOFFTXC: 2062 case E1000_FCRUC: 2063 case E1000_RNBC: 2064 case E1000_RUC: 2065 case E1000_RFC: 2066 case E1000_RJC: 2067 case E1000_MGTPRC: 2068 case E1000_MGTPDC: 2069 case E1000_MGTPTC: 2070 case E1000_TSCTFC: 2071 retval = 0; 2072 break; 2073 default: 2074 DPRINTF("Unknown read register: 0x%x\r\n", offset); 2075 retval = 0; 2076 break; 2077 } 2078 2079 return (retval); 2080 } 2081 2082 static void 2083 e82545_write(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, int baridx, 2084 uint64_t offset, int size, uint64_t value) 2085 { 2086 struct e82545_softc *sc; 2087 2088 //DPRINTF("Write bar:%d offset:0x%lx value:0x%lx size:%d\r\n", baridx, offset, value, size); 2089 2090 sc = pi->pi_arg; 2091 2092 pthread_mutex_lock(&sc->esc_mtx); 2093 2094 switch (baridx) { 2095 case E82545_BAR_IO: 2096 switch (offset) { 2097 case E82545_IOADDR: 2098 if (size != 4) { 2099 DPRINTF("Wrong io addr write sz:%d value:0x%lx\r\n", size, value); 2100 } else 2101 sc->io_addr = (uint32_t)value; 2102 break; 2103 case E82545_IODATA: 2104 if (size != 4) { 2105 DPRINTF("Wrong io data write size:%d value:0x%lx\r\n", size, value); 2106 } else if (sc->io_addr > E82545_IO_REGISTER_MAX) { 2107 DPRINTF("Non-register io write addr:0x%x value:0x%lx\r\n", sc->io_addr, value); 2108 } else 2109 e82545_write_register(sc, sc->io_addr, 2110 (uint32_t)value); 2111 break; 2112 default: 2113 DPRINTF("Unknown io bar write offset:0x%lx value:0x%lx size:%d\r\n", offset, value, size); 2114 break; 2115 } 2116 break; 2117 case E82545_BAR_REGISTER: 2118 if (size != 4) { 2119 DPRINTF("Wrong register write size:%d offset:0x%lx value:0x%lx\r\n", size, offset, value); 2120 } else 2121 e82545_write_register(sc, (uint32_t)offset, 2122 (uint32_t)value); 2123 break; 2124 default: 2125 DPRINTF("Unknown write bar:%d off:0x%lx val:0x%lx size:%d\r\n", 2126 baridx, offset, value, size); 2127 } 2128 2129 pthread_mutex_unlock(&sc->esc_mtx); 2130 } 2131 2132 static uint64_t 2133 e82545_read(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, int baridx, 2134 uint64_t offset, int size) 2135 { 2136 struct e82545_softc *sc; 2137 uint64_t retval; 2138 2139 //DPRINTF("Read bar:%d offset:0x%lx size:%d\r\n", baridx, offset, size); 2140 sc = pi->pi_arg; 2141 retval = 0; 2142 2143 pthread_mutex_lock(&sc->esc_mtx); 2144 2145 switch (baridx) { 2146 case E82545_BAR_IO: 2147 switch (offset) { 2148 case E82545_IOADDR: 2149 if (size != 4) { 2150 DPRINTF("Wrong io addr read sz:%d\r\n", size); 2151 } else 2152 retval = sc->io_addr; 2153 break; 2154 case E82545_IODATA: 2155 if (size != 4) { 2156 DPRINTF("Wrong io data read sz:%d\r\n", size); 2157 } 2158 if (sc->io_addr > E82545_IO_REGISTER_MAX) { 2159 DPRINTF("Non-register io read addr:0x%x\r\n", 2160 sc->io_addr); 2161 } else 2162 retval = e82545_read_register(sc, sc->io_addr); 2163 break; 2164 default: 2165 DPRINTF("Unknown io bar read offset:0x%lx size:%d\r\n", 2166 offset, size); 2167 break; 2168 } 2169 break; 2170 case E82545_BAR_REGISTER: 2171 if (size != 4) { 2172 DPRINTF("Wrong register read size:%d offset:0x%lx\r\n", 2173 size, offset); 2174 } else 2175 retval = e82545_read_register(sc, (uint32_t)offset); 2176 break; 2177 default: 2178 DPRINTF("Unknown read bar:%d offset:0x%lx size:%d\r\n", 2179 baridx, offset, size); 2180 break; 2181 } 2182 2183 pthread_mutex_unlock(&sc->esc_mtx); 2184 2185 return (retval); 2186 } 2187 2188 static void 2189 e82545_reset(struct e82545_softc *sc, int drvr) 2190 { 2191 int i; 2192 2193 e82545_rx_disable(sc); 2194 e82545_tx_disable(sc); 2195 2196 /* clear outstanding interrupts */ 2197 if (sc->esc_irq_asserted) 2198 pci_lintr_deassert(sc->esc_pi); 2199 2200 /* misc */ 2201 if (!drvr) { 2202 sc->esc_FCAL = 0; 2203 sc->esc_FCAH = 0; 2204 sc->esc_FCT = 0; 2205 sc->esc_VET = 0; 2206 sc->esc_FCTTV = 0; 2207 } 2208 sc->esc_LEDCTL = 0x07061302; 2209 sc->esc_PBA = 0x00100030; 2210 2211 /* start nvm in opcode mode. */ 2212 sc->nvm_opaddr = 0; 2213 sc->nvm_mode = E82545_NVM_MODE_OPADDR; 2214 sc->nvm_bits = E82545_NVM_OPADDR_BITS; 2215 sc->eeprom_control = E1000_EECD_PRES | E82545_EECD_FWE_EN; 2216 e82545_init_eeprom(sc); 2217 2218 /* interrupt */ 2219 sc->esc_ICR = 0; 2220 sc->esc_ITR = 250; 2221 sc->esc_ICS = 0; 2222 sc->esc_IMS = 0; 2223 sc->esc_IMC = 0; 2224 2225 /* L2 filters */ 2226 if (!drvr) { 2227 memset(sc->esc_fvlan, 0, sizeof(sc->esc_fvlan)); 2228 memset(sc->esc_fmcast, 0, sizeof(sc->esc_fmcast)); 2229 memset(sc->esc_uni, 0, sizeof(sc->esc_uni)); 2230 2231 /* XXX not necessary on 82545 ?? */ 2232 sc->esc_uni[0].eu_valid = 1; 2233 memcpy(sc->esc_uni[0].eu_eth.octet, sc->esc_mac.octet, 2234 ETHER_ADDR_LEN); 2235 } else { 2236 /* Clear RAH valid bits */ 2237 for (i = 0; i < 16; i++) 2238 sc->esc_uni[i].eu_valid = 0; 2239 } 2240 2241 /* receive */ 2242 if (!drvr) { 2243 sc->esc_RDBAL = 0; 2244 sc->esc_RDBAH = 0; 2245 } 2246 sc->esc_RCTL = 0; 2247 sc->esc_FCRTL = 0; 2248 sc->esc_FCRTH = 0; 2249 sc->esc_RDLEN = 0; 2250 sc->esc_RDH = 0; 2251 sc->esc_RDT = 0; 2252 sc->esc_RDTR = 0; 2253 sc->esc_RXDCTL = (1 << 24) | (1 << 16); /* default GRAN/WTHRESH */ 2254 sc->esc_RADV = 0; 2255 sc->esc_RXCSUM = 0; 2256 2257 /* transmit */ 2258 if (!drvr) { 2259 sc->esc_TDBAL = 0; 2260 sc->esc_TDBAH = 0; 2261 sc->esc_TIPG = 0; 2262 sc->esc_AIT = 0; 2263 sc->esc_TIDV = 0; 2264 sc->esc_TADV = 0; 2265 } 2266 sc->esc_tdba = 0; 2267 sc->esc_txdesc = NULL; 2268 sc->esc_TXCW = 0; 2269 sc->esc_TCTL = 0; 2270 sc->esc_TDLEN = 0; 2271 sc->esc_TDT = 0; 2272 sc->esc_TDHr = sc->esc_TDH = 0; 2273 sc->esc_TXDCTL = 0; 2274 } 2275 2276 static int 2277 e82545_init(struct vmctx *ctx, struct pci_devinst *pi, char *opts) 2278 { 2279 char nstr[80]; 2280 struct e82545_softc *sc; 2281 char *devname; 2282 char *vtopts; 2283 int mac_provided; 2284 2285 DPRINTF("Loading with options: %s\r\n", opts); 2286 2287 /* Setup our softc */ 2288 sc = calloc(1, sizeof(*sc)); 2289 2290 pi->pi_arg = sc; 2291 sc->esc_pi = pi; 2292 sc->esc_ctx = ctx; 2293 2294 pthread_mutex_init(&sc->esc_mtx, NULL); 2295 pthread_cond_init(&sc->esc_rx_cond, NULL); 2296 pthread_cond_init(&sc->esc_tx_cond, NULL); 2297 pthread_create(&sc->esc_tx_tid, NULL, e82545_tx_thread, sc); 2298 snprintf(nstr, sizeof(nstr), "e82545-%d:%d tx", pi->pi_slot, 2299 pi->pi_func); 2300 pthread_set_name_np(sc->esc_tx_tid, nstr); 2301 2302 pci_set_cfgdata16(pi, PCIR_DEVICE, E82545_DEV_ID_82545EM_COPPER); 2303 pci_set_cfgdata16(pi, PCIR_VENDOR, E82545_VENDOR_ID_INTEL); 2304 pci_set_cfgdata8(pi, PCIR_CLASS, PCIC_NETWORK); 2305 pci_set_cfgdata8(pi, PCIR_SUBCLASS, PCIS_NETWORK_ETHERNET); 2306 pci_set_cfgdata16(pi, PCIR_SUBDEV_0, E82545_SUBDEV_ID); 2307 pci_set_cfgdata16(pi, PCIR_SUBVEND_0, E82545_VENDOR_ID_INTEL); 2308 2309 pci_set_cfgdata8(pi, PCIR_HDRTYPE, PCIM_HDRTYPE_NORMAL); 2310 pci_set_cfgdata8(pi, PCIR_INTPIN, 0x1); 2311 2312 /* TODO: this card also supports msi, but the freebsd driver for it 2313 * does not, so I have not implemented it. */ 2314 pci_lintr_request(pi); 2315 2316 pci_emul_alloc_bar(pi, E82545_BAR_REGISTER, PCIBAR_MEM32, 2317 E82545_BAR_REGISTER_LEN); 2318 pci_emul_alloc_bar(pi, E82545_BAR_FLASH, PCIBAR_MEM32, 2319 E82545_BAR_FLASH_LEN); 2320 pci_emul_alloc_bar(pi, E82545_BAR_IO, PCIBAR_IO, 2321 E82545_BAR_IO_LEN); 2322 2323 /* 2324 * Attempt to open the net backend and read the MAC address 2325 * if specified. Copied from virtio-net, slightly modified. 2326 */ 2327 mac_provided = 0; 2328 sc->esc_be = NULL; 2329 if (opts != NULL) { 2330 int err; 2331 2332 devname = vtopts = strdup(opts); 2333 (void) strsep(&vtopts, ","); 2334 2335 if (vtopts != NULL) { 2336 err = net_parsemac(vtopts, sc->esc_mac.octet); 2337 if (err != 0) { 2338 free(devname); 2339 return (err); 2340 } 2341 mac_provided = 1; 2342 } 2343 2344 err = netbe_init(&sc->esc_be, devname, e82545_rx_callback, sc); 2345 free(devname); 2346 if (err) 2347 return (err); 2348 } 2349 2350 if (!mac_provided) { 2351 net_genmac(pi, sc->esc_mac.octet); 2352 } 2353 2354 /* H/w initiated reset */ 2355 e82545_reset(sc, 0); 2356 2357 return (0); 2358 } 2359 2360 struct pci_devemu pci_de_e82545 = { 2361 .pe_emu = "e1000", 2362 .pe_init = e82545_init, 2363 .pe_barwrite = e82545_write, 2364 .pe_barread = e82545_read 2365 }; 2366 PCI_EMUL_SET(pci_de_e82545); 2367 2368