1 /* 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2016 Alexander Motin <mav@FreeBSD.org> 5 * Copyright (c) 2015 Peter Grehan <grehan@freebsd.org> 6 * Copyright (c) 2013 Jeremiah Lott, Avere Systems 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer 14 * in this position and unchanged. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __FBSDID("$FreeBSD$"); 34 35 #include <sys/types.h> 36 #ifndef WITHOUT_CAPSICUM 37 #include <sys/capsicum.h> 38 #endif 39 #include <sys/limits.h> 40 #include <sys/ioctl.h> 41 #include <sys/uio.h> 42 #include <net/ethernet.h> 43 #include <netinet/in.h> 44 #include <netinet/tcp.h> 45 46 #ifndef WITHOUT_CAPSICUM 47 #include <capsicum_helpers.h> 48 #endif 49 #include <machine/vmm_snapshot.h> 50 51 #include <err.h> 52 #include <errno.h> 53 #include <fcntl.h> 54 #include <md5.h> 55 #include <stdio.h> 56 #include <stdlib.h> 57 #include <string.h> 58 #include <sysexits.h> 59 #include <unistd.h> 60 #include <pthread.h> 61 #include <pthread_np.h> 62 63 #include "e1000_regs.h" 64 #include "e1000_defines.h" 65 #include "mii.h" 66 67 #include "bhyverun.h" 68 #include "config.h" 69 #include "debug.h" 70 #include "pci_emul.h" 71 #include "mevent.h" 72 #include "net_utils.h" 73 #include "net_backends.h" 74 75 /* Hardware/register definitions XXX: move some to common code. */ 76 #define E82545_VENDOR_ID_INTEL 0x8086 77 #define E82545_DEV_ID_82545EM_COPPER 0x100F 78 #define E82545_SUBDEV_ID 0x1008 79 80 #define E82545_REVISION_4 4 81 82 #define E82545_MDIC_DATA_MASK 0x0000FFFF 83 #define E82545_MDIC_OP_MASK 0x0c000000 84 #define E82545_MDIC_IE 0x20000000 85 86 #define E82545_EECD_FWE_DIS 0x00000010 /* Flash writes disabled */ 87 #define E82545_EECD_FWE_EN 0x00000020 /* Flash writes enabled */ 88 #define E82545_EECD_FWE_MASK 0x00000030 /* Flash writes mask */ 89 90 #define E82545_BAR_REGISTER 0 91 #define E82545_BAR_REGISTER_LEN (128*1024) 92 #define E82545_BAR_FLASH 1 93 #define E82545_BAR_FLASH_LEN (64*1024) 94 #define E82545_BAR_IO 2 95 #define E82545_BAR_IO_LEN 8 96 97 #define E82545_IOADDR 0x00000000 98 #define E82545_IODATA 0x00000004 99 #define E82545_IO_REGISTER_MAX 0x0001FFFF 100 #define E82545_IO_FLASH_BASE 0x00080000 101 #define E82545_IO_FLASH_MAX 0x000FFFFF 102 103 #define E82545_ARRAY_ENTRY(reg, offset) (reg + (offset<<2)) 104 #define E82545_RAR_MAX 15 105 #define E82545_MTA_MAX 127 106 #define E82545_VFTA_MAX 127 107 108 /* Slightly modified from the driver versions, hardcoded for 3 opcode bits, 109 * followed by 6 address bits. 110 * TODO: make opcode bits and addr bits configurable? 111 * NVM Commands - Microwire */ 112 #define E82545_NVM_OPCODE_BITS 3 113 #define E82545_NVM_ADDR_BITS 6 114 #define E82545_NVM_DATA_BITS 16 115 #define E82545_NVM_OPADDR_BITS (E82545_NVM_OPCODE_BITS + E82545_NVM_ADDR_BITS) 116 #define E82545_NVM_ADDR_MASK ((1 << E82545_NVM_ADDR_BITS)-1) 117 #define E82545_NVM_OPCODE_MASK \ 118 (((1 << E82545_NVM_OPCODE_BITS) - 1) << E82545_NVM_ADDR_BITS) 119 #define E82545_NVM_OPCODE_READ (0x6 << E82545_NVM_ADDR_BITS) /* read */ 120 #define E82545_NVM_OPCODE_WRITE (0x5 << E82545_NVM_ADDR_BITS) /* write */ 121 #define E82545_NVM_OPCODE_ERASE (0x7 << E82545_NVM_ADDR_BITS) /* erase */ 122 #define E82545_NVM_OPCODE_EWEN (0x4 << E82545_NVM_ADDR_BITS) /* wr-enable */ 123 124 #define E82545_NVM_EEPROM_SIZE 64 /* 64 * 16-bit values == 128K */ 125 126 #define E1000_ICR_SRPD 0x00010000 127 128 /* This is an arbitrary number. There is no hard limit on the chip. */ 129 #define I82545_MAX_TXSEGS 64 130 131 /* Legacy receive descriptor */ 132 struct e1000_rx_desc { 133 uint64_t buffer_addr; /* Address of the descriptor's data buffer */ 134 uint16_t length; /* Length of data DMAed into data buffer */ 135 uint16_t csum; /* Packet checksum */ 136 uint8_t status; /* Descriptor status */ 137 uint8_t errors; /* Descriptor Errors */ 138 uint16_t special; 139 }; 140 141 /* Transmit descriptor types */ 142 #define E1000_TXD_MASK (E1000_TXD_CMD_DEXT | 0x00F00000) 143 #define E1000_TXD_TYP_L (0) 144 #define E1000_TXD_TYP_C (E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_C) 145 #define E1000_TXD_TYP_D (E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D) 146 147 /* Legacy transmit descriptor */ 148 struct e1000_tx_desc { 149 uint64_t buffer_addr; /* Address of the descriptor's data buffer */ 150 union { 151 uint32_t data; 152 struct { 153 uint16_t length; /* Data buffer length */ 154 uint8_t cso; /* Checksum offset */ 155 uint8_t cmd; /* Descriptor control */ 156 } flags; 157 } lower; 158 union { 159 uint32_t data; 160 struct { 161 uint8_t status; /* Descriptor status */ 162 uint8_t css; /* Checksum start */ 163 uint16_t special; 164 } fields; 165 } upper; 166 }; 167 168 /* Context descriptor */ 169 struct e1000_context_desc { 170 union { 171 uint32_t ip_config; 172 struct { 173 uint8_t ipcss; /* IP checksum start */ 174 uint8_t ipcso; /* IP checksum offset */ 175 uint16_t ipcse; /* IP checksum end */ 176 } ip_fields; 177 } lower_setup; 178 union { 179 uint32_t tcp_config; 180 struct { 181 uint8_t tucss; /* TCP checksum start */ 182 uint8_t tucso; /* TCP checksum offset */ 183 uint16_t tucse; /* TCP checksum end */ 184 } tcp_fields; 185 } upper_setup; 186 uint32_t cmd_and_length; 187 union { 188 uint32_t data; 189 struct { 190 uint8_t status; /* Descriptor status */ 191 uint8_t hdr_len; /* Header length */ 192 uint16_t mss; /* Maximum segment size */ 193 } fields; 194 } tcp_seg_setup; 195 }; 196 197 /* Data descriptor */ 198 struct e1000_data_desc { 199 uint64_t buffer_addr; /* Address of the descriptor's buffer address */ 200 union { 201 uint32_t data; 202 struct { 203 uint16_t length; /* Data buffer length */ 204 uint8_t typ_len_ext; 205 uint8_t cmd; 206 } flags; 207 } lower; 208 union { 209 uint32_t data; 210 struct { 211 uint8_t status; /* Descriptor status */ 212 uint8_t popts; /* Packet Options */ 213 uint16_t special; 214 } fields; 215 } upper; 216 }; 217 218 union e1000_tx_udesc { 219 struct e1000_tx_desc td; 220 struct e1000_context_desc cd; 221 struct e1000_data_desc dd; 222 }; 223 224 /* Tx checksum info for a packet. */ 225 struct ck_info { 226 int ck_valid; /* ck_info is valid */ 227 uint8_t ck_start; /* start byte of cksum calcuation */ 228 uint8_t ck_off; /* offset of cksum insertion */ 229 uint16_t ck_len; /* length of cksum calc: 0 is to packet-end */ 230 }; 231 232 /* 233 * Debug printf 234 */ 235 static int e82545_debug = 0; 236 #define WPRINTF(msg,params...) PRINTLN("e82545: " msg, params) 237 #define DPRINTF(msg,params...) if (e82545_debug) WPRINTF(msg, params) 238 239 #define MIN(a,b) (((a)<(b))?(a):(b)) 240 #define MAX(a,b) (((a)>(b))?(a):(b)) 241 242 /* s/w representation of the RAL/RAH regs */ 243 struct eth_uni { 244 int eu_valid; 245 int eu_addrsel; 246 struct ether_addr eu_eth; 247 }; 248 249 250 struct e82545_softc { 251 struct pci_devinst *esc_pi; 252 struct vmctx *esc_ctx; 253 struct mevent *esc_mevpitr; 254 pthread_mutex_t esc_mtx; 255 struct ether_addr esc_mac; 256 net_backend_t *esc_be; 257 258 /* General */ 259 uint32_t esc_CTRL; /* x0000 device ctl */ 260 uint32_t esc_FCAL; /* x0028 flow ctl addr lo */ 261 uint32_t esc_FCAH; /* x002C flow ctl addr hi */ 262 uint32_t esc_FCT; /* x0030 flow ctl type */ 263 uint32_t esc_VET; /* x0038 VLAN eth type */ 264 uint32_t esc_FCTTV; /* x0170 flow ctl tx timer */ 265 uint32_t esc_LEDCTL; /* x0E00 LED control */ 266 uint32_t esc_PBA; /* x1000 pkt buffer allocation */ 267 268 /* Interrupt control */ 269 int esc_irq_asserted; 270 uint32_t esc_ICR; /* x00C0 cause read/clear */ 271 uint32_t esc_ITR; /* x00C4 intr throttling */ 272 uint32_t esc_ICS; /* x00C8 cause set */ 273 uint32_t esc_IMS; /* x00D0 mask set/read */ 274 uint32_t esc_IMC; /* x00D8 mask clear */ 275 276 /* Transmit */ 277 union e1000_tx_udesc *esc_txdesc; 278 struct e1000_context_desc esc_txctx; 279 pthread_t esc_tx_tid; 280 pthread_cond_t esc_tx_cond; 281 int esc_tx_enabled; 282 int esc_tx_active; 283 uint32_t esc_TXCW; /* x0178 transmit config */ 284 uint32_t esc_TCTL; /* x0400 transmit ctl */ 285 uint32_t esc_TIPG; /* x0410 inter-packet gap */ 286 uint16_t esc_AIT; /* x0458 Adaptive Interframe Throttle */ 287 uint64_t esc_tdba; /* verified 64-bit desc table addr */ 288 uint32_t esc_TDBAL; /* x3800 desc table addr, low bits */ 289 uint32_t esc_TDBAH; /* x3804 desc table addr, hi 32-bits */ 290 uint32_t esc_TDLEN; /* x3808 # descriptors in bytes */ 291 uint16_t esc_TDH; /* x3810 desc table head idx */ 292 uint16_t esc_TDHr; /* internal read version of TDH */ 293 uint16_t esc_TDT; /* x3818 desc table tail idx */ 294 uint32_t esc_TIDV; /* x3820 intr delay */ 295 uint32_t esc_TXDCTL; /* x3828 desc control */ 296 uint32_t esc_TADV; /* x382C intr absolute delay */ 297 298 /* L2 frame acceptance */ 299 struct eth_uni esc_uni[16]; /* 16 x unicast MAC addresses */ 300 uint32_t esc_fmcast[128]; /* Multicast filter bit-match */ 301 uint32_t esc_fvlan[128]; /* VLAN 4096-bit filter */ 302 303 /* Receive */ 304 struct e1000_rx_desc *esc_rxdesc; 305 pthread_cond_t esc_rx_cond; 306 int esc_rx_enabled; 307 int esc_rx_active; 308 int esc_rx_loopback; 309 uint32_t esc_RCTL; /* x0100 receive ctl */ 310 uint32_t esc_FCRTL; /* x2160 flow cntl thresh, low */ 311 uint32_t esc_FCRTH; /* x2168 flow cntl thresh, hi */ 312 uint64_t esc_rdba; /* verified 64-bit desc table addr */ 313 uint32_t esc_RDBAL; /* x2800 desc table addr, low bits */ 314 uint32_t esc_RDBAH; /* x2804 desc table addr, hi 32-bits*/ 315 uint32_t esc_RDLEN; /* x2808 #descriptors */ 316 uint16_t esc_RDH; /* x2810 desc table head idx */ 317 uint16_t esc_RDT; /* x2818 desc table tail idx */ 318 uint32_t esc_RDTR; /* x2820 intr delay */ 319 uint32_t esc_RXDCTL; /* x2828 desc control */ 320 uint32_t esc_RADV; /* x282C intr absolute delay */ 321 uint32_t esc_RSRPD; /* x2C00 recv small packet detect */ 322 uint32_t esc_RXCSUM; /* x5000 receive cksum ctl */ 323 324 /* IO Port register access */ 325 uint32_t io_addr; 326 327 /* Shadow copy of MDIC */ 328 uint32_t mdi_control; 329 /* Shadow copy of EECD */ 330 uint32_t eeprom_control; 331 /* Latest NVM in/out */ 332 uint16_t nvm_data; 333 uint16_t nvm_opaddr; 334 /* stats */ 335 uint32_t missed_pkt_count; /* dropped for no room in rx queue */ 336 uint32_t pkt_rx_by_size[6]; 337 uint32_t pkt_tx_by_size[6]; 338 uint32_t good_pkt_rx_count; 339 uint32_t bcast_pkt_rx_count; 340 uint32_t mcast_pkt_rx_count; 341 uint32_t good_pkt_tx_count; 342 uint32_t bcast_pkt_tx_count; 343 uint32_t mcast_pkt_tx_count; 344 uint32_t oversize_rx_count; 345 uint32_t tso_tx_count; 346 uint64_t good_octets_rx; 347 uint64_t good_octets_tx; 348 uint64_t missed_octets; /* counts missed and oversized */ 349 350 uint8_t nvm_bits:6; /* number of bits remaining in/out */ 351 uint8_t nvm_mode:2; 352 #define E82545_NVM_MODE_OPADDR 0x0 353 #define E82545_NVM_MODE_DATAIN 0x1 354 #define E82545_NVM_MODE_DATAOUT 0x2 355 /* EEPROM data */ 356 uint16_t eeprom_data[E82545_NVM_EEPROM_SIZE]; 357 }; 358 359 static void e82545_reset(struct e82545_softc *sc, int dev); 360 static void e82545_rx_enable(struct e82545_softc *sc); 361 static void e82545_rx_disable(struct e82545_softc *sc); 362 static void e82545_rx_callback(int fd, enum ev_type type, void *param); 363 static void e82545_tx_start(struct e82545_softc *sc); 364 static void e82545_tx_enable(struct e82545_softc *sc); 365 static void e82545_tx_disable(struct e82545_softc *sc); 366 367 static inline int 368 e82545_size_stat_index(uint32_t size) 369 { 370 if (size <= 64) { 371 return 0; 372 } else if (size >= 1024) { 373 return 5; 374 } else { 375 /* should be 1-4 */ 376 return (ffs(size) - 6); 377 } 378 } 379 380 static void 381 e82545_init_eeprom(struct e82545_softc *sc) 382 { 383 uint16_t checksum, i; 384 385 /* mac addr */ 386 sc->eeprom_data[NVM_MAC_ADDR] = ((uint16_t)sc->esc_mac.octet[0]) | 387 (((uint16_t)sc->esc_mac.octet[1]) << 8); 388 sc->eeprom_data[NVM_MAC_ADDR+1] = ((uint16_t)sc->esc_mac.octet[2]) | 389 (((uint16_t)sc->esc_mac.octet[3]) << 8); 390 sc->eeprom_data[NVM_MAC_ADDR+2] = ((uint16_t)sc->esc_mac.octet[4]) | 391 (((uint16_t)sc->esc_mac.octet[5]) << 8); 392 393 /* pci ids */ 394 sc->eeprom_data[NVM_SUB_DEV_ID] = E82545_SUBDEV_ID; 395 sc->eeprom_data[NVM_SUB_VEN_ID] = E82545_VENDOR_ID_INTEL; 396 sc->eeprom_data[NVM_DEV_ID] = E82545_DEV_ID_82545EM_COPPER; 397 sc->eeprom_data[NVM_VEN_ID] = E82545_VENDOR_ID_INTEL; 398 399 /* fill in the checksum */ 400 checksum = 0; 401 for (i = 0; i < NVM_CHECKSUM_REG; i++) { 402 checksum += sc->eeprom_data[i]; 403 } 404 checksum = NVM_SUM - checksum; 405 sc->eeprom_data[NVM_CHECKSUM_REG] = checksum; 406 DPRINTF("eeprom checksum: 0x%x", checksum); 407 } 408 409 static void 410 e82545_write_mdi(struct e82545_softc *sc, uint8_t reg_addr, 411 uint8_t phy_addr, uint32_t data) 412 { 413 DPRINTF("Write mdi reg:0x%x phy:0x%x data: 0x%x", reg_addr, phy_addr, data); 414 } 415 416 static uint32_t 417 e82545_read_mdi(struct e82545_softc *sc, uint8_t reg_addr, 418 uint8_t phy_addr) 419 { 420 //DPRINTF("Read mdi reg:0x%x phy:0x%x", reg_addr, phy_addr); 421 switch (reg_addr) { 422 case PHY_STATUS: 423 return (MII_SR_LINK_STATUS | MII_SR_AUTONEG_CAPS | 424 MII_SR_AUTONEG_COMPLETE); 425 case PHY_AUTONEG_ADV: 426 return NWAY_AR_SELECTOR_FIELD; 427 case PHY_LP_ABILITY: 428 return 0; 429 case PHY_1000T_STATUS: 430 return (SR_1000T_LP_FD_CAPS | SR_1000T_REMOTE_RX_STATUS | 431 SR_1000T_LOCAL_RX_STATUS); 432 case PHY_ID1: 433 return (M88E1011_I_PHY_ID >> 16) & 0xFFFF; 434 case PHY_ID2: 435 return (M88E1011_I_PHY_ID | E82545_REVISION_4) & 0xFFFF; 436 default: 437 DPRINTF("Unknown mdi read reg:0x%x phy:0x%x", reg_addr, phy_addr); 438 return 0; 439 } 440 /* not reached */ 441 } 442 443 static void 444 e82545_eecd_strobe(struct e82545_softc *sc) 445 { 446 /* Microwire state machine */ 447 /* 448 DPRINTF("eeprom state machine srtobe " 449 "0x%x 0x%x 0x%x 0x%x", 450 sc->nvm_mode, sc->nvm_bits, 451 sc->nvm_opaddr, sc->nvm_data);*/ 452 453 if (sc->nvm_bits == 0) { 454 DPRINTF("eeprom state machine not expecting data! " 455 "0x%x 0x%x 0x%x 0x%x", 456 sc->nvm_mode, sc->nvm_bits, 457 sc->nvm_opaddr, sc->nvm_data); 458 return; 459 } 460 sc->nvm_bits--; 461 if (sc->nvm_mode == E82545_NVM_MODE_DATAOUT) { 462 /* shifting out */ 463 if (sc->nvm_data & 0x8000) { 464 sc->eeprom_control |= E1000_EECD_DO; 465 } else { 466 sc->eeprom_control &= ~E1000_EECD_DO; 467 } 468 sc->nvm_data <<= 1; 469 if (sc->nvm_bits == 0) { 470 /* read done, back to opcode mode. */ 471 sc->nvm_opaddr = 0; 472 sc->nvm_mode = E82545_NVM_MODE_OPADDR; 473 sc->nvm_bits = E82545_NVM_OPADDR_BITS; 474 } 475 } else if (sc->nvm_mode == E82545_NVM_MODE_DATAIN) { 476 /* shifting in */ 477 sc->nvm_data <<= 1; 478 if (sc->eeprom_control & E1000_EECD_DI) { 479 sc->nvm_data |= 1; 480 } 481 if (sc->nvm_bits == 0) { 482 /* eeprom write */ 483 uint16_t op = sc->nvm_opaddr & E82545_NVM_OPCODE_MASK; 484 uint16_t addr = sc->nvm_opaddr & E82545_NVM_ADDR_MASK; 485 if (op != E82545_NVM_OPCODE_WRITE) { 486 DPRINTF("Illegal eeprom write op 0x%x", 487 sc->nvm_opaddr); 488 } else if (addr >= E82545_NVM_EEPROM_SIZE) { 489 DPRINTF("Illegal eeprom write addr 0x%x", 490 sc->nvm_opaddr); 491 } else { 492 DPRINTF("eeprom write eeprom[0x%x] = 0x%x", 493 addr, sc->nvm_data); 494 sc->eeprom_data[addr] = sc->nvm_data; 495 } 496 /* back to opcode mode */ 497 sc->nvm_opaddr = 0; 498 sc->nvm_mode = E82545_NVM_MODE_OPADDR; 499 sc->nvm_bits = E82545_NVM_OPADDR_BITS; 500 } 501 } else if (sc->nvm_mode == E82545_NVM_MODE_OPADDR) { 502 sc->nvm_opaddr <<= 1; 503 if (sc->eeprom_control & E1000_EECD_DI) { 504 sc->nvm_opaddr |= 1; 505 } 506 if (sc->nvm_bits == 0) { 507 uint16_t op = sc->nvm_opaddr & E82545_NVM_OPCODE_MASK; 508 switch (op) { 509 case E82545_NVM_OPCODE_EWEN: 510 DPRINTF("eeprom write enable: 0x%x", 511 sc->nvm_opaddr); 512 /* back to opcode mode */ 513 sc->nvm_opaddr = 0; 514 sc->nvm_mode = E82545_NVM_MODE_OPADDR; 515 sc->nvm_bits = E82545_NVM_OPADDR_BITS; 516 break; 517 case E82545_NVM_OPCODE_READ: 518 { 519 uint16_t addr = sc->nvm_opaddr & 520 E82545_NVM_ADDR_MASK; 521 sc->nvm_mode = E82545_NVM_MODE_DATAOUT; 522 sc->nvm_bits = E82545_NVM_DATA_BITS; 523 if (addr < E82545_NVM_EEPROM_SIZE) { 524 sc->nvm_data = sc->eeprom_data[addr]; 525 DPRINTF("eeprom read: eeprom[0x%x] = 0x%x", 526 addr, sc->nvm_data); 527 } else { 528 DPRINTF("eeprom illegal read: 0x%x", 529 sc->nvm_opaddr); 530 sc->nvm_data = 0; 531 } 532 break; 533 } 534 case E82545_NVM_OPCODE_WRITE: 535 sc->nvm_mode = E82545_NVM_MODE_DATAIN; 536 sc->nvm_bits = E82545_NVM_DATA_BITS; 537 sc->nvm_data = 0; 538 break; 539 default: 540 DPRINTF("eeprom unknown op: 0x%x", 541 sc->nvm_opaddr); 542 /* back to opcode mode */ 543 sc->nvm_opaddr = 0; 544 sc->nvm_mode = E82545_NVM_MODE_OPADDR; 545 sc->nvm_bits = E82545_NVM_OPADDR_BITS; 546 } 547 } 548 } else { 549 DPRINTF("eeprom state machine wrong state! " 550 "0x%x 0x%x 0x%x 0x%x", 551 sc->nvm_mode, sc->nvm_bits, 552 sc->nvm_opaddr, sc->nvm_data); 553 } 554 } 555 556 static void 557 e82545_itr_callback(int fd, enum ev_type type, void *param) 558 { 559 uint32_t new; 560 struct e82545_softc *sc = param; 561 562 pthread_mutex_lock(&sc->esc_mtx); 563 new = sc->esc_ICR & sc->esc_IMS; 564 if (new && !sc->esc_irq_asserted) { 565 DPRINTF("itr callback: lintr assert %x", new); 566 sc->esc_irq_asserted = 1; 567 pci_lintr_assert(sc->esc_pi); 568 } else { 569 mevent_delete(sc->esc_mevpitr); 570 sc->esc_mevpitr = NULL; 571 } 572 pthread_mutex_unlock(&sc->esc_mtx); 573 } 574 575 static void 576 e82545_icr_assert(struct e82545_softc *sc, uint32_t bits) 577 { 578 uint32_t new; 579 580 DPRINTF("icr assert: 0x%x", bits); 581 582 /* 583 * An interrupt is only generated if bits are set that 584 * aren't already in the ICR, these bits are unmasked, 585 * and there isn't an interrupt already pending. 586 */ 587 new = bits & ~sc->esc_ICR & sc->esc_IMS; 588 sc->esc_ICR |= bits; 589 590 if (new == 0) { 591 DPRINTF("icr assert: masked %x, ims %x", new, sc->esc_IMS); 592 } else if (sc->esc_mevpitr != NULL) { 593 DPRINTF("icr assert: throttled %x, ims %x", new, sc->esc_IMS); 594 } else if (!sc->esc_irq_asserted) { 595 DPRINTF("icr assert: lintr assert %x", new); 596 sc->esc_irq_asserted = 1; 597 pci_lintr_assert(sc->esc_pi); 598 if (sc->esc_ITR != 0) { 599 sc->esc_mevpitr = mevent_add( 600 (sc->esc_ITR + 3905) / 3906, /* 256ns -> 1ms */ 601 EVF_TIMER, e82545_itr_callback, sc); 602 } 603 } 604 } 605 606 static void 607 e82545_ims_change(struct e82545_softc *sc, uint32_t bits) 608 { 609 uint32_t new; 610 611 /* 612 * Changing the mask may allow previously asserted 613 * but masked interrupt requests to generate an interrupt. 614 */ 615 new = bits & sc->esc_ICR & ~sc->esc_IMS; 616 sc->esc_IMS |= bits; 617 618 if (new == 0) { 619 DPRINTF("ims change: masked %x, ims %x", new, sc->esc_IMS); 620 } else if (sc->esc_mevpitr != NULL) { 621 DPRINTF("ims change: throttled %x, ims %x", new, sc->esc_IMS); 622 } else if (!sc->esc_irq_asserted) { 623 DPRINTF("ims change: lintr assert %x", new); 624 sc->esc_irq_asserted = 1; 625 pci_lintr_assert(sc->esc_pi); 626 if (sc->esc_ITR != 0) { 627 sc->esc_mevpitr = mevent_add( 628 (sc->esc_ITR + 3905) / 3906, /* 256ns -> 1ms */ 629 EVF_TIMER, e82545_itr_callback, sc); 630 } 631 } 632 } 633 634 static void 635 e82545_icr_deassert(struct e82545_softc *sc, uint32_t bits) 636 { 637 638 DPRINTF("icr deassert: 0x%x", bits); 639 sc->esc_ICR &= ~bits; 640 641 /* 642 * If there are no longer any interrupt sources and there 643 * was an asserted interrupt, clear it 644 */ 645 if (sc->esc_irq_asserted && !(sc->esc_ICR & sc->esc_IMS)) { 646 DPRINTF("icr deassert: lintr deassert %x", bits); 647 pci_lintr_deassert(sc->esc_pi); 648 sc->esc_irq_asserted = 0; 649 } 650 } 651 652 static void 653 e82545_intr_write(struct e82545_softc *sc, uint32_t offset, uint32_t value) 654 { 655 656 DPRINTF("intr_write: off %x, val %x", offset, value); 657 658 switch (offset) { 659 case E1000_ICR: 660 e82545_icr_deassert(sc, value); 661 break; 662 case E1000_ITR: 663 sc->esc_ITR = value; 664 break; 665 case E1000_ICS: 666 sc->esc_ICS = value; /* not used: store for debug */ 667 e82545_icr_assert(sc, value); 668 break; 669 case E1000_IMS: 670 e82545_ims_change(sc, value); 671 break; 672 case E1000_IMC: 673 sc->esc_IMC = value; /* for debug */ 674 sc->esc_IMS &= ~value; 675 // XXX clear interrupts if all ICR bits now masked 676 // and interrupt was pending ? 677 break; 678 default: 679 break; 680 } 681 } 682 683 static uint32_t 684 e82545_intr_read(struct e82545_softc *sc, uint32_t offset) 685 { 686 uint32_t retval; 687 688 retval = 0; 689 690 DPRINTF("intr_read: off %x", offset); 691 692 switch (offset) { 693 case E1000_ICR: 694 retval = sc->esc_ICR; 695 sc->esc_ICR = 0; 696 e82545_icr_deassert(sc, ~0); 697 break; 698 case E1000_ITR: 699 retval = sc->esc_ITR; 700 break; 701 case E1000_ICS: 702 /* write-only register */ 703 break; 704 case E1000_IMS: 705 retval = sc->esc_IMS; 706 break; 707 case E1000_IMC: 708 /* write-only register */ 709 break; 710 default: 711 break; 712 } 713 714 return (retval); 715 } 716 717 static void 718 e82545_devctl(struct e82545_softc *sc, uint32_t val) 719 { 720 721 sc->esc_CTRL = val & ~E1000_CTRL_RST; 722 723 if (val & E1000_CTRL_RST) { 724 DPRINTF("e1k: s/w reset, ctl %x", val); 725 e82545_reset(sc, 1); 726 } 727 /* XXX check for phy reset ? */ 728 } 729 730 static void 731 e82545_rx_update_rdba(struct e82545_softc *sc) 732 { 733 734 /* XXX verify desc base/len within phys mem range */ 735 sc->esc_rdba = (uint64_t)sc->esc_RDBAH << 32 | 736 sc->esc_RDBAL; 737 738 /* Cache host mapping of guest descriptor array */ 739 sc->esc_rxdesc = paddr_guest2host(sc->esc_ctx, 740 sc->esc_rdba, sc->esc_RDLEN); 741 } 742 743 static void 744 e82545_rx_ctl(struct e82545_softc *sc, uint32_t val) 745 { 746 int on; 747 748 on = ((val & E1000_RCTL_EN) == E1000_RCTL_EN); 749 750 /* Save RCTL after stripping reserved bits 31:27,24,21,14,11:10,0 */ 751 sc->esc_RCTL = val & ~0xF9204c01; 752 753 DPRINTF("rx_ctl - %s RCTL %x, val %x", 754 on ? "on" : "off", sc->esc_RCTL, val); 755 756 /* state change requested */ 757 if (on != sc->esc_rx_enabled) { 758 if (on) { 759 /* Catch disallowed/unimplemented settings */ 760 //assert(!(val & E1000_RCTL_LBM_TCVR)); 761 762 if (sc->esc_RCTL & E1000_RCTL_LBM_TCVR) { 763 sc->esc_rx_loopback = 1; 764 } else { 765 sc->esc_rx_loopback = 0; 766 } 767 768 e82545_rx_update_rdba(sc); 769 e82545_rx_enable(sc); 770 } else { 771 e82545_rx_disable(sc); 772 sc->esc_rx_loopback = 0; 773 sc->esc_rdba = 0; 774 sc->esc_rxdesc = NULL; 775 } 776 } 777 } 778 779 static void 780 e82545_tx_update_tdba(struct e82545_softc *sc) 781 { 782 783 /* XXX verify desc base/len within phys mem range */ 784 sc->esc_tdba = (uint64_t)sc->esc_TDBAH << 32 | sc->esc_TDBAL; 785 786 /* Cache host mapping of guest descriptor array */ 787 sc->esc_txdesc = paddr_guest2host(sc->esc_ctx, sc->esc_tdba, 788 sc->esc_TDLEN); 789 } 790 791 static void 792 e82545_tx_ctl(struct e82545_softc *sc, uint32_t val) 793 { 794 int on; 795 796 on = ((val & E1000_TCTL_EN) == E1000_TCTL_EN); 797 798 /* ignore TCTL_EN settings that don't change state */ 799 if (on == sc->esc_tx_enabled) 800 return; 801 802 if (on) { 803 e82545_tx_update_tdba(sc); 804 e82545_tx_enable(sc); 805 } else { 806 e82545_tx_disable(sc); 807 sc->esc_tdba = 0; 808 sc->esc_txdesc = NULL; 809 } 810 811 /* Save TCTL value after stripping reserved bits 31:25,23,2,0 */ 812 sc->esc_TCTL = val & ~0xFE800005; 813 } 814 815 int 816 e82545_bufsz(uint32_t rctl) 817 { 818 819 switch (rctl & (E1000_RCTL_BSEX | E1000_RCTL_SZ_256)) { 820 case (E1000_RCTL_SZ_2048): return (2048); 821 case (E1000_RCTL_SZ_1024): return (1024); 822 case (E1000_RCTL_SZ_512): return (512); 823 case (E1000_RCTL_SZ_256): return (256); 824 case (E1000_RCTL_BSEX|E1000_RCTL_SZ_16384): return (16384); 825 case (E1000_RCTL_BSEX|E1000_RCTL_SZ_8192): return (8192); 826 case (E1000_RCTL_BSEX|E1000_RCTL_SZ_4096): return (4096); 827 } 828 return (256); /* Forbidden value. */ 829 } 830 831 /* XXX one packet at a time until this is debugged */ 832 static void 833 e82545_rx_callback(int fd, enum ev_type type, void *param) 834 { 835 struct e82545_softc *sc = param; 836 struct e1000_rx_desc *rxd; 837 struct iovec vec[64]; 838 int left, len, lim, maxpktsz, maxpktdesc, bufsz, i, n, size; 839 uint32_t cause = 0; 840 uint16_t *tp, tag, head; 841 842 pthread_mutex_lock(&sc->esc_mtx); 843 DPRINTF("rx_run: head %x, tail %x", sc->esc_RDH, sc->esc_RDT); 844 845 if (!sc->esc_rx_enabled || sc->esc_rx_loopback) { 846 DPRINTF("rx disabled (!%d || %d) -- packet(s) dropped", 847 sc->esc_rx_enabled, sc->esc_rx_loopback); 848 while (netbe_rx_discard(sc->esc_be) > 0) { 849 } 850 goto done1; 851 } 852 bufsz = e82545_bufsz(sc->esc_RCTL); 853 maxpktsz = (sc->esc_RCTL & E1000_RCTL_LPE) ? 16384 : 1522; 854 maxpktdesc = (maxpktsz + bufsz - 1) / bufsz; 855 size = sc->esc_RDLEN / 16; 856 head = sc->esc_RDH; 857 left = (size + sc->esc_RDT - head) % size; 858 if (left < maxpktdesc) { 859 DPRINTF("rx overflow (%d < %d) -- packet(s) dropped", 860 left, maxpktdesc); 861 while (netbe_rx_discard(sc->esc_be) > 0) { 862 } 863 goto done1; 864 } 865 866 sc->esc_rx_active = 1; 867 pthread_mutex_unlock(&sc->esc_mtx); 868 869 for (lim = size / 4; lim > 0 && left >= maxpktdesc; lim -= n) { 870 871 /* Grab rx descriptor pointed to by the head pointer */ 872 for (i = 0; i < maxpktdesc; i++) { 873 rxd = &sc->esc_rxdesc[(head + i) % size]; 874 vec[i].iov_base = paddr_guest2host(sc->esc_ctx, 875 rxd->buffer_addr, bufsz); 876 vec[i].iov_len = bufsz; 877 } 878 len = netbe_recv(sc->esc_be, vec, maxpktdesc); 879 if (len <= 0) { 880 DPRINTF("netbe_recv() returned %d", len); 881 goto done; 882 } 883 884 /* 885 * Adjust the packet length based on whether the CRC needs 886 * to be stripped or if the packet is less than the minimum 887 * eth packet size. 888 */ 889 if (len < ETHER_MIN_LEN - ETHER_CRC_LEN) 890 len = ETHER_MIN_LEN - ETHER_CRC_LEN; 891 if (!(sc->esc_RCTL & E1000_RCTL_SECRC)) 892 len += ETHER_CRC_LEN; 893 n = (len + bufsz - 1) / bufsz; 894 895 DPRINTF("packet read %d bytes, %d segs, head %d", 896 len, n, head); 897 898 /* Apply VLAN filter. */ 899 tp = (uint16_t *)vec[0].iov_base + 6; 900 if ((sc->esc_RCTL & E1000_RCTL_VFE) && 901 (ntohs(tp[0]) == sc->esc_VET)) { 902 tag = ntohs(tp[1]) & 0x0fff; 903 if ((sc->esc_fvlan[tag >> 5] & 904 (1 << (tag & 0x1f))) != 0) { 905 DPRINTF("known VLAN %d", tag); 906 } else { 907 DPRINTF("unknown VLAN %d", tag); 908 n = 0; 909 continue; 910 } 911 } 912 913 /* Update all consumed descriptors. */ 914 for (i = 0; i < n - 1; i++) { 915 rxd = &sc->esc_rxdesc[(head + i) % size]; 916 rxd->length = bufsz; 917 rxd->csum = 0; 918 rxd->errors = 0; 919 rxd->special = 0; 920 rxd->status = E1000_RXD_STAT_DD; 921 } 922 rxd = &sc->esc_rxdesc[(head + i) % size]; 923 rxd->length = len % bufsz; 924 rxd->csum = 0; 925 rxd->errors = 0; 926 rxd->special = 0; 927 /* XXX signal no checksum for now */ 928 rxd->status = E1000_RXD_STAT_PIF | E1000_RXD_STAT_IXSM | 929 E1000_RXD_STAT_EOP | E1000_RXD_STAT_DD; 930 931 /* Schedule receive interrupts. */ 932 if (len <= sc->esc_RSRPD) { 933 cause |= E1000_ICR_SRPD | E1000_ICR_RXT0; 934 } else { 935 /* XXX: RDRT and RADV timers should be here. */ 936 cause |= E1000_ICR_RXT0; 937 } 938 939 head = (head + n) % size; 940 left -= n; 941 } 942 943 done: 944 pthread_mutex_lock(&sc->esc_mtx); 945 sc->esc_rx_active = 0; 946 if (sc->esc_rx_enabled == 0) 947 pthread_cond_signal(&sc->esc_rx_cond); 948 949 sc->esc_RDH = head; 950 /* Respect E1000_RCTL_RDMTS */ 951 left = (size + sc->esc_RDT - head) % size; 952 if (left < (size >> (((sc->esc_RCTL >> 8) & 3) + 1))) 953 cause |= E1000_ICR_RXDMT0; 954 /* Assert all accumulated interrupts. */ 955 if (cause != 0) 956 e82545_icr_assert(sc, cause); 957 done1: 958 DPRINTF("rx_run done: head %x, tail %x", sc->esc_RDH, sc->esc_RDT); 959 pthread_mutex_unlock(&sc->esc_mtx); 960 } 961 962 static uint16_t 963 e82545_carry(uint32_t sum) 964 { 965 966 sum = (sum & 0xFFFF) + (sum >> 16); 967 if (sum > 0xFFFF) 968 sum -= 0xFFFF; 969 return (sum); 970 } 971 972 static uint16_t 973 e82545_buf_checksum(uint8_t *buf, int len) 974 { 975 int i; 976 uint32_t sum = 0; 977 978 /* Checksum all the pairs of bytes first... */ 979 for (i = 0; i < (len & ~1U); i += 2) 980 sum += *((u_int16_t *)(buf + i)); 981 982 /* 983 * If there's a single byte left over, checksum it, too. 984 * Network byte order is big-endian, so the remaining byte is 985 * the high byte. 986 */ 987 if (i < len) 988 sum += htons(buf[i] << 8); 989 990 return (e82545_carry(sum)); 991 } 992 993 static uint16_t 994 e82545_iov_checksum(struct iovec *iov, int iovcnt, int off, int len) 995 { 996 int now, odd; 997 uint32_t sum = 0, s; 998 999 /* Skip completely unneeded vectors. */ 1000 while (iovcnt > 0 && iov->iov_len <= off && off > 0) { 1001 off -= iov->iov_len; 1002 iov++; 1003 iovcnt--; 1004 } 1005 1006 /* Calculate checksum of requested range. */ 1007 odd = 0; 1008 while (len > 0 && iovcnt > 0) { 1009 now = MIN(len, iov->iov_len - off); 1010 s = e82545_buf_checksum(iov->iov_base + off, now); 1011 sum += odd ? (s << 8) : s; 1012 odd ^= (now & 1); 1013 len -= now; 1014 off = 0; 1015 iov++; 1016 iovcnt--; 1017 } 1018 1019 return (e82545_carry(sum)); 1020 } 1021 1022 /* 1023 * Return the transmit descriptor type. 1024 */ 1025 int 1026 e82545_txdesc_type(uint32_t lower) 1027 { 1028 int type; 1029 1030 type = 0; 1031 1032 if (lower & E1000_TXD_CMD_DEXT) 1033 type = lower & E1000_TXD_MASK; 1034 1035 return (type); 1036 } 1037 1038 static void 1039 e82545_transmit_checksum(struct iovec *iov, int iovcnt, struct ck_info *ck) 1040 { 1041 uint16_t cksum; 1042 int cklen; 1043 1044 DPRINTF("tx cksum: iovcnt/s/off/len %d/%d/%d/%d", 1045 iovcnt, ck->ck_start, ck->ck_off, ck->ck_len); 1046 cklen = ck->ck_len ? ck->ck_len - ck->ck_start + 1 : INT_MAX; 1047 cksum = e82545_iov_checksum(iov, iovcnt, ck->ck_start, cklen); 1048 *(uint16_t *)((uint8_t *)iov[0].iov_base + ck->ck_off) = ~cksum; 1049 } 1050 1051 static void 1052 e82545_transmit_backend(struct e82545_softc *sc, struct iovec *iov, int iovcnt) 1053 { 1054 1055 if (sc->esc_be == NULL) 1056 return; 1057 1058 (void) netbe_send(sc->esc_be, iov, iovcnt); 1059 } 1060 1061 static void 1062 e82545_transmit_done(struct e82545_softc *sc, uint16_t head, uint16_t tail, 1063 uint16_t dsize, int *tdwb) 1064 { 1065 union e1000_tx_udesc *dsc; 1066 1067 for ( ; head != tail; head = (head + 1) % dsize) { 1068 dsc = &sc->esc_txdesc[head]; 1069 if (dsc->td.lower.data & E1000_TXD_CMD_RS) { 1070 dsc->td.upper.data |= E1000_TXD_STAT_DD; 1071 *tdwb = 1; 1072 } 1073 } 1074 } 1075 1076 static int 1077 e82545_transmit(struct e82545_softc *sc, uint16_t head, uint16_t tail, 1078 uint16_t dsize, uint16_t *rhead, int *tdwb) 1079 { 1080 uint8_t *hdr, *hdrp; 1081 struct iovec iovb[I82545_MAX_TXSEGS + 2]; 1082 struct iovec tiov[I82545_MAX_TXSEGS + 2]; 1083 struct e1000_context_desc *cd; 1084 struct ck_info ckinfo[2]; 1085 struct iovec *iov; 1086 union e1000_tx_udesc *dsc; 1087 int desc, dtype, len, ntype, iovcnt, tcp, tso; 1088 int mss, paylen, seg, tiovcnt, left, now, nleft, nnow, pv, pvoff; 1089 unsigned hdrlen, vlen; 1090 uint32_t tcpsum, tcpseq; 1091 uint16_t ipcs, tcpcs, ipid, ohead; 1092 1093 ckinfo[0].ck_valid = ckinfo[1].ck_valid = 0; 1094 iovcnt = 0; 1095 ntype = 0; 1096 tso = 0; 1097 ohead = head; 1098 1099 /* iovb[0/1] may be used for writable copy of headers. */ 1100 iov = &iovb[2]; 1101 1102 for (desc = 0; ; desc++, head = (head + 1) % dsize) { 1103 if (head == tail) { 1104 *rhead = head; 1105 return (0); 1106 } 1107 dsc = &sc->esc_txdesc[head]; 1108 dtype = e82545_txdesc_type(dsc->td.lower.data); 1109 1110 if (desc == 0) { 1111 switch (dtype) { 1112 case E1000_TXD_TYP_C: 1113 DPRINTF("tx ctxt desc idx %d: %016jx " 1114 "%08x%08x", 1115 head, dsc->td.buffer_addr, 1116 dsc->td.upper.data, dsc->td.lower.data); 1117 /* Save context and return */ 1118 sc->esc_txctx = dsc->cd; 1119 goto done; 1120 case E1000_TXD_TYP_L: 1121 DPRINTF("tx legacy desc idx %d: %08x%08x", 1122 head, dsc->td.upper.data, dsc->td.lower.data); 1123 /* 1124 * legacy cksum start valid in first descriptor 1125 */ 1126 ntype = dtype; 1127 ckinfo[0].ck_start = dsc->td.upper.fields.css; 1128 break; 1129 case E1000_TXD_TYP_D: 1130 DPRINTF("tx data desc idx %d: %08x%08x", 1131 head, dsc->td.upper.data, dsc->td.lower.data); 1132 ntype = dtype; 1133 break; 1134 default: 1135 break; 1136 } 1137 } else { 1138 /* Descriptor type must be consistent */ 1139 assert(dtype == ntype); 1140 DPRINTF("tx next desc idx %d: %08x%08x", 1141 head, dsc->td.upper.data, dsc->td.lower.data); 1142 } 1143 1144 len = (dtype == E1000_TXD_TYP_L) ? dsc->td.lower.flags.length : 1145 dsc->dd.lower.data & 0xFFFFF; 1146 1147 if (len > 0) { 1148 /* Strip checksum supplied by guest. */ 1149 if ((dsc->td.lower.data & E1000_TXD_CMD_EOP) != 0 && 1150 (dsc->td.lower.data & E1000_TXD_CMD_IFCS) == 0) 1151 len -= 2; 1152 if (iovcnt < I82545_MAX_TXSEGS) { 1153 iov[iovcnt].iov_base = paddr_guest2host( 1154 sc->esc_ctx, dsc->td.buffer_addr, len); 1155 iov[iovcnt].iov_len = len; 1156 } 1157 iovcnt++; 1158 } 1159 1160 /* 1161 * Pull out info that is valid in the final descriptor 1162 * and exit descriptor loop. 1163 */ 1164 if (dsc->td.lower.data & E1000_TXD_CMD_EOP) { 1165 if (dtype == E1000_TXD_TYP_L) { 1166 if (dsc->td.lower.data & E1000_TXD_CMD_IC) { 1167 ckinfo[0].ck_valid = 1; 1168 ckinfo[0].ck_off = 1169 dsc->td.lower.flags.cso; 1170 ckinfo[0].ck_len = 0; 1171 } 1172 } else { 1173 cd = &sc->esc_txctx; 1174 if (dsc->dd.lower.data & E1000_TXD_CMD_TSE) 1175 tso = 1; 1176 if (dsc->dd.upper.fields.popts & 1177 E1000_TXD_POPTS_IXSM) 1178 ckinfo[0].ck_valid = 1; 1179 if (dsc->dd.upper.fields.popts & 1180 E1000_TXD_POPTS_IXSM || tso) { 1181 ckinfo[0].ck_start = 1182 cd->lower_setup.ip_fields.ipcss; 1183 ckinfo[0].ck_off = 1184 cd->lower_setup.ip_fields.ipcso; 1185 ckinfo[0].ck_len = 1186 cd->lower_setup.ip_fields.ipcse; 1187 } 1188 if (dsc->dd.upper.fields.popts & 1189 E1000_TXD_POPTS_TXSM) 1190 ckinfo[1].ck_valid = 1; 1191 if (dsc->dd.upper.fields.popts & 1192 E1000_TXD_POPTS_TXSM || tso) { 1193 ckinfo[1].ck_start = 1194 cd->upper_setup.tcp_fields.tucss; 1195 ckinfo[1].ck_off = 1196 cd->upper_setup.tcp_fields.tucso; 1197 ckinfo[1].ck_len = 1198 cd->upper_setup.tcp_fields.tucse; 1199 } 1200 } 1201 break; 1202 } 1203 } 1204 1205 if (iovcnt > I82545_MAX_TXSEGS) { 1206 WPRINTF("tx too many descriptors (%d > %d) -- dropped", 1207 iovcnt, I82545_MAX_TXSEGS); 1208 goto done; 1209 } 1210 1211 hdrlen = vlen = 0; 1212 /* Estimate writable space for VLAN header insertion. */ 1213 if ((sc->esc_CTRL & E1000_CTRL_VME) && 1214 (dsc->td.lower.data & E1000_TXD_CMD_VLE)) { 1215 hdrlen = ETHER_ADDR_LEN*2; 1216 vlen = ETHER_VLAN_ENCAP_LEN; 1217 } 1218 if (!tso) { 1219 /* Estimate required writable space for checksums. */ 1220 if (ckinfo[0].ck_valid) 1221 hdrlen = MAX(hdrlen, ckinfo[0].ck_off + 2); 1222 if (ckinfo[1].ck_valid) 1223 hdrlen = MAX(hdrlen, ckinfo[1].ck_off + 2); 1224 /* Round up writable space to the first vector. */ 1225 if (hdrlen != 0 && iov[0].iov_len > hdrlen && 1226 iov[0].iov_len < hdrlen + 100) 1227 hdrlen = iov[0].iov_len; 1228 } else { 1229 /* In case of TSO header length provided by software. */ 1230 hdrlen = sc->esc_txctx.tcp_seg_setup.fields.hdr_len; 1231 1232 /* 1233 * Cap the header length at 240 based on 7.2.4.5 of 1234 * the Intel 82576EB (Rev 2.63) datasheet. 1235 */ 1236 if (hdrlen > 240) { 1237 WPRINTF("TSO hdrlen too large: %d", hdrlen); 1238 goto done; 1239 } 1240 1241 /* 1242 * If VLAN insertion is requested, ensure the header 1243 * at least holds the amount of data copied during 1244 * VLAN insertion below. 1245 * 1246 * XXX: Realistic packets will include a full Ethernet 1247 * header before the IP header at ckinfo[0].ck_start, 1248 * but this check is sufficient to prevent 1249 * out-of-bounds access below. 1250 */ 1251 if (vlen != 0 && hdrlen < ETHER_ADDR_LEN*2) { 1252 WPRINTF("TSO hdrlen too small for vlan insertion " 1253 "(%d vs %d) -- dropped", hdrlen, 1254 ETHER_ADDR_LEN*2); 1255 goto done; 1256 } 1257 1258 /* 1259 * Ensure that the header length covers the used fields 1260 * in the IP and TCP headers as well as the IP and TCP 1261 * checksums. The following fields are accessed below: 1262 * 1263 * Header | Field | Offset | Length 1264 * -------+-------+--------+------- 1265 * IPv4 | len | 2 | 2 1266 * IPv4 | ID | 4 | 2 1267 * IPv6 | len | 4 | 2 1268 * TCP | seq # | 4 | 4 1269 * TCP | flags | 13 | 1 1270 * UDP | len | 4 | 4 1271 */ 1272 if (hdrlen < ckinfo[0].ck_start + 6 || 1273 hdrlen < ckinfo[0].ck_off + 2) { 1274 WPRINTF("TSO hdrlen too small for IP fields (%d) " 1275 "-- dropped", hdrlen); 1276 goto done; 1277 } 1278 if (sc->esc_txctx.cmd_and_length & E1000_TXD_CMD_TCP) { 1279 if (hdrlen < ckinfo[1].ck_start + 14) { 1280 WPRINTF("TSO hdrlen too small for TCP fields " 1281 "(%d) -- dropped", hdrlen); 1282 goto done; 1283 } 1284 } else { 1285 if (hdrlen < ckinfo[1].ck_start + 8) { 1286 WPRINTF("TSO hdrlen too small for UDP fields " 1287 "(%d) -- dropped", hdrlen); 1288 goto done; 1289 } 1290 } 1291 if (ckinfo[1].ck_valid && hdrlen < ckinfo[1].ck_off + 2) { 1292 WPRINTF("TSO hdrlen too small for TCP/UDP fields " 1293 "(%d) -- dropped", hdrlen); 1294 goto done; 1295 } 1296 } 1297 1298 /* Allocate, fill and prepend writable header vector. */ 1299 if (hdrlen != 0) { 1300 hdr = __builtin_alloca(hdrlen + vlen); 1301 hdr += vlen; 1302 for (left = hdrlen, hdrp = hdr; left > 0; 1303 left -= now, hdrp += now) { 1304 now = MIN(left, iov->iov_len); 1305 memcpy(hdrp, iov->iov_base, now); 1306 iov->iov_base += now; 1307 iov->iov_len -= now; 1308 if (iov->iov_len == 0) { 1309 iov++; 1310 iovcnt--; 1311 } 1312 } 1313 iov--; 1314 iovcnt++; 1315 iov->iov_base = hdr; 1316 iov->iov_len = hdrlen; 1317 } else 1318 hdr = NULL; 1319 1320 /* Insert VLAN tag. */ 1321 if (vlen != 0) { 1322 hdr -= ETHER_VLAN_ENCAP_LEN; 1323 memmove(hdr, hdr + ETHER_VLAN_ENCAP_LEN, ETHER_ADDR_LEN*2); 1324 hdrlen += ETHER_VLAN_ENCAP_LEN; 1325 hdr[ETHER_ADDR_LEN*2 + 0] = sc->esc_VET >> 8; 1326 hdr[ETHER_ADDR_LEN*2 + 1] = sc->esc_VET & 0xff; 1327 hdr[ETHER_ADDR_LEN*2 + 2] = dsc->td.upper.fields.special >> 8; 1328 hdr[ETHER_ADDR_LEN*2 + 3] = dsc->td.upper.fields.special & 0xff; 1329 iov->iov_base = hdr; 1330 iov->iov_len += ETHER_VLAN_ENCAP_LEN; 1331 /* Correct checksum offsets after VLAN tag insertion. */ 1332 ckinfo[0].ck_start += ETHER_VLAN_ENCAP_LEN; 1333 ckinfo[0].ck_off += ETHER_VLAN_ENCAP_LEN; 1334 if (ckinfo[0].ck_len != 0) 1335 ckinfo[0].ck_len += ETHER_VLAN_ENCAP_LEN; 1336 ckinfo[1].ck_start += ETHER_VLAN_ENCAP_LEN; 1337 ckinfo[1].ck_off += ETHER_VLAN_ENCAP_LEN; 1338 if (ckinfo[1].ck_len != 0) 1339 ckinfo[1].ck_len += ETHER_VLAN_ENCAP_LEN; 1340 } 1341 1342 /* Simple non-TSO case. */ 1343 if (!tso) { 1344 /* Calculate checksums and transmit. */ 1345 if (ckinfo[0].ck_valid) 1346 e82545_transmit_checksum(iov, iovcnt, &ckinfo[0]); 1347 if (ckinfo[1].ck_valid) 1348 e82545_transmit_checksum(iov, iovcnt, &ckinfo[1]); 1349 e82545_transmit_backend(sc, iov, iovcnt); 1350 goto done; 1351 } 1352 1353 /* Doing TSO. */ 1354 tcp = (sc->esc_txctx.cmd_and_length & E1000_TXD_CMD_TCP) != 0; 1355 mss = sc->esc_txctx.tcp_seg_setup.fields.mss; 1356 paylen = (sc->esc_txctx.cmd_and_length & 0x000fffff); 1357 DPRINTF("tx %s segmentation offload %d+%d/%d bytes %d iovs", 1358 tcp ? "TCP" : "UDP", hdrlen, paylen, mss, iovcnt); 1359 ipid = ntohs(*(uint16_t *)&hdr[ckinfo[0].ck_start + 4]); 1360 tcpseq = 0; 1361 if (tcp) 1362 tcpseq = ntohl(*(uint32_t *)&hdr[ckinfo[1].ck_start + 4]); 1363 ipcs = *(uint16_t *)&hdr[ckinfo[0].ck_off]; 1364 tcpcs = 0; 1365 if (ckinfo[1].ck_valid) /* Save partial pseudo-header checksum. */ 1366 tcpcs = *(uint16_t *)&hdr[ckinfo[1].ck_off]; 1367 pv = 1; 1368 pvoff = 0; 1369 for (seg = 0, left = paylen; left > 0; seg++, left -= now) { 1370 now = MIN(left, mss); 1371 1372 /* Construct IOVs for the segment. */ 1373 /* Include whole original header. */ 1374 tiov[0].iov_base = hdr; 1375 tiov[0].iov_len = hdrlen; 1376 tiovcnt = 1; 1377 /* Include respective part of payload IOV. */ 1378 for (nleft = now; pv < iovcnt && nleft > 0; nleft -= nnow) { 1379 nnow = MIN(nleft, iov[pv].iov_len - pvoff); 1380 tiov[tiovcnt].iov_base = iov[pv].iov_base + pvoff; 1381 tiov[tiovcnt++].iov_len = nnow; 1382 if (pvoff + nnow == iov[pv].iov_len) { 1383 pv++; 1384 pvoff = 0; 1385 } else 1386 pvoff += nnow; 1387 } 1388 DPRINTF("tx segment %d %d+%d bytes %d iovs", 1389 seg, hdrlen, now, tiovcnt); 1390 1391 /* Update IP header. */ 1392 if (sc->esc_txctx.cmd_and_length & E1000_TXD_CMD_IP) { 1393 /* IPv4 -- set length and ID */ 1394 *(uint16_t *)&hdr[ckinfo[0].ck_start + 2] = 1395 htons(hdrlen - ckinfo[0].ck_start + now); 1396 *(uint16_t *)&hdr[ckinfo[0].ck_start + 4] = 1397 htons(ipid + seg); 1398 } else { 1399 /* IPv6 -- set length */ 1400 *(uint16_t *)&hdr[ckinfo[0].ck_start + 4] = 1401 htons(hdrlen - ckinfo[0].ck_start - 40 + 1402 now); 1403 } 1404 1405 /* Update pseudo-header checksum. */ 1406 tcpsum = tcpcs; 1407 tcpsum += htons(hdrlen - ckinfo[1].ck_start + now); 1408 1409 /* Update TCP/UDP headers. */ 1410 if (tcp) { 1411 /* Update sequence number and FIN/PUSH flags. */ 1412 *(uint32_t *)&hdr[ckinfo[1].ck_start + 4] = 1413 htonl(tcpseq + paylen - left); 1414 if (now < left) { 1415 hdr[ckinfo[1].ck_start + 13] &= 1416 ~(TH_FIN | TH_PUSH); 1417 } 1418 } else { 1419 /* Update payload length. */ 1420 *(uint32_t *)&hdr[ckinfo[1].ck_start + 4] = 1421 hdrlen - ckinfo[1].ck_start + now; 1422 } 1423 1424 /* Calculate checksums and transmit. */ 1425 if (ckinfo[0].ck_valid) { 1426 *(uint16_t *)&hdr[ckinfo[0].ck_off] = ipcs; 1427 e82545_transmit_checksum(tiov, tiovcnt, &ckinfo[0]); 1428 } 1429 if (ckinfo[1].ck_valid) { 1430 *(uint16_t *)&hdr[ckinfo[1].ck_off] = 1431 e82545_carry(tcpsum); 1432 e82545_transmit_checksum(tiov, tiovcnt, &ckinfo[1]); 1433 } 1434 e82545_transmit_backend(sc, tiov, tiovcnt); 1435 } 1436 1437 done: 1438 head = (head + 1) % dsize; 1439 e82545_transmit_done(sc, ohead, head, dsize, tdwb); 1440 1441 *rhead = head; 1442 return (desc + 1); 1443 } 1444 1445 static void 1446 e82545_tx_run(struct e82545_softc *sc) 1447 { 1448 uint32_t cause; 1449 uint16_t head, rhead, tail, size; 1450 int lim, tdwb, sent; 1451 1452 head = sc->esc_TDH; 1453 tail = sc->esc_TDT; 1454 size = sc->esc_TDLEN / 16; 1455 DPRINTF("tx_run: head %x, rhead %x, tail %x", 1456 sc->esc_TDH, sc->esc_TDHr, sc->esc_TDT); 1457 1458 pthread_mutex_unlock(&sc->esc_mtx); 1459 rhead = head; 1460 tdwb = 0; 1461 for (lim = size / 4; sc->esc_tx_enabled && lim > 0; lim -= sent) { 1462 sent = e82545_transmit(sc, head, tail, size, &rhead, &tdwb); 1463 if (sent == 0) 1464 break; 1465 head = rhead; 1466 } 1467 pthread_mutex_lock(&sc->esc_mtx); 1468 1469 sc->esc_TDH = head; 1470 sc->esc_TDHr = rhead; 1471 cause = 0; 1472 if (tdwb) 1473 cause |= E1000_ICR_TXDW; 1474 if (lim != size / 4 && sc->esc_TDH == sc->esc_TDT) 1475 cause |= E1000_ICR_TXQE; 1476 if (cause) 1477 e82545_icr_assert(sc, cause); 1478 1479 DPRINTF("tx_run done: head %x, rhead %x, tail %x", 1480 sc->esc_TDH, sc->esc_TDHr, sc->esc_TDT); 1481 } 1482 1483 static _Noreturn void * 1484 e82545_tx_thread(void *param) 1485 { 1486 struct e82545_softc *sc = param; 1487 1488 pthread_mutex_lock(&sc->esc_mtx); 1489 for (;;) { 1490 while (!sc->esc_tx_enabled || sc->esc_TDHr == sc->esc_TDT) { 1491 if (sc->esc_tx_enabled && sc->esc_TDHr != sc->esc_TDT) 1492 break; 1493 sc->esc_tx_active = 0; 1494 if (sc->esc_tx_enabled == 0) 1495 pthread_cond_signal(&sc->esc_tx_cond); 1496 pthread_cond_wait(&sc->esc_tx_cond, &sc->esc_mtx); 1497 } 1498 sc->esc_tx_active = 1; 1499 1500 /* Process some tx descriptors. Lock dropped inside. */ 1501 e82545_tx_run(sc); 1502 } 1503 } 1504 1505 static void 1506 e82545_tx_start(struct e82545_softc *sc) 1507 { 1508 1509 if (sc->esc_tx_active == 0) 1510 pthread_cond_signal(&sc->esc_tx_cond); 1511 } 1512 1513 static void 1514 e82545_tx_enable(struct e82545_softc *sc) 1515 { 1516 1517 sc->esc_tx_enabled = 1; 1518 } 1519 1520 static void 1521 e82545_tx_disable(struct e82545_softc *sc) 1522 { 1523 1524 sc->esc_tx_enabled = 0; 1525 while (sc->esc_tx_active) 1526 pthread_cond_wait(&sc->esc_tx_cond, &sc->esc_mtx); 1527 } 1528 1529 static void 1530 e82545_rx_enable(struct e82545_softc *sc) 1531 { 1532 1533 sc->esc_rx_enabled = 1; 1534 } 1535 1536 static void 1537 e82545_rx_disable(struct e82545_softc *sc) 1538 { 1539 1540 sc->esc_rx_enabled = 0; 1541 while (sc->esc_rx_active) 1542 pthread_cond_wait(&sc->esc_rx_cond, &sc->esc_mtx); 1543 } 1544 1545 static void 1546 e82545_write_ra(struct e82545_softc *sc, int reg, uint32_t wval) 1547 { 1548 struct eth_uni *eu; 1549 int idx; 1550 1551 idx = reg >> 1; 1552 assert(idx < 15); 1553 1554 eu = &sc->esc_uni[idx]; 1555 1556 if (reg & 0x1) { 1557 /* RAH */ 1558 eu->eu_valid = ((wval & E1000_RAH_AV) == E1000_RAH_AV); 1559 eu->eu_addrsel = (wval >> 16) & 0x3; 1560 eu->eu_eth.octet[5] = wval >> 8; 1561 eu->eu_eth.octet[4] = wval; 1562 } else { 1563 /* RAL */ 1564 eu->eu_eth.octet[3] = wval >> 24; 1565 eu->eu_eth.octet[2] = wval >> 16; 1566 eu->eu_eth.octet[1] = wval >> 8; 1567 eu->eu_eth.octet[0] = wval; 1568 } 1569 } 1570 1571 static uint32_t 1572 e82545_read_ra(struct e82545_softc *sc, int reg) 1573 { 1574 struct eth_uni *eu; 1575 uint32_t retval; 1576 int idx; 1577 1578 idx = reg >> 1; 1579 assert(idx < 15); 1580 1581 eu = &sc->esc_uni[idx]; 1582 1583 if (reg & 0x1) { 1584 /* RAH */ 1585 retval = (eu->eu_valid << 31) | 1586 (eu->eu_addrsel << 16) | 1587 (eu->eu_eth.octet[5] << 8) | 1588 eu->eu_eth.octet[4]; 1589 } else { 1590 /* RAL */ 1591 retval = (eu->eu_eth.octet[3] << 24) | 1592 (eu->eu_eth.octet[2] << 16) | 1593 (eu->eu_eth.octet[1] << 8) | 1594 eu->eu_eth.octet[0]; 1595 } 1596 1597 return (retval); 1598 } 1599 1600 static void 1601 e82545_write_register(struct e82545_softc *sc, uint32_t offset, uint32_t value) 1602 { 1603 int ridx; 1604 1605 if (offset & 0x3) { 1606 DPRINTF("Unaligned register write offset:0x%x value:0x%x", offset, value); 1607 return; 1608 } 1609 DPRINTF("Register write: 0x%x value: 0x%x", offset, value); 1610 1611 switch (offset) { 1612 case E1000_CTRL: 1613 case E1000_CTRL_DUP: 1614 e82545_devctl(sc, value); 1615 break; 1616 case E1000_FCAL: 1617 sc->esc_FCAL = value; 1618 break; 1619 case E1000_FCAH: 1620 sc->esc_FCAH = value & ~0xFFFF0000; 1621 break; 1622 case E1000_FCT: 1623 sc->esc_FCT = value & ~0xFFFF0000; 1624 break; 1625 case E1000_VET: 1626 sc->esc_VET = value & ~0xFFFF0000; 1627 break; 1628 case E1000_FCTTV: 1629 sc->esc_FCTTV = value & ~0xFFFF0000; 1630 break; 1631 case E1000_LEDCTL: 1632 sc->esc_LEDCTL = value & ~0x30303000; 1633 break; 1634 case E1000_PBA: 1635 sc->esc_PBA = value & 0x0000FF80; 1636 break; 1637 case E1000_ICR: 1638 case E1000_ITR: 1639 case E1000_ICS: 1640 case E1000_IMS: 1641 case E1000_IMC: 1642 e82545_intr_write(sc, offset, value); 1643 break; 1644 case E1000_RCTL: 1645 e82545_rx_ctl(sc, value); 1646 break; 1647 case E1000_FCRTL: 1648 sc->esc_FCRTL = value & ~0xFFFF0007; 1649 break; 1650 case E1000_FCRTH: 1651 sc->esc_FCRTH = value & ~0xFFFF0007; 1652 break; 1653 case E1000_RDBAL(0): 1654 sc->esc_RDBAL = value & ~0xF; 1655 if (sc->esc_rx_enabled) { 1656 /* Apparently legal: update cached address */ 1657 e82545_rx_update_rdba(sc); 1658 } 1659 break; 1660 case E1000_RDBAH(0): 1661 assert(!sc->esc_rx_enabled); 1662 sc->esc_RDBAH = value; 1663 break; 1664 case E1000_RDLEN(0): 1665 assert(!sc->esc_rx_enabled); 1666 sc->esc_RDLEN = value & ~0xFFF0007F; 1667 break; 1668 case E1000_RDH(0): 1669 /* XXX should only ever be zero ? Range check ? */ 1670 sc->esc_RDH = value; 1671 break; 1672 case E1000_RDT(0): 1673 /* XXX if this opens up the rx ring, do something ? */ 1674 sc->esc_RDT = value; 1675 break; 1676 case E1000_RDTR: 1677 /* ignore FPD bit 31 */ 1678 sc->esc_RDTR = value & ~0xFFFF0000; 1679 break; 1680 case E1000_RXDCTL(0): 1681 sc->esc_RXDCTL = value & ~0xFEC0C0C0; 1682 break; 1683 case E1000_RADV: 1684 sc->esc_RADV = value & ~0xFFFF0000; 1685 break; 1686 case E1000_RSRPD: 1687 sc->esc_RSRPD = value & ~0xFFFFF000; 1688 break; 1689 case E1000_RXCSUM: 1690 sc->esc_RXCSUM = value & ~0xFFFFF800; 1691 break; 1692 case E1000_TXCW: 1693 sc->esc_TXCW = value & ~0x3FFF0000; 1694 break; 1695 case E1000_TCTL: 1696 e82545_tx_ctl(sc, value); 1697 break; 1698 case E1000_TIPG: 1699 sc->esc_TIPG = value; 1700 break; 1701 case E1000_AIT: 1702 sc->esc_AIT = value; 1703 break; 1704 case E1000_TDBAL(0): 1705 sc->esc_TDBAL = value & ~0xF; 1706 if (sc->esc_tx_enabled) 1707 e82545_tx_update_tdba(sc); 1708 break; 1709 case E1000_TDBAH(0): 1710 sc->esc_TDBAH = value; 1711 if (sc->esc_tx_enabled) 1712 e82545_tx_update_tdba(sc); 1713 break; 1714 case E1000_TDLEN(0): 1715 sc->esc_TDLEN = value & ~0xFFF0007F; 1716 if (sc->esc_tx_enabled) 1717 e82545_tx_update_tdba(sc); 1718 break; 1719 case E1000_TDH(0): 1720 //assert(!sc->esc_tx_enabled); 1721 /* XXX should only ever be zero ? Range check ? */ 1722 sc->esc_TDHr = sc->esc_TDH = value; 1723 break; 1724 case E1000_TDT(0): 1725 /* XXX range check ? */ 1726 sc->esc_TDT = value; 1727 if (sc->esc_tx_enabled) 1728 e82545_tx_start(sc); 1729 break; 1730 case E1000_TIDV: 1731 sc->esc_TIDV = value & ~0xFFFF0000; 1732 break; 1733 case E1000_TXDCTL(0): 1734 //assert(!sc->esc_tx_enabled); 1735 sc->esc_TXDCTL = value & ~0xC0C0C0; 1736 break; 1737 case E1000_TADV: 1738 sc->esc_TADV = value & ~0xFFFF0000; 1739 break; 1740 case E1000_RAL(0) ... E1000_RAH(15): 1741 /* convert to u32 offset */ 1742 ridx = (offset - E1000_RAL(0)) >> 2; 1743 e82545_write_ra(sc, ridx, value); 1744 break; 1745 case E1000_MTA ... (E1000_MTA + (127*4)): 1746 sc->esc_fmcast[(offset - E1000_MTA) >> 2] = value; 1747 break; 1748 case E1000_VFTA ... (E1000_VFTA + (127*4)): 1749 sc->esc_fvlan[(offset - E1000_VFTA) >> 2] = value; 1750 break; 1751 case E1000_EECD: 1752 { 1753 //DPRINTF("EECD write 0x%x -> 0x%x", sc->eeprom_control, value); 1754 /* edge triggered low->high */ 1755 uint32_t eecd_strobe = ((sc->eeprom_control & E1000_EECD_SK) ? 1756 0 : (value & E1000_EECD_SK)); 1757 uint32_t eecd_mask = (E1000_EECD_SK|E1000_EECD_CS| 1758 E1000_EECD_DI|E1000_EECD_REQ); 1759 sc->eeprom_control &= ~eecd_mask; 1760 sc->eeprom_control |= (value & eecd_mask); 1761 /* grant/revoke immediately */ 1762 if (value & E1000_EECD_REQ) { 1763 sc->eeprom_control |= E1000_EECD_GNT; 1764 } else { 1765 sc->eeprom_control &= ~E1000_EECD_GNT; 1766 } 1767 if (eecd_strobe && (sc->eeprom_control & E1000_EECD_CS)) { 1768 e82545_eecd_strobe(sc); 1769 } 1770 return; 1771 } 1772 case E1000_MDIC: 1773 { 1774 uint8_t reg_addr = (uint8_t)((value & E1000_MDIC_REG_MASK) >> 1775 E1000_MDIC_REG_SHIFT); 1776 uint8_t phy_addr = (uint8_t)((value & E1000_MDIC_PHY_MASK) >> 1777 E1000_MDIC_PHY_SHIFT); 1778 sc->mdi_control = 1779 (value & ~(E1000_MDIC_ERROR|E1000_MDIC_DEST)); 1780 if ((value & E1000_MDIC_READY) != 0) { 1781 DPRINTF("Incorrect MDIC ready bit: 0x%x", value); 1782 return; 1783 } 1784 switch (value & E82545_MDIC_OP_MASK) { 1785 case E1000_MDIC_OP_READ: 1786 sc->mdi_control &= ~E82545_MDIC_DATA_MASK; 1787 sc->mdi_control |= e82545_read_mdi(sc, reg_addr, phy_addr); 1788 break; 1789 case E1000_MDIC_OP_WRITE: 1790 e82545_write_mdi(sc, reg_addr, phy_addr, 1791 value & E82545_MDIC_DATA_MASK); 1792 break; 1793 default: 1794 DPRINTF("Unknown MDIC op: 0x%x", value); 1795 return; 1796 } 1797 /* TODO: barrier? */ 1798 sc->mdi_control |= E1000_MDIC_READY; 1799 if (value & E82545_MDIC_IE) { 1800 // TODO: generate interrupt 1801 } 1802 return; 1803 } 1804 case E1000_MANC: 1805 case E1000_STATUS: 1806 return; 1807 default: 1808 DPRINTF("Unknown write register: 0x%x value:%x", offset, value); 1809 return; 1810 } 1811 } 1812 1813 static uint32_t 1814 e82545_read_register(struct e82545_softc *sc, uint32_t offset) 1815 { 1816 uint32_t retval; 1817 int ridx; 1818 1819 if (offset & 0x3) { 1820 DPRINTF("Unaligned register read offset:0x%x", offset); 1821 return 0; 1822 } 1823 1824 DPRINTF("Register read: 0x%x", offset); 1825 1826 switch (offset) { 1827 case E1000_CTRL: 1828 retval = sc->esc_CTRL; 1829 break; 1830 case E1000_STATUS: 1831 retval = E1000_STATUS_FD | E1000_STATUS_LU | 1832 E1000_STATUS_SPEED_1000; 1833 break; 1834 case E1000_FCAL: 1835 retval = sc->esc_FCAL; 1836 break; 1837 case E1000_FCAH: 1838 retval = sc->esc_FCAH; 1839 break; 1840 case E1000_FCT: 1841 retval = sc->esc_FCT; 1842 break; 1843 case E1000_VET: 1844 retval = sc->esc_VET; 1845 break; 1846 case E1000_FCTTV: 1847 retval = sc->esc_FCTTV; 1848 break; 1849 case E1000_LEDCTL: 1850 retval = sc->esc_LEDCTL; 1851 break; 1852 case E1000_PBA: 1853 retval = sc->esc_PBA; 1854 break; 1855 case E1000_ICR: 1856 case E1000_ITR: 1857 case E1000_ICS: 1858 case E1000_IMS: 1859 case E1000_IMC: 1860 retval = e82545_intr_read(sc, offset); 1861 break; 1862 case E1000_RCTL: 1863 retval = sc->esc_RCTL; 1864 break; 1865 case E1000_FCRTL: 1866 retval = sc->esc_FCRTL; 1867 break; 1868 case E1000_FCRTH: 1869 retval = sc->esc_FCRTH; 1870 break; 1871 case E1000_RDBAL(0): 1872 retval = sc->esc_RDBAL; 1873 break; 1874 case E1000_RDBAH(0): 1875 retval = sc->esc_RDBAH; 1876 break; 1877 case E1000_RDLEN(0): 1878 retval = sc->esc_RDLEN; 1879 break; 1880 case E1000_RDH(0): 1881 retval = sc->esc_RDH; 1882 break; 1883 case E1000_RDT(0): 1884 retval = sc->esc_RDT; 1885 break; 1886 case E1000_RDTR: 1887 retval = sc->esc_RDTR; 1888 break; 1889 case E1000_RXDCTL(0): 1890 retval = sc->esc_RXDCTL; 1891 break; 1892 case E1000_RADV: 1893 retval = sc->esc_RADV; 1894 break; 1895 case E1000_RSRPD: 1896 retval = sc->esc_RSRPD; 1897 break; 1898 case E1000_RXCSUM: 1899 retval = sc->esc_RXCSUM; 1900 break; 1901 case E1000_TXCW: 1902 retval = sc->esc_TXCW; 1903 break; 1904 case E1000_TCTL: 1905 retval = sc->esc_TCTL; 1906 break; 1907 case E1000_TIPG: 1908 retval = sc->esc_TIPG; 1909 break; 1910 case E1000_AIT: 1911 retval = sc->esc_AIT; 1912 break; 1913 case E1000_TDBAL(0): 1914 retval = sc->esc_TDBAL; 1915 break; 1916 case E1000_TDBAH(0): 1917 retval = sc->esc_TDBAH; 1918 break; 1919 case E1000_TDLEN(0): 1920 retval = sc->esc_TDLEN; 1921 break; 1922 case E1000_TDH(0): 1923 retval = sc->esc_TDH; 1924 break; 1925 case E1000_TDT(0): 1926 retval = sc->esc_TDT; 1927 break; 1928 case E1000_TIDV: 1929 retval = sc->esc_TIDV; 1930 break; 1931 case E1000_TXDCTL(0): 1932 retval = sc->esc_TXDCTL; 1933 break; 1934 case E1000_TADV: 1935 retval = sc->esc_TADV; 1936 break; 1937 case E1000_RAL(0) ... E1000_RAH(15): 1938 /* convert to u32 offset */ 1939 ridx = (offset - E1000_RAL(0)) >> 2; 1940 retval = e82545_read_ra(sc, ridx); 1941 break; 1942 case E1000_MTA ... (E1000_MTA + (127*4)): 1943 retval = sc->esc_fmcast[(offset - E1000_MTA) >> 2]; 1944 break; 1945 case E1000_VFTA ... (E1000_VFTA + (127*4)): 1946 retval = sc->esc_fvlan[(offset - E1000_VFTA) >> 2]; 1947 break; 1948 case E1000_EECD: 1949 //DPRINTF("EECD read %x", sc->eeprom_control); 1950 retval = sc->eeprom_control; 1951 break; 1952 case E1000_MDIC: 1953 retval = sc->mdi_control; 1954 break; 1955 case E1000_MANC: 1956 retval = 0; 1957 break; 1958 /* stats that we emulate. */ 1959 case E1000_MPC: 1960 retval = sc->missed_pkt_count; 1961 break; 1962 case E1000_PRC64: 1963 retval = sc->pkt_rx_by_size[0]; 1964 break; 1965 case E1000_PRC127: 1966 retval = sc->pkt_rx_by_size[1]; 1967 break; 1968 case E1000_PRC255: 1969 retval = sc->pkt_rx_by_size[2]; 1970 break; 1971 case E1000_PRC511: 1972 retval = sc->pkt_rx_by_size[3]; 1973 break; 1974 case E1000_PRC1023: 1975 retval = sc->pkt_rx_by_size[4]; 1976 break; 1977 case E1000_PRC1522: 1978 retval = sc->pkt_rx_by_size[5]; 1979 break; 1980 case E1000_GPRC: 1981 retval = sc->good_pkt_rx_count; 1982 break; 1983 case E1000_BPRC: 1984 retval = sc->bcast_pkt_rx_count; 1985 break; 1986 case E1000_MPRC: 1987 retval = sc->mcast_pkt_rx_count; 1988 break; 1989 case E1000_GPTC: 1990 case E1000_TPT: 1991 retval = sc->good_pkt_tx_count; 1992 break; 1993 case E1000_GORCL: 1994 retval = (uint32_t)sc->good_octets_rx; 1995 break; 1996 case E1000_GORCH: 1997 retval = (uint32_t)(sc->good_octets_rx >> 32); 1998 break; 1999 case E1000_TOTL: 2000 case E1000_GOTCL: 2001 retval = (uint32_t)sc->good_octets_tx; 2002 break; 2003 case E1000_TOTH: 2004 case E1000_GOTCH: 2005 retval = (uint32_t)(sc->good_octets_tx >> 32); 2006 break; 2007 case E1000_ROC: 2008 retval = sc->oversize_rx_count; 2009 break; 2010 case E1000_TORL: 2011 retval = (uint32_t)(sc->good_octets_rx + sc->missed_octets); 2012 break; 2013 case E1000_TORH: 2014 retval = (uint32_t)((sc->good_octets_rx + 2015 sc->missed_octets) >> 32); 2016 break; 2017 case E1000_TPR: 2018 retval = sc->good_pkt_rx_count + sc->missed_pkt_count + 2019 sc->oversize_rx_count; 2020 break; 2021 case E1000_PTC64: 2022 retval = sc->pkt_tx_by_size[0]; 2023 break; 2024 case E1000_PTC127: 2025 retval = sc->pkt_tx_by_size[1]; 2026 break; 2027 case E1000_PTC255: 2028 retval = sc->pkt_tx_by_size[2]; 2029 break; 2030 case E1000_PTC511: 2031 retval = sc->pkt_tx_by_size[3]; 2032 break; 2033 case E1000_PTC1023: 2034 retval = sc->pkt_tx_by_size[4]; 2035 break; 2036 case E1000_PTC1522: 2037 retval = sc->pkt_tx_by_size[5]; 2038 break; 2039 case E1000_MPTC: 2040 retval = sc->mcast_pkt_tx_count; 2041 break; 2042 case E1000_BPTC: 2043 retval = sc->bcast_pkt_tx_count; 2044 break; 2045 case E1000_TSCTC: 2046 retval = sc->tso_tx_count; 2047 break; 2048 /* stats that are always 0. */ 2049 case E1000_CRCERRS: 2050 case E1000_ALGNERRC: 2051 case E1000_SYMERRS: 2052 case E1000_RXERRC: 2053 case E1000_SCC: 2054 case E1000_ECOL: 2055 case E1000_MCC: 2056 case E1000_LATECOL: 2057 case E1000_COLC: 2058 case E1000_DC: 2059 case E1000_TNCRS: 2060 case E1000_SEC: 2061 case E1000_CEXTERR: 2062 case E1000_RLEC: 2063 case E1000_XONRXC: 2064 case E1000_XONTXC: 2065 case E1000_XOFFRXC: 2066 case E1000_XOFFTXC: 2067 case E1000_FCRUC: 2068 case E1000_RNBC: 2069 case E1000_RUC: 2070 case E1000_RFC: 2071 case E1000_RJC: 2072 case E1000_MGTPRC: 2073 case E1000_MGTPDC: 2074 case E1000_MGTPTC: 2075 case E1000_TSCTFC: 2076 retval = 0; 2077 break; 2078 default: 2079 DPRINTF("Unknown read register: 0x%x", offset); 2080 retval = 0; 2081 break; 2082 } 2083 2084 return (retval); 2085 } 2086 2087 static void 2088 e82545_write(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, int baridx, 2089 uint64_t offset, int size, uint64_t value) 2090 { 2091 struct e82545_softc *sc; 2092 2093 //DPRINTF("Write bar:%d offset:0x%lx value:0x%lx size:%d", baridx, offset, value, size); 2094 2095 sc = pi->pi_arg; 2096 2097 pthread_mutex_lock(&sc->esc_mtx); 2098 2099 switch (baridx) { 2100 case E82545_BAR_IO: 2101 switch (offset) { 2102 case E82545_IOADDR: 2103 if (size != 4) { 2104 DPRINTF("Wrong io addr write sz:%d value:0x%lx", size, value); 2105 } else 2106 sc->io_addr = (uint32_t)value; 2107 break; 2108 case E82545_IODATA: 2109 if (size != 4) { 2110 DPRINTF("Wrong io data write size:%d value:0x%lx", size, value); 2111 } else if (sc->io_addr > E82545_IO_REGISTER_MAX) { 2112 DPRINTF("Non-register io write addr:0x%x value:0x%lx", sc->io_addr, value); 2113 } else 2114 e82545_write_register(sc, sc->io_addr, 2115 (uint32_t)value); 2116 break; 2117 default: 2118 DPRINTF("Unknown io bar write offset:0x%lx value:0x%lx size:%d", offset, value, size); 2119 break; 2120 } 2121 break; 2122 case E82545_BAR_REGISTER: 2123 if (size != 4) { 2124 DPRINTF("Wrong register write size:%d offset:0x%lx value:0x%lx", size, offset, value); 2125 } else 2126 e82545_write_register(sc, (uint32_t)offset, 2127 (uint32_t)value); 2128 break; 2129 default: 2130 DPRINTF("Unknown write bar:%d off:0x%lx val:0x%lx size:%d", 2131 baridx, offset, value, size); 2132 } 2133 2134 pthread_mutex_unlock(&sc->esc_mtx); 2135 } 2136 2137 static uint64_t 2138 e82545_read(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, int baridx, 2139 uint64_t offset, int size) 2140 { 2141 struct e82545_softc *sc; 2142 uint64_t retval; 2143 2144 //DPRINTF("Read bar:%d offset:0x%lx size:%d", baridx, offset, size); 2145 sc = pi->pi_arg; 2146 retval = 0; 2147 2148 pthread_mutex_lock(&sc->esc_mtx); 2149 2150 switch (baridx) { 2151 case E82545_BAR_IO: 2152 switch (offset) { 2153 case E82545_IOADDR: 2154 if (size != 4) { 2155 DPRINTF("Wrong io addr read sz:%d", size); 2156 } else 2157 retval = sc->io_addr; 2158 break; 2159 case E82545_IODATA: 2160 if (size != 4) { 2161 DPRINTF("Wrong io data read sz:%d", size); 2162 } 2163 if (sc->io_addr > E82545_IO_REGISTER_MAX) { 2164 DPRINTF("Non-register io read addr:0x%x", 2165 sc->io_addr); 2166 } else 2167 retval = e82545_read_register(sc, sc->io_addr); 2168 break; 2169 default: 2170 DPRINTF("Unknown io bar read offset:0x%lx size:%d", 2171 offset, size); 2172 break; 2173 } 2174 break; 2175 case E82545_BAR_REGISTER: 2176 if (size != 4) { 2177 DPRINTF("Wrong register read size:%d offset:0x%lx", 2178 size, offset); 2179 } else 2180 retval = e82545_read_register(sc, (uint32_t)offset); 2181 break; 2182 default: 2183 DPRINTF("Unknown read bar:%d offset:0x%lx size:%d", 2184 baridx, offset, size); 2185 break; 2186 } 2187 2188 pthread_mutex_unlock(&sc->esc_mtx); 2189 2190 return (retval); 2191 } 2192 2193 static void 2194 e82545_reset(struct e82545_softc *sc, int drvr) 2195 { 2196 int i; 2197 2198 e82545_rx_disable(sc); 2199 e82545_tx_disable(sc); 2200 2201 /* clear outstanding interrupts */ 2202 if (sc->esc_irq_asserted) 2203 pci_lintr_deassert(sc->esc_pi); 2204 2205 /* misc */ 2206 if (!drvr) { 2207 sc->esc_FCAL = 0; 2208 sc->esc_FCAH = 0; 2209 sc->esc_FCT = 0; 2210 sc->esc_VET = 0; 2211 sc->esc_FCTTV = 0; 2212 } 2213 sc->esc_LEDCTL = 0x07061302; 2214 sc->esc_PBA = 0x00100030; 2215 2216 /* start nvm in opcode mode. */ 2217 sc->nvm_opaddr = 0; 2218 sc->nvm_mode = E82545_NVM_MODE_OPADDR; 2219 sc->nvm_bits = E82545_NVM_OPADDR_BITS; 2220 sc->eeprom_control = E1000_EECD_PRES | E82545_EECD_FWE_EN; 2221 e82545_init_eeprom(sc); 2222 2223 /* interrupt */ 2224 sc->esc_ICR = 0; 2225 sc->esc_ITR = 250; 2226 sc->esc_ICS = 0; 2227 sc->esc_IMS = 0; 2228 sc->esc_IMC = 0; 2229 2230 /* L2 filters */ 2231 if (!drvr) { 2232 memset(sc->esc_fvlan, 0, sizeof(sc->esc_fvlan)); 2233 memset(sc->esc_fmcast, 0, sizeof(sc->esc_fmcast)); 2234 memset(sc->esc_uni, 0, sizeof(sc->esc_uni)); 2235 2236 /* XXX not necessary on 82545 ?? */ 2237 sc->esc_uni[0].eu_valid = 1; 2238 memcpy(sc->esc_uni[0].eu_eth.octet, sc->esc_mac.octet, 2239 ETHER_ADDR_LEN); 2240 } else { 2241 /* Clear RAH valid bits */ 2242 for (i = 0; i < 16; i++) 2243 sc->esc_uni[i].eu_valid = 0; 2244 } 2245 2246 /* receive */ 2247 if (!drvr) { 2248 sc->esc_RDBAL = 0; 2249 sc->esc_RDBAH = 0; 2250 } 2251 sc->esc_RCTL = 0; 2252 sc->esc_FCRTL = 0; 2253 sc->esc_FCRTH = 0; 2254 sc->esc_RDLEN = 0; 2255 sc->esc_RDH = 0; 2256 sc->esc_RDT = 0; 2257 sc->esc_RDTR = 0; 2258 sc->esc_RXDCTL = (1 << 24) | (1 << 16); /* default GRAN/WTHRESH */ 2259 sc->esc_RADV = 0; 2260 sc->esc_RXCSUM = 0; 2261 2262 /* transmit */ 2263 if (!drvr) { 2264 sc->esc_TDBAL = 0; 2265 sc->esc_TDBAH = 0; 2266 sc->esc_TIPG = 0; 2267 sc->esc_AIT = 0; 2268 sc->esc_TIDV = 0; 2269 sc->esc_TADV = 0; 2270 } 2271 sc->esc_tdba = 0; 2272 sc->esc_txdesc = NULL; 2273 sc->esc_TXCW = 0; 2274 sc->esc_TCTL = 0; 2275 sc->esc_TDLEN = 0; 2276 sc->esc_TDT = 0; 2277 sc->esc_TDHr = sc->esc_TDH = 0; 2278 sc->esc_TXDCTL = 0; 2279 } 2280 2281 static int 2282 e82545_init(struct vmctx *ctx, struct pci_devinst *pi, nvlist_t *nvl) 2283 { 2284 char nstr[80]; 2285 struct e82545_softc *sc; 2286 const char *mac; 2287 int err; 2288 2289 /* Setup our softc */ 2290 sc = calloc(1, sizeof(*sc)); 2291 2292 pi->pi_arg = sc; 2293 sc->esc_pi = pi; 2294 sc->esc_ctx = ctx; 2295 2296 pthread_mutex_init(&sc->esc_mtx, NULL); 2297 pthread_cond_init(&sc->esc_rx_cond, NULL); 2298 pthread_cond_init(&sc->esc_tx_cond, NULL); 2299 pthread_create(&sc->esc_tx_tid, NULL, e82545_tx_thread, sc); 2300 snprintf(nstr, sizeof(nstr), "e82545-%d:%d tx", pi->pi_slot, 2301 pi->pi_func); 2302 pthread_set_name_np(sc->esc_tx_tid, nstr); 2303 2304 pci_set_cfgdata16(pi, PCIR_DEVICE, E82545_DEV_ID_82545EM_COPPER); 2305 pci_set_cfgdata16(pi, PCIR_VENDOR, E82545_VENDOR_ID_INTEL); 2306 pci_set_cfgdata8(pi, PCIR_CLASS, PCIC_NETWORK); 2307 pci_set_cfgdata8(pi, PCIR_SUBCLASS, PCIS_NETWORK_ETHERNET); 2308 pci_set_cfgdata16(pi, PCIR_SUBDEV_0, E82545_SUBDEV_ID); 2309 pci_set_cfgdata16(pi, PCIR_SUBVEND_0, E82545_VENDOR_ID_INTEL); 2310 2311 pci_set_cfgdata8(pi, PCIR_HDRTYPE, PCIM_HDRTYPE_NORMAL); 2312 pci_set_cfgdata8(pi, PCIR_INTPIN, 0x1); 2313 2314 /* TODO: this card also supports msi, but the freebsd driver for it 2315 * does not, so I have not implemented it. */ 2316 pci_lintr_request(pi); 2317 2318 pci_emul_alloc_bar(pi, E82545_BAR_REGISTER, PCIBAR_MEM32, 2319 E82545_BAR_REGISTER_LEN); 2320 pci_emul_alloc_bar(pi, E82545_BAR_FLASH, PCIBAR_MEM32, 2321 E82545_BAR_FLASH_LEN); 2322 pci_emul_alloc_bar(pi, E82545_BAR_IO, PCIBAR_IO, 2323 E82545_BAR_IO_LEN); 2324 2325 mac = get_config_value_node(nvl, "mac"); 2326 if (mac != NULL) { 2327 err = net_parsemac(mac, sc->esc_mac.octet); 2328 if (err) { 2329 free(sc); 2330 return (err); 2331 } 2332 } else 2333 net_genmac(pi, sc->esc_mac.octet); 2334 2335 err = netbe_init(&sc->esc_be, nvl, e82545_rx_callback, sc); 2336 if (err) { 2337 free(sc); 2338 return (err); 2339 } 2340 2341 netbe_rx_enable(sc->esc_be); 2342 2343 /* H/w initiated reset */ 2344 e82545_reset(sc, 0); 2345 2346 return (0); 2347 } 2348 2349 #ifdef BHYVE_SNAPSHOT 2350 static int 2351 e82545_snapshot(struct vm_snapshot_meta *meta) 2352 { 2353 int i; 2354 int ret; 2355 struct e82545_softc *sc; 2356 struct pci_devinst *pi; 2357 uint64_t bitmap_value; 2358 2359 pi = meta->dev_data; 2360 sc = pi->pi_arg; 2361 2362 /* esc_mevp and esc_mevpitr should be reinitiated at init. */ 2363 SNAPSHOT_VAR_OR_LEAVE(sc->esc_mac, meta, ret, done); 2364 2365 /* General */ 2366 SNAPSHOT_VAR_OR_LEAVE(sc->esc_CTRL, meta, ret, done); 2367 SNAPSHOT_VAR_OR_LEAVE(sc->esc_FCAL, meta, ret, done); 2368 SNAPSHOT_VAR_OR_LEAVE(sc->esc_FCAH, meta, ret, done); 2369 SNAPSHOT_VAR_OR_LEAVE(sc->esc_FCT, meta, ret, done); 2370 SNAPSHOT_VAR_OR_LEAVE(sc->esc_VET, meta, ret, done); 2371 SNAPSHOT_VAR_OR_LEAVE(sc->esc_FCTTV, meta, ret, done); 2372 SNAPSHOT_VAR_OR_LEAVE(sc->esc_LEDCTL, meta, ret, done); 2373 SNAPSHOT_VAR_OR_LEAVE(sc->esc_PBA, meta, ret, done); 2374 2375 /* Interrupt control */ 2376 SNAPSHOT_VAR_OR_LEAVE(sc->esc_irq_asserted, meta, ret, done); 2377 SNAPSHOT_VAR_OR_LEAVE(sc->esc_ICR, meta, ret, done); 2378 SNAPSHOT_VAR_OR_LEAVE(sc->esc_ITR, meta, ret, done); 2379 SNAPSHOT_VAR_OR_LEAVE(sc->esc_ICS, meta, ret, done); 2380 SNAPSHOT_VAR_OR_LEAVE(sc->esc_IMS, meta, ret, done); 2381 SNAPSHOT_VAR_OR_LEAVE(sc->esc_IMC, meta, ret, done); 2382 2383 /* 2384 * Transmit 2385 * 2386 * The fields in the unions are in superposition to access certain 2387 * bytes in the larger uint variables. 2388 * e.g., ip_config = [ipcss|ipcso|ipcse0|ipcse1] 2389 */ 2390 SNAPSHOT_VAR_OR_LEAVE(sc->esc_txctx.lower_setup.ip_config, meta, ret, done); 2391 SNAPSHOT_VAR_OR_LEAVE(sc->esc_txctx.upper_setup.tcp_config, meta, ret, done); 2392 SNAPSHOT_VAR_OR_LEAVE(sc->esc_txctx.cmd_and_length, meta, ret, done); 2393 SNAPSHOT_VAR_OR_LEAVE(sc->esc_txctx.tcp_seg_setup.data, meta, ret, done); 2394 2395 SNAPSHOT_VAR_OR_LEAVE(sc->esc_tx_enabled, meta, ret, done); 2396 SNAPSHOT_VAR_OR_LEAVE(sc->esc_tx_active, meta, ret, done); 2397 SNAPSHOT_VAR_OR_LEAVE(sc->esc_TXCW, meta, ret, done); 2398 SNAPSHOT_VAR_OR_LEAVE(sc->esc_TCTL, meta, ret, done); 2399 SNAPSHOT_VAR_OR_LEAVE(sc->esc_TIPG, meta, ret, done); 2400 SNAPSHOT_VAR_OR_LEAVE(sc->esc_AIT, meta, ret, done); 2401 SNAPSHOT_VAR_OR_LEAVE(sc->esc_tdba, meta, ret, done); 2402 SNAPSHOT_VAR_OR_LEAVE(sc->esc_TDBAL, meta, ret, done); 2403 SNAPSHOT_VAR_OR_LEAVE(sc->esc_TDBAH, meta, ret, done); 2404 SNAPSHOT_VAR_OR_LEAVE(sc->esc_TDLEN, meta, ret, done); 2405 SNAPSHOT_VAR_OR_LEAVE(sc->esc_TDH, meta, ret, done); 2406 SNAPSHOT_VAR_OR_LEAVE(sc->esc_TDHr, meta, ret, done); 2407 SNAPSHOT_VAR_OR_LEAVE(sc->esc_TDT, meta, ret, done); 2408 SNAPSHOT_VAR_OR_LEAVE(sc->esc_TIDV, meta, ret, done); 2409 SNAPSHOT_VAR_OR_LEAVE(sc->esc_TXDCTL, meta, ret, done); 2410 SNAPSHOT_VAR_OR_LEAVE(sc->esc_TADV, meta, ret, done); 2411 2412 /* Has dependency on esc_TDLEN; reoreder of fields from struct. */ 2413 SNAPSHOT_GUEST2HOST_ADDR_OR_LEAVE(sc->esc_txdesc, sc->esc_TDLEN, 2414 true, meta, ret, done); 2415 2416 /* L2 frame acceptance */ 2417 for (i = 0; i < nitems(sc->esc_uni); i++) { 2418 SNAPSHOT_VAR_OR_LEAVE(sc->esc_uni[i].eu_valid, meta, ret, done); 2419 SNAPSHOT_VAR_OR_LEAVE(sc->esc_uni[i].eu_addrsel, meta, ret, done); 2420 SNAPSHOT_VAR_OR_LEAVE(sc->esc_uni[i].eu_eth, meta, ret, done); 2421 } 2422 2423 SNAPSHOT_BUF_OR_LEAVE(sc->esc_fmcast, sizeof(sc->esc_fmcast), 2424 meta, ret, done); 2425 SNAPSHOT_BUF_OR_LEAVE(sc->esc_fvlan, sizeof(sc->esc_fvlan), 2426 meta, ret, done); 2427 2428 /* Receive */ 2429 SNAPSHOT_VAR_OR_LEAVE(sc->esc_rx_enabled, meta, ret, done); 2430 SNAPSHOT_VAR_OR_LEAVE(sc->esc_rx_active, meta, ret, done); 2431 SNAPSHOT_VAR_OR_LEAVE(sc->esc_rx_loopback, meta, ret, done); 2432 SNAPSHOT_VAR_OR_LEAVE(sc->esc_RCTL, meta, ret, done); 2433 SNAPSHOT_VAR_OR_LEAVE(sc->esc_FCRTL, meta, ret, done); 2434 SNAPSHOT_VAR_OR_LEAVE(sc->esc_FCRTH, meta, ret, done); 2435 SNAPSHOT_VAR_OR_LEAVE(sc->esc_rdba, meta, ret, done); 2436 SNAPSHOT_VAR_OR_LEAVE(sc->esc_RDBAL, meta, ret, done); 2437 SNAPSHOT_VAR_OR_LEAVE(sc->esc_RDBAH, meta, ret, done); 2438 SNAPSHOT_VAR_OR_LEAVE(sc->esc_RDLEN, meta, ret, done); 2439 SNAPSHOT_VAR_OR_LEAVE(sc->esc_RDH, meta, ret, done); 2440 SNAPSHOT_VAR_OR_LEAVE(sc->esc_RDT, meta, ret, done); 2441 SNAPSHOT_VAR_OR_LEAVE(sc->esc_RDTR, meta, ret, done); 2442 SNAPSHOT_VAR_OR_LEAVE(sc->esc_RXDCTL, meta, ret, done); 2443 SNAPSHOT_VAR_OR_LEAVE(sc->esc_RADV, meta, ret, done); 2444 SNAPSHOT_VAR_OR_LEAVE(sc->esc_RSRPD, meta, ret, done); 2445 SNAPSHOT_VAR_OR_LEAVE(sc->esc_RXCSUM, meta, ret, done); 2446 2447 /* Has dependency on esc_RDLEN; reoreder of fields from struct. */ 2448 SNAPSHOT_GUEST2HOST_ADDR_OR_LEAVE(sc->esc_rxdesc, sc->esc_TDLEN, 2449 true, meta, ret, done); 2450 2451 /* IO Port register access */ 2452 SNAPSHOT_VAR_OR_LEAVE(sc->io_addr, meta, ret, done); 2453 2454 /* Shadow copy of MDIC */ 2455 SNAPSHOT_VAR_OR_LEAVE(sc->mdi_control, meta, ret, done); 2456 2457 /* Shadow copy of EECD */ 2458 SNAPSHOT_VAR_OR_LEAVE(sc->eeprom_control, meta, ret, done); 2459 2460 /* Latest NVM in/out */ 2461 SNAPSHOT_VAR_OR_LEAVE(sc->nvm_data, meta, ret, done); 2462 SNAPSHOT_VAR_OR_LEAVE(sc->nvm_opaddr, meta, ret, done); 2463 2464 /* Stats */ 2465 SNAPSHOT_VAR_OR_LEAVE(sc->missed_pkt_count, meta, ret, done); 2466 SNAPSHOT_BUF_OR_LEAVE(sc->pkt_rx_by_size, sizeof(sc->pkt_rx_by_size), 2467 meta, ret, done); 2468 SNAPSHOT_BUF_OR_LEAVE(sc->pkt_tx_by_size, sizeof(sc->pkt_tx_by_size), 2469 meta, ret, done); 2470 SNAPSHOT_VAR_OR_LEAVE(sc->good_pkt_rx_count, meta, ret, done); 2471 SNAPSHOT_VAR_OR_LEAVE(sc->bcast_pkt_rx_count, meta, ret, done); 2472 SNAPSHOT_VAR_OR_LEAVE(sc->mcast_pkt_rx_count, meta, ret, done); 2473 SNAPSHOT_VAR_OR_LEAVE(sc->good_pkt_tx_count, meta, ret, done); 2474 SNAPSHOT_VAR_OR_LEAVE(sc->bcast_pkt_tx_count, meta, ret, done); 2475 SNAPSHOT_VAR_OR_LEAVE(sc->mcast_pkt_tx_count, meta, ret, done); 2476 SNAPSHOT_VAR_OR_LEAVE(sc->oversize_rx_count, meta, ret, done); 2477 SNAPSHOT_VAR_OR_LEAVE(sc->tso_tx_count, meta, ret, done); 2478 SNAPSHOT_VAR_OR_LEAVE(sc->good_octets_rx, meta, ret, done); 2479 SNAPSHOT_VAR_OR_LEAVE(sc->good_octets_tx, meta, ret, done); 2480 SNAPSHOT_VAR_OR_LEAVE(sc->missed_octets, meta, ret, done); 2481 2482 if (meta->op == VM_SNAPSHOT_SAVE) 2483 bitmap_value = sc->nvm_bits; 2484 SNAPSHOT_VAR_OR_LEAVE(bitmap_value, meta, ret, done); 2485 if (meta->op == VM_SNAPSHOT_RESTORE) 2486 sc->nvm_bits = bitmap_value; 2487 2488 if (meta->op == VM_SNAPSHOT_SAVE) 2489 bitmap_value = sc->nvm_bits; 2490 SNAPSHOT_VAR_OR_LEAVE(bitmap_value, meta, ret, done); 2491 if (meta->op == VM_SNAPSHOT_RESTORE) 2492 sc->nvm_bits = bitmap_value; 2493 2494 /* EEPROM data */ 2495 SNAPSHOT_BUF_OR_LEAVE(sc->eeprom_data, sizeof(sc->eeprom_data), 2496 meta, ret, done); 2497 2498 done: 2499 return (ret); 2500 } 2501 #endif 2502 2503 struct pci_devemu pci_de_e82545 = { 2504 .pe_emu = "e1000", 2505 .pe_init = e82545_init, 2506 .pe_legacy_config = netbe_legacy_config, 2507 .pe_barwrite = e82545_write, 2508 .pe_barread = e82545_read, 2509 #ifdef BHYVE_SNAPSHOT 2510 .pe_snapshot = e82545_snapshot, 2511 #endif 2512 }; 2513 PCI_EMUL_SET(pci_de_e82545); 2514 2515