1 /* 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2016 Alexander Motin <mav@FreeBSD.org> 5 * Copyright (c) 2015 Peter Grehan <grehan@freebsd.org> 6 * Copyright (c) 2013 Jeremiah Lott, Avere Systems 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer 14 * in this position and unchanged. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __FBSDID("$FreeBSD$"); 34 35 #include <sys/types.h> 36 #ifndef WITHOUT_CAPSICUM 37 #include <sys/capsicum.h> 38 #endif 39 #include <sys/limits.h> 40 #include <sys/ioctl.h> 41 #include <sys/uio.h> 42 #include <net/ethernet.h> 43 #include <netinet/in.h> 44 #include <netinet/tcp.h> 45 46 #ifndef WITHOUT_CAPSICUM 47 #include <capsicum_helpers.h> 48 #endif 49 #include <err.h> 50 #include <errno.h> 51 #include <fcntl.h> 52 #include <md5.h> 53 #include <stdio.h> 54 #include <stdlib.h> 55 #include <string.h> 56 #include <sysexits.h> 57 #include <unistd.h> 58 #include <pthread.h> 59 #include <pthread_np.h> 60 61 #include "e1000_regs.h" 62 #include "e1000_defines.h" 63 #include "mii.h" 64 65 #include "bhyverun.h" 66 #include "pci_emul.h" 67 #include "mevent.h" 68 #include "net_utils.h" 69 #include "net_backends.h" 70 71 /* Hardware/register definitions XXX: move some to common code. */ 72 #define E82545_VENDOR_ID_INTEL 0x8086 73 #define E82545_DEV_ID_82545EM_COPPER 0x100F 74 #define E82545_SUBDEV_ID 0x1008 75 76 #define E82545_REVISION_4 4 77 78 #define E82545_MDIC_DATA_MASK 0x0000FFFF 79 #define E82545_MDIC_OP_MASK 0x0c000000 80 #define E82545_MDIC_IE 0x20000000 81 82 #define E82545_EECD_FWE_DIS 0x00000010 /* Flash writes disabled */ 83 #define E82545_EECD_FWE_EN 0x00000020 /* Flash writes enabled */ 84 #define E82545_EECD_FWE_MASK 0x00000030 /* Flash writes mask */ 85 86 #define E82545_BAR_REGISTER 0 87 #define E82545_BAR_REGISTER_LEN (128*1024) 88 #define E82545_BAR_FLASH 1 89 #define E82545_BAR_FLASH_LEN (64*1024) 90 #define E82545_BAR_IO 2 91 #define E82545_BAR_IO_LEN 8 92 93 #define E82545_IOADDR 0x00000000 94 #define E82545_IODATA 0x00000004 95 #define E82545_IO_REGISTER_MAX 0x0001FFFF 96 #define E82545_IO_FLASH_BASE 0x00080000 97 #define E82545_IO_FLASH_MAX 0x000FFFFF 98 99 #define E82545_ARRAY_ENTRY(reg, offset) (reg + (offset<<2)) 100 #define E82545_RAR_MAX 15 101 #define E82545_MTA_MAX 127 102 #define E82545_VFTA_MAX 127 103 104 /* Slightly modified from the driver versions, hardcoded for 3 opcode bits, 105 * followed by 6 address bits. 106 * TODO: make opcode bits and addr bits configurable? 107 * NVM Commands - Microwire */ 108 #define E82545_NVM_OPCODE_BITS 3 109 #define E82545_NVM_ADDR_BITS 6 110 #define E82545_NVM_DATA_BITS 16 111 #define E82545_NVM_OPADDR_BITS (E82545_NVM_OPCODE_BITS + E82545_NVM_ADDR_BITS) 112 #define E82545_NVM_ADDR_MASK ((1 << E82545_NVM_ADDR_BITS)-1) 113 #define E82545_NVM_OPCODE_MASK \ 114 (((1 << E82545_NVM_OPCODE_BITS) - 1) << E82545_NVM_ADDR_BITS) 115 #define E82545_NVM_OPCODE_READ (0x6 << E82545_NVM_ADDR_BITS) /* read */ 116 #define E82545_NVM_OPCODE_WRITE (0x5 << E82545_NVM_ADDR_BITS) /* write */ 117 #define E82545_NVM_OPCODE_ERASE (0x7 << E82545_NVM_ADDR_BITS) /* erase */ 118 #define E82545_NVM_OPCODE_EWEN (0x4 << E82545_NVM_ADDR_BITS) /* wr-enable */ 119 120 #define E82545_NVM_EEPROM_SIZE 64 /* 64 * 16-bit values == 128K */ 121 122 #define E1000_ICR_SRPD 0x00010000 123 124 /* This is an arbitrary number. There is no hard limit on the chip. */ 125 #define I82545_MAX_TXSEGS 64 126 127 /* Legacy receive descriptor */ 128 struct e1000_rx_desc { 129 uint64_t buffer_addr; /* Address of the descriptor's data buffer */ 130 uint16_t length; /* Length of data DMAed into data buffer */ 131 uint16_t csum; /* Packet checksum */ 132 uint8_t status; /* Descriptor status */ 133 uint8_t errors; /* Descriptor Errors */ 134 uint16_t special; 135 }; 136 137 /* Transmit descriptor types */ 138 #define E1000_TXD_MASK (E1000_TXD_CMD_DEXT | 0x00F00000) 139 #define E1000_TXD_TYP_L (0) 140 #define E1000_TXD_TYP_C (E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_C) 141 #define E1000_TXD_TYP_D (E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D) 142 143 /* Legacy transmit descriptor */ 144 struct e1000_tx_desc { 145 uint64_t buffer_addr; /* Address of the descriptor's data buffer */ 146 union { 147 uint32_t data; 148 struct { 149 uint16_t length; /* Data buffer length */ 150 uint8_t cso; /* Checksum offset */ 151 uint8_t cmd; /* Descriptor control */ 152 } flags; 153 } lower; 154 union { 155 uint32_t data; 156 struct { 157 uint8_t status; /* Descriptor status */ 158 uint8_t css; /* Checksum start */ 159 uint16_t special; 160 } fields; 161 } upper; 162 }; 163 164 /* Context descriptor */ 165 struct e1000_context_desc { 166 union { 167 uint32_t ip_config; 168 struct { 169 uint8_t ipcss; /* IP checksum start */ 170 uint8_t ipcso; /* IP checksum offset */ 171 uint16_t ipcse; /* IP checksum end */ 172 } ip_fields; 173 } lower_setup; 174 union { 175 uint32_t tcp_config; 176 struct { 177 uint8_t tucss; /* TCP checksum start */ 178 uint8_t tucso; /* TCP checksum offset */ 179 uint16_t tucse; /* TCP checksum end */ 180 } tcp_fields; 181 } upper_setup; 182 uint32_t cmd_and_length; 183 union { 184 uint32_t data; 185 struct { 186 uint8_t status; /* Descriptor status */ 187 uint8_t hdr_len; /* Header length */ 188 uint16_t mss; /* Maximum segment size */ 189 } fields; 190 } tcp_seg_setup; 191 }; 192 193 /* Data descriptor */ 194 struct e1000_data_desc { 195 uint64_t buffer_addr; /* Address of the descriptor's buffer address */ 196 union { 197 uint32_t data; 198 struct { 199 uint16_t length; /* Data buffer length */ 200 uint8_t typ_len_ext; 201 uint8_t cmd; 202 } flags; 203 } lower; 204 union { 205 uint32_t data; 206 struct { 207 uint8_t status; /* Descriptor status */ 208 uint8_t popts; /* Packet Options */ 209 uint16_t special; 210 } fields; 211 } upper; 212 }; 213 214 union e1000_tx_udesc { 215 struct e1000_tx_desc td; 216 struct e1000_context_desc cd; 217 struct e1000_data_desc dd; 218 }; 219 220 /* Tx checksum info for a packet. */ 221 struct ck_info { 222 int ck_valid; /* ck_info is valid */ 223 uint8_t ck_start; /* start byte of cksum calcuation */ 224 uint8_t ck_off; /* offset of cksum insertion */ 225 uint16_t ck_len; /* length of cksum calc: 0 is to packet-end */ 226 }; 227 228 /* 229 * Debug printf 230 */ 231 static int e82545_debug = 0; 232 #define DPRINTF(msg,params...) if (e82545_debug) fprintf(stderr, "e82545: " msg, params) 233 #define WPRINTF(msg,params...) fprintf(stderr, "e82545: " msg, params) 234 235 #define MIN(a,b) (((a)<(b))?(a):(b)) 236 #define MAX(a,b) (((a)>(b))?(a):(b)) 237 238 /* s/w representation of the RAL/RAH regs */ 239 struct eth_uni { 240 int eu_valid; 241 int eu_addrsel; 242 struct ether_addr eu_eth; 243 }; 244 245 246 struct e82545_softc { 247 struct pci_devinst *esc_pi; 248 struct vmctx *esc_ctx; 249 struct mevent *esc_mevpitr; 250 pthread_mutex_t esc_mtx; 251 struct ether_addr esc_mac; 252 net_backend_t *esc_be; 253 254 /* General */ 255 uint32_t esc_CTRL; /* x0000 device ctl */ 256 uint32_t esc_FCAL; /* x0028 flow ctl addr lo */ 257 uint32_t esc_FCAH; /* x002C flow ctl addr hi */ 258 uint32_t esc_FCT; /* x0030 flow ctl type */ 259 uint32_t esc_VET; /* x0038 VLAN eth type */ 260 uint32_t esc_FCTTV; /* x0170 flow ctl tx timer */ 261 uint32_t esc_LEDCTL; /* x0E00 LED control */ 262 uint32_t esc_PBA; /* x1000 pkt buffer allocation */ 263 264 /* Interrupt control */ 265 int esc_irq_asserted; 266 uint32_t esc_ICR; /* x00C0 cause read/clear */ 267 uint32_t esc_ITR; /* x00C4 intr throttling */ 268 uint32_t esc_ICS; /* x00C8 cause set */ 269 uint32_t esc_IMS; /* x00D0 mask set/read */ 270 uint32_t esc_IMC; /* x00D8 mask clear */ 271 272 /* Transmit */ 273 union e1000_tx_udesc *esc_txdesc; 274 struct e1000_context_desc esc_txctx; 275 pthread_t esc_tx_tid; 276 pthread_cond_t esc_tx_cond; 277 int esc_tx_enabled; 278 int esc_tx_active; 279 uint32_t esc_TXCW; /* x0178 transmit config */ 280 uint32_t esc_TCTL; /* x0400 transmit ctl */ 281 uint32_t esc_TIPG; /* x0410 inter-packet gap */ 282 uint16_t esc_AIT; /* x0458 Adaptive Interframe Throttle */ 283 uint64_t esc_tdba; /* verified 64-bit desc table addr */ 284 uint32_t esc_TDBAL; /* x3800 desc table addr, low bits */ 285 uint32_t esc_TDBAH; /* x3804 desc table addr, hi 32-bits */ 286 uint32_t esc_TDLEN; /* x3808 # descriptors in bytes */ 287 uint16_t esc_TDH; /* x3810 desc table head idx */ 288 uint16_t esc_TDHr; /* internal read version of TDH */ 289 uint16_t esc_TDT; /* x3818 desc table tail idx */ 290 uint32_t esc_TIDV; /* x3820 intr delay */ 291 uint32_t esc_TXDCTL; /* x3828 desc control */ 292 uint32_t esc_TADV; /* x382C intr absolute delay */ 293 294 /* L2 frame acceptance */ 295 struct eth_uni esc_uni[16]; /* 16 x unicast MAC addresses */ 296 uint32_t esc_fmcast[128]; /* Multicast filter bit-match */ 297 uint32_t esc_fvlan[128]; /* VLAN 4096-bit filter */ 298 299 /* Receive */ 300 struct e1000_rx_desc *esc_rxdesc; 301 pthread_cond_t esc_rx_cond; 302 int esc_rx_enabled; 303 int esc_rx_active; 304 int esc_rx_loopback; 305 uint32_t esc_RCTL; /* x0100 receive ctl */ 306 uint32_t esc_FCRTL; /* x2160 flow cntl thresh, low */ 307 uint32_t esc_FCRTH; /* x2168 flow cntl thresh, hi */ 308 uint64_t esc_rdba; /* verified 64-bit desc table addr */ 309 uint32_t esc_RDBAL; /* x2800 desc table addr, low bits */ 310 uint32_t esc_RDBAH; /* x2804 desc table addr, hi 32-bits*/ 311 uint32_t esc_RDLEN; /* x2808 #descriptors */ 312 uint16_t esc_RDH; /* x2810 desc table head idx */ 313 uint16_t esc_RDT; /* x2818 desc table tail idx */ 314 uint32_t esc_RDTR; /* x2820 intr delay */ 315 uint32_t esc_RXDCTL; /* x2828 desc control */ 316 uint32_t esc_RADV; /* x282C intr absolute delay */ 317 uint32_t esc_RSRPD; /* x2C00 recv small packet detect */ 318 uint32_t esc_RXCSUM; /* x5000 receive cksum ctl */ 319 320 /* IO Port register access */ 321 uint32_t io_addr; 322 323 /* Shadow copy of MDIC */ 324 uint32_t mdi_control; 325 /* Shadow copy of EECD */ 326 uint32_t eeprom_control; 327 /* Latest NVM in/out */ 328 uint16_t nvm_data; 329 uint16_t nvm_opaddr; 330 /* stats */ 331 uint32_t missed_pkt_count; /* dropped for no room in rx queue */ 332 uint32_t pkt_rx_by_size[6]; 333 uint32_t pkt_tx_by_size[6]; 334 uint32_t good_pkt_rx_count; 335 uint32_t bcast_pkt_rx_count; 336 uint32_t mcast_pkt_rx_count; 337 uint32_t good_pkt_tx_count; 338 uint32_t bcast_pkt_tx_count; 339 uint32_t mcast_pkt_tx_count; 340 uint32_t oversize_rx_count; 341 uint32_t tso_tx_count; 342 uint64_t good_octets_rx; 343 uint64_t good_octets_tx; 344 uint64_t missed_octets; /* counts missed and oversized */ 345 346 uint8_t nvm_bits:6; /* number of bits remaining in/out */ 347 uint8_t nvm_mode:2; 348 #define E82545_NVM_MODE_OPADDR 0x0 349 #define E82545_NVM_MODE_DATAIN 0x1 350 #define E82545_NVM_MODE_DATAOUT 0x2 351 /* EEPROM data */ 352 uint16_t eeprom_data[E82545_NVM_EEPROM_SIZE]; 353 }; 354 355 static void e82545_reset(struct e82545_softc *sc, int dev); 356 static void e82545_rx_enable(struct e82545_softc *sc); 357 static void e82545_rx_disable(struct e82545_softc *sc); 358 static void e82545_rx_callback(int fd, enum ev_type type, void *param); 359 static void e82545_tx_start(struct e82545_softc *sc); 360 static void e82545_tx_enable(struct e82545_softc *sc); 361 static void e82545_tx_disable(struct e82545_softc *sc); 362 363 static inline int 364 e82545_size_stat_index(uint32_t size) 365 { 366 if (size <= 64) { 367 return 0; 368 } else if (size >= 1024) { 369 return 5; 370 } else { 371 /* should be 1-4 */ 372 return (ffs(size) - 6); 373 } 374 } 375 376 static void 377 e82545_init_eeprom(struct e82545_softc *sc) 378 { 379 uint16_t checksum, i; 380 381 /* mac addr */ 382 sc->eeprom_data[NVM_MAC_ADDR] = ((uint16_t)sc->esc_mac.octet[0]) | 383 (((uint16_t)sc->esc_mac.octet[1]) << 8); 384 sc->eeprom_data[NVM_MAC_ADDR+1] = ((uint16_t)sc->esc_mac.octet[2]) | 385 (((uint16_t)sc->esc_mac.octet[3]) << 8); 386 sc->eeprom_data[NVM_MAC_ADDR+2] = ((uint16_t)sc->esc_mac.octet[4]) | 387 (((uint16_t)sc->esc_mac.octet[5]) << 8); 388 389 /* pci ids */ 390 sc->eeprom_data[NVM_SUB_DEV_ID] = E82545_SUBDEV_ID; 391 sc->eeprom_data[NVM_SUB_VEN_ID] = E82545_VENDOR_ID_INTEL; 392 sc->eeprom_data[NVM_DEV_ID] = E82545_DEV_ID_82545EM_COPPER; 393 sc->eeprom_data[NVM_VEN_ID] = E82545_VENDOR_ID_INTEL; 394 395 /* fill in the checksum */ 396 checksum = 0; 397 for (i = 0; i < NVM_CHECKSUM_REG; i++) { 398 checksum += sc->eeprom_data[i]; 399 } 400 checksum = NVM_SUM - checksum; 401 sc->eeprom_data[NVM_CHECKSUM_REG] = checksum; 402 DPRINTF("eeprom checksum: 0x%x\r\n", checksum); 403 } 404 405 static void 406 e82545_write_mdi(struct e82545_softc *sc, uint8_t reg_addr, 407 uint8_t phy_addr, uint32_t data) 408 { 409 DPRINTF("Write mdi reg:0x%x phy:0x%x data: 0x%x\r\n", reg_addr, phy_addr, data); 410 } 411 412 static uint32_t 413 e82545_read_mdi(struct e82545_softc *sc, uint8_t reg_addr, 414 uint8_t phy_addr) 415 { 416 //DPRINTF("Read mdi reg:0x%x phy:0x%x\r\n", reg_addr, phy_addr); 417 switch (reg_addr) { 418 case PHY_STATUS: 419 return (MII_SR_LINK_STATUS | MII_SR_AUTONEG_CAPS | 420 MII_SR_AUTONEG_COMPLETE); 421 case PHY_AUTONEG_ADV: 422 return NWAY_AR_SELECTOR_FIELD; 423 case PHY_LP_ABILITY: 424 return 0; 425 case PHY_1000T_STATUS: 426 return (SR_1000T_LP_FD_CAPS | SR_1000T_REMOTE_RX_STATUS | 427 SR_1000T_LOCAL_RX_STATUS); 428 case PHY_ID1: 429 return (M88E1011_I_PHY_ID >> 16) & 0xFFFF; 430 case PHY_ID2: 431 return (M88E1011_I_PHY_ID | E82545_REVISION_4) & 0xFFFF; 432 default: 433 DPRINTF("Unknown mdi read reg:0x%x phy:0x%x\r\n", reg_addr, phy_addr); 434 return 0; 435 } 436 /* not reached */ 437 } 438 439 static void 440 e82545_eecd_strobe(struct e82545_softc *sc) 441 { 442 /* Microwire state machine */ 443 /* 444 DPRINTF("eeprom state machine srtobe " 445 "0x%x 0x%x 0x%x 0x%x\r\n", 446 sc->nvm_mode, sc->nvm_bits, 447 sc->nvm_opaddr, sc->nvm_data);*/ 448 449 if (sc->nvm_bits == 0) { 450 DPRINTF("eeprom state machine not expecting data! " 451 "0x%x 0x%x 0x%x 0x%x\r\n", 452 sc->nvm_mode, sc->nvm_bits, 453 sc->nvm_opaddr, sc->nvm_data); 454 return; 455 } 456 sc->nvm_bits--; 457 if (sc->nvm_mode == E82545_NVM_MODE_DATAOUT) { 458 /* shifting out */ 459 if (sc->nvm_data & 0x8000) { 460 sc->eeprom_control |= E1000_EECD_DO; 461 } else { 462 sc->eeprom_control &= ~E1000_EECD_DO; 463 } 464 sc->nvm_data <<= 1; 465 if (sc->nvm_bits == 0) { 466 /* read done, back to opcode mode. */ 467 sc->nvm_opaddr = 0; 468 sc->nvm_mode = E82545_NVM_MODE_OPADDR; 469 sc->nvm_bits = E82545_NVM_OPADDR_BITS; 470 } 471 } else if (sc->nvm_mode == E82545_NVM_MODE_DATAIN) { 472 /* shifting in */ 473 sc->nvm_data <<= 1; 474 if (sc->eeprom_control & E1000_EECD_DI) { 475 sc->nvm_data |= 1; 476 } 477 if (sc->nvm_bits == 0) { 478 /* eeprom write */ 479 uint16_t op = sc->nvm_opaddr & E82545_NVM_OPCODE_MASK; 480 uint16_t addr = sc->nvm_opaddr & E82545_NVM_ADDR_MASK; 481 if (op != E82545_NVM_OPCODE_WRITE) { 482 DPRINTF("Illegal eeprom write op 0x%x\r\n", 483 sc->nvm_opaddr); 484 } else if (addr >= E82545_NVM_EEPROM_SIZE) { 485 DPRINTF("Illegal eeprom write addr 0x%x\r\n", 486 sc->nvm_opaddr); 487 } else { 488 DPRINTF("eeprom write eeprom[0x%x] = 0x%x\r\n", 489 addr, sc->nvm_data); 490 sc->eeprom_data[addr] = sc->nvm_data; 491 } 492 /* back to opcode mode */ 493 sc->nvm_opaddr = 0; 494 sc->nvm_mode = E82545_NVM_MODE_OPADDR; 495 sc->nvm_bits = E82545_NVM_OPADDR_BITS; 496 } 497 } else if (sc->nvm_mode == E82545_NVM_MODE_OPADDR) { 498 sc->nvm_opaddr <<= 1; 499 if (sc->eeprom_control & E1000_EECD_DI) { 500 sc->nvm_opaddr |= 1; 501 } 502 if (sc->nvm_bits == 0) { 503 uint16_t op = sc->nvm_opaddr & E82545_NVM_OPCODE_MASK; 504 switch (op) { 505 case E82545_NVM_OPCODE_EWEN: 506 DPRINTF("eeprom write enable: 0x%x\r\n", 507 sc->nvm_opaddr); 508 /* back to opcode mode */ 509 sc->nvm_opaddr = 0; 510 sc->nvm_mode = E82545_NVM_MODE_OPADDR; 511 sc->nvm_bits = E82545_NVM_OPADDR_BITS; 512 break; 513 case E82545_NVM_OPCODE_READ: 514 { 515 uint16_t addr = sc->nvm_opaddr & 516 E82545_NVM_ADDR_MASK; 517 sc->nvm_mode = E82545_NVM_MODE_DATAOUT; 518 sc->nvm_bits = E82545_NVM_DATA_BITS; 519 if (addr < E82545_NVM_EEPROM_SIZE) { 520 sc->nvm_data = sc->eeprom_data[addr]; 521 DPRINTF("eeprom read: eeprom[0x%x] = 0x%x\r\n", 522 addr, sc->nvm_data); 523 } else { 524 DPRINTF("eeprom illegal read: 0x%x\r\n", 525 sc->nvm_opaddr); 526 sc->nvm_data = 0; 527 } 528 break; 529 } 530 case E82545_NVM_OPCODE_WRITE: 531 sc->nvm_mode = E82545_NVM_MODE_DATAIN; 532 sc->nvm_bits = E82545_NVM_DATA_BITS; 533 sc->nvm_data = 0; 534 break; 535 default: 536 DPRINTF("eeprom unknown op: 0x%x\r\r", 537 sc->nvm_opaddr); 538 /* back to opcode mode */ 539 sc->nvm_opaddr = 0; 540 sc->nvm_mode = E82545_NVM_MODE_OPADDR; 541 sc->nvm_bits = E82545_NVM_OPADDR_BITS; 542 } 543 } 544 } else { 545 DPRINTF("eeprom state machine wrong state! " 546 "0x%x 0x%x 0x%x 0x%x\r\n", 547 sc->nvm_mode, sc->nvm_bits, 548 sc->nvm_opaddr, sc->nvm_data); 549 } 550 } 551 552 static void 553 e82545_itr_callback(int fd, enum ev_type type, void *param) 554 { 555 uint32_t new; 556 struct e82545_softc *sc = param; 557 558 pthread_mutex_lock(&sc->esc_mtx); 559 new = sc->esc_ICR & sc->esc_IMS; 560 if (new && !sc->esc_irq_asserted) { 561 DPRINTF("itr callback: lintr assert %x\r\n", new); 562 sc->esc_irq_asserted = 1; 563 pci_lintr_assert(sc->esc_pi); 564 } else { 565 mevent_delete(sc->esc_mevpitr); 566 sc->esc_mevpitr = NULL; 567 } 568 pthread_mutex_unlock(&sc->esc_mtx); 569 } 570 571 static void 572 e82545_icr_assert(struct e82545_softc *sc, uint32_t bits) 573 { 574 uint32_t new; 575 576 DPRINTF("icr assert: 0x%x\r\n", bits); 577 578 /* 579 * An interrupt is only generated if bits are set that 580 * aren't already in the ICR, these bits are unmasked, 581 * and there isn't an interrupt already pending. 582 */ 583 new = bits & ~sc->esc_ICR & sc->esc_IMS; 584 sc->esc_ICR |= bits; 585 586 if (new == 0) { 587 DPRINTF("icr assert: masked %x, ims %x\r\n", new, sc->esc_IMS); 588 } else if (sc->esc_mevpitr != NULL) { 589 DPRINTF("icr assert: throttled %x, ims %x\r\n", new, sc->esc_IMS); 590 } else if (!sc->esc_irq_asserted) { 591 DPRINTF("icr assert: lintr assert %x\r\n", new); 592 sc->esc_irq_asserted = 1; 593 pci_lintr_assert(sc->esc_pi); 594 if (sc->esc_ITR != 0) { 595 sc->esc_mevpitr = mevent_add( 596 (sc->esc_ITR + 3905) / 3906, /* 256ns -> 1ms */ 597 EVF_TIMER, e82545_itr_callback, sc); 598 } 599 } 600 } 601 602 static void 603 e82545_ims_change(struct e82545_softc *sc, uint32_t bits) 604 { 605 uint32_t new; 606 607 /* 608 * Changing the mask may allow previously asserted 609 * but masked interrupt requests to generate an interrupt. 610 */ 611 new = bits & sc->esc_ICR & ~sc->esc_IMS; 612 sc->esc_IMS |= bits; 613 614 if (new == 0) { 615 DPRINTF("ims change: masked %x, ims %x\r\n", new, sc->esc_IMS); 616 } else if (sc->esc_mevpitr != NULL) { 617 DPRINTF("ims change: throttled %x, ims %x\r\n", new, sc->esc_IMS); 618 } else if (!sc->esc_irq_asserted) { 619 DPRINTF("ims change: lintr assert %x\n\r", new); 620 sc->esc_irq_asserted = 1; 621 pci_lintr_assert(sc->esc_pi); 622 if (sc->esc_ITR != 0) { 623 sc->esc_mevpitr = mevent_add( 624 (sc->esc_ITR + 3905) / 3906, /* 256ns -> 1ms */ 625 EVF_TIMER, e82545_itr_callback, sc); 626 } 627 } 628 } 629 630 static void 631 e82545_icr_deassert(struct e82545_softc *sc, uint32_t bits) 632 { 633 634 DPRINTF("icr deassert: 0x%x\r\n", bits); 635 sc->esc_ICR &= ~bits; 636 637 /* 638 * If there are no longer any interrupt sources and there 639 * was an asserted interrupt, clear it 640 */ 641 if (sc->esc_irq_asserted && !(sc->esc_ICR & sc->esc_IMS)) { 642 DPRINTF("icr deassert: lintr deassert %x\r\n", bits); 643 pci_lintr_deassert(sc->esc_pi); 644 sc->esc_irq_asserted = 0; 645 } 646 } 647 648 static void 649 e82545_intr_write(struct e82545_softc *sc, uint32_t offset, uint32_t value) 650 { 651 652 DPRINTF("intr_write: off %x, val %x\n\r", offset, value); 653 654 switch (offset) { 655 case E1000_ICR: 656 e82545_icr_deassert(sc, value); 657 break; 658 case E1000_ITR: 659 sc->esc_ITR = value; 660 break; 661 case E1000_ICS: 662 sc->esc_ICS = value; /* not used: store for debug */ 663 e82545_icr_assert(sc, value); 664 break; 665 case E1000_IMS: 666 e82545_ims_change(sc, value); 667 break; 668 case E1000_IMC: 669 sc->esc_IMC = value; /* for debug */ 670 sc->esc_IMS &= ~value; 671 // XXX clear interrupts if all ICR bits now masked 672 // and interrupt was pending ? 673 break; 674 default: 675 break; 676 } 677 } 678 679 static uint32_t 680 e82545_intr_read(struct e82545_softc *sc, uint32_t offset) 681 { 682 uint32_t retval; 683 684 retval = 0; 685 686 DPRINTF("intr_read: off %x\n\r", offset); 687 688 switch (offset) { 689 case E1000_ICR: 690 retval = sc->esc_ICR; 691 sc->esc_ICR = 0; 692 e82545_icr_deassert(sc, ~0); 693 break; 694 case E1000_ITR: 695 retval = sc->esc_ITR; 696 break; 697 case E1000_ICS: 698 /* write-only register */ 699 break; 700 case E1000_IMS: 701 retval = sc->esc_IMS; 702 break; 703 case E1000_IMC: 704 /* write-only register */ 705 break; 706 default: 707 break; 708 } 709 710 return (retval); 711 } 712 713 static void 714 e82545_devctl(struct e82545_softc *sc, uint32_t val) 715 { 716 717 sc->esc_CTRL = val & ~E1000_CTRL_RST; 718 719 if (val & E1000_CTRL_RST) { 720 DPRINTF("e1k: s/w reset, ctl %x\n", val); 721 e82545_reset(sc, 1); 722 } 723 /* XXX check for phy reset ? */ 724 } 725 726 static void 727 e82545_rx_update_rdba(struct e82545_softc *sc) 728 { 729 730 /* XXX verify desc base/len within phys mem range */ 731 sc->esc_rdba = (uint64_t)sc->esc_RDBAH << 32 | 732 sc->esc_RDBAL; 733 734 /* Cache host mapping of guest descriptor array */ 735 sc->esc_rxdesc = paddr_guest2host(sc->esc_ctx, 736 sc->esc_rdba, sc->esc_RDLEN); 737 } 738 739 static void 740 e82545_rx_ctl(struct e82545_softc *sc, uint32_t val) 741 { 742 int on; 743 744 on = ((val & E1000_RCTL_EN) == E1000_RCTL_EN); 745 746 /* Save RCTL after stripping reserved bits 31:27,24,21,14,11:10,0 */ 747 sc->esc_RCTL = val & ~0xF9204c01; 748 749 DPRINTF("rx_ctl - %s RCTL %x, val %x\n", 750 on ? "on" : "off", sc->esc_RCTL, val); 751 752 /* state change requested */ 753 if (on != sc->esc_rx_enabled) { 754 if (on) { 755 /* Catch disallowed/unimplemented settings */ 756 //assert(!(val & E1000_RCTL_LBM_TCVR)); 757 758 if (sc->esc_RCTL & E1000_RCTL_LBM_TCVR) { 759 sc->esc_rx_loopback = 1; 760 } else { 761 sc->esc_rx_loopback = 0; 762 } 763 764 e82545_rx_update_rdba(sc); 765 e82545_rx_enable(sc); 766 } else { 767 e82545_rx_disable(sc); 768 sc->esc_rx_loopback = 0; 769 sc->esc_rdba = 0; 770 sc->esc_rxdesc = NULL; 771 } 772 } 773 } 774 775 static void 776 e82545_tx_update_tdba(struct e82545_softc *sc) 777 { 778 779 /* XXX verify desc base/len within phys mem range */ 780 sc->esc_tdba = (uint64_t)sc->esc_TDBAH << 32 | sc->esc_TDBAL; 781 782 /* Cache host mapping of guest descriptor array */ 783 sc->esc_txdesc = paddr_guest2host(sc->esc_ctx, sc->esc_tdba, 784 sc->esc_TDLEN); 785 } 786 787 static void 788 e82545_tx_ctl(struct e82545_softc *sc, uint32_t val) 789 { 790 int on; 791 792 on = ((val & E1000_TCTL_EN) == E1000_TCTL_EN); 793 794 /* ignore TCTL_EN settings that don't change state */ 795 if (on == sc->esc_tx_enabled) 796 return; 797 798 if (on) { 799 e82545_tx_update_tdba(sc); 800 e82545_tx_enable(sc); 801 } else { 802 e82545_tx_disable(sc); 803 sc->esc_tdba = 0; 804 sc->esc_txdesc = NULL; 805 } 806 807 /* Save TCTL value after stripping reserved bits 31:25,23,2,0 */ 808 sc->esc_TCTL = val & ~0xFE800005; 809 } 810 811 int 812 e82545_bufsz(uint32_t rctl) 813 { 814 815 switch (rctl & (E1000_RCTL_BSEX | E1000_RCTL_SZ_256)) { 816 case (E1000_RCTL_SZ_2048): return (2048); 817 case (E1000_RCTL_SZ_1024): return (1024); 818 case (E1000_RCTL_SZ_512): return (512); 819 case (E1000_RCTL_SZ_256): return (256); 820 case (E1000_RCTL_BSEX|E1000_RCTL_SZ_16384): return (16384); 821 case (E1000_RCTL_BSEX|E1000_RCTL_SZ_8192): return (8192); 822 case (E1000_RCTL_BSEX|E1000_RCTL_SZ_4096): return (4096); 823 } 824 return (256); /* Forbidden value. */ 825 } 826 827 /* XXX one packet at a time until this is debugged */ 828 static void 829 e82545_rx_callback(int fd, enum ev_type type, void *param) 830 { 831 struct e82545_softc *sc = param; 832 struct e1000_rx_desc *rxd; 833 struct iovec vec[64]; 834 int left, len, lim, maxpktsz, maxpktdesc, bufsz, i, n, size; 835 uint32_t cause = 0; 836 uint16_t *tp, tag, head; 837 838 pthread_mutex_lock(&sc->esc_mtx); 839 DPRINTF("rx_run: head %x, tail %x\r\n", sc->esc_RDH, sc->esc_RDT); 840 841 if (!sc->esc_rx_enabled || sc->esc_rx_loopback) { 842 DPRINTF("rx disabled (!%d || %d) -- packet(s) dropped\r\n", 843 sc->esc_rx_enabled, sc->esc_rx_loopback); 844 while (netbe_rx_discard(sc->esc_be) > 0) { 845 } 846 goto done1; 847 } 848 bufsz = e82545_bufsz(sc->esc_RCTL); 849 maxpktsz = (sc->esc_RCTL & E1000_RCTL_LPE) ? 16384 : 1522; 850 maxpktdesc = (maxpktsz + bufsz - 1) / bufsz; 851 size = sc->esc_RDLEN / 16; 852 head = sc->esc_RDH; 853 left = (size + sc->esc_RDT - head) % size; 854 if (left < maxpktdesc) { 855 DPRINTF("rx overflow (%d < %d) -- packet(s) dropped\r\n", 856 left, maxpktdesc); 857 while (netbe_rx_discard(sc->esc_be) > 0) { 858 } 859 goto done1; 860 } 861 862 sc->esc_rx_active = 1; 863 pthread_mutex_unlock(&sc->esc_mtx); 864 865 for (lim = size / 4; lim > 0 && left >= maxpktdesc; lim -= n) { 866 867 /* Grab rx descriptor pointed to by the head pointer */ 868 for (i = 0; i < maxpktdesc; i++) { 869 rxd = &sc->esc_rxdesc[(head + i) % size]; 870 vec[i].iov_base = paddr_guest2host(sc->esc_ctx, 871 rxd->buffer_addr, bufsz); 872 vec[i].iov_len = bufsz; 873 } 874 len = netbe_recv(sc->esc_be, vec, maxpktdesc); 875 if (len <= 0) { 876 DPRINTF("netbe_recv() returned %d\n", len); 877 goto done; 878 } 879 880 /* 881 * Adjust the packet length based on whether the CRC needs 882 * to be stripped or if the packet is less than the minimum 883 * eth packet size. 884 */ 885 if (len < ETHER_MIN_LEN - ETHER_CRC_LEN) 886 len = ETHER_MIN_LEN - ETHER_CRC_LEN; 887 if (!(sc->esc_RCTL & E1000_RCTL_SECRC)) 888 len += ETHER_CRC_LEN; 889 n = (len + bufsz - 1) / bufsz; 890 891 DPRINTF("packet read %d bytes, %d segs, head %d\r\n", 892 len, n, head); 893 894 /* Apply VLAN filter. */ 895 tp = (uint16_t *)vec[0].iov_base + 6; 896 if ((sc->esc_RCTL & E1000_RCTL_VFE) && 897 (ntohs(tp[0]) == sc->esc_VET)) { 898 tag = ntohs(tp[1]) & 0x0fff; 899 if ((sc->esc_fvlan[tag >> 5] & 900 (1 << (tag & 0x1f))) != 0) { 901 DPRINTF("known VLAN %d\r\n", tag); 902 } else { 903 DPRINTF("unknown VLAN %d\r\n", tag); 904 n = 0; 905 continue; 906 } 907 } 908 909 /* Update all consumed descriptors. */ 910 for (i = 0; i < n - 1; i++) { 911 rxd = &sc->esc_rxdesc[(head + i) % size]; 912 rxd->length = bufsz; 913 rxd->csum = 0; 914 rxd->errors = 0; 915 rxd->special = 0; 916 rxd->status = E1000_RXD_STAT_DD; 917 } 918 rxd = &sc->esc_rxdesc[(head + i) % size]; 919 rxd->length = len % bufsz; 920 rxd->csum = 0; 921 rxd->errors = 0; 922 rxd->special = 0; 923 /* XXX signal no checksum for now */ 924 rxd->status = E1000_RXD_STAT_PIF | E1000_RXD_STAT_IXSM | 925 E1000_RXD_STAT_EOP | E1000_RXD_STAT_DD; 926 927 /* Schedule receive interrupts. */ 928 if (len <= sc->esc_RSRPD) { 929 cause |= E1000_ICR_SRPD | E1000_ICR_RXT0; 930 } else { 931 /* XXX: RDRT and RADV timers should be here. */ 932 cause |= E1000_ICR_RXT0; 933 } 934 935 head = (head + n) % size; 936 left -= n; 937 } 938 939 done: 940 pthread_mutex_lock(&sc->esc_mtx); 941 sc->esc_rx_active = 0; 942 if (sc->esc_rx_enabled == 0) 943 pthread_cond_signal(&sc->esc_rx_cond); 944 945 sc->esc_RDH = head; 946 /* Respect E1000_RCTL_RDMTS */ 947 left = (size + sc->esc_RDT - head) % size; 948 if (left < (size >> (((sc->esc_RCTL >> 8) & 3) + 1))) 949 cause |= E1000_ICR_RXDMT0; 950 /* Assert all accumulated interrupts. */ 951 if (cause != 0) 952 e82545_icr_assert(sc, cause); 953 done1: 954 DPRINTF("rx_run done: head %x, tail %x\r\n", sc->esc_RDH, sc->esc_RDT); 955 pthread_mutex_unlock(&sc->esc_mtx); 956 } 957 958 static uint16_t 959 e82545_carry(uint32_t sum) 960 { 961 962 sum = (sum & 0xFFFF) + (sum >> 16); 963 if (sum > 0xFFFF) 964 sum -= 0xFFFF; 965 return (sum); 966 } 967 968 static uint16_t 969 e82545_buf_checksum(uint8_t *buf, int len) 970 { 971 int i; 972 uint32_t sum = 0; 973 974 /* Checksum all the pairs of bytes first... */ 975 for (i = 0; i < (len & ~1U); i += 2) 976 sum += *((u_int16_t *)(buf + i)); 977 978 /* 979 * If there's a single byte left over, checksum it, too. 980 * Network byte order is big-endian, so the remaining byte is 981 * the high byte. 982 */ 983 if (i < len) 984 sum += htons(buf[i] << 8); 985 986 return (e82545_carry(sum)); 987 } 988 989 static uint16_t 990 e82545_iov_checksum(struct iovec *iov, int iovcnt, int off, int len) 991 { 992 int now, odd; 993 uint32_t sum = 0, s; 994 995 /* Skip completely unneeded vectors. */ 996 while (iovcnt > 0 && iov->iov_len <= off && off > 0) { 997 off -= iov->iov_len; 998 iov++; 999 iovcnt--; 1000 } 1001 1002 /* Calculate checksum of requested range. */ 1003 odd = 0; 1004 while (len > 0 && iovcnt > 0) { 1005 now = MIN(len, iov->iov_len - off); 1006 s = e82545_buf_checksum(iov->iov_base + off, now); 1007 sum += odd ? (s << 8) : s; 1008 odd ^= (now & 1); 1009 len -= now; 1010 off = 0; 1011 iov++; 1012 iovcnt--; 1013 } 1014 1015 return (e82545_carry(sum)); 1016 } 1017 1018 /* 1019 * Return the transmit descriptor type. 1020 */ 1021 int 1022 e82545_txdesc_type(uint32_t lower) 1023 { 1024 int type; 1025 1026 type = 0; 1027 1028 if (lower & E1000_TXD_CMD_DEXT) 1029 type = lower & E1000_TXD_MASK; 1030 1031 return (type); 1032 } 1033 1034 static void 1035 e82545_transmit_checksum(struct iovec *iov, int iovcnt, struct ck_info *ck) 1036 { 1037 uint16_t cksum; 1038 int cklen; 1039 1040 DPRINTF("tx cksum: iovcnt/s/off/len %d/%d/%d/%d\r\n", 1041 iovcnt, ck->ck_start, ck->ck_off, ck->ck_len); 1042 cklen = ck->ck_len ? ck->ck_len - ck->ck_start + 1 : INT_MAX; 1043 cksum = e82545_iov_checksum(iov, iovcnt, ck->ck_start, cklen); 1044 *(uint16_t *)((uint8_t *)iov[0].iov_base + ck->ck_off) = ~cksum; 1045 } 1046 1047 static void 1048 e82545_transmit_backend(struct e82545_softc *sc, struct iovec *iov, int iovcnt) 1049 { 1050 1051 if (sc->esc_be == NULL) 1052 return; 1053 1054 (void) netbe_send(sc->esc_be, iov, iovcnt); 1055 } 1056 1057 static void 1058 e82545_transmit_done(struct e82545_softc *sc, uint16_t head, uint16_t tail, 1059 uint16_t dsize, int *tdwb) 1060 { 1061 union e1000_tx_udesc *dsc; 1062 1063 for ( ; head != tail; head = (head + 1) % dsize) { 1064 dsc = &sc->esc_txdesc[head]; 1065 if (dsc->td.lower.data & E1000_TXD_CMD_RS) { 1066 dsc->td.upper.data |= E1000_TXD_STAT_DD; 1067 *tdwb = 1; 1068 } 1069 } 1070 } 1071 1072 static int 1073 e82545_transmit(struct e82545_softc *sc, uint16_t head, uint16_t tail, 1074 uint16_t dsize, uint16_t *rhead, int *tdwb) 1075 { 1076 uint8_t *hdr, *hdrp; 1077 struct iovec iovb[I82545_MAX_TXSEGS + 2]; 1078 struct iovec tiov[I82545_MAX_TXSEGS + 2]; 1079 struct e1000_context_desc *cd; 1080 struct ck_info ckinfo[2]; 1081 struct iovec *iov; 1082 union e1000_tx_udesc *dsc; 1083 int desc, dtype, len, ntype, iovcnt, tlen, hdrlen, vlen, tcp, tso; 1084 int mss, paylen, seg, tiovcnt, left, now, nleft, nnow, pv, pvoff; 1085 uint32_t tcpsum, tcpseq; 1086 uint16_t ipcs, tcpcs, ipid, ohead; 1087 1088 ckinfo[0].ck_valid = ckinfo[1].ck_valid = 0; 1089 iovcnt = 0; 1090 tlen = 0; 1091 ntype = 0; 1092 tso = 0; 1093 ohead = head; 1094 1095 /* iovb[0/1] may be used for writable copy of headers. */ 1096 iov = &iovb[2]; 1097 1098 for (desc = 0; ; desc++, head = (head + 1) % dsize) { 1099 if (head == tail) { 1100 *rhead = head; 1101 return (0); 1102 } 1103 dsc = &sc->esc_txdesc[head]; 1104 dtype = e82545_txdesc_type(dsc->td.lower.data); 1105 1106 if (desc == 0) { 1107 switch (dtype) { 1108 case E1000_TXD_TYP_C: 1109 DPRINTF("tx ctxt desc idx %d: %016jx " 1110 "%08x%08x\r\n", 1111 head, dsc->td.buffer_addr, 1112 dsc->td.upper.data, dsc->td.lower.data); 1113 /* Save context and return */ 1114 sc->esc_txctx = dsc->cd; 1115 goto done; 1116 case E1000_TXD_TYP_L: 1117 DPRINTF("tx legacy desc idx %d: %08x%08x\r\n", 1118 head, dsc->td.upper.data, dsc->td.lower.data); 1119 /* 1120 * legacy cksum start valid in first descriptor 1121 */ 1122 ntype = dtype; 1123 ckinfo[0].ck_start = dsc->td.upper.fields.css; 1124 break; 1125 case E1000_TXD_TYP_D: 1126 DPRINTF("tx data desc idx %d: %08x%08x\r\n", 1127 head, dsc->td.upper.data, dsc->td.lower.data); 1128 ntype = dtype; 1129 break; 1130 default: 1131 break; 1132 } 1133 } else { 1134 /* Descriptor type must be consistent */ 1135 assert(dtype == ntype); 1136 DPRINTF("tx next desc idx %d: %08x%08x\r\n", 1137 head, dsc->td.upper.data, dsc->td.lower.data); 1138 } 1139 1140 len = (dtype == E1000_TXD_TYP_L) ? dsc->td.lower.flags.length : 1141 dsc->dd.lower.data & 0xFFFFF; 1142 1143 if (len > 0) { 1144 /* Strip checksum supplied by guest. */ 1145 if ((dsc->td.lower.data & E1000_TXD_CMD_EOP) != 0 && 1146 (dsc->td.lower.data & E1000_TXD_CMD_IFCS) == 0) 1147 len -= 2; 1148 tlen += len; 1149 if (iovcnt < I82545_MAX_TXSEGS) { 1150 iov[iovcnt].iov_base = paddr_guest2host( 1151 sc->esc_ctx, dsc->td.buffer_addr, len); 1152 iov[iovcnt].iov_len = len; 1153 } 1154 iovcnt++; 1155 } 1156 1157 /* 1158 * Pull out info that is valid in the final descriptor 1159 * and exit descriptor loop. 1160 */ 1161 if (dsc->td.lower.data & E1000_TXD_CMD_EOP) { 1162 if (dtype == E1000_TXD_TYP_L) { 1163 if (dsc->td.lower.data & E1000_TXD_CMD_IC) { 1164 ckinfo[0].ck_valid = 1; 1165 ckinfo[0].ck_off = 1166 dsc->td.lower.flags.cso; 1167 ckinfo[0].ck_len = 0; 1168 } 1169 } else { 1170 cd = &sc->esc_txctx; 1171 if (dsc->dd.lower.data & E1000_TXD_CMD_TSE) 1172 tso = 1; 1173 if (dsc->dd.upper.fields.popts & 1174 E1000_TXD_POPTS_IXSM) 1175 ckinfo[0].ck_valid = 1; 1176 if (dsc->dd.upper.fields.popts & 1177 E1000_TXD_POPTS_IXSM || tso) { 1178 ckinfo[0].ck_start = 1179 cd->lower_setup.ip_fields.ipcss; 1180 ckinfo[0].ck_off = 1181 cd->lower_setup.ip_fields.ipcso; 1182 ckinfo[0].ck_len = 1183 cd->lower_setup.ip_fields.ipcse; 1184 } 1185 if (dsc->dd.upper.fields.popts & 1186 E1000_TXD_POPTS_TXSM) 1187 ckinfo[1].ck_valid = 1; 1188 if (dsc->dd.upper.fields.popts & 1189 E1000_TXD_POPTS_TXSM || tso) { 1190 ckinfo[1].ck_start = 1191 cd->upper_setup.tcp_fields.tucss; 1192 ckinfo[1].ck_off = 1193 cd->upper_setup.tcp_fields.tucso; 1194 ckinfo[1].ck_len = 1195 cd->upper_setup.tcp_fields.tucse; 1196 } 1197 } 1198 break; 1199 } 1200 } 1201 1202 if (iovcnt > I82545_MAX_TXSEGS) { 1203 WPRINTF("tx too many descriptors (%d > %d) -- dropped\r\n", 1204 iovcnt, I82545_MAX_TXSEGS); 1205 goto done; 1206 } 1207 1208 hdrlen = vlen = 0; 1209 /* Estimate writable space for VLAN header insertion. */ 1210 if ((sc->esc_CTRL & E1000_CTRL_VME) && 1211 (dsc->td.lower.data & E1000_TXD_CMD_VLE)) { 1212 hdrlen = ETHER_ADDR_LEN*2; 1213 vlen = ETHER_VLAN_ENCAP_LEN; 1214 } 1215 if (!tso) { 1216 /* Estimate required writable space for checksums. */ 1217 if (ckinfo[0].ck_valid) 1218 hdrlen = MAX(hdrlen, ckinfo[0].ck_off + 2); 1219 if (ckinfo[1].ck_valid) 1220 hdrlen = MAX(hdrlen, ckinfo[1].ck_off + 2); 1221 /* Round up writable space to the first vector. */ 1222 if (hdrlen != 0 && iov[0].iov_len > hdrlen && 1223 iov[0].iov_len < hdrlen + 100) 1224 hdrlen = iov[0].iov_len; 1225 } else { 1226 /* In case of TSO header length provided by software. */ 1227 hdrlen = sc->esc_txctx.tcp_seg_setup.fields.hdr_len; 1228 } 1229 1230 /* Allocate, fill and prepend writable header vector. */ 1231 if (hdrlen != 0) { 1232 hdr = __builtin_alloca(hdrlen + vlen); 1233 hdr += vlen; 1234 for (left = hdrlen, hdrp = hdr; left > 0; 1235 left -= now, hdrp += now) { 1236 now = MIN(left, iov->iov_len); 1237 memcpy(hdrp, iov->iov_base, now); 1238 iov->iov_base += now; 1239 iov->iov_len -= now; 1240 if (iov->iov_len == 0) { 1241 iov++; 1242 iovcnt--; 1243 } 1244 } 1245 iov--; 1246 iovcnt++; 1247 iov->iov_base = hdr; 1248 iov->iov_len = hdrlen; 1249 } 1250 1251 /* Insert VLAN tag. */ 1252 if (vlen != 0) { 1253 hdr -= ETHER_VLAN_ENCAP_LEN; 1254 memmove(hdr, hdr + ETHER_VLAN_ENCAP_LEN, ETHER_ADDR_LEN*2); 1255 hdrlen += ETHER_VLAN_ENCAP_LEN; 1256 hdr[ETHER_ADDR_LEN*2 + 0] = sc->esc_VET >> 8; 1257 hdr[ETHER_ADDR_LEN*2 + 1] = sc->esc_VET & 0xff; 1258 hdr[ETHER_ADDR_LEN*2 + 2] = dsc->td.upper.fields.special >> 8; 1259 hdr[ETHER_ADDR_LEN*2 + 3] = dsc->td.upper.fields.special & 0xff; 1260 iov->iov_base = hdr; 1261 iov->iov_len += ETHER_VLAN_ENCAP_LEN; 1262 /* Correct checksum offsets after VLAN tag insertion. */ 1263 ckinfo[0].ck_start += ETHER_VLAN_ENCAP_LEN; 1264 ckinfo[0].ck_off += ETHER_VLAN_ENCAP_LEN; 1265 if (ckinfo[0].ck_len != 0) 1266 ckinfo[0].ck_len += ETHER_VLAN_ENCAP_LEN; 1267 ckinfo[1].ck_start += ETHER_VLAN_ENCAP_LEN; 1268 ckinfo[1].ck_off += ETHER_VLAN_ENCAP_LEN; 1269 if (ckinfo[1].ck_len != 0) 1270 ckinfo[1].ck_len += ETHER_VLAN_ENCAP_LEN; 1271 } 1272 1273 /* Simple non-TSO case. */ 1274 if (!tso) { 1275 /* Calculate checksums and transmit. */ 1276 if (ckinfo[0].ck_valid) 1277 e82545_transmit_checksum(iov, iovcnt, &ckinfo[0]); 1278 if (ckinfo[1].ck_valid) 1279 e82545_transmit_checksum(iov, iovcnt, &ckinfo[1]); 1280 e82545_transmit_backend(sc, iov, iovcnt); 1281 goto done; 1282 } 1283 1284 /* Doing TSO. */ 1285 tcp = (sc->esc_txctx.cmd_and_length & E1000_TXD_CMD_TCP) != 0; 1286 mss = sc->esc_txctx.tcp_seg_setup.fields.mss; 1287 paylen = (sc->esc_txctx.cmd_and_length & 0x000fffff); 1288 DPRINTF("tx %s segmentation offload %d+%d/%d bytes %d iovs\r\n", 1289 tcp ? "TCP" : "UDP", hdrlen, paylen, mss, iovcnt); 1290 ipid = ntohs(*(uint16_t *)&hdr[ckinfo[0].ck_start + 4]); 1291 tcpseq = ntohl(*(uint32_t *)&hdr[ckinfo[1].ck_start + 4]); 1292 ipcs = *(uint16_t *)&hdr[ckinfo[0].ck_off]; 1293 tcpcs = 0; 1294 if (ckinfo[1].ck_valid) /* Save partial pseudo-header checksum. */ 1295 tcpcs = *(uint16_t *)&hdr[ckinfo[1].ck_off]; 1296 pv = 1; 1297 pvoff = 0; 1298 for (seg = 0, left = paylen; left > 0; seg++, left -= now) { 1299 now = MIN(left, mss); 1300 1301 /* Construct IOVs for the segment. */ 1302 /* Include whole original header. */ 1303 tiov[0].iov_base = hdr; 1304 tiov[0].iov_len = hdrlen; 1305 tiovcnt = 1; 1306 /* Include respective part of payload IOV. */ 1307 for (nleft = now; pv < iovcnt && nleft > 0; nleft -= nnow) { 1308 nnow = MIN(nleft, iov[pv].iov_len - pvoff); 1309 tiov[tiovcnt].iov_base = iov[pv].iov_base + pvoff; 1310 tiov[tiovcnt++].iov_len = nnow; 1311 if (pvoff + nnow == iov[pv].iov_len) { 1312 pv++; 1313 pvoff = 0; 1314 } else 1315 pvoff += nnow; 1316 } 1317 DPRINTF("tx segment %d %d+%d bytes %d iovs\r\n", 1318 seg, hdrlen, now, tiovcnt); 1319 1320 /* Update IP header. */ 1321 if (sc->esc_txctx.cmd_and_length & E1000_TXD_CMD_IP) { 1322 /* IPv4 -- set length and ID */ 1323 *(uint16_t *)&hdr[ckinfo[0].ck_start + 2] = 1324 htons(hdrlen - ckinfo[0].ck_start + now); 1325 *(uint16_t *)&hdr[ckinfo[0].ck_start + 4] = 1326 htons(ipid + seg); 1327 } else { 1328 /* IPv6 -- set length */ 1329 *(uint16_t *)&hdr[ckinfo[0].ck_start + 4] = 1330 htons(hdrlen - ckinfo[0].ck_start - 40 + 1331 now); 1332 } 1333 1334 /* Update pseudo-header checksum. */ 1335 tcpsum = tcpcs; 1336 tcpsum += htons(hdrlen - ckinfo[1].ck_start + now); 1337 1338 /* Update TCP/UDP headers. */ 1339 if (tcp) { 1340 /* Update sequence number and FIN/PUSH flags. */ 1341 *(uint32_t *)&hdr[ckinfo[1].ck_start + 4] = 1342 htonl(tcpseq + paylen - left); 1343 if (now < left) { 1344 hdr[ckinfo[1].ck_start + 13] &= 1345 ~(TH_FIN | TH_PUSH); 1346 } 1347 } else { 1348 /* Update payload length. */ 1349 *(uint32_t *)&hdr[ckinfo[1].ck_start + 4] = 1350 hdrlen - ckinfo[1].ck_start + now; 1351 } 1352 1353 /* Calculate checksums and transmit. */ 1354 if (ckinfo[0].ck_valid) { 1355 *(uint16_t *)&hdr[ckinfo[0].ck_off] = ipcs; 1356 e82545_transmit_checksum(tiov, tiovcnt, &ckinfo[0]); 1357 } 1358 if (ckinfo[1].ck_valid) { 1359 *(uint16_t *)&hdr[ckinfo[1].ck_off] = 1360 e82545_carry(tcpsum); 1361 e82545_transmit_checksum(tiov, tiovcnt, &ckinfo[1]); 1362 } 1363 e82545_transmit_backend(sc, tiov, tiovcnt); 1364 } 1365 1366 done: 1367 head = (head + 1) % dsize; 1368 e82545_transmit_done(sc, ohead, head, dsize, tdwb); 1369 1370 *rhead = head; 1371 return (desc + 1); 1372 } 1373 1374 static void 1375 e82545_tx_run(struct e82545_softc *sc) 1376 { 1377 uint32_t cause; 1378 uint16_t head, rhead, tail, size; 1379 int lim, tdwb, sent; 1380 1381 head = sc->esc_TDH; 1382 tail = sc->esc_TDT; 1383 size = sc->esc_TDLEN / 16; 1384 DPRINTF("tx_run: head %x, rhead %x, tail %x\r\n", 1385 sc->esc_TDH, sc->esc_TDHr, sc->esc_TDT); 1386 1387 pthread_mutex_unlock(&sc->esc_mtx); 1388 rhead = head; 1389 tdwb = 0; 1390 for (lim = size / 4; sc->esc_tx_enabled && lim > 0; lim -= sent) { 1391 sent = e82545_transmit(sc, head, tail, size, &rhead, &tdwb); 1392 if (sent == 0) 1393 break; 1394 head = rhead; 1395 } 1396 pthread_mutex_lock(&sc->esc_mtx); 1397 1398 sc->esc_TDH = head; 1399 sc->esc_TDHr = rhead; 1400 cause = 0; 1401 if (tdwb) 1402 cause |= E1000_ICR_TXDW; 1403 if (lim != size / 4 && sc->esc_TDH == sc->esc_TDT) 1404 cause |= E1000_ICR_TXQE; 1405 if (cause) 1406 e82545_icr_assert(sc, cause); 1407 1408 DPRINTF("tx_run done: head %x, rhead %x, tail %x\r\n", 1409 sc->esc_TDH, sc->esc_TDHr, sc->esc_TDT); 1410 } 1411 1412 static _Noreturn void * 1413 e82545_tx_thread(void *param) 1414 { 1415 struct e82545_softc *sc = param; 1416 1417 pthread_mutex_lock(&sc->esc_mtx); 1418 for (;;) { 1419 while (!sc->esc_tx_enabled || sc->esc_TDHr == sc->esc_TDT) { 1420 if (sc->esc_tx_enabled && sc->esc_TDHr != sc->esc_TDT) 1421 break; 1422 sc->esc_tx_active = 0; 1423 if (sc->esc_tx_enabled == 0) 1424 pthread_cond_signal(&sc->esc_tx_cond); 1425 pthread_cond_wait(&sc->esc_tx_cond, &sc->esc_mtx); 1426 } 1427 sc->esc_tx_active = 1; 1428 1429 /* Process some tx descriptors. Lock dropped inside. */ 1430 e82545_tx_run(sc); 1431 } 1432 } 1433 1434 static void 1435 e82545_tx_start(struct e82545_softc *sc) 1436 { 1437 1438 if (sc->esc_tx_active == 0) 1439 pthread_cond_signal(&sc->esc_tx_cond); 1440 } 1441 1442 static void 1443 e82545_tx_enable(struct e82545_softc *sc) 1444 { 1445 1446 sc->esc_tx_enabled = 1; 1447 } 1448 1449 static void 1450 e82545_tx_disable(struct e82545_softc *sc) 1451 { 1452 1453 sc->esc_tx_enabled = 0; 1454 while (sc->esc_tx_active) 1455 pthread_cond_wait(&sc->esc_tx_cond, &sc->esc_mtx); 1456 } 1457 1458 static void 1459 e82545_rx_enable(struct e82545_softc *sc) 1460 { 1461 1462 sc->esc_rx_enabled = 1; 1463 } 1464 1465 static void 1466 e82545_rx_disable(struct e82545_softc *sc) 1467 { 1468 1469 sc->esc_rx_enabled = 0; 1470 while (sc->esc_rx_active) 1471 pthread_cond_wait(&sc->esc_rx_cond, &sc->esc_mtx); 1472 } 1473 1474 static void 1475 e82545_write_ra(struct e82545_softc *sc, int reg, uint32_t wval) 1476 { 1477 struct eth_uni *eu; 1478 int idx; 1479 1480 idx = reg >> 1; 1481 assert(idx < 15); 1482 1483 eu = &sc->esc_uni[idx]; 1484 1485 if (reg & 0x1) { 1486 /* RAH */ 1487 eu->eu_valid = ((wval & E1000_RAH_AV) == E1000_RAH_AV); 1488 eu->eu_addrsel = (wval >> 16) & 0x3; 1489 eu->eu_eth.octet[5] = wval >> 8; 1490 eu->eu_eth.octet[4] = wval; 1491 } else { 1492 /* RAL */ 1493 eu->eu_eth.octet[3] = wval >> 24; 1494 eu->eu_eth.octet[2] = wval >> 16; 1495 eu->eu_eth.octet[1] = wval >> 8; 1496 eu->eu_eth.octet[0] = wval; 1497 } 1498 } 1499 1500 static uint32_t 1501 e82545_read_ra(struct e82545_softc *sc, int reg) 1502 { 1503 struct eth_uni *eu; 1504 uint32_t retval; 1505 int idx; 1506 1507 idx = reg >> 1; 1508 assert(idx < 15); 1509 1510 eu = &sc->esc_uni[idx]; 1511 1512 if (reg & 0x1) { 1513 /* RAH */ 1514 retval = (eu->eu_valid << 31) | 1515 (eu->eu_addrsel << 16) | 1516 (eu->eu_eth.octet[5] << 8) | 1517 eu->eu_eth.octet[4]; 1518 } else { 1519 /* RAL */ 1520 retval = (eu->eu_eth.octet[3] << 24) | 1521 (eu->eu_eth.octet[2] << 16) | 1522 (eu->eu_eth.octet[1] << 8) | 1523 eu->eu_eth.octet[0]; 1524 } 1525 1526 return (retval); 1527 } 1528 1529 static void 1530 e82545_write_register(struct e82545_softc *sc, uint32_t offset, uint32_t value) 1531 { 1532 int ridx; 1533 1534 if (offset & 0x3) { 1535 DPRINTF("Unaligned register write offset:0x%x value:0x%x\r\n", offset, value); 1536 return; 1537 } 1538 DPRINTF("Register write: 0x%x value: 0x%x\r\n", offset, value); 1539 1540 switch (offset) { 1541 case E1000_CTRL: 1542 case E1000_CTRL_DUP: 1543 e82545_devctl(sc, value); 1544 break; 1545 case E1000_FCAL: 1546 sc->esc_FCAL = value; 1547 break; 1548 case E1000_FCAH: 1549 sc->esc_FCAH = value & ~0xFFFF0000; 1550 break; 1551 case E1000_FCT: 1552 sc->esc_FCT = value & ~0xFFFF0000; 1553 break; 1554 case E1000_VET: 1555 sc->esc_VET = value & ~0xFFFF0000; 1556 break; 1557 case E1000_FCTTV: 1558 sc->esc_FCTTV = value & ~0xFFFF0000; 1559 break; 1560 case E1000_LEDCTL: 1561 sc->esc_LEDCTL = value & ~0x30303000; 1562 break; 1563 case E1000_PBA: 1564 sc->esc_PBA = value & 0x0000FF80; 1565 break; 1566 case E1000_ICR: 1567 case E1000_ITR: 1568 case E1000_ICS: 1569 case E1000_IMS: 1570 case E1000_IMC: 1571 e82545_intr_write(sc, offset, value); 1572 break; 1573 case E1000_RCTL: 1574 e82545_rx_ctl(sc, value); 1575 break; 1576 case E1000_FCRTL: 1577 sc->esc_FCRTL = value & ~0xFFFF0007; 1578 break; 1579 case E1000_FCRTH: 1580 sc->esc_FCRTH = value & ~0xFFFF0007; 1581 break; 1582 case E1000_RDBAL(0): 1583 sc->esc_RDBAL = value & ~0xF; 1584 if (sc->esc_rx_enabled) { 1585 /* Apparently legal: update cached address */ 1586 e82545_rx_update_rdba(sc); 1587 } 1588 break; 1589 case E1000_RDBAH(0): 1590 assert(!sc->esc_rx_enabled); 1591 sc->esc_RDBAH = value; 1592 break; 1593 case E1000_RDLEN(0): 1594 assert(!sc->esc_rx_enabled); 1595 sc->esc_RDLEN = value & ~0xFFF0007F; 1596 break; 1597 case E1000_RDH(0): 1598 /* XXX should only ever be zero ? Range check ? */ 1599 sc->esc_RDH = value; 1600 break; 1601 case E1000_RDT(0): 1602 /* XXX if this opens up the rx ring, do something ? */ 1603 sc->esc_RDT = value; 1604 break; 1605 case E1000_RDTR: 1606 /* ignore FPD bit 31 */ 1607 sc->esc_RDTR = value & ~0xFFFF0000; 1608 break; 1609 case E1000_RXDCTL(0): 1610 sc->esc_RXDCTL = value & ~0xFEC0C0C0; 1611 break; 1612 case E1000_RADV: 1613 sc->esc_RADV = value & ~0xFFFF0000; 1614 break; 1615 case E1000_RSRPD: 1616 sc->esc_RSRPD = value & ~0xFFFFF000; 1617 break; 1618 case E1000_RXCSUM: 1619 sc->esc_RXCSUM = value & ~0xFFFFF800; 1620 break; 1621 case E1000_TXCW: 1622 sc->esc_TXCW = value & ~0x3FFF0000; 1623 break; 1624 case E1000_TCTL: 1625 e82545_tx_ctl(sc, value); 1626 break; 1627 case E1000_TIPG: 1628 sc->esc_TIPG = value; 1629 break; 1630 case E1000_AIT: 1631 sc->esc_AIT = value; 1632 break; 1633 case E1000_TDBAL(0): 1634 sc->esc_TDBAL = value & ~0xF; 1635 if (sc->esc_tx_enabled) { 1636 /* Apparently legal */ 1637 e82545_tx_update_tdba(sc); 1638 } 1639 break; 1640 case E1000_TDBAH(0): 1641 //assert(!sc->esc_tx_enabled); 1642 sc->esc_TDBAH = value; 1643 break; 1644 case E1000_TDLEN(0): 1645 //assert(!sc->esc_tx_enabled); 1646 sc->esc_TDLEN = value & ~0xFFF0007F; 1647 break; 1648 case E1000_TDH(0): 1649 //assert(!sc->esc_tx_enabled); 1650 /* XXX should only ever be zero ? Range check ? */ 1651 sc->esc_TDHr = sc->esc_TDH = value; 1652 break; 1653 case E1000_TDT(0): 1654 /* XXX range check ? */ 1655 sc->esc_TDT = value; 1656 if (sc->esc_tx_enabled) 1657 e82545_tx_start(sc); 1658 break; 1659 case E1000_TIDV: 1660 sc->esc_TIDV = value & ~0xFFFF0000; 1661 break; 1662 case E1000_TXDCTL(0): 1663 //assert(!sc->esc_tx_enabled); 1664 sc->esc_TXDCTL = value & ~0xC0C0C0; 1665 break; 1666 case E1000_TADV: 1667 sc->esc_TADV = value & ~0xFFFF0000; 1668 break; 1669 case E1000_RAL(0) ... E1000_RAH(15): 1670 /* convert to u32 offset */ 1671 ridx = (offset - E1000_RAL(0)) >> 2; 1672 e82545_write_ra(sc, ridx, value); 1673 break; 1674 case E1000_MTA ... (E1000_MTA + (127*4)): 1675 sc->esc_fmcast[(offset - E1000_MTA) >> 2] = value; 1676 break; 1677 case E1000_VFTA ... (E1000_VFTA + (127*4)): 1678 sc->esc_fvlan[(offset - E1000_VFTA) >> 2] = value; 1679 break; 1680 case E1000_EECD: 1681 { 1682 //DPRINTF("EECD write 0x%x -> 0x%x\r\n", sc->eeprom_control, value); 1683 /* edge triggered low->high */ 1684 uint32_t eecd_strobe = ((sc->eeprom_control & E1000_EECD_SK) ? 1685 0 : (value & E1000_EECD_SK)); 1686 uint32_t eecd_mask = (E1000_EECD_SK|E1000_EECD_CS| 1687 E1000_EECD_DI|E1000_EECD_REQ); 1688 sc->eeprom_control &= ~eecd_mask; 1689 sc->eeprom_control |= (value & eecd_mask); 1690 /* grant/revoke immediately */ 1691 if (value & E1000_EECD_REQ) { 1692 sc->eeprom_control |= E1000_EECD_GNT; 1693 } else { 1694 sc->eeprom_control &= ~E1000_EECD_GNT; 1695 } 1696 if (eecd_strobe && (sc->eeprom_control & E1000_EECD_CS)) { 1697 e82545_eecd_strobe(sc); 1698 } 1699 return; 1700 } 1701 case E1000_MDIC: 1702 { 1703 uint8_t reg_addr = (uint8_t)((value & E1000_MDIC_REG_MASK) >> 1704 E1000_MDIC_REG_SHIFT); 1705 uint8_t phy_addr = (uint8_t)((value & E1000_MDIC_PHY_MASK) >> 1706 E1000_MDIC_PHY_SHIFT); 1707 sc->mdi_control = 1708 (value & ~(E1000_MDIC_ERROR|E1000_MDIC_DEST)); 1709 if ((value & E1000_MDIC_READY) != 0) { 1710 DPRINTF("Incorrect MDIC ready bit: 0x%x\r\n", value); 1711 return; 1712 } 1713 switch (value & E82545_MDIC_OP_MASK) { 1714 case E1000_MDIC_OP_READ: 1715 sc->mdi_control &= ~E82545_MDIC_DATA_MASK; 1716 sc->mdi_control |= e82545_read_mdi(sc, reg_addr, phy_addr); 1717 break; 1718 case E1000_MDIC_OP_WRITE: 1719 e82545_write_mdi(sc, reg_addr, phy_addr, 1720 value & E82545_MDIC_DATA_MASK); 1721 break; 1722 default: 1723 DPRINTF("Unknown MDIC op: 0x%x\r\n", value); 1724 return; 1725 } 1726 /* TODO: barrier? */ 1727 sc->mdi_control |= E1000_MDIC_READY; 1728 if (value & E82545_MDIC_IE) { 1729 // TODO: generate interrupt 1730 } 1731 return; 1732 } 1733 case E1000_MANC: 1734 case E1000_STATUS: 1735 return; 1736 default: 1737 DPRINTF("Unknown write register: 0x%x value:%x\r\n", offset, value); 1738 return; 1739 } 1740 } 1741 1742 static uint32_t 1743 e82545_read_register(struct e82545_softc *sc, uint32_t offset) 1744 { 1745 uint32_t retval; 1746 int ridx; 1747 1748 if (offset & 0x3) { 1749 DPRINTF("Unaligned register read offset:0x%x\r\n", offset); 1750 return 0; 1751 } 1752 1753 DPRINTF("Register read: 0x%x\r\n", offset); 1754 1755 switch (offset) { 1756 case E1000_CTRL: 1757 retval = sc->esc_CTRL; 1758 break; 1759 case E1000_STATUS: 1760 retval = E1000_STATUS_FD | E1000_STATUS_LU | 1761 E1000_STATUS_SPEED_1000; 1762 break; 1763 case E1000_FCAL: 1764 retval = sc->esc_FCAL; 1765 break; 1766 case E1000_FCAH: 1767 retval = sc->esc_FCAH; 1768 break; 1769 case E1000_FCT: 1770 retval = sc->esc_FCT; 1771 break; 1772 case E1000_VET: 1773 retval = sc->esc_VET; 1774 break; 1775 case E1000_FCTTV: 1776 retval = sc->esc_FCTTV; 1777 break; 1778 case E1000_LEDCTL: 1779 retval = sc->esc_LEDCTL; 1780 break; 1781 case E1000_PBA: 1782 retval = sc->esc_PBA; 1783 break; 1784 case E1000_ICR: 1785 case E1000_ITR: 1786 case E1000_ICS: 1787 case E1000_IMS: 1788 case E1000_IMC: 1789 retval = e82545_intr_read(sc, offset); 1790 break; 1791 case E1000_RCTL: 1792 retval = sc->esc_RCTL; 1793 break; 1794 case E1000_FCRTL: 1795 retval = sc->esc_FCRTL; 1796 break; 1797 case E1000_FCRTH: 1798 retval = sc->esc_FCRTH; 1799 break; 1800 case E1000_RDBAL(0): 1801 retval = sc->esc_RDBAL; 1802 break; 1803 case E1000_RDBAH(0): 1804 retval = sc->esc_RDBAH; 1805 break; 1806 case E1000_RDLEN(0): 1807 retval = sc->esc_RDLEN; 1808 break; 1809 case E1000_RDH(0): 1810 retval = sc->esc_RDH; 1811 break; 1812 case E1000_RDT(0): 1813 retval = sc->esc_RDT; 1814 break; 1815 case E1000_RDTR: 1816 retval = sc->esc_RDTR; 1817 break; 1818 case E1000_RXDCTL(0): 1819 retval = sc->esc_RXDCTL; 1820 break; 1821 case E1000_RADV: 1822 retval = sc->esc_RADV; 1823 break; 1824 case E1000_RSRPD: 1825 retval = sc->esc_RSRPD; 1826 break; 1827 case E1000_RXCSUM: 1828 retval = sc->esc_RXCSUM; 1829 break; 1830 case E1000_TXCW: 1831 retval = sc->esc_TXCW; 1832 break; 1833 case E1000_TCTL: 1834 retval = sc->esc_TCTL; 1835 break; 1836 case E1000_TIPG: 1837 retval = sc->esc_TIPG; 1838 break; 1839 case E1000_AIT: 1840 retval = sc->esc_AIT; 1841 break; 1842 case E1000_TDBAL(0): 1843 retval = sc->esc_TDBAL; 1844 break; 1845 case E1000_TDBAH(0): 1846 retval = sc->esc_TDBAH; 1847 break; 1848 case E1000_TDLEN(0): 1849 retval = sc->esc_TDLEN; 1850 break; 1851 case E1000_TDH(0): 1852 retval = sc->esc_TDH; 1853 break; 1854 case E1000_TDT(0): 1855 retval = sc->esc_TDT; 1856 break; 1857 case E1000_TIDV: 1858 retval = sc->esc_TIDV; 1859 break; 1860 case E1000_TXDCTL(0): 1861 retval = sc->esc_TXDCTL; 1862 break; 1863 case E1000_TADV: 1864 retval = sc->esc_TADV; 1865 break; 1866 case E1000_RAL(0) ... E1000_RAH(15): 1867 /* convert to u32 offset */ 1868 ridx = (offset - E1000_RAL(0)) >> 2; 1869 retval = e82545_read_ra(sc, ridx); 1870 break; 1871 case E1000_MTA ... (E1000_MTA + (127*4)): 1872 retval = sc->esc_fmcast[(offset - E1000_MTA) >> 2]; 1873 break; 1874 case E1000_VFTA ... (E1000_VFTA + (127*4)): 1875 retval = sc->esc_fvlan[(offset - E1000_VFTA) >> 2]; 1876 break; 1877 case E1000_EECD: 1878 //DPRINTF("EECD read %x\r\n", sc->eeprom_control); 1879 retval = sc->eeprom_control; 1880 break; 1881 case E1000_MDIC: 1882 retval = sc->mdi_control; 1883 break; 1884 case E1000_MANC: 1885 retval = 0; 1886 break; 1887 /* stats that we emulate. */ 1888 case E1000_MPC: 1889 retval = sc->missed_pkt_count; 1890 break; 1891 case E1000_PRC64: 1892 retval = sc->pkt_rx_by_size[0]; 1893 break; 1894 case E1000_PRC127: 1895 retval = sc->pkt_rx_by_size[1]; 1896 break; 1897 case E1000_PRC255: 1898 retval = sc->pkt_rx_by_size[2]; 1899 break; 1900 case E1000_PRC511: 1901 retval = sc->pkt_rx_by_size[3]; 1902 break; 1903 case E1000_PRC1023: 1904 retval = sc->pkt_rx_by_size[4]; 1905 break; 1906 case E1000_PRC1522: 1907 retval = sc->pkt_rx_by_size[5]; 1908 break; 1909 case E1000_GPRC: 1910 retval = sc->good_pkt_rx_count; 1911 break; 1912 case E1000_BPRC: 1913 retval = sc->bcast_pkt_rx_count; 1914 break; 1915 case E1000_MPRC: 1916 retval = sc->mcast_pkt_rx_count; 1917 break; 1918 case E1000_GPTC: 1919 case E1000_TPT: 1920 retval = sc->good_pkt_tx_count; 1921 break; 1922 case E1000_GORCL: 1923 retval = (uint32_t)sc->good_octets_rx; 1924 break; 1925 case E1000_GORCH: 1926 retval = (uint32_t)(sc->good_octets_rx >> 32); 1927 break; 1928 case E1000_TOTL: 1929 case E1000_GOTCL: 1930 retval = (uint32_t)sc->good_octets_tx; 1931 break; 1932 case E1000_TOTH: 1933 case E1000_GOTCH: 1934 retval = (uint32_t)(sc->good_octets_tx >> 32); 1935 break; 1936 case E1000_ROC: 1937 retval = sc->oversize_rx_count; 1938 break; 1939 case E1000_TORL: 1940 retval = (uint32_t)(sc->good_octets_rx + sc->missed_octets); 1941 break; 1942 case E1000_TORH: 1943 retval = (uint32_t)((sc->good_octets_rx + 1944 sc->missed_octets) >> 32); 1945 break; 1946 case E1000_TPR: 1947 retval = sc->good_pkt_rx_count + sc->missed_pkt_count + 1948 sc->oversize_rx_count; 1949 break; 1950 case E1000_PTC64: 1951 retval = sc->pkt_tx_by_size[0]; 1952 break; 1953 case E1000_PTC127: 1954 retval = sc->pkt_tx_by_size[1]; 1955 break; 1956 case E1000_PTC255: 1957 retval = sc->pkt_tx_by_size[2]; 1958 break; 1959 case E1000_PTC511: 1960 retval = sc->pkt_tx_by_size[3]; 1961 break; 1962 case E1000_PTC1023: 1963 retval = sc->pkt_tx_by_size[4]; 1964 break; 1965 case E1000_PTC1522: 1966 retval = sc->pkt_tx_by_size[5]; 1967 break; 1968 case E1000_MPTC: 1969 retval = sc->mcast_pkt_tx_count; 1970 break; 1971 case E1000_BPTC: 1972 retval = sc->bcast_pkt_tx_count; 1973 break; 1974 case E1000_TSCTC: 1975 retval = sc->tso_tx_count; 1976 break; 1977 /* stats that are always 0. */ 1978 case E1000_CRCERRS: 1979 case E1000_ALGNERRC: 1980 case E1000_SYMERRS: 1981 case E1000_RXERRC: 1982 case E1000_SCC: 1983 case E1000_ECOL: 1984 case E1000_MCC: 1985 case E1000_LATECOL: 1986 case E1000_COLC: 1987 case E1000_DC: 1988 case E1000_TNCRS: 1989 case E1000_SEC: 1990 case E1000_CEXTERR: 1991 case E1000_RLEC: 1992 case E1000_XONRXC: 1993 case E1000_XONTXC: 1994 case E1000_XOFFRXC: 1995 case E1000_XOFFTXC: 1996 case E1000_FCRUC: 1997 case E1000_RNBC: 1998 case E1000_RUC: 1999 case E1000_RFC: 2000 case E1000_RJC: 2001 case E1000_MGTPRC: 2002 case E1000_MGTPDC: 2003 case E1000_MGTPTC: 2004 case E1000_TSCTFC: 2005 retval = 0; 2006 break; 2007 default: 2008 DPRINTF("Unknown read register: 0x%x\r\n", offset); 2009 retval = 0; 2010 break; 2011 } 2012 2013 return (retval); 2014 } 2015 2016 static void 2017 e82545_write(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, int baridx, 2018 uint64_t offset, int size, uint64_t value) 2019 { 2020 struct e82545_softc *sc; 2021 2022 //DPRINTF("Write bar:%d offset:0x%lx value:0x%lx size:%d\r\n", baridx, offset, value, size); 2023 2024 sc = pi->pi_arg; 2025 2026 pthread_mutex_lock(&sc->esc_mtx); 2027 2028 switch (baridx) { 2029 case E82545_BAR_IO: 2030 switch (offset) { 2031 case E82545_IOADDR: 2032 if (size != 4) { 2033 DPRINTF("Wrong io addr write sz:%d value:0x%lx\r\n", size, value); 2034 } else 2035 sc->io_addr = (uint32_t)value; 2036 break; 2037 case E82545_IODATA: 2038 if (size != 4) { 2039 DPRINTF("Wrong io data write size:%d value:0x%lx\r\n", size, value); 2040 } else if (sc->io_addr > E82545_IO_REGISTER_MAX) { 2041 DPRINTF("Non-register io write addr:0x%x value:0x%lx\r\n", sc->io_addr, value); 2042 } else 2043 e82545_write_register(sc, sc->io_addr, 2044 (uint32_t)value); 2045 break; 2046 default: 2047 DPRINTF("Unknown io bar write offset:0x%lx value:0x%lx size:%d\r\n", offset, value, size); 2048 break; 2049 } 2050 break; 2051 case E82545_BAR_REGISTER: 2052 if (size != 4) { 2053 DPRINTF("Wrong register write size:%d offset:0x%lx value:0x%lx\r\n", size, offset, value); 2054 } else 2055 e82545_write_register(sc, (uint32_t)offset, 2056 (uint32_t)value); 2057 break; 2058 default: 2059 DPRINTF("Unknown write bar:%d off:0x%lx val:0x%lx size:%d\r\n", 2060 baridx, offset, value, size); 2061 } 2062 2063 pthread_mutex_unlock(&sc->esc_mtx); 2064 } 2065 2066 static uint64_t 2067 e82545_read(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, int baridx, 2068 uint64_t offset, int size) 2069 { 2070 struct e82545_softc *sc; 2071 uint64_t retval; 2072 2073 //DPRINTF("Read bar:%d offset:0x%lx size:%d\r\n", baridx, offset, size); 2074 sc = pi->pi_arg; 2075 retval = 0; 2076 2077 pthread_mutex_lock(&sc->esc_mtx); 2078 2079 switch (baridx) { 2080 case E82545_BAR_IO: 2081 switch (offset) { 2082 case E82545_IOADDR: 2083 if (size != 4) { 2084 DPRINTF("Wrong io addr read sz:%d\r\n", size); 2085 } else 2086 retval = sc->io_addr; 2087 break; 2088 case E82545_IODATA: 2089 if (size != 4) { 2090 DPRINTF("Wrong io data read sz:%d\r\n", size); 2091 } 2092 if (sc->io_addr > E82545_IO_REGISTER_MAX) { 2093 DPRINTF("Non-register io read addr:0x%x\r\n", 2094 sc->io_addr); 2095 } else 2096 retval = e82545_read_register(sc, sc->io_addr); 2097 break; 2098 default: 2099 DPRINTF("Unknown io bar read offset:0x%lx size:%d\r\n", 2100 offset, size); 2101 break; 2102 } 2103 break; 2104 case E82545_BAR_REGISTER: 2105 if (size != 4) { 2106 DPRINTF("Wrong register read size:%d offset:0x%lx\r\n", 2107 size, offset); 2108 } else 2109 retval = e82545_read_register(sc, (uint32_t)offset); 2110 break; 2111 default: 2112 DPRINTF("Unknown read bar:%d offset:0x%lx size:%d\r\n", 2113 baridx, offset, size); 2114 break; 2115 } 2116 2117 pthread_mutex_unlock(&sc->esc_mtx); 2118 2119 return (retval); 2120 } 2121 2122 static void 2123 e82545_reset(struct e82545_softc *sc, int drvr) 2124 { 2125 int i; 2126 2127 e82545_rx_disable(sc); 2128 e82545_tx_disable(sc); 2129 2130 /* clear outstanding interrupts */ 2131 if (sc->esc_irq_asserted) 2132 pci_lintr_deassert(sc->esc_pi); 2133 2134 /* misc */ 2135 if (!drvr) { 2136 sc->esc_FCAL = 0; 2137 sc->esc_FCAH = 0; 2138 sc->esc_FCT = 0; 2139 sc->esc_VET = 0; 2140 sc->esc_FCTTV = 0; 2141 } 2142 sc->esc_LEDCTL = 0x07061302; 2143 sc->esc_PBA = 0x00100030; 2144 2145 /* start nvm in opcode mode. */ 2146 sc->nvm_opaddr = 0; 2147 sc->nvm_mode = E82545_NVM_MODE_OPADDR; 2148 sc->nvm_bits = E82545_NVM_OPADDR_BITS; 2149 sc->eeprom_control = E1000_EECD_PRES | E82545_EECD_FWE_EN; 2150 e82545_init_eeprom(sc); 2151 2152 /* interrupt */ 2153 sc->esc_ICR = 0; 2154 sc->esc_ITR = 250; 2155 sc->esc_ICS = 0; 2156 sc->esc_IMS = 0; 2157 sc->esc_IMC = 0; 2158 2159 /* L2 filters */ 2160 if (!drvr) { 2161 memset(sc->esc_fvlan, 0, sizeof(sc->esc_fvlan)); 2162 memset(sc->esc_fmcast, 0, sizeof(sc->esc_fmcast)); 2163 memset(sc->esc_uni, 0, sizeof(sc->esc_uni)); 2164 2165 /* XXX not necessary on 82545 ?? */ 2166 sc->esc_uni[0].eu_valid = 1; 2167 memcpy(sc->esc_uni[0].eu_eth.octet, sc->esc_mac.octet, 2168 ETHER_ADDR_LEN); 2169 } else { 2170 /* Clear RAH valid bits */ 2171 for (i = 0; i < 16; i++) 2172 sc->esc_uni[i].eu_valid = 0; 2173 } 2174 2175 /* receive */ 2176 if (!drvr) { 2177 sc->esc_RDBAL = 0; 2178 sc->esc_RDBAH = 0; 2179 } 2180 sc->esc_RCTL = 0; 2181 sc->esc_FCRTL = 0; 2182 sc->esc_FCRTH = 0; 2183 sc->esc_RDLEN = 0; 2184 sc->esc_RDH = 0; 2185 sc->esc_RDT = 0; 2186 sc->esc_RDTR = 0; 2187 sc->esc_RXDCTL = (1 << 24) | (1 << 16); /* default GRAN/WTHRESH */ 2188 sc->esc_RADV = 0; 2189 sc->esc_RXCSUM = 0; 2190 2191 /* transmit */ 2192 if (!drvr) { 2193 sc->esc_TDBAL = 0; 2194 sc->esc_TDBAH = 0; 2195 sc->esc_TIPG = 0; 2196 sc->esc_AIT = 0; 2197 sc->esc_TIDV = 0; 2198 sc->esc_TADV = 0; 2199 } 2200 sc->esc_tdba = 0; 2201 sc->esc_txdesc = NULL; 2202 sc->esc_TXCW = 0; 2203 sc->esc_TCTL = 0; 2204 sc->esc_TDLEN = 0; 2205 sc->esc_TDT = 0; 2206 sc->esc_TDHr = sc->esc_TDH = 0; 2207 sc->esc_TXDCTL = 0; 2208 } 2209 2210 static int 2211 e82545_init(struct vmctx *ctx, struct pci_devinst *pi, char *opts) 2212 { 2213 char nstr[80]; 2214 struct e82545_softc *sc; 2215 char *devname; 2216 char *vtopts; 2217 int mac_provided; 2218 2219 DPRINTF("Loading with options: %s\r\n", opts); 2220 2221 /* Setup our softc */ 2222 sc = calloc(1, sizeof(*sc)); 2223 2224 pi->pi_arg = sc; 2225 sc->esc_pi = pi; 2226 sc->esc_ctx = ctx; 2227 2228 pthread_mutex_init(&sc->esc_mtx, NULL); 2229 pthread_cond_init(&sc->esc_rx_cond, NULL); 2230 pthread_cond_init(&sc->esc_tx_cond, NULL); 2231 pthread_create(&sc->esc_tx_tid, NULL, e82545_tx_thread, sc); 2232 snprintf(nstr, sizeof(nstr), "e82545-%d:%d tx", pi->pi_slot, 2233 pi->pi_func); 2234 pthread_set_name_np(sc->esc_tx_tid, nstr); 2235 2236 pci_set_cfgdata16(pi, PCIR_DEVICE, E82545_DEV_ID_82545EM_COPPER); 2237 pci_set_cfgdata16(pi, PCIR_VENDOR, E82545_VENDOR_ID_INTEL); 2238 pci_set_cfgdata8(pi, PCIR_CLASS, PCIC_NETWORK); 2239 pci_set_cfgdata8(pi, PCIR_SUBCLASS, PCIS_NETWORK_ETHERNET); 2240 pci_set_cfgdata16(pi, PCIR_SUBDEV_0, E82545_SUBDEV_ID); 2241 pci_set_cfgdata16(pi, PCIR_SUBVEND_0, E82545_VENDOR_ID_INTEL); 2242 2243 pci_set_cfgdata8(pi, PCIR_HDRTYPE, PCIM_HDRTYPE_NORMAL); 2244 pci_set_cfgdata8(pi, PCIR_INTPIN, 0x1); 2245 2246 /* TODO: this card also supports msi, but the freebsd driver for it 2247 * does not, so I have not implemented it. */ 2248 pci_lintr_request(pi); 2249 2250 pci_emul_alloc_bar(pi, E82545_BAR_REGISTER, PCIBAR_MEM32, 2251 E82545_BAR_REGISTER_LEN); 2252 pci_emul_alloc_bar(pi, E82545_BAR_FLASH, PCIBAR_MEM32, 2253 E82545_BAR_FLASH_LEN); 2254 pci_emul_alloc_bar(pi, E82545_BAR_IO, PCIBAR_IO, 2255 E82545_BAR_IO_LEN); 2256 2257 /* 2258 * Attempt to open the net backend and read the MAC address 2259 * if specified. Copied from virtio-net, slightly modified. 2260 */ 2261 mac_provided = 0; 2262 sc->esc_be = NULL; 2263 if (opts != NULL) { 2264 int err; 2265 2266 devname = vtopts = strdup(opts); 2267 (void) strsep(&vtopts, ","); 2268 2269 if (vtopts != NULL) { 2270 err = net_parsemac(vtopts, sc->esc_mac.octet); 2271 if (err != 0) { 2272 free(devname); 2273 return (err); 2274 } 2275 mac_provided = 1; 2276 } 2277 2278 err = netbe_init(&sc->esc_be, devname, e82545_rx_callback, sc); 2279 free(devname); 2280 if (err) 2281 return (err); 2282 } 2283 2284 if (!mac_provided) { 2285 net_genmac(pi, sc->esc_mac.octet); 2286 } 2287 2288 /* H/w initiated reset */ 2289 e82545_reset(sc, 0); 2290 2291 return (0); 2292 } 2293 2294 struct pci_devemu pci_de_e82545 = { 2295 .pe_emu = "e1000", 2296 .pe_init = e82545_init, 2297 .pe_barwrite = e82545_write, 2298 .pe_barread = e82545_read 2299 }; 2300 PCI_EMUL_SET(pci_de_e82545); 2301 2302