1 /*- 2 * Copyright (c) 2013 Zhixiang Yu <zcore@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 #include <sys/param.h> 33 #include <sys/linker_set.h> 34 #include <sys/stat.h> 35 #include <sys/uio.h> 36 #include <sys/ioctl.h> 37 #include <sys/disk.h> 38 #include <sys/ata.h> 39 #include <sys/endian.h> 40 41 #include <errno.h> 42 #include <fcntl.h> 43 #include <stdio.h> 44 #include <stdlib.h> 45 #include <stdint.h> 46 #include <string.h> 47 #include <strings.h> 48 #include <unistd.h> 49 #include <assert.h> 50 #include <pthread.h> 51 #include <inttypes.h> 52 53 #include "bhyverun.h" 54 #include "pci_emul.h" 55 #include "ahci.h" 56 #include "block_if.h" 57 58 #define MAX_PORTS 6 /* Intel ICH8 AHCI supports 6 ports */ 59 60 #define PxSIG_ATA 0x00000101 /* ATA drive */ 61 #define PxSIG_ATAPI 0xeb140101 /* ATAPI drive */ 62 63 enum sata_fis_type { 64 FIS_TYPE_REGH2D = 0x27, /* Register FIS - host to device */ 65 FIS_TYPE_REGD2H = 0x34, /* Register FIS - device to host */ 66 FIS_TYPE_DMAACT = 0x39, /* DMA activate FIS - device to host */ 67 FIS_TYPE_DMASETUP = 0x41, /* DMA setup FIS - bidirectional */ 68 FIS_TYPE_DATA = 0x46, /* Data FIS - bidirectional */ 69 FIS_TYPE_BIST = 0x58, /* BIST activate FIS - bidirectional */ 70 FIS_TYPE_PIOSETUP = 0x5F, /* PIO setup FIS - device to host */ 71 FIS_TYPE_SETDEVBITS = 0xA1, /* Set dev bits FIS - device to host */ 72 }; 73 74 /* 75 * SCSI opcodes 76 */ 77 #define TEST_UNIT_READY 0x00 78 #define REQUEST_SENSE 0x03 79 #define INQUIRY 0x12 80 #define START_STOP_UNIT 0x1B 81 #define PREVENT_ALLOW 0x1E 82 #define READ_CAPACITY 0x25 83 #define READ_10 0x28 84 #define POSITION_TO_ELEMENT 0x2B 85 #define READ_TOC 0x43 86 #define GET_EVENT_STATUS_NOTIFICATION 0x4A 87 #define MODE_SENSE_10 0x5A 88 #define READ_12 0xA8 89 #define READ_CD 0xBE 90 91 /* 92 * SCSI mode page codes 93 */ 94 #define MODEPAGE_RW_ERROR_RECOVERY 0x01 95 #define MODEPAGE_CD_CAPABILITIES 0x2A 96 97 /* 98 * ATA commands 99 */ 100 #define ATA_SF_ENAB_SATA_SF 0x10 101 #define ATA_SATA_SF_AN 0x05 102 #define ATA_SF_DIS_SATA_SF 0x90 103 104 /* 105 * Debug printf 106 */ 107 #ifdef AHCI_DEBUG 108 static FILE *dbg; 109 #define DPRINTF(format, arg...) do{fprintf(dbg, format, ##arg);fflush(dbg);}while(0) 110 #else 111 #define DPRINTF(format, arg...) 112 #endif 113 #define WPRINTF(format, arg...) printf(format, ##arg) 114 115 struct ahci_ioreq { 116 struct blockif_req io_req; 117 struct ahci_port *io_pr; 118 STAILQ_ENTRY(ahci_ioreq) io_list; 119 uint8_t *cfis; 120 uint32_t len; 121 uint32_t done; 122 int slot; 123 int prdtl; 124 }; 125 126 struct ahci_port { 127 struct blockif_ctxt *bctx; 128 struct pci_ahci_softc *pr_sc; 129 uint8_t *cmd_lst; 130 uint8_t *rfis; 131 int atapi; 132 int reset; 133 int mult_sectors; 134 uint8_t xfermode; 135 uint8_t sense_key; 136 uint8_t asc; 137 uint32_t pending; 138 139 uint32_t clb; 140 uint32_t clbu; 141 uint32_t fb; 142 uint32_t fbu; 143 uint32_t is; 144 uint32_t ie; 145 uint32_t cmd; 146 uint32_t unused0; 147 uint32_t tfd; 148 uint32_t sig; 149 uint32_t ssts; 150 uint32_t sctl; 151 uint32_t serr; 152 uint32_t sact; 153 uint32_t ci; 154 uint32_t sntf; 155 uint32_t fbs; 156 157 /* 158 * i/o request info 159 */ 160 struct ahci_ioreq *ioreq; 161 int ioqsz; 162 STAILQ_HEAD(ahci_fhead, ahci_ioreq) iofhd; 163 }; 164 165 struct ahci_cmd_hdr { 166 uint16_t flags; 167 uint16_t prdtl; 168 uint32_t prdbc; 169 uint64_t ctba; 170 uint32_t reserved[4]; 171 }; 172 173 struct ahci_prdt_entry { 174 uint64_t dba; 175 uint32_t reserved; 176 #define DBCMASK 0x3fffff 177 uint32_t dbc; 178 }; 179 180 struct pci_ahci_softc { 181 struct pci_devinst *asc_pi; 182 pthread_mutex_t mtx; 183 int ports; 184 uint32_t cap; 185 uint32_t ghc; 186 uint32_t is; 187 uint32_t pi; 188 uint32_t vs; 189 uint32_t ccc_ctl; 190 uint32_t ccc_pts; 191 uint32_t em_loc; 192 uint32_t em_ctl; 193 uint32_t cap2; 194 uint32_t bohc; 195 uint32_t lintr; 196 struct ahci_port port[MAX_PORTS]; 197 }; 198 #define ahci_ctx(sc) ((sc)->asc_pi->pi_vmctx) 199 200 static inline void lba_to_msf(uint8_t *buf, int lba) 201 { 202 lba += 150; 203 buf[0] = (lba / 75) / 60; 204 buf[1] = (lba / 75) % 60; 205 buf[2] = lba % 75; 206 } 207 208 /* 209 * generate HBA intr depending on whether or not ports within 210 * the controller have an interrupt pending. 211 */ 212 static void 213 ahci_generate_intr(struct pci_ahci_softc *sc) 214 { 215 struct pci_devinst *pi; 216 int i; 217 218 pi = sc->asc_pi; 219 220 for (i = 0; i < sc->ports; i++) { 221 struct ahci_port *pr; 222 pr = &sc->port[i]; 223 if (pr->is & pr->ie) 224 sc->is |= (1 << i); 225 } 226 227 DPRINTF("%s %x\n", __func__, sc->is); 228 229 if (sc->is && (sc->ghc & AHCI_GHC_IE)) { 230 if (pci_msi_enabled(pi)) { 231 /* 232 * Generate an MSI interrupt on every edge 233 */ 234 pci_generate_msi(pi, 0); 235 } else if (!sc->lintr) { 236 /* 237 * Only generate a pin-based interrupt if one wasn't 238 * in progress 239 */ 240 sc->lintr = 1; 241 pci_lintr_assert(pi); 242 } 243 } else if (sc->lintr) { 244 /* 245 * No interrupts: deassert pin-based signal if it had 246 * been asserted 247 */ 248 pci_lintr_deassert(pi); 249 sc->lintr = 0; 250 } 251 } 252 253 static void 254 ahci_write_fis(struct ahci_port *p, enum sata_fis_type ft, uint8_t *fis) 255 { 256 int offset, len, irq; 257 258 if (p->rfis == NULL || !(p->cmd & AHCI_P_CMD_FRE)) 259 return; 260 261 switch (ft) { 262 case FIS_TYPE_REGD2H: 263 offset = 0x40; 264 len = 20; 265 irq = AHCI_P_IX_DHR; 266 break; 267 case FIS_TYPE_SETDEVBITS: 268 offset = 0x58; 269 len = 8; 270 irq = AHCI_P_IX_SDB; 271 break; 272 case FIS_TYPE_PIOSETUP: 273 offset = 0x20; 274 len = 20; 275 irq = 0; 276 break; 277 default: 278 WPRINTF("unsupported fis type %d\n", ft); 279 return; 280 } 281 memcpy(p->rfis + offset, fis, len); 282 if (irq) { 283 p->is |= irq; 284 ahci_generate_intr(p->pr_sc); 285 } 286 } 287 288 static void 289 ahci_write_fis_piosetup(struct ahci_port *p) 290 { 291 uint8_t fis[20]; 292 293 memset(fis, 0, sizeof(fis)); 294 fis[0] = FIS_TYPE_PIOSETUP; 295 ahci_write_fis(p, FIS_TYPE_PIOSETUP, fis); 296 } 297 298 static void 299 ahci_write_fis_sdb(struct ahci_port *p, int slot, uint32_t tfd) 300 { 301 uint8_t fis[8]; 302 uint8_t error; 303 304 error = (tfd >> 8) & 0xff; 305 memset(fis, 0, sizeof(fis)); 306 fis[0] = error; 307 fis[2] = tfd & 0x77; 308 *(uint32_t *)(fis + 4) = (1 << slot); 309 if (fis[2] & ATA_S_ERROR) 310 p->is |= AHCI_P_IX_TFE; 311 p->tfd = tfd; 312 ahci_write_fis(p, FIS_TYPE_SETDEVBITS, fis); 313 } 314 315 static void 316 ahci_write_fis_d2h(struct ahci_port *p, int slot, uint8_t *cfis, uint32_t tfd) 317 { 318 uint8_t fis[20]; 319 uint8_t error; 320 321 error = (tfd >> 8) & 0xff; 322 memset(fis, 0, sizeof(fis)); 323 fis[0] = FIS_TYPE_REGD2H; 324 fis[1] = (1 << 6); 325 fis[2] = tfd & 0xff; 326 fis[3] = error; 327 fis[4] = cfis[4]; 328 fis[5] = cfis[5]; 329 fis[6] = cfis[6]; 330 fis[7] = cfis[7]; 331 fis[8] = cfis[8]; 332 fis[9] = cfis[9]; 333 fis[10] = cfis[10]; 334 fis[11] = cfis[11]; 335 fis[12] = cfis[12]; 336 fis[13] = cfis[13]; 337 if (fis[2] & ATA_S_ERROR) 338 p->is |= AHCI_P_IX_TFE; 339 p->tfd = tfd; 340 p->ci &= ~(1 << slot); 341 ahci_write_fis(p, FIS_TYPE_REGD2H, fis); 342 } 343 344 static void 345 ahci_write_reset_fis_d2h(struct ahci_port *p) 346 { 347 uint8_t fis[20]; 348 349 memset(fis, 0, sizeof(fis)); 350 fis[0] = FIS_TYPE_REGD2H; 351 fis[3] = 1; 352 fis[4] = 1; 353 if (p->atapi) { 354 fis[5] = 0x14; 355 fis[6] = 0xeb; 356 } 357 fis[12] = 1; 358 ahci_write_fis(p, FIS_TYPE_REGD2H, fis); 359 } 360 361 static void 362 ahci_port_reset(struct ahci_port *pr) 363 { 364 pr->sctl = 0; 365 pr->serr = 0; 366 pr->sact = 0; 367 pr->xfermode = ATA_UDMA6; 368 pr->mult_sectors = 128; 369 370 if (!pr->bctx) { 371 pr->ssts = ATA_SS_DET_NO_DEVICE; 372 pr->sig = 0xFFFFFFFF; 373 pr->tfd = 0x7F; 374 return; 375 } 376 pr->ssts = ATA_SS_DET_PHY_ONLINE | ATA_SS_SPD_GEN2 | 377 ATA_SS_IPM_ACTIVE; 378 pr->tfd = (1 << 8) | ATA_S_DSC | ATA_S_DMA; 379 if (!pr->atapi) { 380 pr->sig = PxSIG_ATA; 381 pr->tfd |= ATA_S_READY; 382 } else 383 pr->sig = PxSIG_ATAPI; 384 ahci_write_reset_fis_d2h(pr); 385 } 386 387 static void 388 ahci_reset(struct pci_ahci_softc *sc) 389 { 390 int i; 391 392 sc->ghc = AHCI_GHC_AE; 393 sc->is = 0; 394 395 if (sc->lintr) { 396 pci_lintr_deassert(sc->asc_pi); 397 sc->lintr = 0; 398 } 399 400 for (i = 0; i < sc->ports; i++) { 401 sc->port[i].ie = 0; 402 sc->port[i].is = 0; 403 ahci_port_reset(&sc->port[i]); 404 } 405 } 406 407 static void 408 ata_string(uint8_t *dest, const char *src, int len) 409 { 410 int i; 411 412 for (i = 0; i < len; i++) { 413 if (*src) 414 dest[i ^ 1] = *src++; 415 else 416 dest[i ^ 1] = ' '; 417 } 418 } 419 420 static void 421 atapi_string(uint8_t *dest, const char *src, int len) 422 { 423 int i; 424 425 for (i = 0; i < len; i++) { 426 if (*src) 427 dest[i] = *src++; 428 else 429 dest[i] = ' '; 430 } 431 } 432 433 static void 434 ahci_handle_dma(struct ahci_port *p, int slot, uint8_t *cfis, uint32_t done, 435 int seek) 436 { 437 struct ahci_ioreq *aior; 438 struct blockif_req *breq; 439 struct pci_ahci_softc *sc; 440 struct ahci_prdt_entry *prdt; 441 struct ahci_cmd_hdr *hdr; 442 uint64_t lba; 443 uint32_t len; 444 int i, err, iovcnt, ncq, readop; 445 446 sc = p->pr_sc; 447 prdt = (struct ahci_prdt_entry *)(cfis + 0x80); 448 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE); 449 ncq = 0; 450 readop = 1; 451 452 prdt += seek; 453 if (cfis[2] == ATA_WRITE_DMA || cfis[2] == ATA_WRITE_DMA48 || 454 cfis[2] == ATA_WRITE_FPDMA_QUEUED) 455 readop = 0; 456 457 if (cfis[2] == ATA_WRITE_FPDMA_QUEUED || 458 cfis[2] == ATA_READ_FPDMA_QUEUED) { 459 lba = ((uint64_t)cfis[10] << 40) | 460 ((uint64_t)cfis[9] << 32) | 461 ((uint64_t)cfis[8] << 24) | 462 ((uint64_t)cfis[6] << 16) | 463 ((uint64_t)cfis[5] << 8) | 464 cfis[4]; 465 len = cfis[11] << 8 | cfis[3]; 466 if (!len) 467 len = 65536; 468 ncq = 1; 469 } else if (cfis[2] == ATA_READ_DMA48 || cfis[2] == ATA_WRITE_DMA48) { 470 lba = ((uint64_t)cfis[10] << 40) | 471 ((uint64_t)cfis[9] << 32) | 472 ((uint64_t)cfis[8] << 24) | 473 ((uint64_t)cfis[6] << 16) | 474 ((uint64_t)cfis[5] << 8) | 475 cfis[4]; 476 len = cfis[13] << 8 | cfis[12]; 477 if (!len) 478 len = 65536; 479 } else { 480 lba = ((cfis[7] & 0xf) << 24) | (cfis[6] << 16) | 481 (cfis[5] << 8) | cfis[4]; 482 len = cfis[12]; 483 if (!len) 484 len = 256; 485 } 486 lba *= blockif_sectsz(p->bctx); 487 len *= blockif_sectsz(p->bctx); 488 489 /* 490 * Pull request off free list 491 */ 492 aior = STAILQ_FIRST(&p->iofhd); 493 assert(aior != NULL); 494 STAILQ_REMOVE_HEAD(&p->iofhd, io_list); 495 aior->cfis = cfis; 496 aior->slot = slot; 497 aior->len = len; 498 aior->done = done; 499 breq = &aior->io_req; 500 breq->br_offset = lba + done; 501 iovcnt = hdr->prdtl - seek; 502 if (iovcnt > BLOCKIF_IOV_MAX) { 503 aior->prdtl = iovcnt - BLOCKIF_IOV_MAX; 504 iovcnt = BLOCKIF_IOV_MAX; 505 /* 506 * Mark this command in-flight. 507 */ 508 p->pending |= 1 << slot; 509 } else 510 aior->prdtl = 0; 511 breq->br_iovcnt = iovcnt; 512 513 /* 514 * Build up the iovec based on the prdt 515 */ 516 for (i = 0; i < iovcnt; i++) { 517 uint32_t dbcsz; 518 519 dbcsz = (prdt->dbc & DBCMASK) + 1; 520 breq->br_iov[i].iov_base = paddr_guest2host(ahci_ctx(sc), 521 prdt->dba, dbcsz); 522 breq->br_iov[i].iov_len = dbcsz; 523 aior->done += dbcsz; 524 prdt++; 525 } 526 if (readop) 527 err = blockif_read(p->bctx, breq); 528 else 529 err = blockif_write(p->bctx, breq); 530 assert(err == 0); 531 532 if (ncq) 533 p->ci &= ~(1 << slot); 534 } 535 536 static void 537 ahci_handle_flush(struct ahci_port *p, int slot, uint8_t *cfis) 538 { 539 struct ahci_ioreq *aior; 540 struct blockif_req *breq; 541 int err; 542 543 /* 544 * Pull request off free list 545 */ 546 aior = STAILQ_FIRST(&p->iofhd); 547 assert(aior != NULL); 548 STAILQ_REMOVE_HEAD(&p->iofhd, io_list); 549 aior->cfis = cfis; 550 aior->slot = slot; 551 aior->len = 0; 552 aior->done = 0; 553 aior->prdtl = 0; 554 breq = &aior->io_req; 555 556 err = blockif_flush(p->bctx, breq); 557 assert(err == 0); 558 } 559 560 static inline void 561 write_prdt(struct ahci_port *p, int slot, uint8_t *cfis, 562 void *buf, int size) 563 { 564 struct ahci_cmd_hdr *hdr; 565 struct ahci_prdt_entry *prdt; 566 void *from; 567 int i, len; 568 569 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE); 570 len = size; 571 from = buf; 572 prdt = (struct ahci_prdt_entry *)(cfis + 0x80); 573 for (i = 0; i < hdr->prdtl && len; i++) { 574 uint8_t *ptr; 575 uint32_t dbcsz; 576 int sublen; 577 578 dbcsz = (prdt->dbc & DBCMASK) + 1; 579 ptr = paddr_guest2host(ahci_ctx(p->pr_sc), prdt->dba, dbcsz); 580 sublen = len < dbcsz ? len : dbcsz; 581 memcpy(ptr, from, sublen); 582 len -= sublen; 583 from += sublen; 584 prdt++; 585 } 586 hdr->prdbc = size - len; 587 } 588 589 static void 590 handle_identify(struct ahci_port *p, int slot, uint8_t *cfis) 591 { 592 struct ahci_cmd_hdr *hdr; 593 594 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE); 595 if (p->atapi || hdr->prdtl == 0) { 596 p->tfd = (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR; 597 p->is |= AHCI_P_IX_TFE; 598 } else { 599 uint16_t buf[256]; 600 uint64_t sectors; 601 uint16_t cyl; 602 uint8_t sech, heads; 603 604 sectors = blockif_size(p->bctx) / blockif_sectsz(p->bctx); 605 blockif_chs(p->bctx, &cyl, &heads, &sech); 606 memset(buf, 0, sizeof(buf)); 607 buf[0] = 0x0040; 608 buf[1] = cyl; 609 buf[3] = heads; 610 buf[6] = sech; 611 /* TODO emulate different serial? */ 612 ata_string((uint8_t *)(buf+10), "123456", 20); 613 ata_string((uint8_t *)(buf+23), "001", 8); 614 ata_string((uint8_t *)(buf+27), "BHYVE SATA DISK", 40); 615 buf[47] = (0x8000 | 128); 616 buf[48] = 0x1; 617 buf[49] = (1 << 8 | 1 << 9 | 1 << 11); 618 buf[50] = (1 << 14); 619 buf[53] = (1 << 1 | 1 << 2); 620 if (p->mult_sectors) 621 buf[59] = (0x100 | p->mult_sectors); 622 buf[60] = sectors; 623 buf[61] = (sectors >> 16); 624 buf[63] = 0x7; 625 if (p->xfermode & ATA_WDMA0) 626 buf[63] |= (1 << ((p->xfermode & 7) + 8)); 627 buf[64] = 0x3; 628 buf[65] = 100; 629 buf[66] = 100; 630 buf[67] = 100; 631 buf[68] = 100; 632 buf[75] = 31; 633 buf[76] = (1 << 8 | 1 << 2); 634 buf[80] = 0x1f0; 635 buf[81] = 0x28; 636 buf[82] = (1 << 5 | 1 << 14); 637 buf[83] = (1 << 10 | 1 << 12 | 1 << 13 | 1 << 14); 638 buf[84] = (1 << 14); 639 buf[85] = (1 << 5 | 1 << 14); 640 buf[86] = (1 << 10 | 1 << 12 | 1 << 13); 641 buf[87] = (1 << 14); 642 buf[88] = 0x7f; 643 if (p->xfermode & ATA_UDMA0) 644 buf[88] |= (1 << ((p->xfermode & 7) + 8)); 645 buf[93] = (1 | 1 <<14); 646 buf[100] = sectors; 647 buf[101] = (sectors >> 16); 648 buf[102] = (sectors >> 32); 649 buf[103] = (sectors >> 48); 650 ahci_write_fis_piosetup(p); 651 write_prdt(p, slot, cfis, (void *)buf, sizeof(buf)); 652 p->tfd = ATA_S_DSC | ATA_S_READY; 653 p->is |= AHCI_P_IX_DP; 654 } 655 p->ci &= ~(1 << slot); 656 ahci_generate_intr(p->pr_sc); 657 } 658 659 static void 660 handle_atapi_identify(struct ahci_port *p, int slot, uint8_t *cfis) 661 { 662 if (!p->atapi) { 663 p->tfd = (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR; 664 p->is |= AHCI_P_IX_TFE; 665 } else { 666 uint16_t buf[256]; 667 668 memset(buf, 0, sizeof(buf)); 669 buf[0] = (2 << 14 | 5 << 8 | 1 << 7 | 2 << 5); 670 /* TODO emulate different serial? */ 671 ata_string((uint8_t *)(buf+10), "123456", 20); 672 ata_string((uint8_t *)(buf+23), "001", 8); 673 ata_string((uint8_t *)(buf+27), "BHYVE SATA DVD ROM", 40); 674 buf[49] = (1 << 9 | 1 << 8); 675 buf[50] = (1 << 14 | 1); 676 buf[53] = (1 << 2 | 1 << 1); 677 buf[62] = 0x3f; 678 buf[63] = 7; 679 buf[64] = 3; 680 buf[65] = 100; 681 buf[66] = 100; 682 buf[67] = 100; 683 buf[68] = 100; 684 buf[76] = (1 << 2 | 1 << 1); 685 buf[78] = (1 << 5); 686 buf[80] = (0x1f << 4); 687 buf[82] = (1 << 4); 688 buf[83] = (1 << 14); 689 buf[84] = (1 << 14); 690 buf[85] = (1 << 4); 691 buf[87] = (1 << 14); 692 buf[88] = (1 << 14 | 0x7f); 693 ahci_write_fis_piosetup(p); 694 write_prdt(p, slot, cfis, (void *)buf, sizeof(buf)); 695 p->tfd = ATA_S_DSC | ATA_S_READY; 696 p->is |= AHCI_P_IX_DHR; 697 } 698 p->ci &= ~(1 << slot); 699 ahci_generate_intr(p->pr_sc); 700 } 701 702 static void 703 atapi_inquiry(struct ahci_port *p, int slot, uint8_t *cfis) 704 { 705 uint8_t buf[36]; 706 uint8_t *acmd; 707 int len; 708 709 acmd = cfis + 0x40; 710 711 buf[0] = 0x05; 712 buf[1] = 0x80; 713 buf[2] = 0x00; 714 buf[3] = 0x21; 715 buf[4] = 31; 716 buf[5] = 0; 717 buf[6] = 0; 718 buf[7] = 0; 719 atapi_string(buf + 8, "BHYVE", 8); 720 atapi_string(buf + 16, "BHYVE DVD-ROM", 16); 721 atapi_string(buf + 32, "001", 4); 722 723 len = sizeof(buf); 724 if (len > acmd[4]) 725 len = acmd[4]; 726 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 727 write_prdt(p, slot, cfis, buf, len); 728 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC); 729 } 730 731 static void 732 atapi_read_capacity(struct ahci_port *p, int slot, uint8_t *cfis) 733 { 734 uint8_t buf[8]; 735 uint64_t sectors; 736 737 sectors = blockif_size(p->bctx) / 2048; 738 be32enc(buf, sectors - 1); 739 be32enc(buf + 4, 2048); 740 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 741 write_prdt(p, slot, cfis, buf, sizeof(buf)); 742 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC); 743 } 744 745 static void 746 atapi_read_toc(struct ahci_port *p, int slot, uint8_t *cfis) 747 { 748 uint8_t *acmd; 749 uint8_t format; 750 int len; 751 752 acmd = cfis + 0x40; 753 754 len = be16dec(acmd + 7); 755 format = acmd[9] >> 6; 756 switch (format) { 757 case 0: 758 { 759 int msf, size; 760 uint64_t sectors; 761 uint8_t start_track, buf[20], *bp; 762 763 msf = (acmd[1] >> 1) & 1; 764 start_track = acmd[6]; 765 if (start_track > 1 && start_track != 0xaa) { 766 uint32_t tfd; 767 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST; 768 p->asc = 0x24; 769 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR; 770 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 771 ahci_write_fis_d2h(p, slot, cfis, tfd); 772 return; 773 } 774 bp = buf + 2; 775 *bp++ = 1; 776 *bp++ = 1; 777 if (start_track <= 1) { 778 *bp++ = 0; 779 *bp++ = 0x14; 780 *bp++ = 1; 781 *bp++ = 0; 782 if (msf) { 783 *bp++ = 0; 784 lba_to_msf(bp, 0); 785 bp += 3; 786 } else { 787 *bp++ = 0; 788 *bp++ = 0; 789 *bp++ = 0; 790 *bp++ = 0; 791 } 792 } 793 *bp++ = 0; 794 *bp++ = 0x14; 795 *bp++ = 0xaa; 796 *bp++ = 0; 797 sectors = blockif_size(p->bctx) / blockif_sectsz(p->bctx); 798 sectors >>= 2; 799 if (msf) { 800 *bp++ = 0; 801 lba_to_msf(bp, sectors); 802 bp += 3; 803 } else { 804 be32enc(bp, sectors); 805 bp += 4; 806 } 807 size = bp - buf; 808 be16enc(buf, size - 2); 809 if (len > size) 810 len = size; 811 write_prdt(p, slot, cfis, buf, len); 812 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 813 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC); 814 break; 815 } 816 case 1: 817 { 818 uint8_t buf[12]; 819 820 memset(buf, 0, sizeof(buf)); 821 buf[1] = 0xa; 822 buf[2] = 0x1; 823 buf[3] = 0x1; 824 if (len > sizeof(buf)) 825 len = sizeof(buf); 826 write_prdt(p, slot, cfis, buf, len); 827 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 828 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC); 829 break; 830 } 831 case 2: 832 { 833 int msf, size; 834 uint64_t sectors; 835 uint8_t start_track, *bp, buf[50]; 836 837 msf = (acmd[1] >> 1) & 1; 838 start_track = acmd[6]; 839 bp = buf + 2; 840 *bp++ = 1; 841 *bp++ = 1; 842 843 *bp++ = 1; 844 *bp++ = 0x14; 845 *bp++ = 0; 846 *bp++ = 0xa0; 847 *bp++ = 0; 848 *bp++ = 0; 849 *bp++ = 0; 850 *bp++ = 0; 851 *bp++ = 1; 852 *bp++ = 0; 853 *bp++ = 0; 854 855 *bp++ = 1; 856 *bp++ = 0x14; 857 *bp++ = 0; 858 *bp++ = 0xa1; 859 *bp++ = 0; 860 *bp++ = 0; 861 *bp++ = 0; 862 *bp++ = 0; 863 *bp++ = 1; 864 *bp++ = 0; 865 *bp++ = 0; 866 867 *bp++ = 1; 868 *bp++ = 0x14; 869 *bp++ = 0; 870 *bp++ = 0xa2; 871 *bp++ = 0; 872 *bp++ = 0; 873 *bp++ = 0; 874 sectors = blockif_size(p->bctx) / blockif_sectsz(p->bctx); 875 sectors >>= 2; 876 if (msf) { 877 *bp++ = 0; 878 lba_to_msf(bp, sectors); 879 bp += 3; 880 } else { 881 be32enc(bp, sectors); 882 bp += 4; 883 } 884 885 *bp++ = 1; 886 *bp++ = 0x14; 887 *bp++ = 0; 888 *bp++ = 1; 889 *bp++ = 0; 890 *bp++ = 0; 891 *bp++ = 0; 892 if (msf) { 893 *bp++ = 0; 894 lba_to_msf(bp, 0); 895 bp += 3; 896 } else { 897 *bp++ = 0; 898 *bp++ = 0; 899 *bp++ = 0; 900 *bp++ = 0; 901 } 902 903 size = bp - buf; 904 be16enc(buf, size - 2); 905 if (len > size) 906 len = size; 907 write_prdt(p, slot, cfis, buf, len); 908 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 909 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC); 910 break; 911 } 912 default: 913 { 914 uint32_t tfd; 915 916 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST; 917 p->asc = 0x24; 918 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR; 919 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 920 ahci_write_fis_d2h(p, slot, cfis, tfd); 921 break; 922 } 923 } 924 } 925 926 static void 927 atapi_read(struct ahci_port *p, int slot, uint8_t *cfis, 928 uint32_t done, int seek) 929 { 930 struct ahci_ioreq *aior; 931 struct ahci_cmd_hdr *hdr; 932 struct ahci_prdt_entry *prdt; 933 struct blockif_req *breq; 934 struct pci_ahci_softc *sc; 935 uint8_t *acmd; 936 uint64_t lba; 937 uint32_t len; 938 int i, err, iovcnt; 939 940 sc = p->pr_sc; 941 acmd = cfis + 0x40; 942 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE); 943 prdt = (struct ahci_prdt_entry *)(cfis + 0x80); 944 945 prdt += seek; 946 lba = be32dec(acmd + 2); 947 if (acmd[0] == READ_10) 948 len = be16dec(acmd + 7); 949 else 950 len = be32dec(acmd + 6); 951 if (len == 0) { 952 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 953 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC); 954 } 955 lba *= 2048; 956 len *= 2048; 957 958 /* 959 * Pull request off free list 960 */ 961 aior = STAILQ_FIRST(&p->iofhd); 962 assert(aior != NULL); 963 STAILQ_REMOVE_HEAD(&p->iofhd, io_list); 964 aior->cfis = cfis; 965 aior->slot = slot; 966 aior->len = len; 967 aior->done = done; 968 breq = &aior->io_req; 969 breq->br_offset = lba + done; 970 iovcnt = hdr->prdtl - seek; 971 if (iovcnt > BLOCKIF_IOV_MAX) { 972 aior->prdtl = iovcnt - BLOCKIF_IOV_MAX; 973 iovcnt = BLOCKIF_IOV_MAX; 974 } else 975 aior->prdtl = 0; 976 breq->br_iovcnt = iovcnt; 977 978 /* 979 * Build up the iovec based on the prdt 980 */ 981 for (i = 0; i < iovcnt; i++) { 982 uint32_t dbcsz; 983 984 dbcsz = (prdt->dbc & DBCMASK) + 1; 985 breq->br_iov[i].iov_base = paddr_guest2host(ahci_ctx(sc), 986 prdt->dba, dbcsz); 987 breq->br_iov[i].iov_len = dbcsz; 988 aior->done += dbcsz; 989 prdt++; 990 } 991 err = blockif_read(p->bctx, breq); 992 assert(err == 0); 993 } 994 995 static void 996 atapi_request_sense(struct ahci_port *p, int slot, uint8_t *cfis) 997 { 998 uint8_t buf[64]; 999 uint8_t *acmd; 1000 int len; 1001 1002 acmd = cfis + 0x40; 1003 len = acmd[4]; 1004 if (len > sizeof(buf)) 1005 len = sizeof(buf); 1006 memset(buf, 0, len); 1007 buf[0] = 0x70 | (1 << 7); 1008 buf[2] = p->sense_key; 1009 buf[7] = 10; 1010 buf[12] = p->asc; 1011 write_prdt(p, slot, cfis, buf, len); 1012 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1013 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC); 1014 } 1015 1016 static void 1017 atapi_start_stop_unit(struct ahci_port *p, int slot, uint8_t *cfis) 1018 { 1019 uint8_t *acmd = cfis + 0x40; 1020 uint32_t tfd; 1021 1022 switch (acmd[4] & 3) { 1023 case 0: 1024 case 1: 1025 case 3: 1026 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1027 tfd = ATA_S_READY | ATA_S_DSC; 1028 break; 1029 case 2: 1030 /* TODO eject media */ 1031 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1032 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST; 1033 p->asc = 0x53; 1034 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR; 1035 break; 1036 } 1037 ahci_write_fis_d2h(p, slot, cfis, tfd); 1038 } 1039 1040 static void 1041 atapi_mode_sense(struct ahci_port *p, int slot, uint8_t *cfis) 1042 { 1043 uint8_t *acmd; 1044 uint32_t tfd; 1045 uint8_t pc, code; 1046 int len; 1047 1048 acmd = cfis + 0x40; 1049 len = be16dec(acmd + 7); 1050 pc = acmd[2] >> 6; 1051 code = acmd[2] & 0x3f; 1052 1053 switch (pc) { 1054 case 0: 1055 switch (code) { 1056 case MODEPAGE_RW_ERROR_RECOVERY: 1057 { 1058 uint8_t buf[16]; 1059 1060 if (len > sizeof(buf)) 1061 len = sizeof(buf); 1062 1063 memset(buf, 0, sizeof(buf)); 1064 be16enc(buf, 16 - 2); 1065 buf[2] = 0x70; 1066 buf[8] = 0x01; 1067 buf[9] = 16 - 10; 1068 buf[11] = 0x05; 1069 write_prdt(p, slot, cfis, buf, len); 1070 tfd = ATA_S_READY | ATA_S_DSC; 1071 break; 1072 } 1073 case MODEPAGE_CD_CAPABILITIES: 1074 { 1075 uint8_t buf[30]; 1076 1077 if (len > sizeof(buf)) 1078 len = sizeof(buf); 1079 1080 memset(buf, 0, sizeof(buf)); 1081 be16enc(buf, 30 - 2); 1082 buf[2] = 0x70; 1083 buf[8] = 0x2A; 1084 buf[9] = 30 - 10; 1085 buf[10] = 0x08; 1086 buf[12] = 0x71; 1087 be16enc(&buf[18], 2); 1088 be16enc(&buf[20], 512); 1089 write_prdt(p, slot, cfis, buf, len); 1090 tfd = ATA_S_READY | ATA_S_DSC; 1091 break; 1092 } 1093 default: 1094 goto error; 1095 break; 1096 } 1097 break; 1098 case 3: 1099 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST; 1100 p->asc = 0x39; 1101 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR; 1102 break; 1103 error: 1104 case 1: 1105 case 2: 1106 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST; 1107 p->asc = 0x24; 1108 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR; 1109 break; 1110 } 1111 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1112 ahci_write_fis_d2h(p, slot, cfis, tfd); 1113 } 1114 1115 static void 1116 atapi_get_event_status_notification(struct ahci_port *p, int slot, 1117 uint8_t *cfis) 1118 { 1119 uint8_t *acmd; 1120 uint32_t tfd; 1121 1122 acmd = cfis + 0x40; 1123 1124 /* we don't support asynchronous operation */ 1125 if (!(acmd[1] & 1)) { 1126 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST; 1127 p->asc = 0x24; 1128 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR; 1129 } else { 1130 uint8_t buf[8]; 1131 int len; 1132 1133 len = be16dec(acmd + 7); 1134 if (len > sizeof(buf)) 1135 len = sizeof(buf); 1136 1137 memset(buf, 0, sizeof(buf)); 1138 be16enc(buf, 8 - 2); 1139 buf[2] = 0x04; 1140 buf[3] = 0x10; 1141 buf[5] = 0x02; 1142 write_prdt(p, slot, cfis, buf, len); 1143 tfd = ATA_S_READY | ATA_S_DSC; 1144 } 1145 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1146 ahci_write_fis_d2h(p, slot, cfis, tfd); 1147 } 1148 1149 static void 1150 handle_packet_cmd(struct ahci_port *p, int slot, uint8_t *cfis) 1151 { 1152 uint8_t *acmd; 1153 1154 acmd = cfis + 0x40; 1155 1156 #ifdef AHCI_DEBUG 1157 { 1158 int i; 1159 DPRINTF("ACMD:"); 1160 for (i = 0; i < 16; i++) 1161 DPRINTF("%02x ", acmd[i]); 1162 DPRINTF("\n"); 1163 } 1164 #endif 1165 1166 switch (acmd[0]) { 1167 case TEST_UNIT_READY: 1168 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1169 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC); 1170 break; 1171 case INQUIRY: 1172 atapi_inquiry(p, slot, cfis); 1173 break; 1174 case READ_CAPACITY: 1175 atapi_read_capacity(p, slot, cfis); 1176 break; 1177 case PREVENT_ALLOW: 1178 /* TODO */ 1179 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1180 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC); 1181 break; 1182 case READ_TOC: 1183 atapi_read_toc(p, slot, cfis); 1184 break; 1185 case READ_10: 1186 case READ_12: 1187 atapi_read(p, slot, cfis, 0, 0); 1188 break; 1189 case REQUEST_SENSE: 1190 atapi_request_sense(p, slot, cfis); 1191 break; 1192 case START_STOP_UNIT: 1193 atapi_start_stop_unit(p, slot, cfis); 1194 break; 1195 case MODE_SENSE_10: 1196 atapi_mode_sense(p, slot, cfis); 1197 break; 1198 case GET_EVENT_STATUS_NOTIFICATION: 1199 atapi_get_event_status_notification(p, slot, cfis); 1200 break; 1201 default: 1202 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1203 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST; 1204 p->asc = 0x20; 1205 ahci_write_fis_d2h(p, slot, cfis, (p->sense_key << 12) | 1206 ATA_S_READY | ATA_S_ERROR); 1207 break; 1208 } 1209 } 1210 1211 static void 1212 ahci_handle_cmd(struct ahci_port *p, int slot, uint8_t *cfis) 1213 { 1214 1215 switch (cfis[2]) { 1216 case ATA_ATA_IDENTIFY: 1217 handle_identify(p, slot, cfis); 1218 break; 1219 case ATA_SETFEATURES: 1220 { 1221 switch (cfis[3]) { 1222 case ATA_SF_ENAB_SATA_SF: 1223 switch (cfis[12]) { 1224 case ATA_SATA_SF_AN: 1225 p->tfd = ATA_S_DSC | ATA_S_READY; 1226 break; 1227 default: 1228 p->tfd = ATA_S_ERROR | ATA_S_READY; 1229 p->tfd |= (ATA_ERROR_ABORT << 8); 1230 break; 1231 } 1232 break; 1233 case ATA_SF_ENAB_WCACHE: 1234 case ATA_SF_DIS_WCACHE: 1235 case ATA_SF_ENAB_RCACHE: 1236 case ATA_SF_DIS_RCACHE: 1237 p->tfd = ATA_S_DSC | ATA_S_READY; 1238 break; 1239 case ATA_SF_SETXFER: 1240 { 1241 switch (cfis[12] & 0xf8) { 1242 case ATA_PIO: 1243 case ATA_PIO0: 1244 break; 1245 case ATA_WDMA0: 1246 case ATA_UDMA0: 1247 p->xfermode = (cfis[12] & 0x7); 1248 break; 1249 } 1250 p->tfd = ATA_S_DSC | ATA_S_READY; 1251 break; 1252 } 1253 default: 1254 p->tfd = ATA_S_ERROR | ATA_S_READY; 1255 p->tfd |= (ATA_ERROR_ABORT << 8); 1256 break; 1257 } 1258 ahci_write_fis_d2h(p, slot, cfis, p->tfd); 1259 break; 1260 } 1261 case ATA_SET_MULTI: 1262 if (cfis[12] != 0 && 1263 (cfis[12] > 128 || (cfis[12] & (cfis[12] - 1)))) { 1264 p->tfd = ATA_S_ERROR | ATA_S_READY; 1265 p->tfd |= (ATA_ERROR_ABORT << 8); 1266 } else { 1267 p->mult_sectors = cfis[12]; 1268 p->tfd = ATA_S_DSC | ATA_S_READY; 1269 } 1270 p->is |= AHCI_P_IX_DP; 1271 p->ci &= ~(1 << slot); 1272 ahci_generate_intr(p->pr_sc); 1273 break; 1274 case ATA_READ_DMA: 1275 case ATA_WRITE_DMA: 1276 case ATA_READ_DMA48: 1277 case ATA_WRITE_DMA48: 1278 case ATA_READ_FPDMA_QUEUED: 1279 case ATA_WRITE_FPDMA_QUEUED: 1280 ahci_handle_dma(p, slot, cfis, 0, 0); 1281 break; 1282 case ATA_FLUSHCACHE: 1283 case ATA_FLUSHCACHE48: 1284 ahci_handle_flush(p, slot, cfis); 1285 break; 1286 case ATA_STANDBY_CMD: 1287 break; 1288 case ATA_NOP: 1289 case ATA_STANDBY_IMMEDIATE: 1290 case ATA_IDLE_IMMEDIATE: 1291 case ATA_SLEEP: 1292 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC); 1293 break; 1294 case ATA_ATAPI_IDENTIFY: 1295 handle_atapi_identify(p, slot, cfis); 1296 break; 1297 case ATA_PACKET_CMD: 1298 if (!p->atapi) { 1299 p->tfd = (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR; 1300 p->is |= AHCI_P_IX_TFE; 1301 p->ci &= ~(1 << slot); 1302 ahci_generate_intr(p->pr_sc); 1303 } else 1304 handle_packet_cmd(p, slot, cfis); 1305 break; 1306 default: 1307 WPRINTF("Unsupported cmd:%02x\n", cfis[2]); 1308 p->tfd = (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR; 1309 p->is |= AHCI_P_IX_TFE; 1310 p->ci &= ~(1 << slot); 1311 ahci_generate_intr(p->pr_sc); 1312 break; 1313 } 1314 } 1315 1316 static void 1317 ahci_handle_slot(struct ahci_port *p, int slot) 1318 { 1319 struct ahci_cmd_hdr *hdr; 1320 struct ahci_prdt_entry *prdt; 1321 struct pci_ahci_softc *sc; 1322 uint8_t *cfis; 1323 int cfl; 1324 1325 sc = p->pr_sc; 1326 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE); 1327 cfl = (hdr->flags & 0x1f) * 4; 1328 cfis = paddr_guest2host(ahci_ctx(sc), hdr->ctba, 1329 0x80 + hdr->prdtl * sizeof(struct ahci_prdt_entry)); 1330 prdt = (struct ahci_prdt_entry *)(cfis + 0x80); 1331 1332 #ifdef AHCI_DEBUG 1333 DPRINTF("\ncfis:"); 1334 for (i = 0; i < cfl; i++) { 1335 if (i % 10 == 0) 1336 DPRINTF("\n"); 1337 DPRINTF("%02x ", cfis[i]); 1338 } 1339 DPRINTF("\n"); 1340 1341 for (i = 0; i < hdr->prdtl; i++) { 1342 DPRINTF("%d@%08"PRIx64"\n", prdt->dbc & 0x3fffff, prdt->dba); 1343 prdt++; 1344 } 1345 #endif 1346 1347 if (cfis[0] != FIS_TYPE_REGH2D) { 1348 WPRINTF("Not a H2D FIS:%02x\n", cfis[0]); 1349 return; 1350 } 1351 1352 if (cfis[1] & 0x80) { 1353 ahci_handle_cmd(p, slot, cfis); 1354 } else { 1355 if (cfis[15] & (1 << 2)) 1356 p->reset = 1; 1357 else if (p->reset) { 1358 p->reset = 0; 1359 ahci_port_reset(p); 1360 } 1361 p->ci &= ~(1 << slot); 1362 } 1363 } 1364 1365 static void 1366 ahci_handle_port(struct ahci_port *p) 1367 { 1368 int i; 1369 1370 if (!(p->cmd & AHCI_P_CMD_ST)) 1371 return; 1372 1373 /* 1374 * Search for any new commands to issue ignoring those that 1375 * are already in-flight. 1376 */ 1377 for (i = 0; (i < 32) && p->ci; i++) { 1378 if ((p->ci & (1 << i)) && !(p->pending & (1 << i))) 1379 ahci_handle_slot(p, i); 1380 } 1381 } 1382 1383 /* 1384 * blockif callback routine - this runs in the context of the blockif 1385 * i/o thread, so the mutex needs to be acquired. 1386 */ 1387 static void 1388 ata_ioreq_cb(struct blockif_req *br, int err) 1389 { 1390 struct ahci_cmd_hdr *hdr; 1391 struct ahci_ioreq *aior; 1392 struct ahci_port *p; 1393 struct pci_ahci_softc *sc; 1394 uint32_t tfd; 1395 uint8_t *cfis; 1396 int pending, slot, ncq; 1397 1398 DPRINTF("%s %d\n", __func__, err); 1399 1400 ncq = 0; 1401 aior = br->br_param; 1402 p = aior->io_pr; 1403 cfis = aior->cfis; 1404 slot = aior->slot; 1405 pending = aior->prdtl; 1406 sc = p->pr_sc; 1407 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE); 1408 1409 if (cfis[2] == ATA_WRITE_FPDMA_QUEUED || 1410 cfis[2] == ATA_READ_FPDMA_QUEUED) 1411 ncq = 1; 1412 1413 pthread_mutex_lock(&sc->mtx); 1414 1415 /* 1416 * Move the blockif request back to the free list 1417 */ 1418 STAILQ_INSERT_TAIL(&p->iofhd, aior, io_list); 1419 1420 if (pending && !err) { 1421 ahci_handle_dma(p, slot, cfis, aior->done, 1422 hdr->prdtl - pending); 1423 goto out; 1424 } 1425 1426 if (!err && aior->done == aior->len) { 1427 tfd = ATA_S_READY | ATA_S_DSC; 1428 if (ncq) 1429 hdr->prdbc = 0; 1430 else 1431 hdr->prdbc = aior->len; 1432 } else { 1433 tfd = (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR; 1434 hdr->prdbc = 0; 1435 if (ncq) 1436 p->serr |= (1 << slot); 1437 } 1438 1439 /* 1440 * This command is now complete. 1441 */ 1442 p->pending &= ~(1 << slot); 1443 1444 if (ncq) { 1445 p->sact &= ~(1 << slot); 1446 ahci_write_fis_sdb(p, slot, tfd); 1447 } else 1448 ahci_write_fis_d2h(p, slot, cfis, tfd); 1449 1450 out: 1451 pthread_mutex_unlock(&sc->mtx); 1452 DPRINTF("%s exit\n", __func__); 1453 } 1454 1455 static void 1456 atapi_ioreq_cb(struct blockif_req *br, int err) 1457 { 1458 struct ahci_cmd_hdr *hdr; 1459 struct ahci_ioreq *aior; 1460 struct ahci_port *p; 1461 struct pci_ahci_softc *sc; 1462 uint8_t *cfis; 1463 uint32_t tfd; 1464 int pending, slot; 1465 1466 DPRINTF("%s %d\n", __func__, err); 1467 1468 aior = br->br_param; 1469 p = aior->io_pr; 1470 cfis = aior->cfis; 1471 slot = aior->slot; 1472 pending = aior->prdtl; 1473 sc = p->pr_sc; 1474 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + aior->slot * AHCI_CL_SIZE); 1475 1476 pthread_mutex_lock(&sc->mtx); 1477 1478 /* 1479 * Move the blockif request back to the free list 1480 */ 1481 STAILQ_INSERT_TAIL(&p->iofhd, aior, io_list); 1482 1483 if (pending && !err) { 1484 atapi_read(p, slot, cfis, aior->done, hdr->prdtl - pending); 1485 goto out; 1486 } 1487 1488 if (!err && aior->done == aior->len) { 1489 tfd = ATA_S_READY | ATA_S_DSC; 1490 hdr->prdbc = aior->len; 1491 } else { 1492 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST; 1493 p->asc = 0x21; 1494 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR; 1495 hdr->prdbc = 0; 1496 } 1497 1498 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1499 ahci_write_fis_d2h(p, slot, cfis, tfd); 1500 1501 out: 1502 pthread_mutex_unlock(&sc->mtx); 1503 DPRINTF("%s exit\n", __func__); 1504 } 1505 1506 static void 1507 pci_ahci_ioreq_init(struct ahci_port *pr) 1508 { 1509 struct ahci_ioreq *vr; 1510 int i; 1511 1512 pr->ioqsz = blockif_queuesz(pr->bctx); 1513 pr->ioreq = calloc(pr->ioqsz, sizeof(struct ahci_ioreq)); 1514 STAILQ_INIT(&pr->iofhd); 1515 1516 /* 1517 * Add all i/o request entries to the free queue 1518 */ 1519 for (i = 0; i < pr->ioqsz; i++) { 1520 vr = &pr->ioreq[i]; 1521 vr->io_pr = pr; 1522 if (!pr->atapi) 1523 vr->io_req.br_callback = ata_ioreq_cb; 1524 else 1525 vr->io_req.br_callback = atapi_ioreq_cb; 1526 vr->io_req.br_param = vr; 1527 STAILQ_INSERT_TAIL(&pr->iofhd, vr, io_list); 1528 } 1529 } 1530 1531 static void 1532 pci_ahci_port_write(struct pci_ahci_softc *sc, uint64_t offset, uint64_t value) 1533 { 1534 int port = (offset - AHCI_OFFSET) / AHCI_STEP; 1535 offset = (offset - AHCI_OFFSET) % AHCI_STEP; 1536 struct ahci_port *p = &sc->port[port]; 1537 1538 DPRINTF("pci_ahci_port %d: write offset 0x%"PRIx64" value 0x%"PRIx64"\n", 1539 port, offset, value); 1540 1541 switch (offset) { 1542 case AHCI_P_CLB: 1543 p->clb = value; 1544 break; 1545 case AHCI_P_CLBU: 1546 p->clbu = value; 1547 break; 1548 case AHCI_P_FB: 1549 p->fb = value; 1550 break; 1551 case AHCI_P_FBU: 1552 p->fbu = value; 1553 break; 1554 case AHCI_P_IS: 1555 p->is &= ~value; 1556 break; 1557 case AHCI_P_IE: 1558 p->ie = value & 0xFDC000FF; 1559 ahci_generate_intr(sc); 1560 break; 1561 case AHCI_P_CMD: 1562 { 1563 p->cmd = value; 1564 1565 if (!(value & AHCI_P_CMD_ST)) { 1566 p->cmd &= ~(AHCI_P_CMD_CR | AHCI_P_CMD_CCS_MASK); 1567 p->ci = 0; 1568 p->sact = 0; 1569 } else { 1570 uint64_t clb; 1571 1572 p->cmd |= AHCI_P_CMD_CR; 1573 clb = (uint64_t)p->clbu << 32 | p->clb; 1574 p->cmd_lst = paddr_guest2host(ahci_ctx(sc), clb, 1575 AHCI_CL_SIZE * AHCI_MAX_SLOTS); 1576 } 1577 1578 if (value & AHCI_P_CMD_FRE) { 1579 uint64_t fb; 1580 1581 p->cmd |= AHCI_P_CMD_FR; 1582 fb = (uint64_t)p->fbu << 32 | p->fb; 1583 /* we don't support FBSCP, so rfis size is 256Bytes */ 1584 p->rfis = paddr_guest2host(ahci_ctx(sc), fb, 256); 1585 } else { 1586 p->cmd &= ~AHCI_P_CMD_FR; 1587 } 1588 1589 if (value & AHCI_P_CMD_CLO) { 1590 p->tfd = 0; 1591 p->cmd &= ~AHCI_P_CMD_CLO; 1592 } 1593 1594 ahci_handle_port(p); 1595 break; 1596 } 1597 case AHCI_P_TFD: 1598 case AHCI_P_SIG: 1599 case AHCI_P_SSTS: 1600 WPRINTF("pci_ahci_port: read only registers 0x%"PRIx64"\n", offset); 1601 break; 1602 case AHCI_P_SCTL: 1603 if (!(p->cmd & AHCI_P_CMD_ST)) { 1604 if (value & ATA_SC_DET_RESET) 1605 ahci_port_reset(p); 1606 p->sctl = value; 1607 } 1608 break; 1609 case AHCI_P_SERR: 1610 p->serr &= ~value; 1611 break; 1612 case AHCI_P_SACT: 1613 p->sact |= value; 1614 break; 1615 case AHCI_P_CI: 1616 p->ci |= value; 1617 ahci_handle_port(p); 1618 break; 1619 case AHCI_P_SNTF: 1620 case AHCI_P_FBS: 1621 default: 1622 break; 1623 } 1624 } 1625 1626 static void 1627 pci_ahci_host_write(struct pci_ahci_softc *sc, uint64_t offset, uint64_t value) 1628 { 1629 DPRINTF("pci_ahci_host: write offset 0x%"PRIx64" value 0x%"PRIx64"\n", 1630 offset, value); 1631 1632 switch (offset) { 1633 case AHCI_CAP: 1634 case AHCI_PI: 1635 case AHCI_VS: 1636 case AHCI_CAP2: 1637 DPRINTF("pci_ahci_host: read only registers 0x%"PRIx64"\n", offset); 1638 break; 1639 case AHCI_GHC: 1640 if (value & AHCI_GHC_HR) 1641 ahci_reset(sc); 1642 else if (value & AHCI_GHC_IE) { 1643 sc->ghc |= AHCI_GHC_IE; 1644 ahci_generate_intr(sc); 1645 } 1646 break; 1647 case AHCI_IS: 1648 sc->is &= ~value; 1649 ahci_generate_intr(sc); 1650 break; 1651 default: 1652 break; 1653 } 1654 } 1655 1656 static void 1657 pci_ahci_write(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, 1658 int baridx, uint64_t offset, int size, uint64_t value) 1659 { 1660 struct pci_ahci_softc *sc = pi->pi_arg; 1661 1662 assert(baridx == 5); 1663 assert(size == 4); 1664 1665 pthread_mutex_lock(&sc->mtx); 1666 1667 if (offset < AHCI_OFFSET) 1668 pci_ahci_host_write(sc, offset, value); 1669 else if (offset < AHCI_OFFSET + sc->ports * AHCI_STEP) 1670 pci_ahci_port_write(sc, offset, value); 1671 else 1672 WPRINTF("pci_ahci: unknown i/o write offset 0x%"PRIx64"\n", offset); 1673 1674 pthread_mutex_unlock(&sc->mtx); 1675 } 1676 1677 static uint64_t 1678 pci_ahci_host_read(struct pci_ahci_softc *sc, uint64_t offset) 1679 { 1680 uint32_t value; 1681 1682 switch (offset) { 1683 case AHCI_CAP: 1684 case AHCI_GHC: 1685 case AHCI_IS: 1686 case AHCI_PI: 1687 case AHCI_VS: 1688 case AHCI_CCCC: 1689 case AHCI_CCCP: 1690 case AHCI_EM_LOC: 1691 case AHCI_EM_CTL: 1692 case AHCI_CAP2: 1693 { 1694 uint32_t *p = &sc->cap; 1695 p += (offset - AHCI_CAP) / sizeof(uint32_t); 1696 value = *p; 1697 break; 1698 } 1699 default: 1700 value = 0; 1701 break; 1702 } 1703 DPRINTF("pci_ahci_host: read offset 0x%"PRIx64" value 0x%x\n", 1704 offset, value); 1705 1706 return (value); 1707 } 1708 1709 static uint64_t 1710 pci_ahci_port_read(struct pci_ahci_softc *sc, uint64_t offset) 1711 { 1712 uint32_t value; 1713 int port = (offset - AHCI_OFFSET) / AHCI_STEP; 1714 offset = (offset - AHCI_OFFSET) % AHCI_STEP; 1715 1716 switch (offset) { 1717 case AHCI_P_CLB: 1718 case AHCI_P_CLBU: 1719 case AHCI_P_FB: 1720 case AHCI_P_FBU: 1721 case AHCI_P_IS: 1722 case AHCI_P_IE: 1723 case AHCI_P_CMD: 1724 case AHCI_P_TFD: 1725 case AHCI_P_SIG: 1726 case AHCI_P_SSTS: 1727 case AHCI_P_SCTL: 1728 case AHCI_P_SERR: 1729 case AHCI_P_SACT: 1730 case AHCI_P_CI: 1731 case AHCI_P_SNTF: 1732 case AHCI_P_FBS: 1733 { 1734 uint32_t *p= &sc->port[port].clb; 1735 p += (offset - AHCI_P_CLB) / sizeof(uint32_t); 1736 value = *p; 1737 break; 1738 } 1739 default: 1740 value = 0; 1741 break; 1742 } 1743 1744 DPRINTF("pci_ahci_port %d: read offset 0x%"PRIx64" value 0x%x\n", 1745 port, offset, value); 1746 1747 return value; 1748 } 1749 1750 static uint64_t 1751 pci_ahci_read(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, int baridx, 1752 uint64_t offset, int size) 1753 { 1754 struct pci_ahci_softc *sc = pi->pi_arg; 1755 uint32_t value; 1756 1757 assert(baridx == 5); 1758 assert(size == 4); 1759 1760 pthread_mutex_lock(&sc->mtx); 1761 1762 if (offset < AHCI_OFFSET) 1763 value = pci_ahci_host_read(sc, offset); 1764 else if (offset < AHCI_OFFSET + sc->ports * AHCI_STEP) 1765 value = pci_ahci_port_read(sc, offset); 1766 else { 1767 value = 0; 1768 WPRINTF("pci_ahci: unknown i/o read offset 0x%"PRIx64"\n", offset); 1769 } 1770 1771 pthread_mutex_unlock(&sc->mtx); 1772 1773 return (value); 1774 } 1775 1776 static int 1777 pci_ahci_init(struct vmctx *ctx, struct pci_devinst *pi, char *opts, int atapi) 1778 { 1779 char bident[sizeof("XX:X:X")]; 1780 struct blockif_ctxt *bctxt; 1781 struct pci_ahci_softc *sc; 1782 int ret, slots; 1783 1784 ret = 0; 1785 1786 if (opts == NULL) { 1787 fprintf(stderr, "pci_ahci: backing device required\n"); 1788 return (1); 1789 } 1790 1791 #ifdef AHCI_DEBUG 1792 dbg = fopen("/tmp/log", "w+"); 1793 #endif 1794 1795 sc = calloc(1, sizeof(struct pci_ahci_softc)); 1796 pi->pi_arg = sc; 1797 sc->asc_pi = pi; 1798 sc->ports = MAX_PORTS; 1799 1800 /* 1801 * Only use port 0 for a backing device. All other ports will be 1802 * marked as unused 1803 */ 1804 sc->port[0].atapi = atapi; 1805 1806 /* 1807 * Attempt to open the backing image. Use the PCI 1808 * slot/func for the identifier string. 1809 */ 1810 snprintf(bident, sizeof(bident), "%d:%d", pi->pi_slot, pi->pi_func); 1811 bctxt = blockif_open(opts, bident); 1812 if (bctxt == NULL) { 1813 ret = 1; 1814 goto open_fail; 1815 } 1816 sc->port[0].bctx = bctxt; 1817 sc->port[0].pr_sc = sc; 1818 1819 /* 1820 * Allocate blockif request structures and add them 1821 * to the free list 1822 */ 1823 pci_ahci_ioreq_init(&sc->port[0]); 1824 1825 pthread_mutex_init(&sc->mtx, NULL); 1826 1827 /* Intel ICH8 AHCI */ 1828 slots = sc->port[0].ioqsz; 1829 if (slots > 32) 1830 slots = 32; 1831 --slots; 1832 sc->cap = AHCI_CAP_64BIT | AHCI_CAP_SNCQ | AHCI_CAP_SSNTF | 1833 AHCI_CAP_SMPS | AHCI_CAP_SSS | AHCI_CAP_SALP | 1834 AHCI_CAP_SAL | AHCI_CAP_SCLO | (0x3 << AHCI_CAP_ISS_SHIFT)| 1835 AHCI_CAP_PMD | AHCI_CAP_SSC | AHCI_CAP_PSC | 1836 (slots << AHCI_CAP_NCS_SHIFT) | AHCI_CAP_SXS | (sc->ports - 1); 1837 1838 /* Only port 0 implemented */ 1839 sc->pi = 1; 1840 sc->vs = 0x10300; 1841 sc->cap2 = AHCI_CAP2_APST; 1842 ahci_reset(sc); 1843 1844 pci_set_cfgdata16(pi, PCIR_DEVICE, 0x2821); 1845 pci_set_cfgdata16(pi, PCIR_VENDOR, 0x8086); 1846 pci_set_cfgdata8(pi, PCIR_CLASS, PCIC_STORAGE); 1847 pci_set_cfgdata8(pi, PCIR_SUBCLASS, PCIS_STORAGE_SATA); 1848 pci_set_cfgdata8(pi, PCIR_PROGIF, PCIP_STORAGE_SATA_AHCI_1_0); 1849 pci_emul_add_msicap(pi, 1); 1850 pci_emul_alloc_bar(pi, 5, PCIBAR_MEM32, 1851 AHCI_OFFSET + sc->ports * AHCI_STEP); 1852 1853 pci_lintr_request(pi); 1854 1855 open_fail: 1856 if (ret) { 1857 blockif_close(sc->port[0].bctx); 1858 free(sc); 1859 } 1860 1861 return (ret); 1862 } 1863 1864 static int 1865 pci_ahci_hd_init(struct vmctx *ctx, struct pci_devinst *pi, char *opts) 1866 { 1867 1868 return (pci_ahci_init(ctx, pi, opts, 0)); 1869 } 1870 1871 static int 1872 pci_ahci_atapi_init(struct vmctx *ctx, struct pci_devinst *pi, char *opts) 1873 { 1874 1875 return (pci_ahci_init(ctx, pi, opts, 1)); 1876 } 1877 1878 /* 1879 * Use separate emulation names to distinguish drive and atapi devices 1880 */ 1881 struct pci_devemu pci_de_ahci_hd = { 1882 .pe_emu = "ahci-hd", 1883 .pe_init = pci_ahci_hd_init, 1884 .pe_barwrite = pci_ahci_write, 1885 .pe_barread = pci_ahci_read 1886 }; 1887 PCI_EMUL_SET(pci_de_ahci_hd); 1888 1889 struct pci_devemu pci_de_ahci_cd = { 1890 .pe_emu = "ahci-cd", 1891 .pe_init = pci_ahci_atapi_init, 1892 .pe_barwrite = pci_ahci_write, 1893 .pe_barread = pci_ahci_read 1894 }; 1895 PCI_EMUL_SET(pci_de_ahci_cd); 1896