1 /*- 2 * Copyright (c) 2013 Zhixiang Yu <zcore@freebsd.org> 3 * Copyright (c) 2015-2016 Alexander Motin <mav@FreeBSD.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include <sys/param.h> 34 #include <sys/linker_set.h> 35 #include <sys/stat.h> 36 #include <sys/uio.h> 37 #include <sys/ioctl.h> 38 #include <sys/disk.h> 39 #include <sys/ata.h> 40 #include <sys/endian.h> 41 42 #include <errno.h> 43 #include <fcntl.h> 44 #include <stdio.h> 45 #include <stdlib.h> 46 #include <stdint.h> 47 #include <string.h> 48 #include <strings.h> 49 #include <unistd.h> 50 #include <assert.h> 51 #include <pthread.h> 52 #include <pthread_np.h> 53 #include <inttypes.h> 54 #include <md5.h> 55 56 #include "bhyverun.h" 57 #include "pci_emul.h" 58 #include "ahci.h" 59 #include "block_if.h" 60 61 #define DEF_PORTS 6 /* Intel ICH8 AHCI supports 6 ports */ 62 #define MAX_PORTS 32 /* AHCI supports 32 ports */ 63 64 #define PxSIG_ATA 0x00000101 /* ATA drive */ 65 #define PxSIG_ATAPI 0xeb140101 /* ATAPI drive */ 66 67 enum sata_fis_type { 68 FIS_TYPE_REGH2D = 0x27, /* Register FIS - host to device */ 69 FIS_TYPE_REGD2H = 0x34, /* Register FIS - device to host */ 70 FIS_TYPE_DMAACT = 0x39, /* DMA activate FIS - device to host */ 71 FIS_TYPE_DMASETUP = 0x41, /* DMA setup FIS - bidirectional */ 72 FIS_TYPE_DATA = 0x46, /* Data FIS - bidirectional */ 73 FIS_TYPE_BIST = 0x58, /* BIST activate FIS - bidirectional */ 74 FIS_TYPE_PIOSETUP = 0x5F, /* PIO setup FIS - device to host */ 75 FIS_TYPE_SETDEVBITS = 0xA1, /* Set dev bits FIS - device to host */ 76 }; 77 78 /* 79 * SCSI opcodes 80 */ 81 #define TEST_UNIT_READY 0x00 82 #define REQUEST_SENSE 0x03 83 #define INQUIRY 0x12 84 #define START_STOP_UNIT 0x1B 85 #define PREVENT_ALLOW 0x1E 86 #define READ_CAPACITY 0x25 87 #define READ_10 0x28 88 #define POSITION_TO_ELEMENT 0x2B 89 #define READ_TOC 0x43 90 #define GET_EVENT_STATUS_NOTIFICATION 0x4A 91 #define MODE_SENSE_10 0x5A 92 #define REPORT_LUNS 0xA0 93 #define READ_12 0xA8 94 #define READ_CD 0xBE 95 96 /* 97 * SCSI mode page codes 98 */ 99 #define MODEPAGE_RW_ERROR_RECOVERY 0x01 100 #define MODEPAGE_CD_CAPABILITIES 0x2A 101 102 /* 103 * ATA commands 104 */ 105 #define ATA_SF_ENAB_SATA_SF 0x10 106 #define ATA_SATA_SF_AN 0x05 107 #define ATA_SF_DIS_SATA_SF 0x90 108 109 /* 110 * Debug printf 111 */ 112 #ifdef AHCI_DEBUG 113 static FILE *dbg; 114 #define DPRINTF(format, arg...) do{fprintf(dbg, format, ##arg);fflush(dbg);}while(0) 115 #else 116 #define DPRINTF(format, arg...) 117 #endif 118 #define WPRINTF(format, arg...) printf(format, ##arg) 119 120 struct ahci_ioreq { 121 struct blockif_req io_req; 122 struct ahci_port *io_pr; 123 STAILQ_ENTRY(ahci_ioreq) io_flist; 124 TAILQ_ENTRY(ahci_ioreq) io_blist; 125 uint8_t *cfis; 126 uint32_t len; 127 uint32_t done; 128 int slot; 129 int more; 130 }; 131 132 struct ahci_port { 133 struct blockif_ctxt *bctx; 134 struct pci_ahci_softc *pr_sc; 135 uint8_t *cmd_lst; 136 uint8_t *rfis; 137 char ident[20 + 1]; 138 int port; 139 int atapi; 140 int reset; 141 int waitforclear; 142 int mult_sectors; 143 uint8_t xfermode; 144 uint8_t err_cfis[20]; 145 uint8_t sense_key; 146 uint8_t asc; 147 u_int ccs; 148 uint32_t pending; 149 150 uint32_t clb; 151 uint32_t clbu; 152 uint32_t fb; 153 uint32_t fbu; 154 uint32_t is; 155 uint32_t ie; 156 uint32_t cmd; 157 uint32_t unused0; 158 uint32_t tfd; 159 uint32_t sig; 160 uint32_t ssts; 161 uint32_t sctl; 162 uint32_t serr; 163 uint32_t sact; 164 uint32_t ci; 165 uint32_t sntf; 166 uint32_t fbs; 167 168 /* 169 * i/o request info 170 */ 171 struct ahci_ioreq *ioreq; 172 int ioqsz; 173 STAILQ_HEAD(ahci_fhead, ahci_ioreq) iofhd; 174 TAILQ_HEAD(ahci_bhead, ahci_ioreq) iobhd; 175 }; 176 177 struct ahci_cmd_hdr { 178 uint16_t flags; 179 uint16_t prdtl; 180 uint32_t prdbc; 181 uint64_t ctba; 182 uint32_t reserved[4]; 183 }; 184 185 struct ahci_prdt_entry { 186 uint64_t dba; 187 uint32_t reserved; 188 #define DBCMASK 0x3fffff 189 uint32_t dbc; 190 }; 191 192 struct pci_ahci_softc { 193 struct pci_devinst *asc_pi; 194 pthread_mutex_t mtx; 195 int ports; 196 uint32_t cap; 197 uint32_t ghc; 198 uint32_t is; 199 uint32_t pi; 200 uint32_t vs; 201 uint32_t ccc_ctl; 202 uint32_t ccc_pts; 203 uint32_t em_loc; 204 uint32_t em_ctl; 205 uint32_t cap2; 206 uint32_t bohc; 207 uint32_t lintr; 208 struct ahci_port port[MAX_PORTS]; 209 }; 210 #define ahci_ctx(sc) ((sc)->asc_pi->pi_vmctx) 211 212 static void ahci_handle_port(struct ahci_port *p); 213 214 static inline void lba_to_msf(uint8_t *buf, int lba) 215 { 216 lba += 150; 217 buf[0] = (lba / 75) / 60; 218 buf[1] = (lba / 75) % 60; 219 buf[2] = lba % 75; 220 } 221 222 /* 223 * Generate HBA interrupts on global IS register write. 224 */ 225 static void 226 ahci_generate_intr(struct pci_ahci_softc *sc, uint32_t mask) 227 { 228 struct pci_devinst *pi = sc->asc_pi; 229 struct ahci_port *p; 230 int i, nmsg; 231 uint32_t mmask; 232 233 /* Update global IS from PxIS/PxIE. */ 234 for (i = 0; i < sc->ports; i++) { 235 p = &sc->port[i]; 236 if (p->is & p->ie) 237 sc->is |= (1 << i); 238 } 239 DPRINTF("%s(%08x) %08x\n", __func__, mask, sc->is); 240 241 /* If there is nothing enabled -- clear legacy interrupt and exit. */ 242 if (sc->is == 0 || (sc->ghc & AHCI_GHC_IE) == 0) { 243 if (sc->lintr) { 244 pci_lintr_deassert(pi); 245 sc->lintr = 0; 246 } 247 return; 248 } 249 250 /* If there is anything and no MSI -- assert legacy interrupt. */ 251 nmsg = pci_msi_maxmsgnum(pi); 252 if (nmsg == 0) { 253 if (!sc->lintr) { 254 sc->lintr = 1; 255 pci_lintr_assert(pi); 256 } 257 return; 258 } 259 260 /* Assert respective MSIs for ports that were touched. */ 261 for (i = 0; i < nmsg; i++) { 262 if (sc->ports <= nmsg || i < nmsg - 1) 263 mmask = 1 << i; 264 else 265 mmask = 0xffffffff << i; 266 if (sc->is & mask && mmask & mask) 267 pci_generate_msi(pi, i); 268 } 269 } 270 271 /* 272 * Generate HBA interrupt on specific port event. 273 */ 274 static void 275 ahci_port_intr(struct ahci_port *p) 276 { 277 struct pci_ahci_softc *sc = p->pr_sc; 278 struct pci_devinst *pi = sc->asc_pi; 279 int nmsg; 280 281 DPRINTF("%s(%d) %08x/%08x %08x\n", __func__, 282 p->port, p->is, p->ie, sc->is); 283 284 /* If there is nothing enabled -- we are done. */ 285 if ((p->is & p->ie) == 0) 286 return; 287 288 /* In case of non-shared MSI always generate interrupt. */ 289 nmsg = pci_msi_maxmsgnum(pi); 290 if (sc->ports <= nmsg || p->port < nmsg - 1) { 291 sc->is |= (1 << p->port); 292 if ((sc->ghc & AHCI_GHC_IE) == 0) 293 return; 294 pci_generate_msi(pi, p->port); 295 return; 296 } 297 298 /* If IS for this port is already set -- do nothing. */ 299 if (sc->is & (1 << p->port)) 300 return; 301 302 sc->is |= (1 << p->port); 303 304 /* If interrupts are enabled -- generate one. */ 305 if ((sc->ghc & AHCI_GHC_IE) == 0) 306 return; 307 if (nmsg > 0) { 308 pci_generate_msi(pi, nmsg - 1); 309 } else if (!sc->lintr) { 310 sc->lintr = 1; 311 pci_lintr_assert(pi); 312 } 313 } 314 315 static void 316 ahci_write_fis(struct ahci_port *p, enum sata_fis_type ft, uint8_t *fis) 317 { 318 int offset, len, irq; 319 320 if (p->rfis == NULL || !(p->cmd & AHCI_P_CMD_FRE)) 321 return; 322 323 switch (ft) { 324 case FIS_TYPE_REGD2H: 325 offset = 0x40; 326 len = 20; 327 irq = (fis[1] & (1 << 6)) ? AHCI_P_IX_DHR : 0; 328 break; 329 case FIS_TYPE_SETDEVBITS: 330 offset = 0x58; 331 len = 8; 332 irq = (fis[1] & (1 << 6)) ? AHCI_P_IX_SDB : 0; 333 break; 334 case FIS_TYPE_PIOSETUP: 335 offset = 0x20; 336 len = 20; 337 irq = (fis[1] & (1 << 6)) ? AHCI_P_IX_PS : 0; 338 break; 339 default: 340 WPRINTF("unsupported fis type %d\n", ft); 341 return; 342 } 343 if (fis[2] & ATA_S_ERROR) { 344 p->waitforclear = 1; 345 irq |= AHCI_P_IX_TFE; 346 } 347 memcpy(p->rfis + offset, fis, len); 348 if (irq) { 349 if (~p->is & irq) { 350 p->is |= irq; 351 ahci_port_intr(p); 352 } 353 } 354 } 355 356 static void 357 ahci_write_fis_piosetup(struct ahci_port *p) 358 { 359 uint8_t fis[20]; 360 361 memset(fis, 0, sizeof(fis)); 362 fis[0] = FIS_TYPE_PIOSETUP; 363 ahci_write_fis(p, FIS_TYPE_PIOSETUP, fis); 364 } 365 366 static void 367 ahci_write_fis_sdb(struct ahci_port *p, int slot, uint8_t *cfis, uint32_t tfd) 368 { 369 uint8_t fis[8]; 370 uint8_t error; 371 372 error = (tfd >> 8) & 0xff; 373 tfd &= 0x77; 374 memset(fis, 0, sizeof(fis)); 375 fis[0] = FIS_TYPE_SETDEVBITS; 376 fis[1] = (1 << 6); 377 fis[2] = tfd; 378 fis[3] = error; 379 if (fis[2] & ATA_S_ERROR) { 380 p->err_cfis[0] = slot; 381 p->err_cfis[2] = tfd; 382 p->err_cfis[3] = error; 383 memcpy(&p->err_cfis[4], cfis + 4, 16); 384 } else { 385 *(uint32_t *)(fis + 4) = (1 << slot); 386 p->sact &= ~(1 << slot); 387 } 388 p->tfd &= ~0x77; 389 p->tfd |= tfd; 390 ahci_write_fis(p, FIS_TYPE_SETDEVBITS, fis); 391 } 392 393 static void 394 ahci_write_fis_d2h(struct ahci_port *p, int slot, uint8_t *cfis, uint32_t tfd) 395 { 396 uint8_t fis[20]; 397 uint8_t error; 398 399 error = (tfd >> 8) & 0xff; 400 memset(fis, 0, sizeof(fis)); 401 fis[0] = FIS_TYPE_REGD2H; 402 fis[1] = (1 << 6); 403 fis[2] = tfd & 0xff; 404 fis[3] = error; 405 fis[4] = cfis[4]; 406 fis[5] = cfis[5]; 407 fis[6] = cfis[6]; 408 fis[7] = cfis[7]; 409 fis[8] = cfis[8]; 410 fis[9] = cfis[9]; 411 fis[10] = cfis[10]; 412 fis[11] = cfis[11]; 413 fis[12] = cfis[12]; 414 fis[13] = cfis[13]; 415 if (fis[2] & ATA_S_ERROR) { 416 p->err_cfis[0] = 0x80; 417 p->err_cfis[2] = tfd & 0xff; 418 p->err_cfis[3] = error; 419 memcpy(&p->err_cfis[4], cfis + 4, 16); 420 } else 421 p->ci &= ~(1 << slot); 422 p->tfd = tfd; 423 ahci_write_fis(p, FIS_TYPE_REGD2H, fis); 424 } 425 426 static void 427 ahci_write_fis_d2h_ncq(struct ahci_port *p, int slot) 428 { 429 uint8_t fis[20]; 430 431 p->tfd = ATA_S_READY | ATA_S_DSC; 432 memset(fis, 0, sizeof(fis)); 433 fis[0] = FIS_TYPE_REGD2H; 434 fis[1] = 0; /* No interrupt */ 435 fis[2] = p->tfd; /* Status */ 436 fis[3] = 0; /* No error */ 437 p->ci &= ~(1 << slot); 438 ahci_write_fis(p, FIS_TYPE_REGD2H, fis); 439 } 440 441 static void 442 ahci_write_reset_fis_d2h(struct ahci_port *p) 443 { 444 uint8_t fis[20]; 445 446 memset(fis, 0, sizeof(fis)); 447 fis[0] = FIS_TYPE_REGD2H; 448 fis[3] = 1; 449 fis[4] = 1; 450 if (p->atapi) { 451 fis[5] = 0x14; 452 fis[6] = 0xeb; 453 } 454 fis[12] = 1; 455 ahci_write_fis(p, FIS_TYPE_REGD2H, fis); 456 } 457 458 static void 459 ahci_check_stopped(struct ahci_port *p) 460 { 461 /* 462 * If we are no longer processing the command list and nothing 463 * is in-flight, clear the running bit, the current command 464 * slot, the command issue and active bits. 465 */ 466 if (!(p->cmd & AHCI_P_CMD_ST)) { 467 if (p->pending == 0) { 468 p->ccs = 0; 469 p->cmd &= ~(AHCI_P_CMD_CR | AHCI_P_CMD_CCS_MASK); 470 p->ci = 0; 471 p->sact = 0; 472 p->waitforclear = 0; 473 } 474 } 475 } 476 477 static void 478 ahci_port_stop(struct ahci_port *p) 479 { 480 struct ahci_ioreq *aior; 481 uint8_t *cfis; 482 int slot; 483 int error; 484 485 assert(pthread_mutex_isowned_np(&p->pr_sc->mtx)); 486 487 TAILQ_FOREACH(aior, &p->iobhd, io_blist) { 488 /* 489 * Try to cancel the outstanding blockif request. 490 */ 491 error = blockif_cancel(p->bctx, &aior->io_req); 492 if (error != 0) 493 continue; 494 495 slot = aior->slot; 496 cfis = aior->cfis; 497 if (cfis[2] == ATA_WRITE_FPDMA_QUEUED || 498 cfis[2] == ATA_READ_FPDMA_QUEUED || 499 cfis[2] == ATA_SEND_FPDMA_QUEUED) 500 p->sact &= ~(1 << slot); /* NCQ */ 501 else 502 p->ci &= ~(1 << slot); 503 504 /* 505 * This command is now done. 506 */ 507 p->pending &= ~(1 << slot); 508 509 /* 510 * Delete the blockif request from the busy list 511 */ 512 TAILQ_REMOVE(&p->iobhd, aior, io_blist); 513 514 /* 515 * Move the blockif request back to the free list 516 */ 517 STAILQ_INSERT_TAIL(&p->iofhd, aior, io_flist); 518 } 519 520 ahci_check_stopped(p); 521 } 522 523 static void 524 ahci_port_reset(struct ahci_port *pr) 525 { 526 pr->serr = 0; 527 pr->sact = 0; 528 pr->xfermode = ATA_UDMA6; 529 pr->mult_sectors = 128; 530 531 if (!pr->bctx) { 532 pr->ssts = ATA_SS_DET_NO_DEVICE; 533 pr->sig = 0xFFFFFFFF; 534 pr->tfd = 0x7F; 535 return; 536 } 537 pr->ssts = ATA_SS_DET_PHY_ONLINE | ATA_SS_IPM_ACTIVE; 538 if (pr->sctl & ATA_SC_SPD_MASK) 539 pr->ssts |= (pr->sctl & ATA_SC_SPD_MASK); 540 else 541 pr->ssts |= ATA_SS_SPD_GEN3; 542 pr->tfd = (1 << 8) | ATA_S_DSC | ATA_S_DMA; 543 if (!pr->atapi) { 544 pr->sig = PxSIG_ATA; 545 pr->tfd |= ATA_S_READY; 546 } else 547 pr->sig = PxSIG_ATAPI; 548 ahci_write_reset_fis_d2h(pr); 549 } 550 551 static void 552 ahci_reset(struct pci_ahci_softc *sc) 553 { 554 int i; 555 556 sc->ghc = AHCI_GHC_AE; 557 sc->is = 0; 558 559 if (sc->lintr) { 560 pci_lintr_deassert(sc->asc_pi); 561 sc->lintr = 0; 562 } 563 564 for (i = 0; i < sc->ports; i++) { 565 sc->port[i].ie = 0; 566 sc->port[i].is = 0; 567 sc->port[i].cmd = (AHCI_P_CMD_SUD | AHCI_P_CMD_POD); 568 if (sc->port[i].bctx) 569 sc->port[i].cmd |= AHCI_P_CMD_CPS; 570 sc->port[i].sctl = 0; 571 ahci_port_reset(&sc->port[i]); 572 } 573 } 574 575 static void 576 ata_string(uint8_t *dest, const char *src, int len) 577 { 578 int i; 579 580 for (i = 0; i < len; i++) { 581 if (*src) 582 dest[i ^ 1] = *src++; 583 else 584 dest[i ^ 1] = ' '; 585 } 586 } 587 588 static void 589 atapi_string(uint8_t *dest, const char *src, int len) 590 { 591 int i; 592 593 for (i = 0; i < len; i++) { 594 if (*src) 595 dest[i] = *src++; 596 else 597 dest[i] = ' '; 598 } 599 } 600 601 /* 602 * Build up the iovec based on the PRDT, 'done' and 'len'. 603 */ 604 static void 605 ahci_build_iov(struct ahci_port *p, struct ahci_ioreq *aior, 606 struct ahci_prdt_entry *prdt, uint16_t prdtl) 607 { 608 struct blockif_req *breq = &aior->io_req; 609 int i, j, skip, todo, left, extra; 610 uint32_t dbcsz; 611 612 /* Copy part of PRDT between 'done' and 'len' bytes into the iov. */ 613 skip = aior->done; 614 left = aior->len - aior->done; 615 todo = 0; 616 for (i = 0, j = 0; i < prdtl && j < BLOCKIF_IOV_MAX && left > 0; 617 i++, prdt++) { 618 dbcsz = (prdt->dbc & DBCMASK) + 1; 619 /* Skip already done part of the PRDT */ 620 if (dbcsz <= skip) { 621 skip -= dbcsz; 622 continue; 623 } 624 dbcsz -= skip; 625 if (dbcsz > left) 626 dbcsz = left; 627 breq->br_iov[j].iov_base = paddr_guest2host(ahci_ctx(p->pr_sc), 628 prdt->dba + skip, dbcsz); 629 breq->br_iov[j].iov_len = dbcsz; 630 todo += dbcsz; 631 left -= dbcsz; 632 skip = 0; 633 j++; 634 } 635 636 /* If we got limited by IOV length, round I/O down to sector size. */ 637 if (j == BLOCKIF_IOV_MAX) { 638 extra = todo % blockif_sectsz(p->bctx); 639 todo -= extra; 640 assert(todo > 0); 641 while (extra > 0) { 642 if (breq->br_iov[j - 1].iov_len > extra) { 643 breq->br_iov[j - 1].iov_len -= extra; 644 break; 645 } 646 extra -= breq->br_iov[j - 1].iov_len; 647 j--; 648 } 649 } 650 651 breq->br_iovcnt = j; 652 breq->br_resid = todo; 653 aior->done += todo; 654 aior->more = (aior->done < aior->len && i < prdtl); 655 } 656 657 static void 658 ahci_handle_rw(struct ahci_port *p, int slot, uint8_t *cfis, uint32_t done) 659 { 660 struct ahci_ioreq *aior; 661 struct blockif_req *breq; 662 struct ahci_prdt_entry *prdt; 663 struct ahci_cmd_hdr *hdr; 664 uint64_t lba; 665 uint32_t len; 666 int err, first, ncq, readop; 667 668 prdt = (struct ahci_prdt_entry *)(cfis + 0x80); 669 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE); 670 ncq = 0; 671 readop = 1; 672 first = (done == 0); 673 674 if (cfis[2] == ATA_WRITE || cfis[2] == ATA_WRITE48 || 675 cfis[2] == ATA_WRITE_MUL || cfis[2] == ATA_WRITE_MUL48 || 676 cfis[2] == ATA_WRITE_DMA || cfis[2] == ATA_WRITE_DMA48 || 677 cfis[2] == ATA_WRITE_FPDMA_QUEUED) 678 readop = 0; 679 680 if (cfis[2] == ATA_WRITE_FPDMA_QUEUED || 681 cfis[2] == ATA_READ_FPDMA_QUEUED) { 682 lba = ((uint64_t)cfis[10] << 40) | 683 ((uint64_t)cfis[9] << 32) | 684 ((uint64_t)cfis[8] << 24) | 685 ((uint64_t)cfis[6] << 16) | 686 ((uint64_t)cfis[5] << 8) | 687 cfis[4]; 688 len = cfis[11] << 8 | cfis[3]; 689 if (!len) 690 len = 65536; 691 ncq = 1; 692 } else if (cfis[2] == ATA_READ48 || cfis[2] == ATA_WRITE48 || 693 cfis[2] == ATA_READ_MUL48 || cfis[2] == ATA_WRITE_MUL48 || 694 cfis[2] == ATA_READ_DMA48 || cfis[2] == ATA_WRITE_DMA48) { 695 lba = ((uint64_t)cfis[10] << 40) | 696 ((uint64_t)cfis[9] << 32) | 697 ((uint64_t)cfis[8] << 24) | 698 ((uint64_t)cfis[6] << 16) | 699 ((uint64_t)cfis[5] << 8) | 700 cfis[4]; 701 len = cfis[13] << 8 | cfis[12]; 702 if (!len) 703 len = 65536; 704 } else { 705 lba = ((cfis[7] & 0xf) << 24) | (cfis[6] << 16) | 706 (cfis[5] << 8) | cfis[4]; 707 len = cfis[12]; 708 if (!len) 709 len = 256; 710 } 711 lba *= blockif_sectsz(p->bctx); 712 len *= blockif_sectsz(p->bctx); 713 714 /* Pull request off free list */ 715 aior = STAILQ_FIRST(&p->iofhd); 716 assert(aior != NULL); 717 STAILQ_REMOVE_HEAD(&p->iofhd, io_flist); 718 719 aior->cfis = cfis; 720 aior->slot = slot; 721 aior->len = len; 722 aior->done = done; 723 breq = &aior->io_req; 724 breq->br_offset = lba + done; 725 ahci_build_iov(p, aior, prdt, hdr->prdtl); 726 727 /* Mark this command in-flight. */ 728 p->pending |= 1 << slot; 729 730 /* Stuff request onto busy list. */ 731 TAILQ_INSERT_HEAD(&p->iobhd, aior, io_blist); 732 733 if (ncq && first) 734 ahci_write_fis_d2h_ncq(p, slot); 735 736 if (readop) 737 err = blockif_read(p->bctx, breq); 738 else 739 err = blockif_write(p->bctx, breq); 740 assert(err == 0); 741 } 742 743 static void 744 ahci_handle_flush(struct ahci_port *p, int slot, uint8_t *cfis) 745 { 746 struct ahci_ioreq *aior; 747 struct blockif_req *breq; 748 int err; 749 750 /* 751 * Pull request off free list 752 */ 753 aior = STAILQ_FIRST(&p->iofhd); 754 assert(aior != NULL); 755 STAILQ_REMOVE_HEAD(&p->iofhd, io_flist); 756 aior->cfis = cfis; 757 aior->slot = slot; 758 aior->len = 0; 759 aior->done = 0; 760 aior->more = 0; 761 breq = &aior->io_req; 762 763 /* 764 * Mark this command in-flight. 765 */ 766 p->pending |= 1 << slot; 767 768 /* 769 * Stuff request onto busy list 770 */ 771 TAILQ_INSERT_HEAD(&p->iobhd, aior, io_blist); 772 773 err = blockif_flush(p->bctx, breq); 774 assert(err == 0); 775 } 776 777 static inline void 778 read_prdt(struct ahci_port *p, int slot, uint8_t *cfis, 779 void *buf, int size) 780 { 781 struct ahci_cmd_hdr *hdr; 782 struct ahci_prdt_entry *prdt; 783 void *to; 784 int i, len; 785 786 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE); 787 len = size; 788 to = buf; 789 prdt = (struct ahci_prdt_entry *)(cfis + 0x80); 790 for (i = 0; i < hdr->prdtl && len; i++) { 791 uint8_t *ptr; 792 uint32_t dbcsz; 793 int sublen; 794 795 dbcsz = (prdt->dbc & DBCMASK) + 1; 796 ptr = paddr_guest2host(ahci_ctx(p->pr_sc), prdt->dba, dbcsz); 797 sublen = MIN(len, dbcsz); 798 memcpy(to, ptr, sublen); 799 len -= sublen; 800 to += sublen; 801 prdt++; 802 } 803 } 804 805 static void 806 ahci_handle_dsm_trim(struct ahci_port *p, int slot, uint8_t *cfis, uint32_t done) 807 { 808 struct ahci_ioreq *aior; 809 struct blockif_req *breq; 810 uint8_t *entry; 811 uint64_t elba; 812 uint32_t len, elen; 813 int err, first, ncq; 814 uint8_t buf[512]; 815 816 first = (done == 0); 817 if (cfis[2] == ATA_DATA_SET_MANAGEMENT) { 818 len = (uint16_t)cfis[13] << 8 | cfis[12]; 819 len *= 512; 820 ncq = 0; 821 } else { /* ATA_SEND_FPDMA_QUEUED */ 822 len = (uint16_t)cfis[11] << 8 | cfis[3]; 823 len *= 512; 824 ncq = 1; 825 } 826 read_prdt(p, slot, cfis, buf, sizeof(buf)); 827 828 next: 829 entry = &buf[done]; 830 elba = ((uint64_t)entry[5] << 40) | 831 ((uint64_t)entry[4] << 32) | 832 ((uint64_t)entry[3] << 24) | 833 ((uint64_t)entry[2] << 16) | 834 ((uint64_t)entry[1] << 8) | 835 entry[0]; 836 elen = (uint16_t)entry[7] << 8 | entry[6]; 837 done += 8; 838 if (elen == 0) { 839 if (done >= len) { 840 if (ncq) { 841 if (first) 842 ahci_write_fis_d2h_ncq(p, slot); 843 ahci_write_fis_sdb(p, slot, cfis, 844 ATA_S_READY | ATA_S_DSC); 845 } else { 846 ahci_write_fis_d2h(p, slot, cfis, 847 ATA_S_READY | ATA_S_DSC); 848 } 849 p->pending &= ~(1 << slot); 850 ahci_check_stopped(p); 851 if (!first) 852 ahci_handle_port(p); 853 return; 854 } 855 goto next; 856 } 857 858 /* 859 * Pull request off free list 860 */ 861 aior = STAILQ_FIRST(&p->iofhd); 862 assert(aior != NULL); 863 STAILQ_REMOVE_HEAD(&p->iofhd, io_flist); 864 aior->cfis = cfis; 865 aior->slot = slot; 866 aior->len = len; 867 aior->done = done; 868 aior->more = (len != done); 869 870 breq = &aior->io_req; 871 breq->br_offset = elba * blockif_sectsz(p->bctx); 872 breq->br_resid = elen * blockif_sectsz(p->bctx); 873 874 /* 875 * Mark this command in-flight. 876 */ 877 p->pending |= 1 << slot; 878 879 /* 880 * Stuff request onto busy list 881 */ 882 TAILQ_INSERT_HEAD(&p->iobhd, aior, io_blist); 883 884 if (ncq && first) 885 ahci_write_fis_d2h_ncq(p, slot); 886 887 err = blockif_delete(p->bctx, breq); 888 assert(err == 0); 889 } 890 891 static inline void 892 write_prdt(struct ahci_port *p, int slot, uint8_t *cfis, 893 void *buf, int size) 894 { 895 struct ahci_cmd_hdr *hdr; 896 struct ahci_prdt_entry *prdt; 897 void *from; 898 int i, len; 899 900 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE); 901 len = size; 902 from = buf; 903 prdt = (struct ahci_prdt_entry *)(cfis + 0x80); 904 for (i = 0; i < hdr->prdtl && len; i++) { 905 uint8_t *ptr; 906 uint32_t dbcsz; 907 int sublen; 908 909 dbcsz = (prdt->dbc & DBCMASK) + 1; 910 ptr = paddr_guest2host(ahci_ctx(p->pr_sc), prdt->dba, dbcsz); 911 sublen = MIN(len, dbcsz); 912 memcpy(ptr, from, sublen); 913 len -= sublen; 914 from += sublen; 915 prdt++; 916 } 917 hdr->prdbc = size - len; 918 } 919 920 static void 921 ahci_checksum(uint8_t *buf, int size) 922 { 923 int i; 924 uint8_t sum = 0; 925 926 for (i = 0; i < size - 1; i++) 927 sum += buf[i]; 928 buf[size - 1] = 0x100 - sum; 929 } 930 931 static void 932 ahci_handle_read_log(struct ahci_port *p, int slot, uint8_t *cfis) 933 { 934 struct ahci_cmd_hdr *hdr; 935 uint8_t buf[512]; 936 937 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE); 938 if (p->atapi || hdr->prdtl == 0 || cfis[4] != 0x10 || 939 cfis[5] != 0 || cfis[9] != 0 || cfis[12] != 1 || cfis[13] != 0) { 940 ahci_write_fis_d2h(p, slot, cfis, 941 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR); 942 return; 943 } 944 945 memset(buf, 0, sizeof(buf)); 946 memcpy(buf, p->err_cfis, sizeof(p->err_cfis)); 947 ahci_checksum(buf, sizeof(buf)); 948 949 if (cfis[2] == ATA_READ_LOG_EXT) 950 ahci_write_fis_piosetup(p); 951 write_prdt(p, slot, cfis, (void *)buf, sizeof(buf)); 952 ahci_write_fis_d2h(p, slot, cfis, ATA_S_DSC | ATA_S_READY); 953 } 954 955 static void 956 handle_identify(struct ahci_port *p, int slot, uint8_t *cfis) 957 { 958 struct ahci_cmd_hdr *hdr; 959 960 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE); 961 if (p->atapi || hdr->prdtl == 0) { 962 ahci_write_fis_d2h(p, slot, cfis, 963 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR); 964 } else { 965 uint16_t buf[256]; 966 uint64_t sectors; 967 int sectsz, psectsz, psectoff, candelete, ro; 968 uint16_t cyl; 969 uint8_t sech, heads; 970 971 ro = blockif_is_ro(p->bctx); 972 candelete = blockif_candelete(p->bctx); 973 sectsz = blockif_sectsz(p->bctx); 974 sectors = blockif_size(p->bctx) / sectsz; 975 blockif_chs(p->bctx, &cyl, &heads, &sech); 976 blockif_psectsz(p->bctx, &psectsz, &psectoff); 977 memset(buf, 0, sizeof(buf)); 978 buf[0] = 0x0040; 979 buf[1] = cyl; 980 buf[3] = heads; 981 buf[6] = sech; 982 ata_string((uint8_t *)(buf+10), p->ident, 20); 983 ata_string((uint8_t *)(buf+23), "001", 8); 984 ata_string((uint8_t *)(buf+27), "BHYVE SATA DISK", 40); 985 buf[47] = (0x8000 | 128); 986 buf[48] = 0; 987 buf[49] = (1 << 8 | 1 << 9 | 1 << 11); 988 buf[50] = (1 << 14); 989 buf[53] = (1 << 1 | 1 << 2); 990 if (p->mult_sectors) 991 buf[59] = (0x100 | p->mult_sectors); 992 if (sectors <= 0x0fffffff) { 993 buf[60] = sectors; 994 buf[61] = (sectors >> 16); 995 } else { 996 buf[60] = 0xffff; 997 buf[61] = 0x0fff; 998 } 999 buf[63] = 0x7; 1000 if (p->xfermode & ATA_WDMA0) 1001 buf[63] |= (1 << ((p->xfermode & 7) + 8)); 1002 buf[64] = 0x3; 1003 buf[65] = 120; 1004 buf[66] = 120; 1005 buf[67] = 120; 1006 buf[68] = 120; 1007 buf[69] = 0; 1008 buf[75] = 31; 1009 buf[76] = (ATA_SATA_GEN1 | ATA_SATA_GEN2 | ATA_SATA_GEN3 | 1010 ATA_SUPPORT_NCQ); 1011 buf[77] = (ATA_SUPPORT_RCVSND_FPDMA_QUEUED | 1012 (p->ssts & ATA_SS_SPD_MASK) >> 3); 1013 buf[80] = 0x3f0; 1014 buf[81] = 0x28; 1015 buf[82] = (ATA_SUPPORT_POWERMGT | ATA_SUPPORT_WRITECACHE| 1016 ATA_SUPPORT_LOOKAHEAD | ATA_SUPPORT_NOP); 1017 buf[83] = (ATA_SUPPORT_ADDRESS48 | ATA_SUPPORT_FLUSHCACHE | 1018 ATA_SUPPORT_FLUSHCACHE48 | 1 << 14); 1019 buf[84] = (1 << 14); 1020 buf[85] = (ATA_SUPPORT_POWERMGT | ATA_SUPPORT_WRITECACHE| 1021 ATA_SUPPORT_LOOKAHEAD | ATA_SUPPORT_NOP); 1022 buf[86] = (ATA_SUPPORT_ADDRESS48 | ATA_SUPPORT_FLUSHCACHE | 1023 ATA_SUPPORT_FLUSHCACHE48 | 1 << 15); 1024 buf[87] = (1 << 14); 1025 buf[88] = 0x7f; 1026 if (p->xfermode & ATA_UDMA0) 1027 buf[88] |= (1 << ((p->xfermode & 7) + 8)); 1028 buf[100] = sectors; 1029 buf[101] = (sectors >> 16); 1030 buf[102] = (sectors >> 32); 1031 buf[103] = (sectors >> 48); 1032 if (candelete && !ro) { 1033 buf[69] |= ATA_SUPPORT_RZAT | ATA_SUPPORT_DRAT; 1034 buf[105] = 1; 1035 buf[169] = ATA_SUPPORT_DSM_TRIM; 1036 } 1037 buf[106] = 0x4000; 1038 buf[209] = 0x4000; 1039 if (psectsz > sectsz) { 1040 buf[106] |= 0x2000; 1041 buf[106] |= ffsl(psectsz / sectsz) - 1; 1042 buf[209] |= (psectoff / sectsz); 1043 } 1044 if (sectsz > 512) { 1045 buf[106] |= 0x1000; 1046 buf[117] = sectsz / 2; 1047 buf[118] = ((sectsz / 2) >> 16); 1048 } 1049 buf[119] = (ATA_SUPPORT_RWLOGDMAEXT | 1 << 14); 1050 buf[120] = (ATA_SUPPORT_RWLOGDMAEXT | 1 << 14); 1051 buf[222] = 0x1020; 1052 buf[255] = 0x00a5; 1053 ahci_checksum((uint8_t *)buf, sizeof(buf)); 1054 ahci_write_fis_piosetup(p); 1055 write_prdt(p, slot, cfis, (void *)buf, sizeof(buf)); 1056 ahci_write_fis_d2h(p, slot, cfis, ATA_S_DSC | ATA_S_READY); 1057 } 1058 } 1059 1060 static void 1061 handle_atapi_identify(struct ahci_port *p, int slot, uint8_t *cfis) 1062 { 1063 if (!p->atapi) { 1064 ahci_write_fis_d2h(p, slot, cfis, 1065 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR); 1066 } else { 1067 uint16_t buf[256]; 1068 1069 memset(buf, 0, sizeof(buf)); 1070 buf[0] = (2 << 14 | 5 << 8 | 1 << 7 | 2 << 5); 1071 ata_string((uint8_t *)(buf+10), p->ident, 20); 1072 ata_string((uint8_t *)(buf+23), "001", 8); 1073 ata_string((uint8_t *)(buf+27), "BHYVE SATA DVD ROM", 40); 1074 buf[49] = (1 << 9 | 1 << 8); 1075 buf[50] = (1 << 14 | 1); 1076 buf[53] = (1 << 2 | 1 << 1); 1077 buf[62] = 0x3f; 1078 buf[63] = 7; 1079 if (p->xfermode & ATA_WDMA0) 1080 buf[63] |= (1 << ((p->xfermode & 7) + 8)); 1081 buf[64] = 3; 1082 buf[65] = 120; 1083 buf[66] = 120; 1084 buf[67] = 120; 1085 buf[68] = 120; 1086 buf[76] = (ATA_SATA_GEN1 | ATA_SATA_GEN2 | ATA_SATA_GEN3); 1087 buf[77] = ((p->ssts & ATA_SS_SPD_MASK) >> 3); 1088 buf[78] = (1 << 5); 1089 buf[80] = 0x3f0; 1090 buf[82] = (ATA_SUPPORT_POWERMGT | ATA_SUPPORT_PACKET | 1091 ATA_SUPPORT_RESET | ATA_SUPPORT_NOP); 1092 buf[83] = (1 << 14); 1093 buf[84] = (1 << 14); 1094 buf[85] = (ATA_SUPPORT_POWERMGT | ATA_SUPPORT_PACKET | 1095 ATA_SUPPORT_RESET | ATA_SUPPORT_NOP); 1096 buf[87] = (1 << 14); 1097 buf[88] = 0x7f; 1098 if (p->xfermode & ATA_UDMA0) 1099 buf[88] |= (1 << ((p->xfermode & 7) + 8)); 1100 buf[222] = 0x1020; 1101 buf[255] = 0x00a5; 1102 ahci_checksum((uint8_t *)buf, sizeof(buf)); 1103 ahci_write_fis_piosetup(p); 1104 write_prdt(p, slot, cfis, (void *)buf, sizeof(buf)); 1105 ahci_write_fis_d2h(p, slot, cfis, ATA_S_DSC | ATA_S_READY); 1106 } 1107 } 1108 1109 static void 1110 atapi_inquiry(struct ahci_port *p, int slot, uint8_t *cfis) 1111 { 1112 uint8_t buf[36]; 1113 uint8_t *acmd; 1114 int len; 1115 uint32_t tfd; 1116 1117 acmd = cfis + 0x40; 1118 1119 if (acmd[1] & 1) { /* VPD */ 1120 if (acmd[2] == 0) { /* Supported VPD pages */ 1121 buf[0] = 0x05; 1122 buf[1] = 0; 1123 buf[2] = 0; 1124 buf[3] = 1; 1125 buf[4] = 0; 1126 len = 4 + buf[3]; 1127 } else { 1128 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST; 1129 p->asc = 0x24; 1130 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR; 1131 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1132 ahci_write_fis_d2h(p, slot, cfis, tfd); 1133 return; 1134 } 1135 } else { 1136 buf[0] = 0x05; 1137 buf[1] = 0x80; 1138 buf[2] = 0x00; 1139 buf[3] = 0x21; 1140 buf[4] = 31; 1141 buf[5] = 0; 1142 buf[6] = 0; 1143 buf[7] = 0; 1144 atapi_string(buf + 8, "BHYVE", 8); 1145 atapi_string(buf + 16, "BHYVE DVD-ROM", 16); 1146 atapi_string(buf + 32, "001", 4); 1147 len = sizeof(buf); 1148 } 1149 1150 if (len > acmd[4]) 1151 len = acmd[4]; 1152 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1153 write_prdt(p, slot, cfis, buf, len); 1154 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC); 1155 } 1156 1157 static void 1158 atapi_read_capacity(struct ahci_port *p, int slot, uint8_t *cfis) 1159 { 1160 uint8_t buf[8]; 1161 uint64_t sectors; 1162 1163 sectors = blockif_size(p->bctx) / 2048; 1164 be32enc(buf, sectors - 1); 1165 be32enc(buf + 4, 2048); 1166 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1167 write_prdt(p, slot, cfis, buf, sizeof(buf)); 1168 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC); 1169 } 1170 1171 static void 1172 atapi_read_toc(struct ahci_port *p, int slot, uint8_t *cfis) 1173 { 1174 uint8_t *acmd; 1175 uint8_t format; 1176 int len; 1177 1178 acmd = cfis + 0x40; 1179 1180 len = be16dec(acmd + 7); 1181 format = acmd[9] >> 6; 1182 switch (format) { 1183 case 0: 1184 { 1185 int msf, size; 1186 uint64_t sectors; 1187 uint8_t start_track, buf[20], *bp; 1188 1189 msf = (acmd[1] >> 1) & 1; 1190 start_track = acmd[6]; 1191 if (start_track > 1 && start_track != 0xaa) { 1192 uint32_t tfd; 1193 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST; 1194 p->asc = 0x24; 1195 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR; 1196 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1197 ahci_write_fis_d2h(p, slot, cfis, tfd); 1198 return; 1199 } 1200 bp = buf + 2; 1201 *bp++ = 1; 1202 *bp++ = 1; 1203 if (start_track <= 1) { 1204 *bp++ = 0; 1205 *bp++ = 0x14; 1206 *bp++ = 1; 1207 *bp++ = 0; 1208 if (msf) { 1209 *bp++ = 0; 1210 lba_to_msf(bp, 0); 1211 bp += 3; 1212 } else { 1213 *bp++ = 0; 1214 *bp++ = 0; 1215 *bp++ = 0; 1216 *bp++ = 0; 1217 } 1218 } 1219 *bp++ = 0; 1220 *bp++ = 0x14; 1221 *bp++ = 0xaa; 1222 *bp++ = 0; 1223 sectors = blockif_size(p->bctx) / blockif_sectsz(p->bctx); 1224 sectors >>= 2; 1225 if (msf) { 1226 *bp++ = 0; 1227 lba_to_msf(bp, sectors); 1228 bp += 3; 1229 } else { 1230 be32enc(bp, sectors); 1231 bp += 4; 1232 } 1233 size = bp - buf; 1234 be16enc(buf, size - 2); 1235 if (len > size) 1236 len = size; 1237 write_prdt(p, slot, cfis, buf, len); 1238 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1239 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC); 1240 break; 1241 } 1242 case 1: 1243 { 1244 uint8_t buf[12]; 1245 1246 memset(buf, 0, sizeof(buf)); 1247 buf[1] = 0xa; 1248 buf[2] = 0x1; 1249 buf[3] = 0x1; 1250 if (len > sizeof(buf)) 1251 len = sizeof(buf); 1252 write_prdt(p, slot, cfis, buf, len); 1253 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1254 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC); 1255 break; 1256 } 1257 case 2: 1258 { 1259 int msf, size; 1260 uint64_t sectors; 1261 uint8_t *bp, buf[50]; 1262 1263 msf = (acmd[1] >> 1) & 1; 1264 bp = buf + 2; 1265 *bp++ = 1; 1266 *bp++ = 1; 1267 1268 *bp++ = 1; 1269 *bp++ = 0x14; 1270 *bp++ = 0; 1271 *bp++ = 0xa0; 1272 *bp++ = 0; 1273 *bp++ = 0; 1274 *bp++ = 0; 1275 *bp++ = 0; 1276 *bp++ = 1; 1277 *bp++ = 0; 1278 *bp++ = 0; 1279 1280 *bp++ = 1; 1281 *bp++ = 0x14; 1282 *bp++ = 0; 1283 *bp++ = 0xa1; 1284 *bp++ = 0; 1285 *bp++ = 0; 1286 *bp++ = 0; 1287 *bp++ = 0; 1288 *bp++ = 1; 1289 *bp++ = 0; 1290 *bp++ = 0; 1291 1292 *bp++ = 1; 1293 *bp++ = 0x14; 1294 *bp++ = 0; 1295 *bp++ = 0xa2; 1296 *bp++ = 0; 1297 *bp++ = 0; 1298 *bp++ = 0; 1299 sectors = blockif_size(p->bctx) / blockif_sectsz(p->bctx); 1300 sectors >>= 2; 1301 if (msf) { 1302 *bp++ = 0; 1303 lba_to_msf(bp, sectors); 1304 bp += 3; 1305 } else { 1306 be32enc(bp, sectors); 1307 bp += 4; 1308 } 1309 1310 *bp++ = 1; 1311 *bp++ = 0x14; 1312 *bp++ = 0; 1313 *bp++ = 1; 1314 *bp++ = 0; 1315 *bp++ = 0; 1316 *bp++ = 0; 1317 if (msf) { 1318 *bp++ = 0; 1319 lba_to_msf(bp, 0); 1320 bp += 3; 1321 } else { 1322 *bp++ = 0; 1323 *bp++ = 0; 1324 *bp++ = 0; 1325 *bp++ = 0; 1326 } 1327 1328 size = bp - buf; 1329 be16enc(buf, size - 2); 1330 if (len > size) 1331 len = size; 1332 write_prdt(p, slot, cfis, buf, len); 1333 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1334 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC); 1335 break; 1336 } 1337 default: 1338 { 1339 uint32_t tfd; 1340 1341 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST; 1342 p->asc = 0x24; 1343 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR; 1344 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1345 ahci_write_fis_d2h(p, slot, cfis, tfd); 1346 break; 1347 } 1348 } 1349 } 1350 1351 static void 1352 atapi_report_luns(struct ahci_port *p, int slot, uint8_t *cfis) 1353 { 1354 uint8_t buf[16]; 1355 1356 memset(buf, 0, sizeof(buf)); 1357 buf[3] = 8; 1358 1359 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1360 write_prdt(p, slot, cfis, buf, sizeof(buf)); 1361 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC); 1362 } 1363 1364 static void 1365 atapi_read(struct ahci_port *p, int slot, uint8_t *cfis, uint32_t done) 1366 { 1367 struct ahci_ioreq *aior; 1368 struct ahci_cmd_hdr *hdr; 1369 struct ahci_prdt_entry *prdt; 1370 struct blockif_req *breq; 1371 uint8_t *acmd; 1372 uint64_t lba; 1373 uint32_t len; 1374 int err; 1375 1376 acmd = cfis + 0x40; 1377 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE); 1378 prdt = (struct ahci_prdt_entry *)(cfis + 0x80); 1379 1380 lba = be32dec(acmd + 2); 1381 if (acmd[0] == READ_10) 1382 len = be16dec(acmd + 7); 1383 else 1384 len = be32dec(acmd + 6); 1385 if (len == 0) { 1386 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1387 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC); 1388 } 1389 lba *= 2048; 1390 len *= 2048; 1391 1392 /* 1393 * Pull request off free list 1394 */ 1395 aior = STAILQ_FIRST(&p->iofhd); 1396 assert(aior != NULL); 1397 STAILQ_REMOVE_HEAD(&p->iofhd, io_flist); 1398 aior->cfis = cfis; 1399 aior->slot = slot; 1400 aior->len = len; 1401 aior->done = done; 1402 breq = &aior->io_req; 1403 breq->br_offset = lba + done; 1404 ahci_build_iov(p, aior, prdt, hdr->prdtl); 1405 1406 /* Mark this command in-flight. */ 1407 p->pending |= 1 << slot; 1408 1409 /* Stuff request onto busy list. */ 1410 TAILQ_INSERT_HEAD(&p->iobhd, aior, io_blist); 1411 1412 err = blockif_read(p->bctx, breq); 1413 assert(err == 0); 1414 } 1415 1416 static void 1417 atapi_request_sense(struct ahci_port *p, int slot, uint8_t *cfis) 1418 { 1419 uint8_t buf[64]; 1420 uint8_t *acmd; 1421 int len; 1422 1423 acmd = cfis + 0x40; 1424 len = acmd[4]; 1425 if (len > sizeof(buf)) 1426 len = sizeof(buf); 1427 memset(buf, 0, len); 1428 buf[0] = 0x70 | (1 << 7); 1429 buf[2] = p->sense_key; 1430 buf[7] = 10; 1431 buf[12] = p->asc; 1432 write_prdt(p, slot, cfis, buf, len); 1433 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1434 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC); 1435 } 1436 1437 static void 1438 atapi_start_stop_unit(struct ahci_port *p, int slot, uint8_t *cfis) 1439 { 1440 uint8_t *acmd = cfis + 0x40; 1441 uint32_t tfd; 1442 1443 switch (acmd[4] & 3) { 1444 case 0: 1445 case 1: 1446 case 3: 1447 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1448 tfd = ATA_S_READY | ATA_S_DSC; 1449 break; 1450 case 2: 1451 /* TODO eject media */ 1452 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1453 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST; 1454 p->asc = 0x53; 1455 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR; 1456 break; 1457 } 1458 ahci_write_fis_d2h(p, slot, cfis, tfd); 1459 } 1460 1461 static void 1462 atapi_mode_sense(struct ahci_port *p, int slot, uint8_t *cfis) 1463 { 1464 uint8_t *acmd; 1465 uint32_t tfd; 1466 uint8_t pc, code; 1467 int len; 1468 1469 acmd = cfis + 0x40; 1470 len = be16dec(acmd + 7); 1471 pc = acmd[2] >> 6; 1472 code = acmd[2] & 0x3f; 1473 1474 switch (pc) { 1475 case 0: 1476 switch (code) { 1477 case MODEPAGE_RW_ERROR_RECOVERY: 1478 { 1479 uint8_t buf[16]; 1480 1481 if (len > sizeof(buf)) 1482 len = sizeof(buf); 1483 1484 memset(buf, 0, sizeof(buf)); 1485 be16enc(buf, 16 - 2); 1486 buf[2] = 0x70; 1487 buf[8] = 0x01; 1488 buf[9] = 16 - 10; 1489 buf[11] = 0x05; 1490 write_prdt(p, slot, cfis, buf, len); 1491 tfd = ATA_S_READY | ATA_S_DSC; 1492 break; 1493 } 1494 case MODEPAGE_CD_CAPABILITIES: 1495 { 1496 uint8_t buf[30]; 1497 1498 if (len > sizeof(buf)) 1499 len = sizeof(buf); 1500 1501 memset(buf, 0, sizeof(buf)); 1502 be16enc(buf, 30 - 2); 1503 buf[2] = 0x70; 1504 buf[8] = 0x2A; 1505 buf[9] = 30 - 10; 1506 buf[10] = 0x08; 1507 buf[12] = 0x71; 1508 be16enc(&buf[18], 2); 1509 be16enc(&buf[20], 512); 1510 write_prdt(p, slot, cfis, buf, len); 1511 tfd = ATA_S_READY | ATA_S_DSC; 1512 break; 1513 } 1514 default: 1515 goto error; 1516 break; 1517 } 1518 break; 1519 case 3: 1520 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST; 1521 p->asc = 0x39; 1522 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR; 1523 break; 1524 error: 1525 case 1: 1526 case 2: 1527 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST; 1528 p->asc = 0x24; 1529 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR; 1530 break; 1531 } 1532 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1533 ahci_write_fis_d2h(p, slot, cfis, tfd); 1534 } 1535 1536 static void 1537 atapi_get_event_status_notification(struct ahci_port *p, int slot, 1538 uint8_t *cfis) 1539 { 1540 uint8_t *acmd; 1541 uint32_t tfd; 1542 1543 acmd = cfis + 0x40; 1544 1545 /* we don't support asynchronous operation */ 1546 if (!(acmd[1] & 1)) { 1547 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST; 1548 p->asc = 0x24; 1549 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR; 1550 } else { 1551 uint8_t buf[8]; 1552 int len; 1553 1554 len = be16dec(acmd + 7); 1555 if (len > sizeof(buf)) 1556 len = sizeof(buf); 1557 1558 memset(buf, 0, sizeof(buf)); 1559 be16enc(buf, 8 - 2); 1560 buf[2] = 0x04; 1561 buf[3] = 0x10; 1562 buf[5] = 0x02; 1563 write_prdt(p, slot, cfis, buf, len); 1564 tfd = ATA_S_READY | ATA_S_DSC; 1565 } 1566 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1567 ahci_write_fis_d2h(p, slot, cfis, tfd); 1568 } 1569 1570 static void 1571 handle_packet_cmd(struct ahci_port *p, int slot, uint8_t *cfis) 1572 { 1573 uint8_t *acmd; 1574 1575 acmd = cfis + 0x40; 1576 1577 #ifdef AHCI_DEBUG 1578 { 1579 int i; 1580 DPRINTF("ACMD:"); 1581 for (i = 0; i < 16; i++) 1582 DPRINTF("%02x ", acmd[i]); 1583 DPRINTF("\n"); 1584 } 1585 #endif 1586 1587 switch (acmd[0]) { 1588 case TEST_UNIT_READY: 1589 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1590 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC); 1591 break; 1592 case INQUIRY: 1593 atapi_inquiry(p, slot, cfis); 1594 break; 1595 case READ_CAPACITY: 1596 atapi_read_capacity(p, slot, cfis); 1597 break; 1598 case PREVENT_ALLOW: 1599 /* TODO */ 1600 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1601 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC); 1602 break; 1603 case READ_TOC: 1604 atapi_read_toc(p, slot, cfis); 1605 break; 1606 case REPORT_LUNS: 1607 atapi_report_luns(p, slot, cfis); 1608 break; 1609 case READ_10: 1610 case READ_12: 1611 atapi_read(p, slot, cfis, 0); 1612 break; 1613 case REQUEST_SENSE: 1614 atapi_request_sense(p, slot, cfis); 1615 break; 1616 case START_STOP_UNIT: 1617 atapi_start_stop_unit(p, slot, cfis); 1618 break; 1619 case MODE_SENSE_10: 1620 atapi_mode_sense(p, slot, cfis); 1621 break; 1622 case GET_EVENT_STATUS_NOTIFICATION: 1623 atapi_get_event_status_notification(p, slot, cfis); 1624 break; 1625 default: 1626 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1627 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST; 1628 p->asc = 0x20; 1629 ahci_write_fis_d2h(p, slot, cfis, (p->sense_key << 12) | 1630 ATA_S_READY | ATA_S_ERROR); 1631 break; 1632 } 1633 } 1634 1635 static void 1636 ahci_handle_cmd(struct ahci_port *p, int slot, uint8_t *cfis) 1637 { 1638 1639 p->tfd |= ATA_S_BUSY; 1640 switch (cfis[2]) { 1641 case ATA_ATA_IDENTIFY: 1642 handle_identify(p, slot, cfis); 1643 break; 1644 case ATA_SETFEATURES: 1645 { 1646 switch (cfis[3]) { 1647 case ATA_SF_ENAB_SATA_SF: 1648 switch (cfis[12]) { 1649 case ATA_SATA_SF_AN: 1650 p->tfd = ATA_S_DSC | ATA_S_READY; 1651 break; 1652 default: 1653 p->tfd = ATA_S_ERROR | ATA_S_READY; 1654 p->tfd |= (ATA_ERROR_ABORT << 8); 1655 break; 1656 } 1657 break; 1658 case ATA_SF_ENAB_WCACHE: 1659 case ATA_SF_DIS_WCACHE: 1660 case ATA_SF_ENAB_RCACHE: 1661 case ATA_SF_DIS_RCACHE: 1662 p->tfd = ATA_S_DSC | ATA_S_READY; 1663 break; 1664 case ATA_SF_SETXFER: 1665 { 1666 switch (cfis[12] & 0xf8) { 1667 case ATA_PIO: 1668 case ATA_PIO0: 1669 break; 1670 case ATA_WDMA0: 1671 case ATA_UDMA0: 1672 p->xfermode = (cfis[12] & 0x7); 1673 break; 1674 } 1675 p->tfd = ATA_S_DSC | ATA_S_READY; 1676 break; 1677 } 1678 default: 1679 p->tfd = ATA_S_ERROR | ATA_S_READY; 1680 p->tfd |= (ATA_ERROR_ABORT << 8); 1681 break; 1682 } 1683 ahci_write_fis_d2h(p, slot, cfis, p->tfd); 1684 break; 1685 } 1686 case ATA_SET_MULTI: 1687 if (cfis[12] != 0 && 1688 (cfis[12] > 128 || (cfis[12] & (cfis[12] - 1)))) { 1689 p->tfd = ATA_S_ERROR | ATA_S_READY; 1690 p->tfd |= (ATA_ERROR_ABORT << 8); 1691 } else { 1692 p->mult_sectors = cfis[12]; 1693 p->tfd = ATA_S_DSC | ATA_S_READY; 1694 } 1695 ahci_write_fis_d2h(p, slot, cfis, p->tfd); 1696 break; 1697 case ATA_READ: 1698 case ATA_WRITE: 1699 case ATA_READ48: 1700 case ATA_WRITE48: 1701 case ATA_READ_MUL: 1702 case ATA_WRITE_MUL: 1703 case ATA_READ_MUL48: 1704 case ATA_WRITE_MUL48: 1705 case ATA_READ_DMA: 1706 case ATA_WRITE_DMA: 1707 case ATA_READ_DMA48: 1708 case ATA_WRITE_DMA48: 1709 case ATA_READ_FPDMA_QUEUED: 1710 case ATA_WRITE_FPDMA_QUEUED: 1711 ahci_handle_rw(p, slot, cfis, 0); 1712 break; 1713 case ATA_FLUSHCACHE: 1714 case ATA_FLUSHCACHE48: 1715 ahci_handle_flush(p, slot, cfis); 1716 break; 1717 case ATA_DATA_SET_MANAGEMENT: 1718 if (cfis[11] == 0 && cfis[3] == ATA_DSM_TRIM && 1719 cfis[13] == 0 && cfis[12] == 1) { 1720 ahci_handle_dsm_trim(p, slot, cfis, 0); 1721 break; 1722 } 1723 ahci_write_fis_d2h(p, slot, cfis, 1724 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR); 1725 break; 1726 case ATA_SEND_FPDMA_QUEUED: 1727 if ((cfis[13] & 0x1f) == ATA_SFPDMA_DSM && 1728 cfis[17] == 0 && cfis[16] == ATA_DSM_TRIM && 1729 cfis[11] == 0 && cfis[3] == 1) { 1730 ahci_handle_dsm_trim(p, slot, cfis, 0); 1731 break; 1732 } 1733 ahci_write_fis_d2h(p, slot, cfis, 1734 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR); 1735 break; 1736 case ATA_READ_LOG_EXT: 1737 case ATA_READ_LOG_DMA_EXT: 1738 ahci_handle_read_log(p, slot, cfis); 1739 break; 1740 case ATA_SECURITY_FREEZE_LOCK: 1741 case ATA_SMART_CMD: 1742 case ATA_NOP: 1743 ahci_write_fis_d2h(p, slot, cfis, 1744 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR); 1745 break; 1746 case ATA_CHECK_POWER_MODE: 1747 cfis[12] = 0xff; /* always on */ 1748 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC); 1749 break; 1750 case ATA_STANDBY_CMD: 1751 case ATA_STANDBY_IMMEDIATE: 1752 case ATA_IDLE_CMD: 1753 case ATA_IDLE_IMMEDIATE: 1754 case ATA_SLEEP: 1755 case ATA_READ_VERIFY: 1756 case ATA_READ_VERIFY48: 1757 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC); 1758 break; 1759 case ATA_ATAPI_IDENTIFY: 1760 handle_atapi_identify(p, slot, cfis); 1761 break; 1762 case ATA_PACKET_CMD: 1763 if (!p->atapi) { 1764 ahci_write_fis_d2h(p, slot, cfis, 1765 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR); 1766 } else 1767 handle_packet_cmd(p, slot, cfis); 1768 break; 1769 default: 1770 WPRINTF("Unsupported cmd:%02x\n", cfis[2]); 1771 ahci_write_fis_d2h(p, slot, cfis, 1772 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR); 1773 break; 1774 } 1775 } 1776 1777 static void 1778 ahci_handle_slot(struct ahci_port *p, int slot) 1779 { 1780 struct ahci_cmd_hdr *hdr; 1781 #ifdef AHCI_DEBUG 1782 struct ahci_prdt_entry *prdt; 1783 #endif 1784 struct pci_ahci_softc *sc; 1785 uint8_t *cfis; 1786 #ifdef AHCI_DEBUG 1787 int cfl, i; 1788 #endif 1789 1790 sc = p->pr_sc; 1791 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE); 1792 #ifdef AHCI_DEBUG 1793 cfl = (hdr->flags & 0x1f) * 4; 1794 #endif 1795 cfis = paddr_guest2host(ahci_ctx(sc), hdr->ctba, 1796 0x80 + hdr->prdtl * sizeof(struct ahci_prdt_entry)); 1797 #ifdef AHCI_DEBUG 1798 prdt = (struct ahci_prdt_entry *)(cfis + 0x80); 1799 1800 DPRINTF("\ncfis:"); 1801 for (i = 0; i < cfl; i++) { 1802 if (i % 10 == 0) 1803 DPRINTF("\n"); 1804 DPRINTF("%02x ", cfis[i]); 1805 } 1806 DPRINTF("\n"); 1807 1808 for (i = 0; i < hdr->prdtl; i++) { 1809 DPRINTF("%d@%08"PRIx64"\n", prdt->dbc & 0x3fffff, prdt->dba); 1810 prdt++; 1811 } 1812 #endif 1813 1814 if (cfis[0] != FIS_TYPE_REGH2D) { 1815 WPRINTF("Not a H2D FIS:%02x\n", cfis[0]); 1816 return; 1817 } 1818 1819 if (cfis[1] & 0x80) { 1820 ahci_handle_cmd(p, slot, cfis); 1821 } else { 1822 if (cfis[15] & (1 << 2)) 1823 p->reset = 1; 1824 else if (p->reset) { 1825 p->reset = 0; 1826 ahci_port_reset(p); 1827 } 1828 p->ci &= ~(1 << slot); 1829 } 1830 } 1831 1832 static void 1833 ahci_handle_port(struct ahci_port *p) 1834 { 1835 1836 if (!(p->cmd & AHCI_P_CMD_ST)) 1837 return; 1838 1839 /* 1840 * Search for any new commands to issue ignoring those that 1841 * are already in-flight. Stop if device is busy or in error. 1842 */ 1843 for (; (p->ci & ~p->pending) != 0; p->ccs = ((p->ccs + 1) & 31)) { 1844 if ((p->tfd & (ATA_S_BUSY | ATA_S_DRQ)) != 0) 1845 break; 1846 if (p->waitforclear) 1847 break; 1848 if ((p->ci & ~p->pending & (1 << p->ccs)) != 0) { 1849 p->cmd &= ~AHCI_P_CMD_CCS_MASK; 1850 p->cmd |= p->ccs << AHCI_P_CMD_CCS_SHIFT; 1851 ahci_handle_slot(p, p->ccs); 1852 } 1853 } 1854 } 1855 1856 /* 1857 * blockif callback routine - this runs in the context of the blockif 1858 * i/o thread, so the mutex needs to be acquired. 1859 */ 1860 static void 1861 ata_ioreq_cb(struct blockif_req *br, int err) 1862 { 1863 struct ahci_cmd_hdr *hdr; 1864 struct ahci_ioreq *aior; 1865 struct ahci_port *p; 1866 struct pci_ahci_softc *sc; 1867 uint32_t tfd; 1868 uint8_t *cfis; 1869 int slot, ncq, dsm; 1870 1871 DPRINTF("%s %d\n", __func__, err); 1872 1873 ncq = dsm = 0; 1874 aior = br->br_param; 1875 p = aior->io_pr; 1876 cfis = aior->cfis; 1877 slot = aior->slot; 1878 sc = p->pr_sc; 1879 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE); 1880 1881 if (cfis[2] == ATA_WRITE_FPDMA_QUEUED || 1882 cfis[2] == ATA_READ_FPDMA_QUEUED || 1883 cfis[2] == ATA_SEND_FPDMA_QUEUED) 1884 ncq = 1; 1885 if (cfis[2] == ATA_DATA_SET_MANAGEMENT || 1886 (cfis[2] == ATA_SEND_FPDMA_QUEUED && 1887 (cfis[13] & 0x1f) == ATA_SFPDMA_DSM)) 1888 dsm = 1; 1889 1890 pthread_mutex_lock(&sc->mtx); 1891 1892 /* 1893 * Delete the blockif request from the busy list 1894 */ 1895 TAILQ_REMOVE(&p->iobhd, aior, io_blist); 1896 1897 /* 1898 * Move the blockif request back to the free list 1899 */ 1900 STAILQ_INSERT_TAIL(&p->iofhd, aior, io_flist); 1901 1902 if (!err) 1903 hdr->prdbc = aior->done; 1904 1905 if (!err && aior->more) { 1906 if (dsm) 1907 ahci_handle_dsm_trim(p, slot, cfis, aior->done); 1908 else 1909 ahci_handle_rw(p, slot, cfis, aior->done); 1910 goto out; 1911 } 1912 1913 if (!err) 1914 tfd = ATA_S_READY | ATA_S_DSC; 1915 else 1916 tfd = (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR; 1917 if (ncq) 1918 ahci_write_fis_sdb(p, slot, cfis, tfd); 1919 else 1920 ahci_write_fis_d2h(p, slot, cfis, tfd); 1921 1922 /* 1923 * This command is now complete. 1924 */ 1925 p->pending &= ~(1 << slot); 1926 1927 ahci_check_stopped(p); 1928 ahci_handle_port(p); 1929 out: 1930 pthread_mutex_unlock(&sc->mtx); 1931 DPRINTF("%s exit\n", __func__); 1932 } 1933 1934 static void 1935 atapi_ioreq_cb(struct blockif_req *br, int err) 1936 { 1937 struct ahci_cmd_hdr *hdr; 1938 struct ahci_ioreq *aior; 1939 struct ahci_port *p; 1940 struct pci_ahci_softc *sc; 1941 uint8_t *cfis; 1942 uint32_t tfd; 1943 int slot; 1944 1945 DPRINTF("%s %d\n", __func__, err); 1946 1947 aior = br->br_param; 1948 p = aior->io_pr; 1949 cfis = aior->cfis; 1950 slot = aior->slot; 1951 sc = p->pr_sc; 1952 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + aior->slot * AHCI_CL_SIZE); 1953 1954 pthread_mutex_lock(&sc->mtx); 1955 1956 /* 1957 * Delete the blockif request from the busy list 1958 */ 1959 TAILQ_REMOVE(&p->iobhd, aior, io_blist); 1960 1961 /* 1962 * Move the blockif request back to the free list 1963 */ 1964 STAILQ_INSERT_TAIL(&p->iofhd, aior, io_flist); 1965 1966 if (!err) 1967 hdr->prdbc = aior->done; 1968 1969 if (!err && aior->more) { 1970 atapi_read(p, slot, cfis, aior->done); 1971 goto out; 1972 } 1973 1974 if (!err) { 1975 tfd = ATA_S_READY | ATA_S_DSC; 1976 } else { 1977 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST; 1978 p->asc = 0x21; 1979 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR; 1980 } 1981 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1982 ahci_write_fis_d2h(p, slot, cfis, tfd); 1983 1984 /* 1985 * This command is now complete. 1986 */ 1987 p->pending &= ~(1 << slot); 1988 1989 ahci_check_stopped(p); 1990 ahci_handle_port(p); 1991 out: 1992 pthread_mutex_unlock(&sc->mtx); 1993 DPRINTF("%s exit\n", __func__); 1994 } 1995 1996 static void 1997 pci_ahci_ioreq_init(struct ahci_port *pr) 1998 { 1999 struct ahci_ioreq *vr; 2000 int i; 2001 2002 pr->ioqsz = blockif_queuesz(pr->bctx); 2003 pr->ioreq = calloc(pr->ioqsz, sizeof(struct ahci_ioreq)); 2004 STAILQ_INIT(&pr->iofhd); 2005 2006 /* 2007 * Add all i/o request entries to the free queue 2008 */ 2009 for (i = 0; i < pr->ioqsz; i++) { 2010 vr = &pr->ioreq[i]; 2011 vr->io_pr = pr; 2012 if (!pr->atapi) 2013 vr->io_req.br_callback = ata_ioreq_cb; 2014 else 2015 vr->io_req.br_callback = atapi_ioreq_cb; 2016 vr->io_req.br_param = vr; 2017 STAILQ_INSERT_TAIL(&pr->iofhd, vr, io_flist); 2018 } 2019 2020 TAILQ_INIT(&pr->iobhd); 2021 } 2022 2023 static void 2024 pci_ahci_port_write(struct pci_ahci_softc *sc, uint64_t offset, uint64_t value) 2025 { 2026 int port = (offset - AHCI_OFFSET) / AHCI_STEP; 2027 offset = (offset - AHCI_OFFSET) % AHCI_STEP; 2028 struct ahci_port *p = &sc->port[port]; 2029 2030 DPRINTF("pci_ahci_port %d: write offset 0x%"PRIx64" value 0x%"PRIx64"\n", 2031 port, offset, value); 2032 2033 switch (offset) { 2034 case AHCI_P_CLB: 2035 p->clb = value; 2036 break; 2037 case AHCI_P_CLBU: 2038 p->clbu = value; 2039 break; 2040 case AHCI_P_FB: 2041 p->fb = value; 2042 break; 2043 case AHCI_P_FBU: 2044 p->fbu = value; 2045 break; 2046 case AHCI_P_IS: 2047 p->is &= ~value; 2048 ahci_port_intr(p); 2049 break; 2050 case AHCI_P_IE: 2051 p->ie = value & 0xFDC000FF; 2052 ahci_port_intr(p); 2053 break; 2054 case AHCI_P_CMD: 2055 { 2056 p->cmd &= ~(AHCI_P_CMD_ST | AHCI_P_CMD_SUD | AHCI_P_CMD_POD | 2057 AHCI_P_CMD_CLO | AHCI_P_CMD_FRE | AHCI_P_CMD_APSTE | 2058 AHCI_P_CMD_ATAPI | AHCI_P_CMD_DLAE | AHCI_P_CMD_ALPE | 2059 AHCI_P_CMD_ASP | AHCI_P_CMD_ICC_MASK); 2060 p->cmd |= (AHCI_P_CMD_ST | AHCI_P_CMD_SUD | AHCI_P_CMD_POD | 2061 AHCI_P_CMD_CLO | AHCI_P_CMD_FRE | AHCI_P_CMD_APSTE | 2062 AHCI_P_CMD_ATAPI | AHCI_P_CMD_DLAE | AHCI_P_CMD_ALPE | 2063 AHCI_P_CMD_ASP | AHCI_P_CMD_ICC_MASK) & value; 2064 2065 if (!(value & AHCI_P_CMD_ST)) { 2066 ahci_port_stop(p); 2067 } else { 2068 uint64_t clb; 2069 2070 p->cmd |= AHCI_P_CMD_CR; 2071 clb = (uint64_t)p->clbu << 32 | p->clb; 2072 p->cmd_lst = paddr_guest2host(ahci_ctx(sc), clb, 2073 AHCI_CL_SIZE * AHCI_MAX_SLOTS); 2074 } 2075 2076 if (value & AHCI_P_CMD_FRE) { 2077 uint64_t fb; 2078 2079 p->cmd |= AHCI_P_CMD_FR; 2080 fb = (uint64_t)p->fbu << 32 | p->fb; 2081 /* we don't support FBSCP, so rfis size is 256Bytes */ 2082 p->rfis = paddr_guest2host(ahci_ctx(sc), fb, 256); 2083 } else { 2084 p->cmd &= ~AHCI_P_CMD_FR; 2085 } 2086 2087 if (value & AHCI_P_CMD_CLO) { 2088 p->tfd &= ~(ATA_S_BUSY | ATA_S_DRQ); 2089 p->cmd &= ~AHCI_P_CMD_CLO; 2090 } 2091 2092 if (value & AHCI_P_CMD_ICC_MASK) { 2093 p->cmd &= ~AHCI_P_CMD_ICC_MASK; 2094 } 2095 2096 ahci_handle_port(p); 2097 break; 2098 } 2099 case AHCI_P_TFD: 2100 case AHCI_P_SIG: 2101 case AHCI_P_SSTS: 2102 WPRINTF("pci_ahci_port: read only registers 0x%"PRIx64"\n", offset); 2103 break; 2104 case AHCI_P_SCTL: 2105 p->sctl = value; 2106 if (!(p->cmd & AHCI_P_CMD_ST)) { 2107 if (value & ATA_SC_DET_RESET) 2108 ahci_port_reset(p); 2109 } 2110 break; 2111 case AHCI_P_SERR: 2112 p->serr &= ~value; 2113 break; 2114 case AHCI_P_SACT: 2115 p->sact |= value; 2116 break; 2117 case AHCI_P_CI: 2118 p->ci |= value; 2119 ahci_handle_port(p); 2120 break; 2121 case AHCI_P_SNTF: 2122 case AHCI_P_FBS: 2123 default: 2124 break; 2125 } 2126 } 2127 2128 static void 2129 pci_ahci_host_write(struct pci_ahci_softc *sc, uint64_t offset, uint64_t value) 2130 { 2131 DPRINTF("pci_ahci_host: write offset 0x%"PRIx64" value 0x%"PRIx64"\n", 2132 offset, value); 2133 2134 switch (offset) { 2135 case AHCI_CAP: 2136 case AHCI_PI: 2137 case AHCI_VS: 2138 case AHCI_CAP2: 2139 DPRINTF("pci_ahci_host: read only registers 0x%"PRIx64"\n", offset); 2140 break; 2141 case AHCI_GHC: 2142 if (value & AHCI_GHC_HR) { 2143 ahci_reset(sc); 2144 break; 2145 } 2146 if (value & AHCI_GHC_IE) 2147 sc->ghc |= AHCI_GHC_IE; 2148 else 2149 sc->ghc &= ~AHCI_GHC_IE; 2150 ahci_generate_intr(sc, 0xffffffff); 2151 break; 2152 case AHCI_IS: 2153 sc->is &= ~value; 2154 ahci_generate_intr(sc, value); 2155 break; 2156 default: 2157 break; 2158 } 2159 } 2160 2161 static void 2162 pci_ahci_write(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, 2163 int baridx, uint64_t offset, int size, uint64_t value) 2164 { 2165 struct pci_ahci_softc *sc = pi->pi_arg; 2166 2167 assert(baridx == 5); 2168 assert((offset % 4) == 0 && size == 4); 2169 2170 pthread_mutex_lock(&sc->mtx); 2171 2172 if (offset < AHCI_OFFSET) 2173 pci_ahci_host_write(sc, offset, value); 2174 else if (offset < AHCI_OFFSET + sc->ports * AHCI_STEP) 2175 pci_ahci_port_write(sc, offset, value); 2176 else 2177 WPRINTF("pci_ahci: unknown i/o write offset 0x%"PRIx64"\n", offset); 2178 2179 pthread_mutex_unlock(&sc->mtx); 2180 } 2181 2182 static uint64_t 2183 pci_ahci_host_read(struct pci_ahci_softc *sc, uint64_t offset) 2184 { 2185 uint32_t value; 2186 2187 switch (offset) { 2188 case AHCI_CAP: 2189 case AHCI_GHC: 2190 case AHCI_IS: 2191 case AHCI_PI: 2192 case AHCI_VS: 2193 case AHCI_CCCC: 2194 case AHCI_CCCP: 2195 case AHCI_EM_LOC: 2196 case AHCI_EM_CTL: 2197 case AHCI_CAP2: 2198 { 2199 uint32_t *p = &sc->cap; 2200 p += (offset - AHCI_CAP) / sizeof(uint32_t); 2201 value = *p; 2202 break; 2203 } 2204 default: 2205 value = 0; 2206 break; 2207 } 2208 DPRINTF("pci_ahci_host: read offset 0x%"PRIx64" value 0x%x\n", 2209 offset, value); 2210 2211 return (value); 2212 } 2213 2214 static uint64_t 2215 pci_ahci_port_read(struct pci_ahci_softc *sc, uint64_t offset) 2216 { 2217 uint32_t value; 2218 int port = (offset - AHCI_OFFSET) / AHCI_STEP; 2219 offset = (offset - AHCI_OFFSET) % AHCI_STEP; 2220 2221 switch (offset) { 2222 case AHCI_P_CLB: 2223 case AHCI_P_CLBU: 2224 case AHCI_P_FB: 2225 case AHCI_P_FBU: 2226 case AHCI_P_IS: 2227 case AHCI_P_IE: 2228 case AHCI_P_CMD: 2229 case AHCI_P_TFD: 2230 case AHCI_P_SIG: 2231 case AHCI_P_SSTS: 2232 case AHCI_P_SCTL: 2233 case AHCI_P_SERR: 2234 case AHCI_P_SACT: 2235 case AHCI_P_CI: 2236 case AHCI_P_SNTF: 2237 case AHCI_P_FBS: 2238 { 2239 uint32_t *p= &sc->port[port].clb; 2240 p += (offset - AHCI_P_CLB) / sizeof(uint32_t); 2241 value = *p; 2242 break; 2243 } 2244 default: 2245 value = 0; 2246 break; 2247 } 2248 2249 DPRINTF("pci_ahci_port %d: read offset 0x%"PRIx64" value 0x%x\n", 2250 port, offset, value); 2251 2252 return value; 2253 } 2254 2255 static uint64_t 2256 pci_ahci_read(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, int baridx, 2257 uint64_t regoff, int size) 2258 { 2259 struct pci_ahci_softc *sc = pi->pi_arg; 2260 uint64_t offset; 2261 uint32_t value; 2262 2263 assert(baridx == 5); 2264 assert(size == 1 || size == 2 || size == 4); 2265 assert((regoff & (size - 1)) == 0); 2266 2267 pthread_mutex_lock(&sc->mtx); 2268 2269 offset = regoff & ~0x3; /* round down to a multiple of 4 bytes */ 2270 if (offset < AHCI_OFFSET) 2271 value = pci_ahci_host_read(sc, offset); 2272 else if (offset < AHCI_OFFSET + sc->ports * AHCI_STEP) 2273 value = pci_ahci_port_read(sc, offset); 2274 else { 2275 value = 0; 2276 WPRINTF("pci_ahci: unknown i/o read offset 0x%"PRIx64"\n", 2277 regoff); 2278 } 2279 value >>= 8 * (regoff & 0x3); 2280 2281 pthread_mutex_unlock(&sc->mtx); 2282 2283 return (value); 2284 } 2285 2286 static int 2287 pci_ahci_init(struct vmctx *ctx, struct pci_devinst *pi, char *opts, int atapi) 2288 { 2289 char bident[sizeof("XX:XX:XX")]; 2290 struct blockif_ctxt *bctxt; 2291 struct pci_ahci_softc *sc; 2292 int ret, slots, p; 2293 MD5_CTX mdctx; 2294 u_char digest[16]; 2295 char *next, *next2; 2296 2297 ret = 0; 2298 2299 #ifdef AHCI_DEBUG 2300 dbg = fopen("/tmp/log", "w+"); 2301 #endif 2302 2303 sc = calloc(1, sizeof(struct pci_ahci_softc)); 2304 pi->pi_arg = sc; 2305 sc->asc_pi = pi; 2306 pthread_mutex_init(&sc->mtx, NULL); 2307 sc->ports = 0; 2308 sc->pi = 0; 2309 slots = 32; 2310 2311 for (p = 0; p < MAX_PORTS && opts != NULL; p++, opts = next) { 2312 /* Identify and cut off type of present port. */ 2313 if (strncmp(opts, "hd:", 3) == 0) { 2314 atapi = 0; 2315 opts += 3; 2316 } else if (strncmp(opts, "cd:", 3) == 0) { 2317 atapi = 1; 2318 opts += 3; 2319 } 2320 2321 /* Find and cut off the next port options. */ 2322 next = strstr(opts, ",hd:"); 2323 next2 = strstr(opts, ",cd:"); 2324 if (next == NULL || (next2 != NULL && next2 < next)) 2325 next = next2; 2326 if (next != NULL) { 2327 next[0] = 0; 2328 next++; 2329 } 2330 2331 if (opts[0] == 0) 2332 continue; 2333 2334 /* 2335 * Attempt to open the backing image. Use the PCI slot/func 2336 * and the port number for the identifier string. 2337 */ 2338 snprintf(bident, sizeof(bident), "%d:%d:%d", pi->pi_slot, 2339 pi->pi_func, p); 2340 bctxt = blockif_open(opts, bident); 2341 if (bctxt == NULL) { 2342 sc->ports = p; 2343 ret = 1; 2344 goto open_fail; 2345 } 2346 sc->port[p].bctx = bctxt; 2347 sc->port[p].pr_sc = sc; 2348 sc->port[p].port = p; 2349 sc->port[p].atapi = atapi; 2350 2351 /* 2352 * Create an identifier for the backing file. 2353 * Use parts of the md5 sum of the filename 2354 */ 2355 MD5Init(&mdctx); 2356 MD5Update(&mdctx, opts, strlen(opts)); 2357 MD5Final(digest, &mdctx); 2358 sprintf(sc->port[p].ident, "BHYVE-%02X%02X-%02X%02X-%02X%02X", 2359 digest[0], digest[1], digest[2], digest[3], digest[4], 2360 digest[5]); 2361 2362 /* 2363 * Allocate blockif request structures and add them 2364 * to the free list 2365 */ 2366 pci_ahci_ioreq_init(&sc->port[p]); 2367 2368 sc->pi |= (1 << p); 2369 if (sc->port[p].ioqsz < slots) 2370 slots = sc->port[p].ioqsz; 2371 } 2372 sc->ports = p; 2373 2374 /* Intel ICH8 AHCI */ 2375 --slots; 2376 if (sc->ports < DEF_PORTS) 2377 sc->ports = DEF_PORTS; 2378 sc->cap = AHCI_CAP_64BIT | AHCI_CAP_SNCQ | AHCI_CAP_SSNTF | 2379 AHCI_CAP_SMPS | AHCI_CAP_SSS | AHCI_CAP_SALP | 2380 AHCI_CAP_SAL | AHCI_CAP_SCLO | (0x3 << AHCI_CAP_ISS_SHIFT)| 2381 AHCI_CAP_PMD | AHCI_CAP_SSC | AHCI_CAP_PSC | 2382 (slots << AHCI_CAP_NCS_SHIFT) | AHCI_CAP_SXS | (sc->ports - 1); 2383 2384 sc->vs = 0x10300; 2385 sc->cap2 = AHCI_CAP2_APST; 2386 ahci_reset(sc); 2387 2388 pci_set_cfgdata16(pi, PCIR_DEVICE, 0x2821); 2389 pci_set_cfgdata16(pi, PCIR_VENDOR, 0x8086); 2390 pci_set_cfgdata8(pi, PCIR_CLASS, PCIC_STORAGE); 2391 pci_set_cfgdata8(pi, PCIR_SUBCLASS, PCIS_STORAGE_SATA); 2392 pci_set_cfgdata8(pi, PCIR_PROGIF, PCIP_STORAGE_SATA_AHCI_1_0); 2393 p = MIN(sc->ports, 16); 2394 p = flsl(p) - ((p & (p - 1)) ? 0 : 1); 2395 pci_emul_add_msicap(pi, 1 << p); 2396 pci_emul_alloc_bar(pi, 5, PCIBAR_MEM32, 2397 AHCI_OFFSET + sc->ports * AHCI_STEP); 2398 2399 pci_lintr_request(pi); 2400 2401 open_fail: 2402 if (ret) { 2403 for (p = 0; p < sc->ports; p++) { 2404 if (sc->port[p].bctx != NULL) 2405 blockif_close(sc->port[p].bctx); 2406 } 2407 free(sc); 2408 } 2409 2410 return (ret); 2411 } 2412 2413 static int 2414 pci_ahci_hd_init(struct vmctx *ctx, struct pci_devinst *pi, char *opts) 2415 { 2416 2417 return (pci_ahci_init(ctx, pi, opts, 0)); 2418 } 2419 2420 static int 2421 pci_ahci_atapi_init(struct vmctx *ctx, struct pci_devinst *pi, char *opts) 2422 { 2423 2424 return (pci_ahci_init(ctx, pi, opts, 1)); 2425 } 2426 2427 /* 2428 * Use separate emulation names to distinguish drive and atapi devices 2429 */ 2430 struct pci_devemu pci_de_ahci = { 2431 .pe_emu = "ahci", 2432 .pe_init = pci_ahci_hd_init, 2433 .pe_barwrite = pci_ahci_write, 2434 .pe_barread = pci_ahci_read 2435 }; 2436 PCI_EMUL_SET(pci_de_ahci); 2437 2438 struct pci_devemu pci_de_ahci_hd = { 2439 .pe_emu = "ahci-hd", 2440 .pe_init = pci_ahci_hd_init, 2441 .pe_barwrite = pci_ahci_write, 2442 .pe_barread = pci_ahci_read 2443 }; 2444 PCI_EMUL_SET(pci_de_ahci_hd); 2445 2446 struct pci_devemu pci_de_ahci_cd = { 2447 .pe_emu = "ahci-cd", 2448 .pe_init = pci_ahci_atapi_init, 2449 .pe_barwrite = pci_ahci_write, 2450 .pe_barread = pci_ahci_read 2451 }; 2452 PCI_EMUL_SET(pci_de_ahci_cd); 2453