1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2013 Neel Natu <neel@freebsd.org> 5 * Copyright (c) 2013 Tycho Nightingale <tycho.nightingale@pluribusnetworks.com> 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 #include <sys/types.h> 32 #include <machine/vmm.h> 33 #include <machine/vmm_snapshot.h> 34 35 #include <err.h> 36 #include <stdio.h> 37 #include <stdlib.h> 38 #include <string.h> 39 40 #include <vmmapi.h> 41 42 #include "acpi.h" 43 #include "debug.h" 44 #include "bootrom.h" 45 #include "config.h" 46 #include "inout.h" 47 #include "pci_emul.h" 48 #include "pci_irq.h" 49 #include "pci_lpc.h" 50 #include "pci_passthru.h" 51 #include "pctestdev.h" 52 #include "tpm_device.h" 53 #include "uart_emul.h" 54 55 #define IO_ICU1 0x20 56 #define IO_ICU2 0xA0 57 58 SET_DECLARE(lpc_dsdt_set, struct lpc_dsdt); 59 SET_DECLARE(lpc_sysres_set, struct lpc_sysres); 60 61 #define ELCR_PORT 0x4d0 62 SYSRES_IO(ELCR_PORT, 2); 63 64 #define IO_TIMER1_PORT 0x40 65 66 #define NMISC_PORT 0x61 67 SYSRES_IO(NMISC_PORT, 1); 68 69 static struct pci_devinst *lpc_bridge; 70 71 #define LPC_UART_NUM 4 72 static struct lpc_uart_softc { 73 struct uart_softc *uart_softc; 74 int iobase; 75 int irq; 76 int enabled; 77 } lpc_uart_softc[LPC_UART_NUM]; 78 79 static const char *lpc_uart_names[LPC_UART_NUM] = { 80 "com1", "com2", "com3", "com4" 81 }; 82 83 static const char *lpc_uart_acpi_names[LPC_UART_NUM] = { 84 "COM1", "COM2", "COM3", "COM4" 85 }; 86 87 /* 88 * LPC device configuration is in the following form: 89 * <lpc_device_name>[,<options>] 90 * For e.g. "com1,stdio" or "bootrom,/var/romfile" 91 */ 92 int 93 lpc_device_parse(const char *opts) 94 { 95 int unit, error; 96 char *str, *cpy, *lpcdev, *node_name; 97 const char *romfile, *varfile, *tpm_type, *tpm_path; 98 99 error = -1; 100 str = cpy = strdup(opts); 101 lpcdev = strsep(&str, ","); 102 if (lpcdev != NULL) { 103 if (strcasecmp(lpcdev, "bootrom") == 0) { 104 romfile = strsep(&str, ","); 105 if (romfile == NULL) { 106 errx(4, "invalid bootrom option \"%s\"", opts); 107 } 108 set_config_value("lpc.bootrom", romfile); 109 110 varfile = strsep(&str, ","); 111 if (varfile == NULL) { 112 error = 0; 113 goto done; 114 } 115 if (strchr(varfile, '=') == NULL) { 116 set_config_value("lpc.bootvars", varfile); 117 } else { 118 /* varfile doesn't exist, it's another config 119 * option */ 120 pci_parse_legacy_config(find_config_node("lpc"), 121 varfile); 122 } 123 124 pci_parse_legacy_config(find_config_node("lpc"), str); 125 error = 0; 126 goto done; 127 } 128 if (strcasecmp(lpcdev, "tpm") == 0) { 129 nvlist_t *nvl = create_config_node("tpm"); 130 131 tpm_type = strsep(&str, ","); 132 if (tpm_type == NULL) { 133 errx(4, "invalid tpm type \"%s\"", opts); 134 } 135 set_config_value_node(nvl, "type", tpm_type); 136 137 tpm_path = strsep(&str, ","); 138 if (tpm_path == NULL) { 139 errx(4, "invalid tpm path \"%s\"", opts); 140 } 141 set_config_value_node(nvl, "path", tpm_path); 142 143 pci_parse_legacy_config(find_config_node("tpm"), str); 144 145 set_config_value_node_if_unset(nvl, "version", "2.0"); 146 error = 0; 147 goto done; 148 } 149 for (unit = 0; unit < LPC_UART_NUM; unit++) { 150 if (strcasecmp(lpcdev, lpc_uart_names[unit]) == 0) { 151 asprintf(&node_name, "lpc.%s.path", 152 lpc_uart_names[unit]); 153 set_config_value(node_name, str); 154 free(node_name); 155 error = 0; 156 goto done; 157 } 158 } 159 if (strcasecmp(lpcdev, pctestdev_getname()) == 0) { 160 asprintf(&node_name, "lpc.%s", pctestdev_getname()); 161 set_config_bool(node_name, true); 162 free(node_name); 163 error = 0; 164 goto done; 165 } 166 } 167 168 done: 169 free(cpy); 170 171 return (error); 172 } 173 174 void 175 lpc_print_supported_devices(void) 176 { 177 size_t i; 178 179 printf("bootrom\n"); 180 for (i = 0; i < LPC_UART_NUM; i++) 181 printf("%s\n", lpc_uart_names[i]); 182 printf("tpm\n"); 183 printf("%s\n", pctestdev_getname()); 184 } 185 186 const char * 187 lpc_bootrom(void) 188 { 189 190 return (get_config_value("lpc.bootrom")); 191 } 192 193 const char * 194 lpc_fwcfg(void) 195 { 196 return (get_config_value("lpc.fwcfg")); 197 } 198 199 static void 200 lpc_uart_intr_assert(void *arg) 201 { 202 struct lpc_uart_softc *sc = arg; 203 204 assert(sc->irq >= 0); 205 206 vm_isa_pulse_irq(lpc_bridge->pi_vmctx, sc->irq, sc->irq); 207 } 208 209 static void 210 lpc_uart_intr_deassert(void *arg __unused) 211 { 212 /* 213 * The COM devices on the LPC bus generate edge triggered interrupts, 214 * so nothing more to do here. 215 */ 216 } 217 218 static int 219 lpc_uart_io_handler(struct vmctx *ctx __unused, int in, 220 int port, int bytes, uint32_t *eax, void *arg) 221 { 222 int offset; 223 struct lpc_uart_softc *sc = arg; 224 225 offset = port - sc->iobase; 226 227 switch (bytes) { 228 case 1: 229 if (in) 230 *eax = uart_read(sc->uart_softc, offset); 231 else 232 uart_write(sc->uart_softc, offset, *eax); 233 break; 234 case 2: 235 if (in) { 236 *eax = uart_read(sc->uart_softc, offset); 237 *eax |= uart_read(sc->uart_softc, offset + 1) << 8; 238 } else { 239 uart_write(sc->uart_softc, offset, *eax); 240 uart_write(sc->uart_softc, offset + 1, *eax >> 8); 241 } 242 break; 243 default: 244 return (-1); 245 } 246 247 return (0); 248 } 249 250 static int 251 lpc_init(struct vmctx *ctx) 252 { 253 struct lpc_uart_softc *sc; 254 struct inout_port iop; 255 const char *backend, *name; 256 char *node_name; 257 int unit, error; 258 const nvlist_t *nvl; 259 260 nvl = find_config_node("lpc"); 261 if (nvl != NULL && nvlist_exists(nvl, "bootrom")) { 262 error = bootrom_loadrom(ctx, nvl); 263 if (error) 264 return (error); 265 } 266 267 /* COM1 and COM2 */ 268 for (unit = 0; unit < LPC_UART_NUM; unit++) { 269 sc = &lpc_uart_softc[unit]; 270 name = lpc_uart_names[unit]; 271 272 if (uart_legacy_alloc(unit, &sc->iobase, &sc->irq) != 0) { 273 EPRINTLN("Unable to allocate resources for " 274 "LPC device %s", name); 275 return (-1); 276 } 277 pci_irq_reserve(sc->irq); 278 279 sc->uart_softc = uart_init(lpc_uart_intr_assert, 280 lpc_uart_intr_deassert, sc); 281 282 asprintf(&node_name, "lpc.%s.path", name); 283 backend = get_config_value(node_name); 284 free(node_name); 285 if (uart_set_backend(sc->uart_softc, backend) != 0) { 286 EPRINTLN("Unable to initialize backend '%s' " 287 "for LPC device %s", backend, name); 288 return (-1); 289 } 290 291 bzero(&iop, sizeof(struct inout_port)); 292 iop.name = name; 293 iop.port = sc->iobase; 294 iop.size = UART_IO_BAR_SIZE; 295 iop.flags = IOPORT_F_INOUT; 296 iop.handler = lpc_uart_io_handler; 297 iop.arg = sc; 298 299 error = register_inout(&iop); 300 assert(error == 0); 301 sc->enabled = 1; 302 } 303 304 /* pc-testdev */ 305 asprintf(&node_name, "lpc.%s", pctestdev_getname()); 306 if (get_config_bool_default(node_name, false)) { 307 error = pctestdev_init(ctx); 308 if (error) 309 return (error); 310 } 311 free(node_name); 312 313 return (0); 314 } 315 316 static void 317 pci_lpc_write_dsdt(struct pci_devinst *pi) 318 { 319 struct lpc_dsdt **ldpp, *ldp; 320 321 dsdt_line(""); 322 dsdt_line("Device (ISA)"); 323 dsdt_line("{"); 324 dsdt_line(" Name (_ADR, 0x%04X%04X)", pi->pi_slot, pi->pi_func); 325 dsdt_line(" OperationRegion (LPCR, PCI_Config, 0x00, 0x100)"); 326 dsdt_line(" Field (LPCR, AnyAcc, NoLock, Preserve)"); 327 dsdt_line(" {"); 328 dsdt_line(" Offset (0x60),"); 329 dsdt_line(" PIRA, 8,"); 330 dsdt_line(" PIRB, 8,"); 331 dsdt_line(" PIRC, 8,"); 332 dsdt_line(" PIRD, 8,"); 333 dsdt_line(" Offset (0x68),"); 334 dsdt_line(" PIRE, 8,"); 335 dsdt_line(" PIRF, 8,"); 336 dsdt_line(" PIRG, 8,"); 337 dsdt_line(" PIRH, 8"); 338 dsdt_line(" }"); 339 dsdt_line(""); 340 341 dsdt_indent(1); 342 SET_FOREACH(ldpp, lpc_dsdt_set) { 343 ldp = *ldpp; 344 ldp->handler(); 345 } 346 347 dsdt_line(""); 348 dsdt_line("Device (PIC)"); 349 dsdt_line("{"); 350 dsdt_line(" Name (_HID, EisaId (\"PNP0000\"))"); 351 dsdt_line(" Name (_CRS, ResourceTemplate ()"); 352 dsdt_line(" {"); 353 dsdt_indent(2); 354 dsdt_fixed_ioport(IO_ICU1, 2); 355 dsdt_fixed_ioport(IO_ICU2, 2); 356 dsdt_fixed_irq(2); 357 dsdt_unindent(2); 358 dsdt_line(" })"); 359 dsdt_line("}"); 360 361 dsdt_line(""); 362 dsdt_line("Device (TIMR)"); 363 dsdt_line("{"); 364 dsdt_line(" Name (_HID, EisaId (\"PNP0100\"))"); 365 dsdt_line(" Name (_CRS, ResourceTemplate ()"); 366 dsdt_line(" {"); 367 dsdt_indent(2); 368 dsdt_fixed_ioport(IO_TIMER1_PORT, 4); 369 dsdt_fixed_irq(0); 370 dsdt_unindent(2); 371 dsdt_line(" })"); 372 dsdt_line("}"); 373 dsdt_unindent(1); 374 375 dsdt_line("}"); 376 } 377 378 static void 379 pci_lpc_sysres_dsdt(void) 380 { 381 struct lpc_sysres **lspp, *lsp; 382 383 dsdt_line(""); 384 dsdt_line("Device (SIO)"); 385 dsdt_line("{"); 386 dsdt_line(" Name (_HID, EisaId (\"PNP0C02\"))"); 387 dsdt_line(" Name (_CRS, ResourceTemplate ()"); 388 dsdt_line(" {"); 389 390 dsdt_indent(2); 391 SET_FOREACH(lspp, lpc_sysres_set) { 392 lsp = *lspp; 393 switch (lsp->type) { 394 case LPC_SYSRES_IO: 395 dsdt_fixed_ioport(lsp->base, lsp->length); 396 break; 397 case LPC_SYSRES_MEM: 398 dsdt_fixed_mem32(lsp->base, lsp->length); 399 break; 400 } 401 } 402 dsdt_unindent(2); 403 404 dsdt_line(" })"); 405 dsdt_line("}"); 406 } 407 LPC_DSDT(pci_lpc_sysres_dsdt); 408 409 static void 410 pci_lpc_uart_dsdt(void) 411 { 412 struct lpc_uart_softc *sc; 413 int unit; 414 415 for (unit = 0; unit < LPC_UART_NUM; unit++) { 416 sc = &lpc_uart_softc[unit]; 417 if (!sc->enabled) 418 continue; 419 dsdt_line(""); 420 dsdt_line("Device (%s)", lpc_uart_acpi_names[unit]); 421 dsdt_line("{"); 422 dsdt_line(" Name (_HID, EisaId (\"PNP0501\"))"); 423 dsdt_line(" Name (_UID, %d)", unit + 1); 424 dsdt_line(" Name (_CRS, ResourceTemplate ()"); 425 dsdt_line(" {"); 426 dsdt_indent(2); 427 dsdt_fixed_ioport(sc->iobase, UART_IO_BAR_SIZE); 428 dsdt_fixed_irq(sc->irq); 429 dsdt_unindent(2); 430 dsdt_line(" })"); 431 dsdt_line("}"); 432 } 433 } 434 LPC_DSDT(pci_lpc_uart_dsdt); 435 436 static int 437 pci_lpc_cfgwrite(struct pci_devinst *pi, int coff, int bytes, uint32_t val) 438 { 439 int pirq_pin; 440 441 if (bytes == 1) { 442 pirq_pin = 0; 443 if (coff >= 0x60 && coff <= 0x63) 444 pirq_pin = coff - 0x60 + 1; 445 if (coff >= 0x68 && coff <= 0x6b) 446 pirq_pin = coff - 0x68 + 5; 447 if (pirq_pin != 0) { 448 pirq_write(pi->pi_vmctx, pirq_pin, val); 449 pci_set_cfgdata8(pi, coff, pirq_read(pirq_pin)); 450 return (0); 451 } 452 } 453 return (-1); 454 } 455 456 static void 457 pci_lpc_write(struct pci_devinst *pi __unused, int baridx __unused, 458 uint64_t offset __unused, int size __unused, uint64_t value __unused) 459 { 460 } 461 462 static uint64_t 463 pci_lpc_read(struct pci_devinst *pi __unused, int baridx __unused, 464 uint64_t offset __unused, int size __unused) 465 { 466 return (0); 467 } 468 469 #define LPC_DEV 0x7000 470 #define LPC_VENDOR 0x8086 471 #define LPC_REVID 0x00 472 #define LPC_SUBVEND_0 0x0000 473 #define LPC_SUBDEV_0 0x0000 474 475 static int 476 pci_lpc_get_sel(struct pcisel *const sel) 477 { 478 assert(sel != NULL); 479 480 memset(sel, 0, sizeof(*sel)); 481 482 for (uint8_t slot = 0; slot <= PCI_SLOTMAX; ++slot) { 483 uint8_t max_func = 0; 484 485 sel->pc_dev = slot; 486 sel->pc_func = 0; 487 488 if (pci_host_read_config(sel, PCIR_HDRTYPE, 1) & PCIM_MFDEV) 489 max_func = PCI_FUNCMAX; 490 491 for (uint8_t func = 0; func <= max_func; ++func) { 492 sel->pc_func = func; 493 494 if (pci_host_read_config(sel, PCIR_CLASS, 1) == 495 PCIC_BRIDGE && 496 pci_host_read_config(sel, PCIR_SUBCLASS, 1) == 497 PCIS_BRIDGE_ISA) { 498 return (0); 499 } 500 } 501 } 502 503 warnx("%s: Unable to find host selector of LPC bridge.", __func__); 504 505 return (-1); 506 } 507 508 static int 509 pci_lpc_init(struct pci_devinst *pi, nvlist_t *nvl) 510 { 511 struct pcisel sel = { 0 }; 512 struct pcisel *selp = NULL; 513 uint16_t device, subdevice, subvendor, vendor; 514 uint8_t revid; 515 516 /* 517 * Do not allow more than one LPC bridge to be configured. 518 */ 519 if (lpc_bridge != NULL) { 520 EPRINTLN("Only one LPC bridge is allowed."); 521 return (-1); 522 } 523 524 /* 525 * Enforce that the LPC can only be configured on bus 0. This 526 * simplifies the ACPI DSDT because it can provide a decode for 527 * all legacy i/o ports behind bus 0. 528 */ 529 if (pi->pi_bus != 0) { 530 EPRINTLN("LPC bridge can be present only on bus 0."); 531 return (-1); 532 } 533 534 if (lpc_init(pi->pi_vmctx) != 0) 535 return (-1); 536 537 if (pci_lpc_get_sel(&sel) == 0) 538 selp = &sel; 539 540 vendor = pci_config_read_reg(selp, nvl, PCIR_VENDOR, 2, LPC_VENDOR); 541 device = pci_config_read_reg(selp, nvl, PCIR_DEVICE, 2, LPC_DEV); 542 revid = pci_config_read_reg(selp, nvl, PCIR_REVID, 1, LPC_REVID); 543 subvendor = pci_config_read_reg(selp, nvl, PCIR_SUBVEND_0, 2, 544 LPC_SUBVEND_0); 545 subdevice = pci_config_read_reg(selp, nvl, PCIR_SUBDEV_0, 2, 546 LPC_SUBDEV_0); 547 548 /* initialize config space */ 549 pci_set_cfgdata16(pi, PCIR_VENDOR, vendor); 550 pci_set_cfgdata16(pi, PCIR_DEVICE, device); 551 pci_set_cfgdata8(pi, PCIR_CLASS, PCIC_BRIDGE); 552 pci_set_cfgdata8(pi, PCIR_SUBCLASS, PCIS_BRIDGE_ISA); 553 pci_set_cfgdata8(pi, PCIR_REVID, revid); 554 pci_set_cfgdata16(pi, PCIR_SUBVEND_0, subvendor); 555 pci_set_cfgdata16(pi, PCIR_SUBDEV_0, subdevice); 556 557 lpc_bridge = pi; 558 559 return (0); 560 } 561 562 char * 563 lpc_pirq_name(int pin) 564 { 565 char *name; 566 567 if (lpc_bridge == NULL) 568 return (NULL); 569 asprintf(&name, "\\_SB.PC00.ISA.LNK%c,", 'A' + pin - 1); 570 return (name); 571 } 572 573 void 574 lpc_pirq_routed(void) 575 { 576 int pin; 577 578 if (lpc_bridge == NULL) 579 return; 580 581 for (pin = 0; pin < 4; pin++) 582 pci_set_cfgdata8(lpc_bridge, 0x60 + pin, pirq_read(pin + 1)); 583 for (pin = 0; pin < 4; pin++) 584 pci_set_cfgdata8(lpc_bridge, 0x68 + pin, pirq_read(pin + 5)); 585 } 586 587 #ifdef BHYVE_SNAPSHOT 588 static int 589 pci_lpc_snapshot(struct vm_snapshot_meta *meta) 590 { 591 int unit, ret; 592 struct uart_softc *sc; 593 594 for (unit = 0; unit < LPC_UART_NUM; unit++) { 595 sc = lpc_uart_softc[unit].uart_softc; 596 597 ret = uart_snapshot(sc, meta); 598 if (ret != 0) 599 goto done; 600 } 601 602 done: 603 return (ret); 604 } 605 #endif 606 607 static const struct pci_devemu pci_de_lpc = { 608 .pe_emu = "lpc", 609 .pe_init = pci_lpc_init, 610 .pe_write_dsdt = pci_lpc_write_dsdt, 611 .pe_cfgwrite = pci_lpc_cfgwrite, 612 .pe_barwrite = pci_lpc_write, 613 .pe_barread = pci_lpc_read, 614 #ifdef BHYVE_SNAPSHOT 615 .pe_snapshot = pci_lpc_snapshot, 616 #endif 617 }; 618 PCI_EMUL_SET(pci_de_lpc); 619