1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2013 Neel Natu <neel@freebsd.org> 5 * Copyright (c) 2013 Tycho Nightingale <tycho.nightingale@pluribusnetworks.com> 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <sys/types.h> 31 #include <machine/vmm.h> 32 #include <machine/vmm_snapshot.h> 33 34 #include <err.h> 35 #include <stdio.h> 36 #include <stdlib.h> 37 #include <string.h> 38 39 #include <vmmapi.h> 40 41 #include "acpi.h" 42 #include "debug.h" 43 #include "bootrom.h" 44 #include "config.h" 45 #include "inout.h" 46 #include "pci_emul.h" 47 #include "pci_irq.h" 48 #include "pci_lpc.h" 49 #include "pci_passthru.h" 50 #include "pctestdev.h" 51 #include "tpm_device.h" 52 #include "uart_emul.h" 53 54 #define IO_ICU1 0x20 55 #define IO_ICU2 0xA0 56 57 SET_DECLARE(lpc_dsdt_set, struct lpc_dsdt); 58 SET_DECLARE(lpc_sysres_set, struct lpc_sysres); 59 60 #define ELCR_PORT 0x4d0 61 SYSRES_IO(ELCR_PORT, 2); 62 63 #define IO_TIMER1_PORT 0x40 64 65 #define NMISC_PORT 0x61 66 SYSRES_IO(NMISC_PORT, 1); 67 68 static struct pci_devinst *lpc_bridge; 69 70 #define LPC_UART_NUM 4 71 static struct lpc_uart_softc { 72 struct uart_ns16550_softc *uart_softc; 73 int iobase; 74 int irq; 75 int enabled; 76 } lpc_uart_softc[LPC_UART_NUM]; 77 78 static const char *lpc_uart_names[LPC_UART_NUM] = { 79 "com1", "com2", "com3", "com4" 80 }; 81 82 static const char *lpc_uart_acpi_names[LPC_UART_NUM] = { 83 "COM1", "COM2", "COM3", "COM4" 84 }; 85 86 /* 87 * LPC device configuration is in the following form: 88 * <lpc_device_name>[,<options>] 89 * For e.g. "com1,stdio" or "bootrom,/var/romfile" 90 */ 91 int 92 lpc_device_parse(const char *opts) 93 { 94 int unit, error; 95 char *str, *cpy, *lpcdev, *node_name; 96 const char *romfile, *varfile, *tpm_type, *tpm_path; 97 98 error = -1; 99 str = cpy = strdup(opts); 100 lpcdev = strsep(&str, ","); 101 if (lpcdev != NULL) { 102 if (strcasecmp(lpcdev, "bootrom") == 0) { 103 romfile = strsep(&str, ","); 104 if (romfile == NULL) { 105 errx(4, "invalid bootrom option \"%s\"", opts); 106 } 107 set_config_value("lpc.bootrom", romfile); 108 109 varfile = strsep(&str, ","); 110 if (varfile == NULL) { 111 error = 0; 112 goto done; 113 } 114 if (strchr(varfile, '=') == NULL) { 115 set_config_value("lpc.bootvars", varfile); 116 } else { 117 /* varfile doesn't exist, it's another config 118 * option */ 119 pci_parse_legacy_config(find_config_node("lpc"), 120 varfile); 121 } 122 123 pci_parse_legacy_config(find_config_node("lpc"), str); 124 error = 0; 125 goto done; 126 } 127 if (strcasecmp(lpcdev, "tpm") == 0) { 128 nvlist_t *nvl = create_config_node("tpm"); 129 130 tpm_type = strsep(&str, ","); 131 if (tpm_type == NULL) { 132 errx(4, "invalid tpm type \"%s\"", opts); 133 } 134 set_config_value_node(nvl, "type", tpm_type); 135 136 tpm_path = strsep(&str, ","); 137 if (tpm_path == NULL) { 138 errx(4, "invalid tpm path \"%s\"", opts); 139 } 140 set_config_value_node(nvl, "path", tpm_path); 141 142 pci_parse_legacy_config(find_config_node("tpm"), str); 143 144 set_config_value_node_if_unset(nvl, "version", "2.0"); 145 error = 0; 146 goto done; 147 } 148 for (unit = 0; unit < LPC_UART_NUM; unit++) { 149 if (strcasecmp(lpcdev, lpc_uart_names[unit]) == 0) { 150 asprintf(&node_name, "lpc.%s.path", 151 lpc_uart_names[unit]); 152 set_config_value(node_name, str); 153 free(node_name); 154 error = 0; 155 goto done; 156 } 157 } 158 if (strcasecmp(lpcdev, pctestdev_getname()) == 0) { 159 asprintf(&node_name, "lpc.%s", pctestdev_getname()); 160 set_config_bool(node_name, true); 161 free(node_name); 162 error = 0; 163 goto done; 164 } 165 } 166 167 done: 168 free(cpy); 169 170 return (error); 171 } 172 173 void 174 lpc_print_supported_devices(void) 175 { 176 size_t i; 177 178 printf("bootrom\n"); 179 for (i = 0; i < LPC_UART_NUM; i++) 180 printf("%s\n", lpc_uart_names[i]); 181 printf("tpm\n"); 182 printf("%s\n", pctestdev_getname()); 183 } 184 185 const char * 186 lpc_bootrom(void) 187 { 188 189 return (get_config_value("lpc.bootrom")); 190 } 191 192 const char * 193 lpc_fwcfg(void) 194 { 195 return (get_config_value("lpc.fwcfg")); 196 } 197 198 static void 199 lpc_uart_intr_assert(void *arg) 200 { 201 struct lpc_uart_softc *sc = arg; 202 203 assert(sc->irq >= 0); 204 205 vm_isa_pulse_irq(lpc_bridge->pi_vmctx, sc->irq, sc->irq); 206 } 207 208 static void 209 lpc_uart_intr_deassert(void *arg __unused) 210 { 211 /* 212 * The COM devices on the LPC bus generate edge triggered interrupts, 213 * so nothing more to do here. 214 */ 215 } 216 217 static int 218 lpc_uart_io_handler(struct vmctx *ctx __unused, int in, 219 int port, int bytes, uint32_t *eax, void *arg) 220 { 221 int offset; 222 struct lpc_uart_softc *sc = arg; 223 224 offset = port - sc->iobase; 225 226 switch (bytes) { 227 case 1: 228 if (in) 229 *eax = uart_ns16550_read(sc->uart_softc, offset); 230 else 231 uart_ns16550_write(sc->uart_softc, offset, *eax); 232 break; 233 case 2: 234 if (in) { 235 *eax = uart_ns16550_read(sc->uart_softc, offset); 236 *eax |= 237 uart_ns16550_read(sc->uart_softc, offset + 1) << 8; 238 } else { 239 uart_ns16550_write(sc->uart_softc, offset, *eax); 240 uart_ns16550_write(sc->uart_softc, offset + 1, 241 *eax >> 8); 242 } 243 break; 244 default: 245 return (-1); 246 } 247 248 return (0); 249 } 250 251 static int 252 lpc_init(struct vmctx *ctx) 253 { 254 struct lpc_uart_softc *sc; 255 struct inout_port iop; 256 const char *backend, *name; 257 char *node_name; 258 int unit, error; 259 const nvlist_t *nvl; 260 261 nvl = find_config_node("lpc"); 262 if (nvl != NULL && nvlist_exists(nvl, "bootrom")) { 263 error = bootrom_loadrom(ctx, nvl); 264 if (error) 265 return (error); 266 } 267 268 /* COM1 and COM2 */ 269 for (unit = 0; unit < LPC_UART_NUM; unit++) { 270 sc = &lpc_uart_softc[unit]; 271 name = lpc_uart_names[unit]; 272 273 if (uart_legacy_alloc(unit, &sc->iobase, &sc->irq) != 0) { 274 EPRINTLN("Unable to allocate resources for " 275 "LPC device %s", name); 276 return (-1); 277 } 278 pci_irq_reserve(sc->irq); 279 280 sc->uart_softc = uart_ns16550_init(lpc_uart_intr_assert, 281 lpc_uart_intr_deassert, sc); 282 283 asprintf(&node_name, "lpc.%s.path", name); 284 backend = get_config_value(node_name); 285 free(node_name); 286 if (backend != NULL && 287 uart_ns16550_tty_open(sc->uart_softc, backend) != 0) { 288 EPRINTLN("Unable to initialize backend '%s' " 289 "for LPC device %s", backend, name); 290 return (-1); 291 } 292 293 bzero(&iop, sizeof(struct inout_port)); 294 iop.name = name; 295 iop.port = sc->iobase; 296 iop.size = UART_NS16550_IO_BAR_SIZE; 297 iop.flags = IOPORT_F_INOUT; 298 iop.handler = lpc_uart_io_handler; 299 iop.arg = sc; 300 301 error = register_inout(&iop); 302 assert(error == 0); 303 sc->enabled = 1; 304 } 305 306 /* pc-testdev */ 307 asprintf(&node_name, "lpc.%s", pctestdev_getname()); 308 if (get_config_bool_default(node_name, false)) { 309 error = pctestdev_init(ctx); 310 if (error) 311 return (error); 312 } 313 free(node_name); 314 315 return (0); 316 } 317 318 static void 319 pci_lpc_write_dsdt(struct pci_devinst *pi) 320 { 321 struct lpc_dsdt **ldpp, *ldp; 322 323 dsdt_line(""); 324 dsdt_line("Device (ISA)"); 325 dsdt_line("{"); 326 dsdt_line(" Name (_ADR, 0x%04X%04X)", pi->pi_slot, pi->pi_func); 327 dsdt_line(" OperationRegion (LPCR, PCI_Config, 0x00, 0x100)"); 328 dsdt_line(" Field (LPCR, AnyAcc, NoLock, Preserve)"); 329 dsdt_line(" {"); 330 dsdt_line(" Offset (0x60),"); 331 dsdt_line(" PIRA, 8,"); 332 dsdt_line(" PIRB, 8,"); 333 dsdt_line(" PIRC, 8,"); 334 dsdt_line(" PIRD, 8,"); 335 dsdt_line(" Offset (0x68),"); 336 dsdt_line(" PIRE, 8,"); 337 dsdt_line(" PIRF, 8,"); 338 dsdt_line(" PIRG, 8,"); 339 dsdt_line(" PIRH, 8"); 340 dsdt_line(" }"); 341 dsdt_line(""); 342 343 dsdt_indent(1); 344 SET_FOREACH(ldpp, lpc_dsdt_set) { 345 ldp = *ldpp; 346 ldp->handler(); 347 } 348 349 dsdt_line(""); 350 dsdt_line("Device (PIC)"); 351 dsdt_line("{"); 352 dsdt_line(" Name (_HID, EisaId (\"PNP0000\"))"); 353 dsdt_line(" Name (_CRS, ResourceTemplate ()"); 354 dsdt_line(" {"); 355 dsdt_indent(2); 356 dsdt_fixed_ioport(IO_ICU1, 2); 357 dsdt_fixed_ioport(IO_ICU2, 2); 358 dsdt_fixed_irq(2); 359 dsdt_unindent(2); 360 dsdt_line(" })"); 361 dsdt_line("}"); 362 363 dsdt_line(""); 364 dsdt_line("Device (TIMR)"); 365 dsdt_line("{"); 366 dsdt_line(" Name (_HID, EisaId (\"PNP0100\"))"); 367 dsdt_line(" Name (_CRS, ResourceTemplate ()"); 368 dsdt_line(" {"); 369 dsdt_indent(2); 370 dsdt_fixed_ioport(IO_TIMER1_PORT, 4); 371 dsdt_fixed_irq(0); 372 dsdt_unindent(2); 373 dsdt_line(" })"); 374 dsdt_line("}"); 375 dsdt_unindent(1); 376 377 dsdt_line("}"); 378 } 379 380 static void 381 pci_lpc_sysres_dsdt(void) 382 { 383 struct lpc_sysres **lspp, *lsp; 384 385 dsdt_line(""); 386 dsdt_line("Device (SIO)"); 387 dsdt_line("{"); 388 dsdt_line(" Name (_HID, EisaId (\"PNP0C02\"))"); 389 dsdt_line(" Name (_CRS, ResourceTemplate ()"); 390 dsdt_line(" {"); 391 392 dsdt_indent(2); 393 SET_FOREACH(lspp, lpc_sysres_set) { 394 lsp = *lspp; 395 switch (lsp->type) { 396 case LPC_SYSRES_IO: 397 dsdt_fixed_ioport(lsp->base, lsp->length); 398 break; 399 case LPC_SYSRES_MEM: 400 dsdt_fixed_mem32(lsp->base, lsp->length); 401 break; 402 } 403 } 404 dsdt_unindent(2); 405 406 dsdt_line(" })"); 407 dsdt_line("}"); 408 } 409 LPC_DSDT(pci_lpc_sysres_dsdt); 410 411 static void 412 pci_lpc_uart_dsdt(void) 413 { 414 struct lpc_uart_softc *sc; 415 int unit; 416 417 for (unit = 0; unit < LPC_UART_NUM; unit++) { 418 sc = &lpc_uart_softc[unit]; 419 if (!sc->enabled) 420 continue; 421 dsdt_line(""); 422 dsdt_line("Device (%s)", lpc_uart_acpi_names[unit]); 423 dsdt_line("{"); 424 dsdt_line(" Name (_HID, EisaId (\"PNP0501\"))"); 425 dsdt_line(" Name (_UID, %d)", unit + 1); 426 dsdt_line(" Name (_CRS, ResourceTemplate ()"); 427 dsdt_line(" {"); 428 dsdt_indent(2); 429 dsdt_fixed_ioport(sc->iobase, UART_NS16550_IO_BAR_SIZE); 430 dsdt_fixed_irq(sc->irq); 431 dsdt_unindent(2); 432 dsdt_line(" })"); 433 dsdt_line("}"); 434 } 435 } 436 LPC_DSDT(pci_lpc_uart_dsdt); 437 438 static int 439 pci_lpc_cfgwrite(struct pci_devinst *pi, int coff, int bytes, uint32_t val) 440 { 441 int pirq_pin; 442 443 if (bytes == 1) { 444 pirq_pin = 0; 445 if (coff >= 0x60 && coff <= 0x63) 446 pirq_pin = coff - 0x60 + 1; 447 if (coff >= 0x68 && coff <= 0x6b) 448 pirq_pin = coff - 0x68 + 5; 449 if (pirq_pin != 0) { 450 pirq_write(pi->pi_vmctx, pirq_pin, val); 451 pci_set_cfgdata8(pi, coff, pirq_read(pirq_pin)); 452 return (0); 453 } 454 } 455 return (-1); 456 } 457 458 static void 459 pci_lpc_write(struct pci_devinst *pi __unused, int baridx __unused, 460 uint64_t offset __unused, int size __unused, uint64_t value __unused) 461 { 462 } 463 464 static uint64_t 465 pci_lpc_read(struct pci_devinst *pi __unused, int baridx __unused, 466 uint64_t offset __unused, int size __unused) 467 { 468 return (0); 469 } 470 471 #define LPC_DEV 0x7000 472 #define LPC_VENDOR 0x8086 473 #define LPC_REVID 0x00 474 #define LPC_SUBVEND_0 0x0000 475 #define LPC_SUBDEV_0 0x0000 476 477 static int 478 pci_lpc_get_sel(struct pcisel *const sel) 479 { 480 assert(sel != NULL); 481 482 memset(sel, 0, sizeof(*sel)); 483 484 for (uint8_t slot = 0; slot <= PCI_SLOTMAX; ++slot) { 485 uint8_t max_func = 0; 486 487 sel->pc_dev = slot; 488 sel->pc_func = 0; 489 490 if (pci_host_read_config(sel, PCIR_HDRTYPE, 1) & PCIM_MFDEV) 491 max_func = PCI_FUNCMAX; 492 493 for (uint8_t func = 0; func <= max_func; ++func) { 494 sel->pc_func = func; 495 496 if (pci_host_read_config(sel, PCIR_CLASS, 1) == 497 PCIC_BRIDGE && 498 pci_host_read_config(sel, PCIR_SUBCLASS, 1) == 499 PCIS_BRIDGE_ISA) { 500 return (0); 501 } 502 } 503 } 504 505 warnx("%s: Unable to find host selector of LPC bridge.", __func__); 506 507 return (-1); 508 } 509 510 static int 511 pci_lpc_init(struct pci_devinst *pi, nvlist_t *nvl) 512 { 513 struct pcisel sel = { 0 }; 514 struct pcisel *selp = NULL; 515 uint16_t device, subdevice, subvendor, vendor; 516 uint8_t revid; 517 518 /* 519 * Do not allow more than one LPC bridge to be configured. 520 */ 521 if (lpc_bridge != NULL) { 522 EPRINTLN("Only one LPC bridge is allowed."); 523 return (-1); 524 } 525 526 /* 527 * Enforce that the LPC can only be configured on bus 0. This 528 * simplifies the ACPI DSDT because it can provide a decode for 529 * all legacy i/o ports behind bus 0. 530 */ 531 if (pi->pi_bus != 0) { 532 EPRINTLN("LPC bridge can be present only on bus 0."); 533 return (-1); 534 } 535 536 if (lpc_init(pi->pi_vmctx) != 0) 537 return (-1); 538 539 if (pci_lpc_get_sel(&sel) == 0) 540 selp = &sel; 541 542 vendor = pci_config_read_reg(selp, nvl, PCIR_VENDOR, 2, LPC_VENDOR); 543 device = pci_config_read_reg(selp, nvl, PCIR_DEVICE, 2, LPC_DEV); 544 revid = pci_config_read_reg(selp, nvl, PCIR_REVID, 1, LPC_REVID); 545 subvendor = pci_config_read_reg(selp, nvl, PCIR_SUBVEND_0, 2, 546 LPC_SUBVEND_0); 547 subdevice = pci_config_read_reg(selp, nvl, PCIR_SUBDEV_0, 2, 548 LPC_SUBDEV_0); 549 550 /* initialize config space */ 551 pci_set_cfgdata16(pi, PCIR_VENDOR, vendor); 552 pci_set_cfgdata16(pi, PCIR_DEVICE, device); 553 pci_set_cfgdata8(pi, PCIR_CLASS, PCIC_BRIDGE); 554 pci_set_cfgdata8(pi, PCIR_SUBCLASS, PCIS_BRIDGE_ISA); 555 pci_set_cfgdata8(pi, PCIR_REVID, revid); 556 pci_set_cfgdata16(pi, PCIR_SUBVEND_0, subvendor); 557 pci_set_cfgdata16(pi, PCIR_SUBDEV_0, subdevice); 558 559 lpc_bridge = pi; 560 561 return (0); 562 } 563 564 char * 565 lpc_pirq_name(int pin) 566 { 567 char *name; 568 569 if (lpc_bridge == NULL) 570 return (NULL); 571 asprintf(&name, "\\_SB.PC00.ISA.LNK%c,", 'A' + pin - 1); 572 return (name); 573 } 574 575 void 576 lpc_pirq_routed(void) 577 { 578 int pin; 579 580 if (lpc_bridge == NULL) 581 return; 582 583 for (pin = 0; pin < 4; pin++) 584 pci_set_cfgdata8(lpc_bridge, 0x60 + pin, pirq_read(pin + 1)); 585 for (pin = 0; pin < 4; pin++) 586 pci_set_cfgdata8(lpc_bridge, 0x68 + pin, pirq_read(pin + 5)); 587 } 588 589 #ifdef BHYVE_SNAPSHOT 590 static int 591 pci_lpc_snapshot(struct vm_snapshot_meta *meta) 592 { 593 int unit, ret; 594 struct uart_ns16550_softc *sc; 595 596 for (unit = 0; unit < LPC_UART_NUM; unit++) { 597 sc = lpc_uart_softc[unit].uart_softc; 598 599 ret = uart_ns16550_snapshot(sc, meta); 600 if (ret != 0) 601 goto done; 602 } 603 604 done: 605 return (ret); 606 } 607 #endif 608 609 static const struct pci_devemu pci_de_lpc = { 610 .pe_emu = "lpc", 611 .pe_init = pci_lpc_init, 612 .pe_write_dsdt = pci_lpc_write_dsdt, 613 .pe_cfgwrite = pci_lpc_cfgwrite, 614 .pe_barwrite = pci_lpc_write, 615 .pe_barread = pci_lpc_read, 616 #ifdef BHYVE_SNAPSHOT 617 .pe_snapshot = pci_lpc_snapshot, 618 #endif 619 }; 620 PCI_EMUL_SET(pci_de_lpc); 621