1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2013 Neel Natu <neel@freebsd.org> 5 * Copyright (c) 2013 Tycho Nightingale <tycho.nightingale@pluribusnetworks.com> 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <sys/types.h> 31 #include <machine/vmm.h> 32 #include <machine/vmm_snapshot.h> 33 34 #include <err.h> 35 #include <stdio.h> 36 #include <stdlib.h> 37 #include <string.h> 38 39 #include <vmmapi.h> 40 41 #include "acpi.h" 42 #include "debug.h" 43 #include "bootrom.h" 44 #include "config.h" 45 #include "inout.h" 46 #include "pci_emul.h" 47 #include "pci_irq.h" 48 #include "pci_lpc.h" 49 #include "pci_passthru.h" 50 #include "pctestdev.h" 51 #include "tpm_device.h" 52 #include "uart_emul.h" 53 54 #define IO_ICU1 0x20 55 #define IO_ICU2 0xA0 56 57 SET_DECLARE(lpc_dsdt_set, struct lpc_dsdt); 58 SET_DECLARE(lpc_sysres_set, struct lpc_sysres); 59 60 #define ELCR_PORT 0x4d0 61 SYSRES_IO(ELCR_PORT, 2); 62 63 #define IO_TIMER1_PORT 0x40 64 65 #define NMISC_PORT 0x61 66 SYSRES_IO(NMISC_PORT, 1); 67 68 static struct pci_devinst *lpc_bridge; 69 70 #define LPC_UART_NUM 4 71 static struct lpc_uart_softc { 72 struct uart_softc *uart_softc; 73 int iobase; 74 int irq; 75 int enabled; 76 } lpc_uart_softc[LPC_UART_NUM]; 77 78 static const char *lpc_uart_names[LPC_UART_NUM] = { 79 "com1", "com2", "com3", "com4" 80 }; 81 82 static const char *lpc_uart_acpi_names[LPC_UART_NUM] = { 83 "COM1", "COM2", "COM3", "COM4" 84 }; 85 86 /* 87 * LPC device configuration is in the following form: 88 * <lpc_device_name>[,<options>] 89 * For e.g. "com1,stdio" or "bootrom,/var/romfile" 90 */ 91 int 92 lpc_device_parse(const char *opts) 93 { 94 int unit, error; 95 char *str, *cpy, *lpcdev, *node_name; 96 const char *romfile, *varfile, *tpm_type, *tpm_path; 97 98 error = -1; 99 str = cpy = strdup(opts); 100 lpcdev = strsep(&str, ","); 101 if (lpcdev != NULL) { 102 if (strcasecmp(lpcdev, "bootrom") == 0) { 103 romfile = strsep(&str, ","); 104 if (romfile == NULL) { 105 errx(4, "invalid bootrom option \"%s\"", opts); 106 } 107 set_config_value("lpc.bootrom", romfile); 108 109 varfile = strsep(&str, ","); 110 if (varfile == NULL) { 111 error = 0; 112 goto done; 113 } 114 if (strchr(varfile, '=') == NULL) { 115 set_config_value("lpc.bootvars", varfile); 116 } else { 117 /* varfile doesn't exist, it's another config 118 * option */ 119 pci_parse_legacy_config(find_config_node("lpc"), 120 varfile); 121 } 122 123 pci_parse_legacy_config(find_config_node("lpc"), str); 124 error = 0; 125 goto done; 126 } 127 if (strcasecmp(lpcdev, "tpm") == 0) { 128 nvlist_t *nvl = create_config_node("tpm"); 129 130 tpm_type = strsep(&str, ","); 131 if (tpm_type == NULL) { 132 errx(4, "invalid tpm type \"%s\"", opts); 133 } 134 set_config_value_node(nvl, "type", tpm_type); 135 136 tpm_path = strsep(&str, ","); 137 if (tpm_path == NULL) { 138 errx(4, "invalid tpm path \"%s\"", opts); 139 } 140 set_config_value_node(nvl, "path", tpm_path); 141 142 pci_parse_legacy_config(find_config_node("tpm"), str); 143 144 set_config_value_node_if_unset(nvl, "version", "2.0"); 145 error = 0; 146 goto done; 147 } 148 for (unit = 0; unit < LPC_UART_NUM; unit++) { 149 if (strcasecmp(lpcdev, lpc_uart_names[unit]) == 0) { 150 asprintf(&node_name, "lpc.%s.path", 151 lpc_uart_names[unit]); 152 set_config_value(node_name, str); 153 free(node_name); 154 error = 0; 155 goto done; 156 } 157 } 158 if (strcasecmp(lpcdev, pctestdev_getname()) == 0) { 159 asprintf(&node_name, "lpc.%s", pctestdev_getname()); 160 set_config_bool(node_name, true); 161 free(node_name); 162 error = 0; 163 goto done; 164 } 165 } 166 167 done: 168 free(cpy); 169 170 return (error); 171 } 172 173 void 174 lpc_print_supported_devices(void) 175 { 176 size_t i; 177 178 printf("bootrom\n"); 179 for (i = 0; i < LPC_UART_NUM; i++) 180 printf("%s\n", lpc_uart_names[i]); 181 printf("tpm\n"); 182 printf("%s\n", pctestdev_getname()); 183 } 184 185 const char * 186 lpc_bootrom(void) 187 { 188 189 return (get_config_value("lpc.bootrom")); 190 } 191 192 const char * 193 lpc_fwcfg(void) 194 { 195 return (get_config_value("lpc.fwcfg")); 196 } 197 198 static void 199 lpc_uart_intr_assert(void *arg) 200 { 201 struct lpc_uart_softc *sc = arg; 202 203 assert(sc->irq >= 0); 204 205 vm_isa_pulse_irq(lpc_bridge->pi_vmctx, sc->irq, sc->irq); 206 } 207 208 static void 209 lpc_uart_intr_deassert(void *arg __unused) 210 { 211 /* 212 * The COM devices on the LPC bus generate edge triggered interrupts, 213 * so nothing more to do here. 214 */ 215 } 216 217 static int 218 lpc_uart_io_handler(struct vmctx *ctx __unused, int in, 219 int port, int bytes, uint32_t *eax, void *arg) 220 { 221 int offset; 222 struct lpc_uart_softc *sc = arg; 223 224 offset = port - sc->iobase; 225 226 switch (bytes) { 227 case 1: 228 if (in) 229 *eax = uart_read(sc->uart_softc, offset); 230 else 231 uart_write(sc->uart_softc, offset, *eax); 232 break; 233 case 2: 234 if (in) { 235 *eax = uart_read(sc->uart_softc, offset); 236 *eax |= uart_read(sc->uart_softc, offset + 1) << 8; 237 } else { 238 uart_write(sc->uart_softc, offset, *eax); 239 uart_write(sc->uart_softc, offset + 1, *eax >> 8); 240 } 241 break; 242 default: 243 return (-1); 244 } 245 246 return (0); 247 } 248 249 static int 250 lpc_init(struct vmctx *ctx) 251 { 252 struct lpc_uart_softc *sc; 253 struct inout_port iop; 254 const char *backend, *name; 255 char *node_name; 256 int unit, error; 257 const nvlist_t *nvl; 258 259 nvl = find_config_node("lpc"); 260 if (nvl != NULL && nvlist_exists(nvl, "bootrom")) { 261 error = bootrom_loadrom(ctx, nvl); 262 if (error) 263 return (error); 264 } 265 266 /* COM1 and COM2 */ 267 for (unit = 0; unit < LPC_UART_NUM; unit++) { 268 sc = &lpc_uart_softc[unit]; 269 name = lpc_uart_names[unit]; 270 271 if (uart_legacy_alloc(unit, &sc->iobase, &sc->irq) != 0) { 272 EPRINTLN("Unable to allocate resources for " 273 "LPC device %s", name); 274 return (-1); 275 } 276 pci_irq_reserve(sc->irq); 277 278 sc->uart_softc = uart_init(lpc_uart_intr_assert, 279 lpc_uart_intr_deassert, sc); 280 281 asprintf(&node_name, "lpc.%s.path", name); 282 backend = get_config_value(node_name); 283 free(node_name); 284 if (uart_set_backend(sc->uart_softc, backend) != 0) { 285 EPRINTLN("Unable to initialize backend '%s' " 286 "for LPC device %s", backend, name); 287 return (-1); 288 } 289 290 bzero(&iop, sizeof(struct inout_port)); 291 iop.name = name; 292 iop.port = sc->iobase; 293 iop.size = UART_IO_BAR_SIZE; 294 iop.flags = IOPORT_F_INOUT; 295 iop.handler = lpc_uart_io_handler; 296 iop.arg = sc; 297 298 error = register_inout(&iop); 299 assert(error == 0); 300 sc->enabled = 1; 301 } 302 303 /* pc-testdev */ 304 asprintf(&node_name, "lpc.%s", pctestdev_getname()); 305 if (get_config_bool_default(node_name, false)) { 306 error = pctestdev_init(ctx); 307 if (error) 308 return (error); 309 } 310 free(node_name); 311 312 return (0); 313 } 314 315 static void 316 pci_lpc_write_dsdt(struct pci_devinst *pi) 317 { 318 struct lpc_dsdt **ldpp, *ldp; 319 320 dsdt_line(""); 321 dsdt_line("Device (ISA)"); 322 dsdt_line("{"); 323 dsdt_line(" Name (_ADR, 0x%04X%04X)", pi->pi_slot, pi->pi_func); 324 dsdt_line(" OperationRegion (LPCR, PCI_Config, 0x00, 0x100)"); 325 dsdt_line(" Field (LPCR, AnyAcc, NoLock, Preserve)"); 326 dsdt_line(" {"); 327 dsdt_line(" Offset (0x60),"); 328 dsdt_line(" PIRA, 8,"); 329 dsdt_line(" PIRB, 8,"); 330 dsdt_line(" PIRC, 8,"); 331 dsdt_line(" PIRD, 8,"); 332 dsdt_line(" Offset (0x68),"); 333 dsdt_line(" PIRE, 8,"); 334 dsdt_line(" PIRF, 8,"); 335 dsdt_line(" PIRG, 8,"); 336 dsdt_line(" PIRH, 8"); 337 dsdt_line(" }"); 338 dsdt_line(""); 339 340 dsdt_indent(1); 341 SET_FOREACH(ldpp, lpc_dsdt_set) { 342 ldp = *ldpp; 343 ldp->handler(); 344 } 345 346 dsdt_line(""); 347 dsdt_line("Device (PIC)"); 348 dsdt_line("{"); 349 dsdt_line(" Name (_HID, EisaId (\"PNP0000\"))"); 350 dsdt_line(" Name (_CRS, ResourceTemplate ()"); 351 dsdt_line(" {"); 352 dsdt_indent(2); 353 dsdt_fixed_ioport(IO_ICU1, 2); 354 dsdt_fixed_ioport(IO_ICU2, 2); 355 dsdt_fixed_irq(2); 356 dsdt_unindent(2); 357 dsdt_line(" })"); 358 dsdt_line("}"); 359 360 dsdt_line(""); 361 dsdt_line("Device (TIMR)"); 362 dsdt_line("{"); 363 dsdt_line(" Name (_HID, EisaId (\"PNP0100\"))"); 364 dsdt_line(" Name (_CRS, ResourceTemplate ()"); 365 dsdt_line(" {"); 366 dsdt_indent(2); 367 dsdt_fixed_ioport(IO_TIMER1_PORT, 4); 368 dsdt_fixed_irq(0); 369 dsdt_unindent(2); 370 dsdt_line(" })"); 371 dsdt_line("}"); 372 dsdt_unindent(1); 373 374 dsdt_line("}"); 375 } 376 377 static void 378 pci_lpc_sysres_dsdt(void) 379 { 380 struct lpc_sysres **lspp, *lsp; 381 382 dsdt_line(""); 383 dsdt_line("Device (SIO)"); 384 dsdt_line("{"); 385 dsdt_line(" Name (_HID, EisaId (\"PNP0C02\"))"); 386 dsdt_line(" Name (_CRS, ResourceTemplate ()"); 387 dsdt_line(" {"); 388 389 dsdt_indent(2); 390 SET_FOREACH(lspp, lpc_sysres_set) { 391 lsp = *lspp; 392 switch (lsp->type) { 393 case LPC_SYSRES_IO: 394 dsdt_fixed_ioport(lsp->base, lsp->length); 395 break; 396 case LPC_SYSRES_MEM: 397 dsdt_fixed_mem32(lsp->base, lsp->length); 398 break; 399 } 400 } 401 dsdt_unindent(2); 402 403 dsdt_line(" })"); 404 dsdt_line("}"); 405 } 406 LPC_DSDT(pci_lpc_sysres_dsdt); 407 408 static void 409 pci_lpc_uart_dsdt(void) 410 { 411 struct lpc_uart_softc *sc; 412 int unit; 413 414 for (unit = 0; unit < LPC_UART_NUM; unit++) { 415 sc = &lpc_uart_softc[unit]; 416 if (!sc->enabled) 417 continue; 418 dsdt_line(""); 419 dsdt_line("Device (%s)", lpc_uart_acpi_names[unit]); 420 dsdt_line("{"); 421 dsdt_line(" Name (_HID, EisaId (\"PNP0501\"))"); 422 dsdt_line(" Name (_UID, %d)", unit + 1); 423 dsdt_line(" Name (_CRS, ResourceTemplate ()"); 424 dsdt_line(" {"); 425 dsdt_indent(2); 426 dsdt_fixed_ioport(sc->iobase, UART_IO_BAR_SIZE); 427 dsdt_fixed_irq(sc->irq); 428 dsdt_unindent(2); 429 dsdt_line(" })"); 430 dsdt_line("}"); 431 } 432 } 433 LPC_DSDT(pci_lpc_uart_dsdt); 434 435 static int 436 pci_lpc_cfgwrite(struct pci_devinst *pi, int coff, int bytes, uint32_t val) 437 { 438 int pirq_pin; 439 440 if (bytes == 1) { 441 pirq_pin = 0; 442 if (coff >= 0x60 && coff <= 0x63) 443 pirq_pin = coff - 0x60 + 1; 444 if (coff >= 0x68 && coff <= 0x6b) 445 pirq_pin = coff - 0x68 + 5; 446 if (pirq_pin != 0) { 447 pirq_write(pi->pi_vmctx, pirq_pin, val); 448 pci_set_cfgdata8(pi, coff, pirq_read(pirq_pin)); 449 return (0); 450 } 451 } 452 return (-1); 453 } 454 455 static void 456 pci_lpc_write(struct pci_devinst *pi __unused, int baridx __unused, 457 uint64_t offset __unused, int size __unused, uint64_t value __unused) 458 { 459 } 460 461 static uint64_t 462 pci_lpc_read(struct pci_devinst *pi __unused, int baridx __unused, 463 uint64_t offset __unused, int size __unused) 464 { 465 return (0); 466 } 467 468 #define LPC_DEV 0x7000 469 #define LPC_VENDOR 0x8086 470 #define LPC_REVID 0x00 471 #define LPC_SUBVEND_0 0x0000 472 #define LPC_SUBDEV_0 0x0000 473 474 static int 475 pci_lpc_get_sel(struct pcisel *const sel) 476 { 477 assert(sel != NULL); 478 479 memset(sel, 0, sizeof(*sel)); 480 481 for (uint8_t slot = 0; slot <= PCI_SLOTMAX; ++slot) { 482 uint8_t max_func = 0; 483 484 sel->pc_dev = slot; 485 sel->pc_func = 0; 486 487 if (pci_host_read_config(sel, PCIR_HDRTYPE, 1) & PCIM_MFDEV) 488 max_func = PCI_FUNCMAX; 489 490 for (uint8_t func = 0; func <= max_func; ++func) { 491 sel->pc_func = func; 492 493 if (pci_host_read_config(sel, PCIR_CLASS, 1) == 494 PCIC_BRIDGE && 495 pci_host_read_config(sel, PCIR_SUBCLASS, 1) == 496 PCIS_BRIDGE_ISA) { 497 return (0); 498 } 499 } 500 } 501 502 warnx("%s: Unable to find host selector of LPC bridge.", __func__); 503 504 return (-1); 505 } 506 507 static int 508 pci_lpc_init(struct pci_devinst *pi, nvlist_t *nvl) 509 { 510 struct pcisel sel = { 0 }; 511 struct pcisel *selp = NULL; 512 uint16_t device, subdevice, subvendor, vendor; 513 uint8_t revid; 514 515 /* 516 * Do not allow more than one LPC bridge to be configured. 517 */ 518 if (lpc_bridge != NULL) { 519 EPRINTLN("Only one LPC bridge is allowed."); 520 return (-1); 521 } 522 523 /* 524 * Enforce that the LPC can only be configured on bus 0. This 525 * simplifies the ACPI DSDT because it can provide a decode for 526 * all legacy i/o ports behind bus 0. 527 */ 528 if (pi->pi_bus != 0) { 529 EPRINTLN("LPC bridge can be present only on bus 0."); 530 return (-1); 531 } 532 533 if (lpc_init(pi->pi_vmctx) != 0) 534 return (-1); 535 536 if (pci_lpc_get_sel(&sel) == 0) 537 selp = &sel; 538 539 vendor = pci_config_read_reg(selp, nvl, PCIR_VENDOR, 2, LPC_VENDOR); 540 device = pci_config_read_reg(selp, nvl, PCIR_DEVICE, 2, LPC_DEV); 541 revid = pci_config_read_reg(selp, nvl, PCIR_REVID, 1, LPC_REVID); 542 subvendor = pci_config_read_reg(selp, nvl, PCIR_SUBVEND_0, 2, 543 LPC_SUBVEND_0); 544 subdevice = pci_config_read_reg(selp, nvl, PCIR_SUBDEV_0, 2, 545 LPC_SUBDEV_0); 546 547 /* initialize config space */ 548 pci_set_cfgdata16(pi, PCIR_VENDOR, vendor); 549 pci_set_cfgdata16(pi, PCIR_DEVICE, device); 550 pci_set_cfgdata8(pi, PCIR_CLASS, PCIC_BRIDGE); 551 pci_set_cfgdata8(pi, PCIR_SUBCLASS, PCIS_BRIDGE_ISA); 552 pci_set_cfgdata8(pi, PCIR_REVID, revid); 553 pci_set_cfgdata16(pi, PCIR_SUBVEND_0, subvendor); 554 pci_set_cfgdata16(pi, PCIR_SUBDEV_0, subdevice); 555 556 lpc_bridge = pi; 557 558 return (0); 559 } 560 561 char * 562 lpc_pirq_name(int pin) 563 { 564 char *name; 565 566 if (lpc_bridge == NULL) 567 return (NULL); 568 asprintf(&name, "\\_SB.PC00.ISA.LNK%c,", 'A' + pin - 1); 569 return (name); 570 } 571 572 void 573 lpc_pirq_routed(void) 574 { 575 int pin; 576 577 if (lpc_bridge == NULL) 578 return; 579 580 for (pin = 0; pin < 4; pin++) 581 pci_set_cfgdata8(lpc_bridge, 0x60 + pin, pirq_read(pin + 1)); 582 for (pin = 0; pin < 4; pin++) 583 pci_set_cfgdata8(lpc_bridge, 0x68 + pin, pirq_read(pin + 5)); 584 } 585 586 #ifdef BHYVE_SNAPSHOT 587 static int 588 pci_lpc_snapshot(struct vm_snapshot_meta *meta) 589 { 590 int unit, ret; 591 struct uart_softc *sc; 592 593 for (unit = 0; unit < LPC_UART_NUM; unit++) { 594 sc = lpc_uart_softc[unit].uart_softc; 595 596 ret = uart_snapshot(sc, meta); 597 if (ret != 0) 598 goto done; 599 } 600 601 done: 602 return (ret); 603 } 604 #endif 605 606 static const struct pci_devemu pci_de_lpc = { 607 .pe_emu = "lpc", 608 .pe_init = pci_lpc_init, 609 .pe_write_dsdt = pci_lpc_write_dsdt, 610 .pe_cfgwrite = pci_lpc_cfgwrite, 611 .pe_barwrite = pci_lpc_write, 612 .pe_barread = pci_lpc_read, 613 #ifdef BHYVE_SNAPSHOT 614 .pe_snapshot = pci_lpc_snapshot, 615 #endif 616 }; 617 PCI_EMUL_SET(pci_de_lpc); 618