1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2014 Hudson River Trading LLC 5 * Written by: John H. Baldwin <jhb@FreeBSD.org> 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <sys/param.h> 31 #include <machine/vmm.h> 32 33 #include <assert.h> 34 #include <pthread.h> 35 #include <stdbool.h> 36 #include <stdio.h> 37 #include <stdlib.h> 38 #include <vmmapi.h> 39 40 #include "acpi.h" 41 #include "inout.h" 42 #include "pci_emul.h" 43 #include "pci_irq.h" 44 #include "pci_lpc.h" 45 46 /* 47 * Implement an 8 pin PCI interrupt router compatible with the router 48 * present on Intel's ICH10 chip. 49 */ 50 51 /* Fields in each PIRQ register. */ 52 #define PIRQ_DIS 0x80 53 #define PIRQ_IRQ 0x0f 54 55 /* Only IRQs 3-7, 9-12, and 14-15 are permitted. */ 56 #define PERMITTED_IRQS 0xdef8 57 #define IRQ_PERMITTED(irq) (((1U << (irq)) & PERMITTED_IRQS) != 0) 58 59 /* IRQ count to disable an IRQ. */ 60 #define IRQ_DISABLED 0xff 61 62 #define NPIRQS 8 63 static struct pirq { 64 uint8_t reg; 65 int use_count; 66 int active_count; 67 pthread_mutex_t lock; 68 } pirqs[NPIRQS]; 69 70 #define NIRQ_COUNTS 16 71 static u_char irq_counts[NIRQ_COUNTS]; 72 static int pirq_cold = 1; 73 74 /* 75 * Returns true if this pin is enabled with a valid IRQ. Setting the 76 * register to a reserved IRQ causes interrupts to not be asserted as 77 * if the pin was disabled. 78 */ 79 static bool 80 pirq_valid_irq(int reg) 81 { 82 83 if (reg & PIRQ_DIS) 84 return (false); 85 return (IRQ_PERMITTED(reg & PIRQ_IRQ)); 86 } 87 88 uint8_t 89 pirq_read(int pin) 90 { 91 92 assert(pin > 0 && pin <= NPIRQS); 93 return (pirqs[pin - 1].reg); 94 } 95 96 void 97 pirq_write(struct vmctx *ctx, int pin, uint8_t val) 98 { 99 struct pirq *pirq; 100 101 assert(pin > 0 && pin <= NPIRQS); 102 pirq = &pirqs[pin - 1]; 103 pthread_mutex_lock(&pirq->lock); 104 if (pirq->reg != (val & (PIRQ_DIS | PIRQ_IRQ))) { 105 if (pirq->active_count != 0 && pirq_valid_irq(pirq->reg)) 106 vm_isa_deassert_irq(ctx, pirq->reg & PIRQ_IRQ, -1); 107 pirq->reg = val & (PIRQ_DIS | PIRQ_IRQ); 108 if (pirq->active_count != 0 && pirq_valid_irq(pirq->reg)) 109 vm_isa_assert_irq(ctx, pirq->reg & PIRQ_IRQ, -1); 110 } 111 pthread_mutex_unlock(&pirq->lock); 112 } 113 114 void 115 pci_irq_reserve(int irq) 116 { 117 118 assert(irq >= 0 && irq < NIRQ_COUNTS); 119 assert(pirq_cold); 120 assert(irq_counts[irq] == 0 || irq_counts[irq] == IRQ_DISABLED); 121 irq_counts[irq] = IRQ_DISABLED; 122 } 123 124 void 125 pci_irq_use(int irq) 126 { 127 128 assert(irq >= 0 && irq < NIRQ_COUNTS); 129 assert(pirq_cold); 130 assert(irq_counts[irq] != IRQ_DISABLED); 131 irq_counts[irq]++; 132 } 133 134 void 135 pci_irq_init(struct vmctx *ctx __unused) 136 { 137 int i; 138 139 for (i = 0; i < NPIRQS; i++) { 140 pirqs[i].reg = PIRQ_DIS; 141 pirqs[i].use_count = 0; 142 pirqs[i].active_count = 0; 143 pthread_mutex_init(&pirqs[i].lock, NULL); 144 } 145 for (i = 0; i < NIRQ_COUNTS; i++) { 146 if (IRQ_PERMITTED(i)) 147 irq_counts[i] = 0; 148 else 149 irq_counts[i] = IRQ_DISABLED; 150 } 151 } 152 153 void 154 pci_irq_assert(struct pci_devinst *pi) 155 { 156 struct pirq *pirq; 157 int pin; 158 159 pin = pi->pi_lintr.pirq_pin; 160 if (pin > 0) { 161 assert(pin <= NPIRQS); 162 pirq = &pirqs[pin - 1]; 163 pthread_mutex_lock(&pirq->lock); 164 pirq->active_count++; 165 if (pirq->active_count == 1 && pirq_valid_irq(pirq->reg)) { 166 vm_isa_assert_irq(pi->pi_vmctx, pirq->reg & PIRQ_IRQ, 167 pi->pi_lintr.ioapic_irq); 168 pthread_mutex_unlock(&pirq->lock); 169 return; 170 } 171 pthread_mutex_unlock(&pirq->lock); 172 } 173 vm_ioapic_assert_irq(pi->pi_vmctx, pi->pi_lintr.ioapic_irq); 174 } 175 176 void 177 pci_irq_deassert(struct pci_devinst *pi) 178 { 179 struct pirq *pirq; 180 int pin; 181 182 pin = pi->pi_lintr.pirq_pin; 183 if (pin > 0) { 184 assert(pin <= NPIRQS); 185 pirq = &pirqs[pin - 1]; 186 pthread_mutex_lock(&pirq->lock); 187 pirq->active_count--; 188 if (pirq->active_count == 0 && pirq_valid_irq(pirq->reg)) { 189 vm_isa_deassert_irq(pi->pi_vmctx, pirq->reg & PIRQ_IRQ, 190 pi->pi_lintr.ioapic_irq); 191 pthread_mutex_unlock(&pirq->lock); 192 return; 193 } 194 pthread_mutex_unlock(&pirq->lock); 195 } 196 vm_ioapic_deassert_irq(pi->pi_vmctx, pi->pi_lintr.ioapic_irq); 197 } 198 199 int 200 pirq_alloc_pin(struct pci_devinst *pi) 201 { 202 struct vmctx *ctx = pi->pi_vmctx; 203 int best_count, best_irq, best_pin, irq, pin; 204 205 pirq_cold = 0; 206 207 if (lpc_bootrom()) { 208 /* For external bootrom use fixed mapping. */ 209 best_pin = (4 + pi->pi_slot + pi->pi_lintr.pin) % 8; 210 } else { 211 /* Find the least-used PIRQ pin. */ 212 best_pin = 0; 213 best_count = pirqs[0].use_count; 214 for (pin = 1; pin < NPIRQS; pin++) { 215 if (pirqs[pin].use_count < best_count) { 216 best_pin = pin; 217 best_count = pirqs[pin].use_count; 218 } 219 } 220 } 221 pirqs[best_pin].use_count++; 222 223 /* Second, route this pin to an IRQ. */ 224 if (pirqs[best_pin].reg == PIRQ_DIS) { 225 best_irq = -1; 226 best_count = 0; 227 for (irq = 0; irq < NIRQ_COUNTS; irq++) { 228 if (irq_counts[irq] == IRQ_DISABLED) 229 continue; 230 if (best_irq == -1 || irq_counts[irq] < best_count) { 231 best_irq = irq; 232 best_count = irq_counts[irq]; 233 } 234 } 235 assert(best_irq >= 0); 236 irq_counts[best_irq]++; 237 pirqs[best_pin].reg = best_irq; 238 vm_isa_set_irq_trigger(ctx, best_irq, LEVEL_TRIGGER); 239 } 240 241 return (best_pin + 1); 242 } 243 244 int 245 pirq_irq(int pin) 246 { 247 assert(pin > 0 && pin <= NPIRQS); 248 return (pirqs[pin - 1].reg & PIRQ_IRQ); 249 } 250 251 /* XXX: Generate $PIR table. */ 252 253 static void 254 pirq_dsdt(void) 255 { 256 char *irq_prs, *old; 257 int irq, pin; 258 259 irq_prs = NULL; 260 for (irq = 0; irq < NIRQ_COUNTS; irq++) { 261 if (!IRQ_PERMITTED(irq)) 262 continue; 263 if (irq_prs == NULL) 264 asprintf(&irq_prs, "%d", irq); 265 else { 266 old = irq_prs; 267 asprintf(&irq_prs, "%s,%d", old, irq); 268 free(old); 269 } 270 } 271 272 /* 273 * A helper method to validate a link register's value. This 274 * duplicates pirq_valid_irq(). 275 */ 276 dsdt_line(""); 277 dsdt_line("Method (PIRV, 1, NotSerialized)"); 278 dsdt_line("{"); 279 dsdt_line(" If (And (Arg0, 0x%02X))", PIRQ_DIS); 280 dsdt_line(" {"); 281 dsdt_line(" Return (0x00)"); 282 dsdt_line(" }"); 283 dsdt_line(" And (Arg0, 0x%02X, Local0)", PIRQ_IRQ); 284 dsdt_line(" If (LLess (Local0, 0x03))"); 285 dsdt_line(" {"); 286 dsdt_line(" Return (0x00)"); 287 dsdt_line(" }"); 288 dsdt_line(" If (LEqual (Local0, 0x08))"); 289 dsdt_line(" {"); 290 dsdt_line(" Return (0x00)"); 291 dsdt_line(" }"); 292 dsdt_line(" If (LEqual (Local0, 0x0D))"); 293 dsdt_line(" {"); 294 dsdt_line(" Return (0x00)"); 295 dsdt_line(" }"); 296 dsdt_line(" Return (0x01)"); 297 dsdt_line("}"); 298 299 for (pin = 0; pin < NPIRQS; pin++) { 300 dsdt_line(""); 301 dsdt_line("Device (LNK%c)", 'A' + pin); 302 dsdt_line("{"); 303 dsdt_line(" Name (_HID, EisaId (\"PNP0C0F\"))"); 304 dsdt_line(" Name (_UID, 0x%02X)", pin + 1); 305 dsdt_line(" Method (_STA, 0, NotSerialized)"); 306 dsdt_line(" {"); 307 dsdt_line(" If (PIRV (PIR%c))", 'A' + pin); 308 dsdt_line(" {"); 309 dsdt_line(" Return (0x0B)"); 310 dsdt_line(" }"); 311 dsdt_line(" Else"); 312 dsdt_line(" {"); 313 dsdt_line(" Return (0x09)"); 314 dsdt_line(" }"); 315 dsdt_line(" }"); 316 dsdt_line(" Name (_PRS, ResourceTemplate ()"); 317 dsdt_line(" {"); 318 dsdt_line(" IRQ (Level, ActiveLow, Shared, )"); 319 dsdt_line(" {%s}", irq_prs); 320 dsdt_line(" })"); 321 dsdt_line(" Name (CB%02X, ResourceTemplate ()", pin + 1); 322 dsdt_line(" {"); 323 dsdt_line(" IRQ (Level, ActiveLow, Shared, )"); 324 dsdt_line(" {}"); 325 dsdt_line(" })"); 326 dsdt_line(" CreateWordField (CB%02X, 0x01, CIR%c)", 327 pin + 1, 'A' + pin); 328 dsdt_line(" Method (_CRS, 0, NotSerialized)"); 329 dsdt_line(" {"); 330 dsdt_line(" And (PIR%c, 0x%02X, Local0)", 'A' + pin, 331 PIRQ_DIS | PIRQ_IRQ); 332 dsdt_line(" If (PIRV (Local0))"); 333 dsdt_line(" {"); 334 dsdt_line(" ShiftLeft (0x01, Local0, CIR%c)", 'A' + pin); 335 dsdt_line(" }"); 336 dsdt_line(" Else"); 337 dsdt_line(" {"); 338 dsdt_line(" Store (0x00, CIR%c)", 'A' + pin); 339 dsdt_line(" }"); 340 dsdt_line(" Return (CB%02X)", pin + 1); 341 dsdt_line(" }"); 342 dsdt_line(" Method (_DIS, 0, NotSerialized)"); 343 dsdt_line(" {"); 344 dsdt_line(" Store (0x80, PIR%c)", 'A' + pin); 345 dsdt_line(" }"); 346 dsdt_line(" Method (_SRS, 1, NotSerialized)"); 347 dsdt_line(" {"); 348 dsdt_line(" CreateWordField (Arg0, 0x01, SIR%c)", 'A' + pin); 349 dsdt_line(" FindSetRightBit (SIR%c, Local0)", 'A' + pin); 350 dsdt_line(" Store (Decrement (Local0), PIR%c)", 'A' + pin); 351 dsdt_line(" }"); 352 dsdt_line("}"); 353 } 354 free(irq_prs); 355 } 356 LPC_DSDT(pirq_dsdt); 357