1 /** @file 2 IGD OpRegion definition from Intel Integrated Graphics Device OpRegion 3 Specification. 4 5 https://01.org/sites/default/files/documentation/skl_opregion_rev0p5.pdf 6 7 Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR> 8 SPDX-License-Identifier: BSD-2-Clause-Patent 9 10 **/ 11 12 /* 13 * See 14 * <https://github.com/tianocore/edk2-platforms/blob/82979ab1ca44101e0b92a9c4bda1dfe64a8249f6/Silicon/Intel/IntelSiliconPkg/Include/IndustryStandard/IgdOpRegion.h> 15 */ 16 17 #pragma once 18 19 #include <sys/types.h> 20 21 #define IGD_OPREGION_HEADER_SIGN "IntelGraphicsMem" 22 #define IGD_OPREGION_HEADER_MBOX1 BIT0 23 #define IGD_OPREGION_HEADER_MBOX2 BIT1 24 #define IGD_OPREGION_HEADER_MBOX3 BIT2 25 #define IGD_OPREGION_HEADER_MBOX4 BIT3 26 #define IGD_OPREGION_HEADER_MBOX5 BIT4 27 28 #define IGD_OPREGION_VBT_SIZE_6K (6 * 1024UL) 29 30 /** 31 OpRegion structures: 32 Sub-structures define the different parts of the OpRegion followed by the 33 main structure representing the entire OpRegion. 34 @note These structures are packed to 1 byte offsets because the exact 35 data location is required by the supporting design specification due to 36 the fact that the data is used by ASL and Graphics driver code compiled 37 separately. 38 **/ 39 40 /// 41 /// OpRegion Mailbox 0 Header structure. The OpRegion Header is used to 42 /// identify a block of memory as the graphics driver OpRegion. 43 /// Offset 0x0, Size 0x100 44 /// 45 struct igd_opregion_header { 46 int8_t sign[0x10]; ///< Offset 0x00 OpRegion Signature 47 uint32_t size; ///< Offset 0x10 OpRegion Size 48 uint32_t over; ///< Offset 0x14 OpRegion Structure Version 49 uint8_t sver[0x20]; ///< Offset 0x18 System BIOS Build Version 50 uint8_t vver[0x10]; ///< Offset 0x38 Video BIOS Build Version 51 uint8_t gver[0x10]; ///< Offset 0x48 Graphic Driver Build Version 52 uint32_t mbox; ///< Offset 0x58 Supported Mailboxes 53 uint32_t dmod; ///< Offset 0x5C Driver Model 54 uint32_t pcon; ///< Offset 0x60 Platform Configuration 55 int16_t dver[0x10]; ///< Offset 0x64 GOP Version 56 uint8_t rm01[0x7C]; ///< Offset 0x84 Reserved Must be zero 57 } __packed; 58 59 /// 60 /// OpRegion Mailbox 1 - Public ACPI Methods 61 /// Offset 0x100, Size 0x100 62 /// 63 struct igd_opregion_mbox1 { 64 uint32_t drdy; ///< Offset 0x100 Driver Readiness 65 uint32_t csts; ///< Offset 0x104 Status 66 uint32_t cevt; ///< Offset 0x108 Current Event 67 uint8_t rm11[0x14]; ///< Offset 0x10C Reserved Must be Zero 68 uint32_t didl[8]; ///< Offset 0x120 Supported Display Devices ID List 69 uint32_t 70 cpdl[8]; ///< Offset 0x140 Currently Attached Display Devices List 71 uint32_t 72 cadl[8]; ///< Offset 0x160 Currently Active Display Devices List 73 uint32_t nadl[8]; ///< Offset 0x180 Next Active Devices List 74 uint32_t aslp; ///< Offset 0x1A0 ASL Sleep Time Out 75 uint32_t tidx; ///< Offset 0x1A4 Toggle Table Index 76 uint32_t chpd; ///< Offset 0x1A8 Current Hotplug Enable Indicator 77 uint32_t clid; ///< Offset 0x1AC Current Lid State Indicator 78 uint32_t cdck; ///< Offset 0x1B0 Current Docking State Indicator 79 uint32_t sxsw; ///< Offset 0x1B4 Display Switch Notification on Sx 80 ///< StateResume 81 uint32_t evts; ///< Offset 0x1B8 Events supported by ASL 82 uint32_t cnot; ///< Offset 0x1BC Current OS Notification 83 uint32_t NRDY; ///< Offset 0x1C0 Driver Status 84 uint8_t did2[0x1C]; ///< Offset 0x1C4 Extended Supported Devices ID 85 ///< List(DOD) 86 uint8_t 87 cpd2[0x1C]; ///< Offset 0x1E0 Extended Attached Display Devices List 88 uint8_t rm12[4]; ///< Offset 0x1FC - 0x1FF Reserved Must be zero 89 } __packed; 90 91 /// 92 /// OpRegion Mailbox 2 - Software SCI Interface 93 /// Offset 0x200, Size 0x100 94 /// 95 struct igd_opregion_mbox2 { 96 uint32_t scic; ///< Offset 0x200 Software SCI Command / Status / Data 97 uint32_t parm; ///< Offset 0x204 Software SCI Parameters 98 uint32_t dslp; ///< Offset 0x208 Driver Sleep Time Out 99 uint8_t rm21[0xF4]; ///< Offset 0x20C - 0x2FF Reserved Must be zero 100 } __packed; 101 102 /// 103 /// OpRegion Mailbox 3 - BIOS/Driver Notification - ASLE Support 104 /// Offset 0x300, Size 0x100 105 /// 106 struct igd_opregion_mbox3 { 107 uint32_t ardy; ///< Offset 0x300 Driver Readiness 108 uint32_t aslc; ///< Offset 0x304 ASLE Interrupt Command / Status 109 uint32_t tche; ///< Offset 0x308 Technology Enabled Indicator 110 uint32_t alsi; ///< Offset 0x30C Current ALS Luminance Reading 111 uint32_t bclp; ///< Offset 0x310 Requested Backlight Brightness 112 uint32_t pfit; ///< Offset 0x314 Panel Fitting State or Request 113 uint32_t cblv; ///< Offset 0x318 Current Brightness Level 114 uint16_t bclm[0x14]; ///< Offset 0x31C Backlight Brightness Levels Duty 115 ///< Cycle Mapping Table 116 uint32_t cpfm; ///< Offset 0x344 Current Panel Fitting Mode 117 uint32_t epfm; ///< Offset 0x348 Enabled Panel Fitting Modes 118 uint8_t plut[0x4A]; ///< Offset 0x34C Panel Look Up Table & Identifier 119 uint32_t pfmb; ///< Offset 0x396 PWM Frequency and Minimum Brightness 120 uint32_t ccdv; ///< Offset 0x39A Color Correction Default Values 121 uint32_t pcft; ///< Offset 0x39E Power Conservation Features 122 uint32_t srot; ///< Offset 0x3A2 Supported Rotation Angles 123 uint32_t iuer; ///< Offset 0x3A6 Intel Ultrabook(TM) Event Register 124 uint64_t fdss; ///< Offset 0x3AA DSS Buffer address allocated for IFFS 125 ///< feature 126 uint32_t fdsp; ///< Offset 0x3B2 Size of DSS buffer 127 uint32_t stat; ///< Offset 0x3B6 State Indicator 128 uint64_t rvda; ///< Offset 0x3BA Absolute/Relative Address of Raw VBT 129 ///< Data from OpRegion Base 130 uint32_t rvds; ///< Offset 0x3C2 Raw VBT Data Size 131 uint8_t rsvd2[0x3A]; ///< Offset 0x3C6 - 0x3FF Reserved Must be zero. 132 ///< Bug in spec 0x45(69) 133 } __packed; 134 135 /// 136 /// OpRegion Mailbox 4 - VBT Video BIOS Table 137 /// Offset 0x400, Size 0x1800 138 /// 139 struct igd_opregion_mbox4 { 140 uint8_t rvbt[IGD_OPREGION_VBT_SIZE_6K]; ///< Offset 0x400 - 0x1BFF Raw 141 ///< VBT Data 142 } __packed; 143 144 /// 145 /// OpRegion Mailbox 5 - BIOS/Driver Notification - Data storage BIOS to Driver 146 /// data sync Offset 0x1C00, Size 0x400 147 /// 148 struct igd_opregion_mbox5 { 149 uint32_t phed; ///< Offset 0x1C00 Panel Header 150 uint8_t bddc[0x100]; ///< Offset 0x1C04 Panel EDID (DDC data) 151 uint8_t rm51[0x2FC]; ///< Offset 0x1D04 - 0x1FFF Reserved Must be zero 152 } __packed; 153 154 /// 155 /// IGD OpRegion Structure 156 /// 157 struct igd_opregion { 158 struct igd_opregion_header 159 header; ///< OpRegion header (Offset 0x0, Size 0x100) 160 struct igd_opregion_mbox1 mbox1; ///< Mailbox 1: Public ACPI Methods 161 ///< (Offset 0x100, Size 0x100) 162 struct igd_opregion_mbox2 mbox2; ///< Mailbox 2: Software SCI Interface 163 ///< (Offset 0x200, Size 0x100) 164 struct igd_opregion_mbox3 165 mbox3; ///< Mailbox 3: BIOS to Driver Notification (Offset 0x300, 166 ///< Size 0x100) 167 struct igd_opregion_mbox4 mbox4; ///< Mailbox 4: Video BIOS Table (VBT) 168 ///< (Offset 0x400, Size 0x1800) 169 struct igd_opregion_mbox5 170 mbox5; ///< Mailbox 5: BIOS to Driver Notification Extension (Offset 171 ///< 0x1C00, Size 0x400) 172 } __packed; 173 174 /// 175 /// VBT Header Structure 176 /// 177 struct vbt_header { 178 uint8_t product_string[20]; 179 uint16_t version; 180 uint16_t header_size; 181 uint16_t table_size; 182 uint8_t checksum; 183 uint8_t reserved1; 184 uint32_t bios_data_offset; 185 uint32_t aim_data_offset[4]; 186 } __packed; 187