xref: /freebsd/usr.sbin/bhyve/amd64/mptbl.c (revision edf8578117e8844e02c0121147f45e4609b30680)
1 /*-
2  * SPDX-License-Identifier: BSD-2-Clause
3  *
4  * Copyright (c) 2012 NetApp, Inc.
5  * All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  * 1. Redistributions of source code must retain the above copyright
11  *    notice, this list of conditions and the following disclaimer.
12  * 2. Redistributions in binary form must reproduce the above copyright
13  *    notice, this list of conditions and the following disclaimer in the
14  *    documentation and/or other materials provided with the distribution.
15  *
16  * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19  * ARE DISCLAIMED.  IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
20  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26  * SUCH DAMAGE.
27  */
28 
29 #include <sys/cdefs.h>
30 #include <sys/types.h>
31 #include <sys/errno.h>
32 #include <x86/mptable.h>
33 
34 #include <stdio.h>
35 #include <string.h>
36 
37 #include "acpi.h"
38 #include "debug.h"
39 #include "bhyverun.h"
40 #include "mptbl.h"
41 #include "pci_emul.h"
42 
43 #define MPTABLE_BASE		0xF0000
44 
45 /* floating pointer length + maximum length of configuration table */
46 #define	MPTABLE_MAX_LENGTH	(65536 + 16)
47 
48 #define LAPIC_PADDR		0xFEE00000
49 #define LAPIC_VERSION 		16
50 
51 #define IOAPIC_PADDR		0xFEC00000
52 #define IOAPIC_VERSION		0x11
53 
54 #define MP_SPECREV		4
55 #define MPFP_SIG		"_MP_"
56 
57 /* Configuration header defines */
58 #define MPCH_SIG		"PCMP"
59 #define MPCH_OEMID		"BHyVe   "
60 #define MPCH_OEMID_LEN          8
61 #define MPCH_PRODID             "Hypervisor  "
62 #define MPCH_PRODID_LEN         12
63 
64 /* Processor entry defines */
65 #define MPEP_SIG_FAMILY		6	/* XXX bhyve should supply this */
66 #define MPEP_SIG_MODEL		26
67 #define MPEP_SIG_STEPPING	5
68 #define MPEP_SIG		\
69 	((MPEP_SIG_FAMILY << 8) | \
70 	 (MPEP_SIG_MODEL << 4)	| \
71 	 (MPEP_SIG_STEPPING))
72 
73 #define MPEP_FEATURES           (0xBFEBFBFF) /* XXX Intel i7 */
74 
75 /* Number of local intr entries */
76 #define	MPEII_NUM_LOCAL_IRQ	2
77 
78 /* Bus entry defines */
79 #define MPE_NUM_BUSES		2
80 #define MPE_BUSNAME_LEN		6
81 #define MPE_BUSNAME_ISA		"ISA   "
82 #define MPE_BUSNAME_PCI		"PCI   "
83 
84 static void *oem_tbl_start;
85 static int oem_tbl_size;
86 
87 static uint8_t
88 mpt_compute_checksum(void *base, size_t len)
89 {
90 	uint8_t	*bytes;
91 	uint8_t	sum;
92 
93 	for(bytes = base, sum = 0; len > 0; len--) {
94 		sum += *bytes++;
95 	}
96 
97 	return (256 - sum);
98 }
99 
100 static void
101 mpt_build_mpfp(mpfps_t mpfp, vm_paddr_t gpa)
102 {
103 
104 	memset(mpfp, 0, sizeof(*mpfp));
105 	memcpy(mpfp->signature, MPFP_SIG, 4);
106 	mpfp->pap = gpa + sizeof(*mpfp);
107 	mpfp->length = 1;
108 	mpfp->spec_rev = MP_SPECREV;
109 	mpfp->checksum = mpt_compute_checksum(mpfp, sizeof(*mpfp));
110 }
111 
112 static void
113 mpt_build_mpch(mpcth_t mpch)
114 {
115 
116 	memset(mpch, 0, sizeof(*mpch));
117 	memcpy(mpch->signature, MPCH_SIG, 4);
118 	mpch->spec_rev = MP_SPECREV;
119 	memcpy(mpch->oem_id, MPCH_OEMID, MPCH_OEMID_LEN);
120 	memcpy(mpch->product_id, MPCH_PRODID, MPCH_PRODID_LEN);
121 	mpch->apic_address = LAPIC_PADDR;
122 }
123 
124 static void
125 mpt_build_proc_entries(proc_entry_ptr mpep, int ncpu)
126 {
127 	int i;
128 
129 	for (i = 0; i < ncpu; i++) {
130 		memset(mpep, 0, sizeof(*mpep));
131 		mpep->type = MPCT_ENTRY_PROCESSOR;
132 		mpep->apic_id = i; // XXX
133 		mpep->apic_version = LAPIC_VERSION;
134 		mpep->cpu_flags = PROCENTRY_FLAG_EN;
135 		if (i == 0)
136 			mpep->cpu_flags |= PROCENTRY_FLAG_BP;
137 		mpep->cpu_signature = MPEP_SIG;
138 		mpep->feature_flags = MPEP_FEATURES;
139 		mpep++;
140 	}
141 }
142 
143 static void
144 mpt_build_localint_entries(int_entry_ptr mpie)
145 {
146 
147 	/* Hardcode LINT0 as ExtINT on all CPUs. */
148 	memset(mpie, 0, sizeof(*mpie));
149 	mpie->type = MPCT_ENTRY_LOCAL_INT;
150 	mpie->int_type = INTENTRY_TYPE_EXTINT;
151 	mpie->int_flags = INTENTRY_FLAGS_POLARITY_CONFORM |
152 	    INTENTRY_FLAGS_TRIGGER_CONFORM;
153 	mpie->dst_apic_id = 0xff;
154 	mpie->dst_apic_int = 0;
155 	mpie++;
156 
157 	/* Hardcode LINT1 as NMI on all CPUs. */
158 	memset(mpie, 0, sizeof(*mpie));
159 	mpie->type = MPCT_ENTRY_LOCAL_INT;
160 	mpie->int_type = INTENTRY_TYPE_NMI;
161 	mpie->int_flags = INTENTRY_FLAGS_POLARITY_CONFORM |
162 	    INTENTRY_FLAGS_TRIGGER_CONFORM;
163 	mpie->dst_apic_id = 0xff;
164 	mpie->dst_apic_int = 1;
165 }
166 
167 static void
168 mpt_build_bus_entries(bus_entry_ptr mpeb)
169 {
170 
171 	memset(mpeb, 0, sizeof(*mpeb));
172 	mpeb->type = MPCT_ENTRY_BUS;
173 	mpeb->bus_id = 0;
174 	memcpy(mpeb->bus_type, MPE_BUSNAME_PCI, MPE_BUSNAME_LEN);
175 	mpeb++;
176 
177 	memset(mpeb, 0, sizeof(*mpeb));
178 	mpeb->type = MPCT_ENTRY_BUS;
179 	mpeb->bus_id = 1;
180 	memcpy(mpeb->bus_type, MPE_BUSNAME_ISA, MPE_BUSNAME_LEN);
181 }
182 
183 static void
184 mpt_build_ioapic_entries(io_apic_entry_ptr mpei, int id)
185 {
186 
187 	memset(mpei, 0, sizeof(*mpei));
188 	mpei->type = MPCT_ENTRY_IOAPIC;
189 	mpei->apic_id = id;
190 	mpei->apic_version = IOAPIC_VERSION;
191 	mpei->apic_flags = IOAPICENTRY_FLAG_EN;
192 	mpei->apic_address = IOAPIC_PADDR;
193 }
194 
195 static int
196 mpt_count_ioint_entries(void)
197 {
198 	int bus, count;
199 
200 	count = 0;
201 	for (bus = 0; bus <= PCI_BUSMAX; bus++)
202 		count += pci_count_lintr(bus);
203 
204 	/*
205 	 * Always include entries for the first 16 pins along with a entry
206 	 * for each active PCI INTx pin.
207 	 */
208 	return (16 + count);
209 }
210 
211 static void
212 mpt_generate_pci_int(int bus, int slot, int pin, int pirq_pin __unused,
213     int ioapic_irq, void *arg)
214 {
215 	int_entry_ptr *mpiep, mpie;
216 
217 	mpiep = arg;
218 	mpie = *mpiep;
219 	memset(mpie, 0, sizeof(*mpie));
220 
221 	/*
222 	 * This is always after another I/O interrupt entry, so cheat
223 	 * and fetch the I/O APIC ID from the prior entry.
224 	 */
225 	mpie->type = MPCT_ENTRY_INT;
226 	mpie->int_type = INTENTRY_TYPE_INT;
227 	mpie->src_bus_id = bus;
228 	mpie->src_bus_irq = slot << 2 | (pin - 1);
229 	mpie->dst_apic_id = mpie[-1].dst_apic_id;
230 	mpie->dst_apic_int = ioapic_irq;
231 
232 	*mpiep = mpie + 1;
233 }
234 
235 static void
236 mpt_build_ioint_entries(int_entry_ptr mpie, int id)
237 {
238 	int pin, bus;
239 
240 	/*
241 	 * The following config is taken from kernel mptable.c
242 	 * mptable_parse_default_config_ints(...), for now
243 	 * just use the default config, tweek later if needed.
244 	 */
245 
246 	/* First, generate the first 16 pins. */
247 	for (pin = 0; pin < 16; pin++) {
248 		memset(mpie, 0, sizeof(*mpie));
249 		mpie->type = MPCT_ENTRY_INT;
250 		mpie->src_bus_id = 1;
251 		mpie->dst_apic_id = id;
252 
253 		/*
254 		 * All default configs route IRQs from bus 0 to the first 16
255 		 * pins of the first I/O APIC with an APIC ID of 2.
256 		 */
257 		mpie->dst_apic_int = pin;
258 		switch (pin) {
259 		case 0:
260 			/* Pin 0 is an ExtINT pin. */
261 			mpie->int_type = INTENTRY_TYPE_EXTINT;
262 			break;
263 		case 2:
264 			/* IRQ 0 is routed to pin 2. */
265 			mpie->int_type = INTENTRY_TYPE_INT;
266 			mpie->src_bus_irq = 0;
267 			break;
268 		case SCI_INT:
269 			/* ACPI SCI is level triggered and active-lo. */
270 			mpie->int_flags = INTENTRY_FLAGS_POLARITY_ACTIVELO |
271 			    INTENTRY_FLAGS_TRIGGER_LEVEL;
272 			mpie->int_type = INTENTRY_TYPE_INT;
273 			mpie->src_bus_irq = SCI_INT;
274 			break;
275 		default:
276 			/* All other pins are identity mapped. */
277 			mpie->int_type = INTENTRY_TYPE_INT;
278 			mpie->src_bus_irq = pin;
279 			break;
280 		}
281 		mpie++;
282 	}
283 
284 	/* Next, generate entries for any PCI INTx interrupts. */
285 	for (bus = 0; bus <= PCI_BUSMAX; bus++)
286 		pci_walk_lintr(bus, mpt_generate_pci_int, &mpie);
287 }
288 
289 void
290 mptable_add_oemtbl(void *tbl, int tblsz)
291 {
292 
293 	oem_tbl_start = tbl;
294 	oem_tbl_size = tblsz;
295 }
296 
297 int
298 mptable_build(struct vmctx *ctx, int ncpu)
299 {
300 	mpcth_t			mpch;
301 	bus_entry_ptr		mpeb;
302 	io_apic_entry_ptr	mpei;
303 	proc_entry_ptr		mpep;
304 	mpfps_t			mpfp;
305 	int_entry_ptr		mpie;
306 	int			ioints, bus;
307 	char 			*curraddr;
308 	char 			*startaddr;
309 
310 	startaddr = paddr_guest2host(ctx, MPTABLE_BASE, MPTABLE_MAX_LENGTH);
311 	if (startaddr == NULL) {
312 		EPRINTLN("mptable requires mapped mem");
313 		return (ENOMEM);
314 	}
315 
316 	/*
317 	 * There is no way to advertise multiple PCI hierarchies via MPtable
318 	 * so require that there is no PCI hierarchy with a non-zero bus
319 	 * number.
320 	 */
321 	for (bus = 1; bus <= PCI_BUSMAX; bus++) {
322 		if (pci_bus_configured(bus)) {
323 			EPRINTLN("MPtable is incompatible with "
324 			    "multiple PCI hierarchies.");
325 			EPRINTLN("MPtable generation can be disabled "
326 			    "by passing the -Y option to bhyve(8).");
327 			return (EINVAL);
328 		}
329 	}
330 
331 	curraddr = startaddr;
332 	mpfp = (mpfps_t)curraddr;
333 	mpt_build_mpfp(mpfp, MPTABLE_BASE);
334 	curraddr += sizeof(*mpfp);
335 
336 	mpch = (mpcth_t)curraddr;
337 	mpt_build_mpch(mpch);
338 	curraddr += sizeof(*mpch);
339 
340 	mpep = (proc_entry_ptr)curraddr;
341 	mpt_build_proc_entries(mpep, ncpu);
342 	curraddr += sizeof(*mpep) * ncpu;
343 	mpch->entry_count += ncpu;
344 
345 	mpeb = (bus_entry_ptr) curraddr;
346 	mpt_build_bus_entries(mpeb);
347 	curraddr += sizeof(*mpeb) * MPE_NUM_BUSES;
348 	mpch->entry_count += MPE_NUM_BUSES;
349 
350 	mpei = (io_apic_entry_ptr)curraddr;
351 	mpt_build_ioapic_entries(mpei, 0);
352 	curraddr += sizeof(*mpei);
353 	mpch->entry_count++;
354 
355 	mpie = (int_entry_ptr) curraddr;
356 	ioints = mpt_count_ioint_entries();
357 	mpt_build_ioint_entries(mpie, 0);
358 	curraddr += sizeof(*mpie) * ioints;
359 	mpch->entry_count += ioints;
360 
361 	mpie = (int_entry_ptr)curraddr;
362 	mpt_build_localint_entries(mpie);
363 	curraddr += sizeof(*mpie) * MPEII_NUM_LOCAL_IRQ;
364 	mpch->entry_count += MPEII_NUM_LOCAL_IRQ;
365 
366 	if (oem_tbl_start) {
367 		mpch->oem_table_pointer = curraddr - startaddr + MPTABLE_BASE;
368 		mpch->oem_table_size = oem_tbl_size;
369 		memcpy(curraddr, oem_tbl_start, oem_tbl_size);
370 	}
371 
372 	mpch->base_table_length = curraddr - (char *)mpch;
373 	mpch->checksum = mpt_compute_checksum(mpch, mpch->base_table_length);
374 
375 	return (0);
376 }
377