1af610cabSElliott Mitchell /*-
2af610cabSElliott Mitchell * SPDX-License-Identifier: MIT OR GPL-2.0-only
3af610cabSElliott Mitchell *
42d795ab1SJulien Grall * Copyright © 2015 Julien Grall
5af610cabSElliott Mitchell * Copyright © 2013 Spectra Logic Corporation
6af610cabSElliott Mitchell * Copyright © 2018 John Baldwin/The FreeBSD Foundation
7af610cabSElliott Mitchell * Copyright © 2019 Roger Pau Monné/Citrix Systems R&D
8af610cabSElliott Mitchell * Copyright © 2021 Elliott Mitchell
9af610cabSElliott Mitchell *
10af610cabSElliott Mitchell * This file may be distributed separately from the Linux kernel, or
11af610cabSElliott Mitchell * incorporated into other software packages, subject to the following license:
12af610cabSElliott Mitchell *
13af610cabSElliott Mitchell * Permission is hereby granted, free of charge, to any person obtaining a copy
14af610cabSElliott Mitchell * of this source file (the "Software"), to deal in the Software without
15af610cabSElliott Mitchell * restriction, including without limitation the rights to use, copy, modify,
16af610cabSElliott Mitchell * merge, publish, distribute, sublicense, and/or sell copies of the Software,
17af610cabSElliott Mitchell * and to permit persons to whom the Software is furnished to do so, subject to
18af610cabSElliott Mitchell * the following conditions:
19af610cabSElliott Mitchell *
20af610cabSElliott Mitchell * The above copyright notice and this permission notice shall be included in
21af610cabSElliott Mitchell * all copies or substantial portions of the Software.
22af610cabSElliott Mitchell *
23af610cabSElliott Mitchell * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
24af610cabSElliott Mitchell * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
25af610cabSElliott Mitchell * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
26af610cabSElliott Mitchell * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
27af610cabSElliott Mitchell * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
28af610cabSElliott Mitchell * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
29af610cabSElliott Mitchell * IN THE SOFTWARE.
30af610cabSElliott Mitchell */
31af610cabSElliott Mitchell
32af610cabSElliott Mitchell #include <sys/param.h>
332d795ab1SJulien Grall #include <sys/systm.h>
34af610cabSElliott Mitchell #include <sys/bus.h>
352d795ab1SJulien Grall #include <sys/malloc.h>
36af610cabSElliott Mitchell #include <sys/kernel.h>
372d795ab1SJulien Grall #include <sys/limits.h>
382d795ab1SJulien Grall #include <sys/lock.h>
392d795ab1SJulien Grall #include <sys/mutex.h>
402d795ab1SJulien Grall #include <sys/interrupt.h>
41af610cabSElliott Mitchell #include <sys/pcpu.h>
42af610cabSElliott Mitchell #include <sys/proc.h>
43af610cabSElliott Mitchell #include <sys/smp.h>
44af610cabSElliott Mitchell #include <sys/stddef.h>
45af610cabSElliott Mitchell
46af610cabSElliott Mitchell #include <xen/xen-os.h>
47af610cabSElliott Mitchell #include <xen/xen_intr.h>
482d795ab1SJulien Grall #include <machine/xen/arch-intr.h>
49af610cabSElliott Mitchell
50af610cabSElliott Mitchell #include <x86/apicvar.h>
51af610cabSElliott Mitchell
52af610cabSElliott Mitchell /************************ Xen x86 interrupt interface ************************/
53af610cabSElliott Mitchell
54af610cabSElliott Mitchell /*
55af610cabSElliott Mitchell * Pointers to the interrupt counters
56af610cabSElliott Mitchell */
57af610cabSElliott Mitchell DPCPU_DEFINE_STATIC(u_long *, pintrcnt);
58af610cabSElliott Mitchell
59af610cabSElliott Mitchell static void
xen_intrcnt_init(void * dummy __unused)60af610cabSElliott Mitchell xen_intrcnt_init(void *dummy __unused)
61af610cabSElliott Mitchell {
62af610cabSElliott Mitchell unsigned int i;
63af610cabSElliott Mitchell
64af610cabSElliott Mitchell if (!xen_domain())
65af610cabSElliott Mitchell return;
66af610cabSElliott Mitchell
67af610cabSElliott Mitchell CPU_FOREACH(i) {
68af610cabSElliott Mitchell char buf[MAXCOMLEN + 1];
69af610cabSElliott Mitchell
70af610cabSElliott Mitchell snprintf(buf, sizeof(buf), "cpu%d:xen", i);
71af610cabSElliott Mitchell intrcnt_add(buf, DPCPU_ID_PTR(i, pintrcnt));
72af610cabSElliott Mitchell }
73af610cabSElliott Mitchell }
74af610cabSElliott Mitchell SYSINIT(xen_intrcnt_init, SI_SUB_INTR, SI_ORDER_MIDDLE, xen_intrcnt_init, NULL);
75af610cabSElliott Mitchell
76af610cabSElliott Mitchell /*
77af610cabSElliott Mitchell * Transition from assembly language, called from
78af610cabSElliott Mitchell * sys/{amd64/amd64|i386/i386}/apic_vector.S
79af610cabSElliott Mitchell */
80af610cabSElliott Mitchell extern void xen_arch_intr_handle_upcall(struct trapframe *);
81af610cabSElliott Mitchell void
xen_arch_intr_handle_upcall(struct trapframe * trap_frame)82af610cabSElliott Mitchell xen_arch_intr_handle_upcall(struct trapframe *trap_frame)
83af610cabSElliott Mitchell {
84af610cabSElliott Mitchell struct trapframe *old;
85af610cabSElliott Mitchell
86af610cabSElliott Mitchell /*
87af610cabSElliott Mitchell * Disable preemption in order to always check and fire events
88af610cabSElliott Mitchell * on the right vCPU
89af610cabSElliott Mitchell */
90af610cabSElliott Mitchell critical_enter();
91af610cabSElliott Mitchell
92af610cabSElliott Mitchell ++*DPCPU_GET(pintrcnt);
93af610cabSElliott Mitchell
94af610cabSElliott Mitchell ++curthread->td_intr_nesting_level;
95af610cabSElliott Mitchell old = curthread->td_intr_frame;
96af610cabSElliott Mitchell curthread->td_intr_frame = trap_frame;
97af610cabSElliott Mitchell
98af610cabSElliott Mitchell xen_intr_handle_upcall(NULL);
99af610cabSElliott Mitchell
100af610cabSElliott Mitchell curthread->td_intr_frame = old;
101af610cabSElliott Mitchell --curthread->td_intr_nesting_level;
102af610cabSElliott Mitchell
103af610cabSElliott Mitchell if (xen_evtchn_needs_ack)
104af610cabSElliott Mitchell lapic_eoi();
105af610cabSElliott Mitchell
106af610cabSElliott Mitchell critical_exit();
107af610cabSElliott Mitchell }
1082d795ab1SJulien Grall
1092d795ab1SJulien Grall /******************************** EVTCHN PIC *********************************/
1102d795ab1SJulien Grall
111*6699c22cSElliott Mitchell static MALLOC_DEFINE(M_XENINTR, "xen_intr", "Xen Interrupt Services");
112*6699c22cSElliott Mitchell
113*6699c22cSElliott Mitchell /*
114*6699c22cSElliott Mitchell * Lock for x86-related structures. Notably modifying
115*6699c22cSElliott Mitchell * xen_intr_auto_vector_count, and allocating interrupts require this lock be
116*6699c22cSElliott Mitchell * held.
117*6699c22cSElliott Mitchell */
118*6699c22cSElliott Mitchell static struct mtx xen_intr_x86_lock;
119*6699c22cSElliott Mitchell
120*6699c22cSElliott Mitchell static u_int first_evtchn_irq;
121*6699c22cSElliott Mitchell
122*6699c22cSElliott Mitchell static u_int xen_intr_auto_vector_count;
123*6699c22cSElliott Mitchell
124*6699c22cSElliott Mitchell /*
125*6699c22cSElliott Mitchell * list of released isrcs
126*6699c22cSElliott Mitchell * This is meant to overlay struct xenisrc, with only the xen_arch_isrc_t
127*6699c22cSElliott Mitchell * portion being preserved, everything else can be wiped.
128*6699c22cSElliott Mitchell */
129*6699c22cSElliott Mitchell struct avail_list {
130*6699c22cSElliott Mitchell xen_arch_isrc_t preserve;
131*6699c22cSElliott Mitchell SLIST_ENTRY(avail_list) free;
132*6699c22cSElliott Mitchell };
133*6699c22cSElliott Mitchell static SLIST_HEAD(free, avail_list) avail_list =
134*6699c22cSElliott Mitchell SLIST_HEAD_INITIALIZER(avail_list);
135*6699c22cSElliott Mitchell
136*6699c22cSElliott Mitchell void
xen_intr_alloc_irqs(void)137*6699c22cSElliott Mitchell xen_intr_alloc_irqs(void)
138*6699c22cSElliott Mitchell {
139*6699c22cSElliott Mitchell
140*6699c22cSElliott Mitchell if (num_io_irqs > UINT_MAX - NR_EVENT_CHANNELS)
141*6699c22cSElliott Mitchell panic("IRQ allocation overflow (num_msi_irqs too high?)");
142*6699c22cSElliott Mitchell first_evtchn_irq = num_io_irqs;
143*6699c22cSElliott Mitchell num_io_irqs += NR_EVENT_CHANNELS;
144*6699c22cSElliott Mitchell }
145*6699c22cSElliott Mitchell
1462d795ab1SJulien Grall static void
xen_intr_pic_enable_source(struct intsrc * isrc)1472d795ab1SJulien Grall xen_intr_pic_enable_source(struct intsrc *isrc)
1482d795ab1SJulien Grall {
1492d795ab1SJulien Grall
1502d795ab1SJulien Grall _Static_assert(offsetof(struct xenisrc, xi_arch.intsrc) == 0,
1512d795ab1SJulien Grall "xi_arch MUST be at top of xenisrc for x86");
1522d795ab1SJulien Grall xen_intr_enable_source((struct xenisrc *)isrc);
1532d795ab1SJulien Grall }
1542d795ab1SJulien Grall
1552d795ab1SJulien Grall /*
1562d795ab1SJulien Grall * Perform any necessary end-of-interrupt acknowledgements.
1572d795ab1SJulien Grall *
1582d795ab1SJulien Grall * \param isrc The interrupt source to EOI.
1592d795ab1SJulien Grall */
1602d795ab1SJulien Grall static void
xen_intr_pic_disable_source(struct intsrc * isrc,int eoi)1612d795ab1SJulien Grall xen_intr_pic_disable_source(struct intsrc *isrc, int eoi)
1622d795ab1SJulien Grall {
1632d795ab1SJulien Grall
1642d795ab1SJulien Grall _Static_assert(offsetof(struct xenisrc, xi_arch.intsrc) == 0,
1652d795ab1SJulien Grall "xi_arch MUST be at top of xenisrc for x86");
1662d795ab1SJulien Grall xen_intr_disable_source((struct xenisrc *)isrc);
1672d795ab1SJulien Grall }
1682d795ab1SJulien Grall
1692d795ab1SJulien Grall static void
xen_intr_pic_eoi_source(struct intsrc * isrc)1702d795ab1SJulien Grall xen_intr_pic_eoi_source(struct intsrc *isrc)
1712d795ab1SJulien Grall {
1722d795ab1SJulien Grall
1732d795ab1SJulien Grall /* Nothing to do on end-of-interrupt */
1742d795ab1SJulien Grall }
1752d795ab1SJulien Grall
1762d795ab1SJulien Grall static void
xen_intr_pic_enable_intr(struct intsrc * isrc)1772d795ab1SJulien Grall xen_intr_pic_enable_intr(struct intsrc *isrc)
1782d795ab1SJulien Grall {
1792d795ab1SJulien Grall
1802d795ab1SJulien Grall _Static_assert(offsetof(struct xenisrc, xi_arch.intsrc) == 0,
1812d795ab1SJulien Grall "xi_arch MUST be at top of xenisrc for x86");
1822d795ab1SJulien Grall xen_intr_enable_intr((struct xenisrc *)isrc);
1832d795ab1SJulien Grall }
1842d795ab1SJulien Grall
1852d795ab1SJulien Grall static void
xen_intr_pic_disable_intr(struct intsrc * isrc)1862d795ab1SJulien Grall xen_intr_pic_disable_intr(struct intsrc *isrc)
1872d795ab1SJulien Grall {
1882d795ab1SJulien Grall
1892d795ab1SJulien Grall _Static_assert(offsetof(struct xenisrc, xi_arch.intsrc) == 0,
1902d795ab1SJulien Grall "xi_arch MUST be at top of xenisrc for x86");
1912d795ab1SJulien Grall xen_intr_disable_intr((struct xenisrc *)isrc);
1922d795ab1SJulien Grall }
1932d795ab1SJulien Grall
1942d795ab1SJulien Grall /**
1952d795ab1SJulien Grall * Determine the global interrupt vector number for
1962d795ab1SJulien Grall * a Xen interrupt source.
1972d795ab1SJulien Grall *
1982d795ab1SJulien Grall * \param isrc The interrupt source to query.
1992d795ab1SJulien Grall *
2002d795ab1SJulien Grall * \return The vector number corresponding to the given interrupt source.
2012d795ab1SJulien Grall */
2022d795ab1SJulien Grall static int
xen_intr_pic_vector(struct intsrc * isrc)2032d795ab1SJulien Grall xen_intr_pic_vector(struct intsrc *isrc)
2042d795ab1SJulien Grall {
2052d795ab1SJulien Grall
2062d795ab1SJulien Grall _Static_assert(offsetof(struct xenisrc, xi_arch.intsrc) == 0,
2072d795ab1SJulien Grall "xi_arch MUST be at top of xenisrc for x86");
2082d795ab1SJulien Grall
2092d795ab1SJulien Grall return (((struct xenisrc *)isrc)->xi_arch.vector);
2102d795ab1SJulien Grall }
2112d795ab1SJulien Grall
2122d795ab1SJulien Grall /**
2132d795ab1SJulien Grall * Determine whether or not interrupt events are pending on the
2142d795ab1SJulien Grall * the given interrupt source.
2152d795ab1SJulien Grall *
2162d795ab1SJulien Grall * \param isrc The interrupt source to query.
2172d795ab1SJulien Grall *
2182d795ab1SJulien Grall * \returns 0 if no events are pending, otherwise non-zero.
2192d795ab1SJulien Grall */
2202d795ab1SJulien Grall static int
xen_intr_pic_source_pending(struct intsrc * isrc)2212d795ab1SJulien Grall xen_intr_pic_source_pending(struct intsrc *isrc)
2222d795ab1SJulien Grall {
2232d795ab1SJulien Grall /*
2242d795ab1SJulien Grall * EventChannels are edge triggered and never masked.
2252d795ab1SJulien Grall * There can be no pending events.
2262d795ab1SJulien Grall */
2272d795ab1SJulien Grall return (0);
2282d795ab1SJulien Grall }
2292d795ab1SJulien Grall
2302d795ab1SJulien Grall /**
2312d795ab1SJulien Grall * Prepare this PIC for system suspension.
2322d795ab1SJulien Grall */
2332d795ab1SJulien Grall static void
xen_intr_pic_suspend(struct pic * pic)2342d795ab1SJulien Grall xen_intr_pic_suspend(struct pic *pic)
2352d795ab1SJulien Grall {
2362d795ab1SJulien Grall
2372d795ab1SJulien Grall /* Nothing to do on suspend */
2382d795ab1SJulien Grall }
2392d795ab1SJulien Grall
2402d795ab1SJulien Grall static void
xen_intr_pic_resume(struct pic * pic,bool suspend_cancelled)2412d795ab1SJulien Grall xen_intr_pic_resume(struct pic *pic, bool suspend_cancelled)
2422d795ab1SJulien Grall {
2432d795ab1SJulien Grall
2442d795ab1SJulien Grall if (!suspend_cancelled)
2452d795ab1SJulien Grall xen_intr_resume();
2462d795ab1SJulien Grall }
2472d795ab1SJulien Grall
2482d795ab1SJulien Grall /**
2492d795ab1SJulien Grall * Perform configuration of an interrupt source.
2502d795ab1SJulien Grall *
2512d795ab1SJulien Grall * \param isrc The interrupt source to configure.
2522d795ab1SJulien Grall * \param trig Edge or level.
2532d795ab1SJulien Grall * \param pol Active high or low.
2542d795ab1SJulien Grall *
2552d795ab1SJulien Grall * \returns 0 if no events are pending, otherwise non-zero.
2562d795ab1SJulien Grall */
2572d795ab1SJulien Grall static int
xen_intr_pic_config_intr(struct intsrc * isrc,enum intr_trigger trig,enum intr_polarity pol)2582d795ab1SJulien Grall xen_intr_pic_config_intr(struct intsrc *isrc, enum intr_trigger trig,
2592d795ab1SJulien Grall enum intr_polarity pol)
2602d795ab1SJulien Grall {
2612d795ab1SJulien Grall /* Configuration is only possible via the evtchn apis. */
2622d795ab1SJulien Grall return (ENODEV);
2632d795ab1SJulien Grall }
2642d795ab1SJulien Grall
2652d795ab1SJulien Grall
2662d795ab1SJulien Grall static int
xen_intr_pic_assign_cpu(struct intsrc * isrc,u_int apic_id)2672d795ab1SJulien Grall xen_intr_pic_assign_cpu(struct intsrc *isrc, u_int apic_id)
2682d795ab1SJulien Grall {
2692d795ab1SJulien Grall
2702d795ab1SJulien Grall _Static_assert(offsetof(struct xenisrc, xi_arch.intsrc) == 0,
2712d795ab1SJulien Grall "xi_arch MUST be at top of xenisrc for x86");
2722d795ab1SJulien Grall return (xen_intr_assign_cpu((struct xenisrc *)isrc,
2732d795ab1SJulien Grall apic_cpuid(apic_id)));
2742d795ab1SJulien Grall }
2752d795ab1SJulien Grall
2762d795ab1SJulien Grall /**
2772d795ab1SJulien Grall * PIC interface for all event channel port types except physical IRQs.
2782d795ab1SJulien Grall */
279*6699c22cSElliott Mitchell static struct pic xen_intr_pic = {
2802d795ab1SJulien Grall .pic_enable_source = xen_intr_pic_enable_source,
2812d795ab1SJulien Grall .pic_disable_source = xen_intr_pic_disable_source,
2822d795ab1SJulien Grall .pic_eoi_source = xen_intr_pic_eoi_source,
2832d795ab1SJulien Grall .pic_enable_intr = xen_intr_pic_enable_intr,
2842d795ab1SJulien Grall .pic_disable_intr = xen_intr_pic_disable_intr,
2852d795ab1SJulien Grall .pic_vector = xen_intr_pic_vector,
2862d795ab1SJulien Grall .pic_source_pending = xen_intr_pic_source_pending,
2872d795ab1SJulien Grall .pic_suspend = xen_intr_pic_suspend,
2882d795ab1SJulien Grall .pic_resume = xen_intr_pic_resume,
2892d795ab1SJulien Grall .pic_config_intr = xen_intr_pic_config_intr,
2902d795ab1SJulien Grall .pic_assign_cpu = xen_intr_pic_assign_cpu,
2912d795ab1SJulien Grall };
2922d795ab1SJulien Grall
2932d795ab1SJulien Grall /******************************* ARCH wrappers *******************************/
2942d795ab1SJulien Grall
2952d795ab1SJulien Grall void
xen_arch_intr_init(void)2962d795ab1SJulien Grall xen_arch_intr_init(void)
2972d795ab1SJulien Grall {
2982d795ab1SJulien Grall int error;
2992d795ab1SJulien Grall
300*6699c22cSElliott Mitchell mtx_init(&xen_intr_x86_lock, "xen-x86-table-lock", NULL, MTX_DEF);
301*6699c22cSElliott Mitchell
3022d795ab1SJulien Grall error = intr_register_pic(&xen_intr_pic);
3032d795ab1SJulien Grall if (error != 0)
3042d795ab1SJulien Grall panic("%s(): failed registering Xen/x86 PIC, error=%d\n",
3052d795ab1SJulien Grall __func__, error);
3062d795ab1SJulien Grall }
307*6699c22cSElliott Mitchell
308*6699c22cSElliott Mitchell /**
309*6699c22cSElliott Mitchell * Allocate a Xen interrupt source object.
310*6699c22cSElliott Mitchell *
311*6699c22cSElliott Mitchell * \param type The type of interrupt source to create.
312*6699c22cSElliott Mitchell *
313*6699c22cSElliott Mitchell * \return A pointer to a newly allocated Xen interrupt source
314*6699c22cSElliott Mitchell * object or NULL.
315*6699c22cSElliott Mitchell */
316*6699c22cSElliott Mitchell struct xenisrc *
xen_arch_intr_alloc(void)317*6699c22cSElliott Mitchell xen_arch_intr_alloc(void)
318*6699c22cSElliott Mitchell {
319*6699c22cSElliott Mitchell static int warned;
320*6699c22cSElliott Mitchell struct xenisrc *isrc;
321*6699c22cSElliott Mitchell unsigned int vector;
322*6699c22cSElliott Mitchell int error;
323*6699c22cSElliott Mitchell
324*6699c22cSElliott Mitchell mtx_lock(&xen_intr_x86_lock);
325*6699c22cSElliott Mitchell isrc = (struct xenisrc *)SLIST_FIRST(&avail_list);
326*6699c22cSElliott Mitchell if (isrc != NULL) {
327*6699c22cSElliott Mitchell SLIST_REMOVE_HEAD(&avail_list, free);
328*6699c22cSElliott Mitchell mtx_unlock(&xen_intr_x86_lock);
329*6699c22cSElliott Mitchell
330*6699c22cSElliott Mitchell KASSERT(isrc->xi_arch.intsrc.is_pic == &xen_intr_pic,
331*6699c22cSElliott Mitchell ("interrupt not owned by Xen code?"));
332*6699c22cSElliott Mitchell
333*6699c22cSElliott Mitchell KASSERT(isrc->xi_arch.intsrc.is_handlers == 0,
334*6699c22cSElliott Mitchell ("Free evtchn still has handlers"));
335*6699c22cSElliott Mitchell
336*6699c22cSElliott Mitchell return (isrc);
337*6699c22cSElliott Mitchell }
338*6699c22cSElliott Mitchell
339*6699c22cSElliott Mitchell if (xen_intr_auto_vector_count >= NR_EVENT_CHANNELS) {
340*6699c22cSElliott Mitchell if (!warned) {
341*6699c22cSElliott Mitchell warned = 1;
342*6699c22cSElliott Mitchell printf("%s: Xen interrupts exhausted.\n", __func__);
343*6699c22cSElliott Mitchell }
344*6699c22cSElliott Mitchell mtx_unlock(&xen_intr_x86_lock);
345*6699c22cSElliott Mitchell return (NULL);
346*6699c22cSElliott Mitchell }
347*6699c22cSElliott Mitchell
348*6699c22cSElliott Mitchell vector = first_evtchn_irq + xen_intr_auto_vector_count;
349*6699c22cSElliott Mitchell xen_intr_auto_vector_count++;
350*6699c22cSElliott Mitchell
351*6699c22cSElliott Mitchell KASSERT((intr_lookup_source(vector) == NULL),
352*6699c22cSElliott Mitchell ("Trying to use an already allocated vector"));
353*6699c22cSElliott Mitchell
354*6699c22cSElliott Mitchell mtx_unlock(&xen_intr_x86_lock);
355*6699c22cSElliott Mitchell isrc = malloc(sizeof(*isrc), M_XENINTR, M_WAITOK | M_ZERO);
356*6699c22cSElliott Mitchell isrc->xi_arch.intsrc.is_pic = &xen_intr_pic;
357*6699c22cSElliott Mitchell isrc->xi_arch.vector = vector;
358*6699c22cSElliott Mitchell error = intr_register_source(&isrc->xi_arch.intsrc);
359*6699c22cSElliott Mitchell if (error != 0)
360*6699c22cSElliott Mitchell panic("%s(): failed registering interrupt %u, error=%d\n",
361*6699c22cSElliott Mitchell __func__, vector, error);
362*6699c22cSElliott Mitchell
363*6699c22cSElliott Mitchell return (isrc);
364*6699c22cSElliott Mitchell }
365*6699c22cSElliott Mitchell
366*6699c22cSElliott Mitchell void
xen_arch_intr_release(struct xenisrc * isrc)367*6699c22cSElliott Mitchell xen_arch_intr_release(struct xenisrc *isrc)
368*6699c22cSElliott Mitchell {
369*6699c22cSElliott Mitchell
370*6699c22cSElliott Mitchell KASSERT(isrc->xi_arch.intsrc.is_handlers == 0,
371*6699c22cSElliott Mitchell ("Release called, but xenisrc still in use"));
372*6699c22cSElliott Mitchell
373*6699c22cSElliott Mitchell _Static_assert(sizeof(struct xenisrc) >= sizeof(struct avail_list),
374*6699c22cSElliott Mitchell "unused structure MUST be no larger than in-use structure");
375*6699c22cSElliott Mitchell _Static_assert(offsetof(struct xenisrc, xi_arch) ==
376*6699c22cSElliott Mitchell offsetof(struct avail_list, preserve),
377*6699c22cSElliott Mitchell "unused structure does not properly overlay in-use structure");
378*6699c22cSElliott Mitchell
379*6699c22cSElliott Mitchell mtx_lock(&xen_intr_x86_lock);
380*6699c22cSElliott Mitchell SLIST_INSERT_HEAD(&avail_list, (struct avail_list *)isrc, free);
381*6699c22cSElliott Mitchell mtx_unlock(&xen_intr_x86_lock);
382*6699c22cSElliott Mitchell }
383