1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 1998-2003 Poul-Henning Kamp 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 #include "opt_clock.h" 33 34 #include <sys/param.h> 35 #include <sys/bus.h> 36 #include <sys/cpu.h> 37 #include <sys/eventhandler.h> 38 #include <sys/limits.h> 39 #include <sys/malloc.h> 40 #include <sys/systm.h> 41 #include <sys/sysctl.h> 42 #include <sys/time.h> 43 #include <sys/timetc.h> 44 #include <sys/kernel.h> 45 #include <sys/power.h> 46 #include <sys/smp.h> 47 #include <sys/vdso.h> 48 #include <machine/clock.h> 49 #include <machine/cputypes.h> 50 #include <machine/md_var.h> 51 #include <machine/specialreg.h> 52 #include <x86/vmware.h> 53 #include <dev/acpica/acpi_hpet.h> 54 #include <contrib/dev/acpica/include/acpi.h> 55 56 #include "cpufreq_if.h" 57 58 uint64_t tsc_freq; 59 int tsc_is_invariant; 60 int tsc_perf_stat; 61 62 static eventhandler_tag tsc_levels_tag, tsc_pre_tag, tsc_post_tag; 63 64 SYSCTL_INT(_kern_timecounter, OID_AUTO, invariant_tsc, CTLFLAG_RDTUN, 65 &tsc_is_invariant, 0, "Indicates whether the TSC is P-state invariant"); 66 67 #ifdef SMP 68 int smp_tsc; 69 SYSCTL_INT(_kern_timecounter, OID_AUTO, smp_tsc, CTLFLAG_RDTUN, &smp_tsc, 0, 70 "Indicates whether the TSC is safe to use in SMP mode"); 71 72 int smp_tsc_adjust = 0; 73 SYSCTL_INT(_kern_timecounter, OID_AUTO, smp_tsc_adjust, CTLFLAG_RDTUN, 74 &smp_tsc_adjust, 0, "Try to adjust TSC on APs to match BSP"); 75 #endif 76 77 static int tsc_shift = 1; 78 SYSCTL_INT(_kern_timecounter, OID_AUTO, tsc_shift, CTLFLAG_RDTUN, 79 &tsc_shift, 0, "Shift to pre-apply for the maximum TSC frequency"); 80 81 static int tsc_disabled; 82 SYSCTL_INT(_machdep, OID_AUTO, disable_tsc, CTLFLAG_RDTUN, &tsc_disabled, 0, 83 "Disable x86 Time Stamp Counter"); 84 85 static int tsc_skip_calibration; 86 SYSCTL_INT(_machdep, OID_AUTO, disable_tsc_calibration, CTLFLAG_RDTUN | 87 CTLFLAG_NOFETCH, &tsc_skip_calibration, 0, 88 "Disable TSC frequency calibration"); 89 90 static void tsc_freq_changed(void *arg, const struct cf_level *level, 91 int status); 92 static void tsc_freq_changing(void *arg, const struct cf_level *level, 93 int *status); 94 static unsigned tsc_get_timecount(struct timecounter *tc); 95 static inline unsigned tsc_get_timecount_low(struct timecounter *tc); 96 static unsigned tsc_get_timecount_lfence(struct timecounter *tc); 97 static unsigned tsc_get_timecount_low_lfence(struct timecounter *tc); 98 static unsigned tsc_get_timecount_mfence(struct timecounter *tc); 99 static unsigned tsc_get_timecount_low_mfence(struct timecounter *tc); 100 static void tsc_levels_changed(void *arg, int unit); 101 static uint32_t x86_tsc_vdso_timehands(struct vdso_timehands *vdso_th, 102 struct timecounter *tc); 103 #ifdef COMPAT_FREEBSD32 104 static uint32_t x86_tsc_vdso_timehands32(struct vdso_timehands32 *vdso_th32, 105 struct timecounter *tc); 106 #endif 107 108 static struct timecounter tsc_timecounter = { 109 .tc_get_timecount = tsc_get_timecount, 110 .tc_counter_mask = ~0u, 111 .tc_name = "TSC", 112 .tc_quality = 800, /* adjusted in code */ 113 .tc_fill_vdso_timehands = x86_tsc_vdso_timehands, 114 #ifdef COMPAT_FREEBSD32 115 .tc_fill_vdso_timehands32 = x86_tsc_vdso_timehands32, 116 #endif 117 }; 118 119 static void 120 tsc_freq_vmware(void) 121 { 122 u_int regs[4]; 123 124 if (hv_high >= 0x40000010) { 125 do_cpuid(0x40000010, regs); 126 tsc_freq = regs[0] * 1000; 127 } else { 128 vmware_hvcall(VMW_HVCMD_GETHZ, regs); 129 if (regs[1] != UINT_MAX) 130 tsc_freq = regs[0] | ((uint64_t)regs[1] << 32); 131 } 132 tsc_is_invariant = 1; 133 } 134 135 /* 136 * Calculate TSC frequency using information from the CPUID leaf 0x15 137 * 'Time Stamp Counter and Nominal Core Crystal Clock'. If leaf 0x15 138 * is not functional, as it is on Skylake/Kabylake, try 0x16 'Processor 139 * Frequency Information'. Leaf 0x16 is described in the SDM as 140 * informational only, but if 0x15 did not work, and TSC calibration 141 * is disabled, it is the best we can get at all. It should still be 142 * an improvement over the parsing of the CPU model name in 143 * tsc_freq_intel(), when available. 144 */ 145 static bool 146 tsc_freq_cpuid(uint64_t *res) 147 { 148 u_int regs[4]; 149 150 if (cpu_high < 0x15) 151 return (false); 152 do_cpuid(0x15, regs); 153 if (regs[0] != 0 && regs[1] != 0 && regs[2] != 0) { 154 *res = (uint64_t)regs[2] * regs[1] / regs[0]; 155 return (true); 156 } 157 158 if (cpu_high < 0x16) 159 return (false); 160 do_cpuid(0x16, regs); 161 if (regs[0] != 0) { 162 *res = (uint64_t)regs[0] * 1000000; 163 return (true); 164 } 165 166 return (false); 167 } 168 169 static void 170 tsc_freq_intel(void) 171 { 172 char brand[48]; 173 u_int regs[4]; 174 uint64_t freq; 175 char *p; 176 u_int i; 177 178 /* 179 * Intel Processor Identification and the CPUID Instruction 180 * Application Note 485. 181 * http://www.intel.com/assets/pdf/appnote/241618.pdf 182 */ 183 if (cpu_exthigh >= 0x80000004) { 184 p = brand; 185 for (i = 0x80000002; i < 0x80000005; i++) { 186 do_cpuid(i, regs); 187 memcpy(p, regs, sizeof(regs)); 188 p += sizeof(regs); 189 } 190 p = NULL; 191 for (i = 0; i < sizeof(brand) - 1; i++) 192 if (brand[i] == 'H' && brand[i + 1] == 'z') 193 p = brand + i; 194 if (p != NULL) { 195 p -= 5; 196 switch (p[4]) { 197 case 'M': 198 i = 1; 199 break; 200 case 'G': 201 i = 1000; 202 break; 203 case 'T': 204 i = 1000000; 205 break; 206 default: 207 return; 208 } 209 #define C2D(c) ((c) - '0') 210 if (p[1] == '.') { 211 freq = C2D(p[0]) * 1000; 212 freq += C2D(p[2]) * 100; 213 freq += C2D(p[3]) * 10; 214 freq *= i * 1000; 215 } else { 216 freq = C2D(p[0]) * 1000; 217 freq += C2D(p[1]) * 100; 218 freq += C2D(p[2]) * 10; 219 freq += C2D(p[3]); 220 freq *= i * 1000000; 221 } 222 #undef C2D 223 tsc_freq = freq; 224 } 225 } 226 } 227 228 static void 229 probe_tsc_freq(void) 230 { 231 uint64_t tmp_freq, tsc1, tsc2; 232 int no_cpuid_override; 233 uint16_t bootflags; 234 235 if (cpu_power_ecx & CPUID_PERF_STAT) { 236 /* 237 * XXX Some emulators expose host CPUID without actual support 238 * for these MSRs. We must test whether they really work. 239 */ 240 wrmsr(MSR_MPERF, 0); 241 wrmsr(MSR_APERF, 0); 242 DELAY(10); 243 if (rdmsr(MSR_MPERF) > 0 && rdmsr(MSR_APERF) > 0) 244 tsc_perf_stat = 1; 245 } 246 247 if (vm_guest == VM_GUEST_VMWARE) { 248 tsc_freq_vmware(); 249 return; 250 } 251 252 switch (cpu_vendor_id) { 253 case CPU_VENDOR_AMD: 254 case CPU_VENDOR_HYGON: 255 if ((amd_pminfo & AMDPM_TSC_INVARIANT) != 0 || 256 (vm_guest == VM_GUEST_NO && 257 CPUID_TO_FAMILY(cpu_id) >= 0x10)) 258 tsc_is_invariant = 1; 259 if (cpu_feature & CPUID_SSE2) { 260 tsc_timecounter.tc_get_timecount = 261 tsc_get_timecount_mfence; 262 } 263 break; 264 case CPU_VENDOR_INTEL: 265 if ((amd_pminfo & AMDPM_TSC_INVARIANT) != 0 || 266 (vm_guest == VM_GUEST_NO && 267 ((CPUID_TO_FAMILY(cpu_id) == 0x6 && 268 CPUID_TO_MODEL(cpu_id) >= 0xe) || 269 (CPUID_TO_FAMILY(cpu_id) == 0xf && 270 CPUID_TO_MODEL(cpu_id) >= 0x3)))) 271 tsc_is_invariant = 1; 272 if (cpu_feature & CPUID_SSE2) { 273 tsc_timecounter.tc_get_timecount = 274 tsc_get_timecount_lfence; 275 } 276 break; 277 case CPU_VENDOR_CENTAUR: 278 if (vm_guest == VM_GUEST_NO && 279 CPUID_TO_FAMILY(cpu_id) == 0x6 && 280 CPUID_TO_MODEL(cpu_id) >= 0xf && 281 (rdmsr(0x1203) & 0x100000000ULL) == 0) 282 tsc_is_invariant = 1; 283 if (cpu_feature & CPUID_SSE2) { 284 tsc_timecounter.tc_get_timecount = 285 tsc_get_timecount_lfence; 286 } 287 break; 288 } 289 290 if (!TUNABLE_INT_FETCH("machdep.disable_tsc_calibration", 291 &tsc_skip_calibration)) { 292 /* 293 * User did not give the order about calibration. 294 * If he did, we do not try to guess. 295 * 296 * Otherwise, if ACPI FADT reports that the platform 297 * is legacy-free and CPUID provides TSC frequency, 298 * use it. The calibration could fail anyway since 299 * ISA timer can be absent or power gated. 300 */ 301 if (acpi_get_fadt_bootflags(&bootflags) && 302 (bootflags & ACPI_FADT_LEGACY_DEVICES) == 0 && 303 tsc_freq_cpuid(&tmp_freq)) { 304 printf("Skipping TSC calibration since no legacy " 305 "devices reported by FADT and CPUID works\n"); 306 tsc_skip_calibration = 1; 307 } 308 } 309 if (tsc_skip_calibration) { 310 if (tsc_freq_cpuid(&tmp_freq)) 311 tsc_freq = tmp_freq; 312 else if (cpu_vendor_id == CPU_VENDOR_INTEL) 313 tsc_freq_intel(); 314 } else { 315 if (bootverbose) 316 printf("Calibrating TSC clock ... "); 317 tsc1 = rdtsc(); 318 DELAY(1000000); 319 tsc2 = rdtsc(); 320 tsc_freq = tsc2 - tsc1; 321 322 /* 323 * If the difference between calibrated frequency and 324 * the frequency reported by CPUID 0x15/0x16 leafs 325 * differ significantly, this probably means that 326 * calibration is bogus. It happens on machines 327 * without 8254 timer and with BIOS not properly 328 * reporting it in FADT boot flags. 329 */ 330 if (tsc_freq_cpuid(&tmp_freq) && qabs(tsc_freq - tmp_freq) > 331 uqmin(tsc_freq, tmp_freq)) { 332 no_cpuid_override = 0; 333 TUNABLE_INT_FETCH("machdep.disable_tsc_cpuid_override", 334 &no_cpuid_override); 335 if (!no_cpuid_override) { 336 if (bootverbose) { 337 printf( 338 "TSC clock: calibration freq %ju Hz, CPUID freq %ju Hz%s\n", 339 (uintmax_t)tsc_freq, 340 (uintmax_t)tmp_freq, 341 no_cpuid_override ? "" : 342 ", doing CPUID override"); 343 } 344 tsc_freq = tmp_freq; 345 } 346 } 347 } 348 if (bootverbose) 349 printf("TSC clock: %ju Hz\n", (intmax_t)tsc_freq); 350 } 351 352 void 353 init_TSC(void) 354 { 355 356 if ((cpu_feature & CPUID_TSC) == 0 || tsc_disabled) 357 return; 358 359 #ifdef __i386__ 360 /* The TSC is known to be broken on certain CPUs. */ 361 switch (cpu_vendor_id) { 362 case CPU_VENDOR_AMD: 363 switch (cpu_id & 0xFF0) { 364 case 0x500: 365 /* K5 Model 0 */ 366 return; 367 } 368 break; 369 case CPU_VENDOR_CENTAUR: 370 switch (cpu_id & 0xff0) { 371 case 0x540: 372 /* 373 * http://www.centtech.com/c6_data_sheet.pdf 374 * 375 * I-12 RDTSC may return incoherent values in EDX:EAX 376 * I-13 RDTSC hangs when certain event counters are used 377 */ 378 return; 379 } 380 break; 381 case CPU_VENDOR_NSC: 382 switch (cpu_id & 0xff0) { 383 case 0x540: 384 if ((cpu_id & CPUID_STEPPING) == 0) 385 return; 386 break; 387 } 388 break; 389 } 390 #endif 391 392 probe_tsc_freq(); 393 394 /* 395 * Inform CPU accounting about our boot-time clock rate. This will 396 * be updated if someone loads a cpufreq driver after boot that 397 * discovers a new max frequency. 398 */ 399 if (tsc_freq != 0) 400 set_cputicker(rdtsc, tsc_freq, !tsc_is_invariant); 401 402 if (tsc_is_invariant) 403 return; 404 405 /* Register to find out about changes in CPU frequency. */ 406 tsc_pre_tag = EVENTHANDLER_REGISTER(cpufreq_pre_change, 407 tsc_freq_changing, NULL, EVENTHANDLER_PRI_FIRST); 408 tsc_post_tag = EVENTHANDLER_REGISTER(cpufreq_post_change, 409 tsc_freq_changed, NULL, EVENTHANDLER_PRI_FIRST); 410 tsc_levels_tag = EVENTHANDLER_REGISTER(cpufreq_levels_changed, 411 tsc_levels_changed, NULL, EVENTHANDLER_PRI_ANY); 412 } 413 414 #ifdef SMP 415 416 /* 417 * RDTSC is not a serializing instruction, and does not drain 418 * instruction stream, so we need to drain the stream before executing 419 * it. It could be fixed by use of RDTSCP, except the instruction is 420 * not available everywhere. 421 * 422 * Use CPUID for draining in the boot-time SMP constistency test. The 423 * timecounters use MFENCE for AMD CPUs, and LFENCE for others (Intel 424 * and VIA) when SSE2 is present, and nothing on older machines which 425 * also do not issue RDTSC prematurely. There, testing for SSE2 and 426 * vendor is too cumbersome, and we learn about TSC presence from CPUID. 427 * 428 * Do not use do_cpuid(), since we do not need CPUID results, which 429 * have to be written into memory with do_cpuid(). 430 */ 431 #define TSC_READ(x) \ 432 static void \ 433 tsc_read_##x(void *arg) \ 434 { \ 435 uint64_t *tsc = arg; \ 436 u_int cpu = PCPU_GET(cpuid); \ 437 \ 438 __asm __volatile("cpuid" : : : "eax", "ebx", "ecx", "edx"); \ 439 tsc[cpu * 3 + x] = rdtsc(); \ 440 } 441 TSC_READ(0) 442 TSC_READ(1) 443 TSC_READ(2) 444 #undef TSC_READ 445 446 #define N 1000 447 448 static void 449 comp_smp_tsc(void *arg) 450 { 451 uint64_t *tsc; 452 int64_t d1, d2; 453 u_int cpu = PCPU_GET(cpuid); 454 u_int i, j, size; 455 456 size = (mp_maxid + 1) * 3; 457 for (i = 0, tsc = arg; i < N; i++, tsc += size) 458 CPU_FOREACH(j) { 459 if (j == cpu) 460 continue; 461 d1 = tsc[cpu * 3 + 1] - tsc[j * 3]; 462 d2 = tsc[cpu * 3 + 2] - tsc[j * 3 + 1]; 463 if (d1 <= 0 || d2 <= 0) { 464 smp_tsc = 0; 465 return; 466 } 467 } 468 } 469 470 static void 471 adj_smp_tsc(void *arg) 472 { 473 uint64_t *tsc; 474 int64_t d, min, max; 475 u_int cpu = PCPU_GET(cpuid); 476 u_int first, i, size; 477 478 first = CPU_FIRST(); 479 if (cpu == first) 480 return; 481 min = INT64_MIN; 482 max = INT64_MAX; 483 size = (mp_maxid + 1) * 3; 484 for (i = 0, tsc = arg; i < N; i++, tsc += size) { 485 d = tsc[first * 3] - tsc[cpu * 3 + 1]; 486 if (d > min) 487 min = d; 488 d = tsc[first * 3 + 1] - tsc[cpu * 3 + 2]; 489 if (d > min) 490 min = d; 491 d = tsc[first * 3 + 1] - tsc[cpu * 3]; 492 if (d < max) 493 max = d; 494 d = tsc[first * 3 + 2] - tsc[cpu * 3 + 1]; 495 if (d < max) 496 max = d; 497 } 498 if (min > max) 499 return; 500 d = min / 2 + max / 2; 501 __asm __volatile ( 502 "movl $0x10, %%ecx\n\t" 503 "rdmsr\n\t" 504 "addl %%edi, %%eax\n\t" 505 "adcl %%esi, %%edx\n\t" 506 "wrmsr\n" 507 : /* No output */ 508 : "D" ((uint32_t)d), "S" ((uint32_t)(d >> 32)) 509 : "ax", "cx", "dx", "cc" 510 ); 511 } 512 513 static int 514 test_tsc(int adj_max_count) 515 { 516 uint64_t *data, *tsc; 517 u_int i, size, adj; 518 519 if ((!smp_tsc && !tsc_is_invariant) || vm_guest) 520 return (-100); 521 size = (mp_maxid + 1) * 3; 522 data = malloc(sizeof(*data) * size * N, M_TEMP, M_WAITOK); 523 adj = 0; 524 retry: 525 for (i = 0, tsc = data; i < N; i++, tsc += size) 526 smp_rendezvous(tsc_read_0, tsc_read_1, tsc_read_2, tsc); 527 smp_tsc = 1; /* XXX */ 528 smp_rendezvous(smp_no_rendezvous_barrier, comp_smp_tsc, 529 smp_no_rendezvous_barrier, data); 530 if (!smp_tsc && adj < adj_max_count) { 531 adj++; 532 smp_rendezvous(smp_no_rendezvous_barrier, adj_smp_tsc, 533 smp_no_rendezvous_barrier, data); 534 goto retry; 535 } 536 free(data, M_TEMP); 537 if (bootverbose) 538 printf("SMP: %sed TSC synchronization test%s\n", 539 smp_tsc ? "pass" : "fail", 540 adj > 0 ? " after adjustment" : ""); 541 if (smp_tsc && tsc_is_invariant) { 542 switch (cpu_vendor_id) { 543 case CPU_VENDOR_AMD: 544 case CPU_VENDOR_HYGON: 545 /* 546 * Starting with Family 15h processors, TSC clock 547 * source is in the north bridge. Check whether 548 * we have a single-socket/multi-core platform. 549 * XXX Need more work for complex cases. 550 */ 551 if (CPUID_TO_FAMILY(cpu_id) < 0x15 || 552 (amd_feature2 & AMDID2_CMP) == 0 || 553 smp_cpus > (cpu_procinfo2 & AMDID_CMP_CORES) + 1) 554 break; 555 return (1000); 556 case CPU_VENDOR_INTEL: 557 /* 558 * XXX Assume Intel platforms have synchronized TSCs. 559 */ 560 return (1000); 561 } 562 return (800); 563 } 564 return (-100); 565 } 566 567 #undef N 568 569 #endif /* SMP */ 570 571 static void 572 init_TSC_tc(void) 573 { 574 uint64_t max_freq; 575 int shift; 576 577 if ((cpu_feature & CPUID_TSC) == 0 || tsc_disabled) 578 return; 579 580 /* 581 * Limit timecounter frequency to fit in an int and prevent it from 582 * overflowing too fast. 583 */ 584 max_freq = UINT_MAX; 585 586 /* 587 * We can not use the TSC if we support APM. Precise timekeeping 588 * on an APM'ed machine is at best a fools pursuit, since 589 * any and all of the time spent in various SMM code can't 590 * be reliably accounted for. Reading the RTC is your only 591 * source of reliable time info. The i8254 loses too, of course, 592 * but we need to have some kind of time... 593 * We don't know at this point whether APM is going to be used 594 * or not, nor when it might be activated. Play it safe. 595 */ 596 if (power_pm_get_type() == POWER_PM_TYPE_APM) { 597 tsc_timecounter.tc_quality = -1000; 598 if (bootverbose) 599 printf("TSC timecounter disabled: APM enabled.\n"); 600 goto init; 601 } 602 603 /* 604 * Intel CPUs without a C-state invariant TSC can stop the TSC 605 * in either C2 or C3. Disable use of C2 and C3 while using 606 * the TSC as the timecounter. The timecounter can be changed 607 * to enable C2 and C3. 608 * 609 * Note that the TSC is used as the cputicker for computing 610 * thread runtime regardless of the timecounter setting, so 611 * using an alternate timecounter and enabling C2 or C3 can 612 * result incorrect runtimes for kernel idle threads (but not 613 * for any non-idle threads). 614 */ 615 if (cpu_vendor_id == CPU_VENDOR_INTEL && 616 (amd_pminfo & AMDPM_TSC_INVARIANT) == 0) { 617 tsc_timecounter.tc_flags |= TC_FLAGS_C2STOP; 618 if (bootverbose) 619 printf("TSC timecounter disables C2 and C3.\n"); 620 } 621 622 /* 623 * We can not use the TSC in SMP mode unless the TSCs on all CPUs 624 * are synchronized. If the user is sure that the system has 625 * synchronized TSCs, set kern.timecounter.smp_tsc tunable to a 626 * non-zero value. The TSC seems unreliable in virtualized SMP 627 * environments, so it is set to a negative quality in those cases. 628 */ 629 #ifdef SMP 630 if (mp_ncpus > 1) 631 tsc_timecounter.tc_quality = test_tsc(smp_tsc_adjust); 632 else 633 #endif /* SMP */ 634 if (tsc_is_invariant) 635 tsc_timecounter.tc_quality = 1000; 636 max_freq >>= tsc_shift; 637 638 init: 639 for (shift = 0; shift <= 31 && (tsc_freq >> shift) > max_freq; shift++) 640 ; 641 if ((cpu_feature & CPUID_SSE2) != 0 && mp_ncpus > 1) { 642 if (cpu_vendor_id == CPU_VENDOR_AMD || 643 cpu_vendor_id == CPU_VENDOR_HYGON) { 644 tsc_timecounter.tc_get_timecount = shift > 0 ? 645 tsc_get_timecount_low_mfence : 646 tsc_get_timecount_mfence; 647 } else { 648 tsc_timecounter.tc_get_timecount = shift > 0 ? 649 tsc_get_timecount_low_lfence : 650 tsc_get_timecount_lfence; 651 } 652 } else { 653 tsc_timecounter.tc_get_timecount = shift > 0 ? 654 tsc_get_timecount_low : tsc_get_timecount; 655 } 656 if (shift > 0) { 657 tsc_timecounter.tc_name = "TSC-low"; 658 if (bootverbose) 659 printf("TSC timecounter discards lower %d bit(s)\n", 660 shift); 661 } 662 if (tsc_freq != 0) { 663 tsc_timecounter.tc_frequency = tsc_freq >> shift; 664 tsc_timecounter.tc_priv = (void *)(intptr_t)shift; 665 tc_init(&tsc_timecounter); 666 } 667 } 668 SYSINIT(tsc_tc, SI_SUB_SMP, SI_ORDER_ANY, init_TSC_tc, NULL); 669 670 void 671 resume_TSC(void) 672 { 673 #ifdef SMP 674 int quality; 675 676 /* If TSC was not good on boot, it is unlikely to become good now. */ 677 if (tsc_timecounter.tc_quality < 0) 678 return; 679 /* Nothing to do with UP. */ 680 if (mp_ncpus < 2) 681 return; 682 683 /* 684 * If TSC was good, a single synchronization should be enough, 685 * but honour smp_tsc_adjust if it's set. 686 */ 687 quality = test_tsc(MAX(smp_tsc_adjust, 1)); 688 if (quality != tsc_timecounter.tc_quality) { 689 printf("TSC timecounter quality changed: %d -> %d\n", 690 tsc_timecounter.tc_quality, quality); 691 tsc_timecounter.tc_quality = quality; 692 } 693 #endif /* SMP */ 694 } 695 696 /* 697 * When cpufreq levels change, find out about the (new) max frequency. We 698 * use this to update CPU accounting in case it got a lower estimate at boot. 699 */ 700 static void 701 tsc_levels_changed(void *arg, int unit) 702 { 703 device_t cf_dev; 704 struct cf_level *levels; 705 int count, error; 706 uint64_t max_freq; 707 708 /* Only use values from the first CPU, assuming all are equal. */ 709 if (unit != 0) 710 return; 711 712 /* Find the appropriate cpufreq device instance. */ 713 cf_dev = devclass_get_device(devclass_find("cpufreq"), unit); 714 if (cf_dev == NULL) { 715 printf("tsc_levels_changed() called but no cpufreq device?\n"); 716 return; 717 } 718 719 /* Get settings from the device and find the max frequency. */ 720 count = 64; 721 levels = malloc(count * sizeof(*levels), M_TEMP, M_NOWAIT); 722 if (levels == NULL) 723 return; 724 error = CPUFREQ_LEVELS(cf_dev, levels, &count); 725 if (error == 0 && count != 0) { 726 max_freq = (uint64_t)levels[0].total_set.freq * 1000000; 727 set_cputicker(rdtsc, max_freq, 1); 728 } else 729 printf("tsc_levels_changed: no max freq found\n"); 730 free(levels, M_TEMP); 731 } 732 733 /* 734 * If the TSC timecounter is in use, veto the pending change. It may be 735 * possible in the future to handle a dynamically-changing timecounter rate. 736 */ 737 static void 738 tsc_freq_changing(void *arg, const struct cf_level *level, int *status) 739 { 740 741 if (*status != 0 || timecounter != &tsc_timecounter) 742 return; 743 744 printf("timecounter TSC must not be in use when " 745 "changing frequencies; change denied\n"); 746 *status = EBUSY; 747 } 748 749 /* Update TSC freq with the value indicated by the caller. */ 750 static void 751 tsc_freq_changed(void *arg, const struct cf_level *level, int status) 752 { 753 uint64_t freq; 754 755 /* If there was an error during the transition, don't do anything. */ 756 if (tsc_disabled || status != 0) 757 return; 758 759 /* Total setting for this level gives the new frequency in MHz. */ 760 freq = (uint64_t)level->total_set.freq * 1000000; 761 atomic_store_rel_64(&tsc_freq, freq); 762 tsc_timecounter.tc_frequency = 763 freq >> (int)(intptr_t)tsc_timecounter.tc_priv; 764 } 765 766 static int 767 sysctl_machdep_tsc_freq(SYSCTL_HANDLER_ARGS) 768 { 769 int error; 770 uint64_t freq; 771 772 freq = atomic_load_acq_64(&tsc_freq); 773 if (freq == 0) 774 return (EOPNOTSUPP); 775 error = sysctl_handle_64(oidp, &freq, 0, req); 776 if (error == 0 && req->newptr != NULL) { 777 atomic_store_rel_64(&tsc_freq, freq); 778 atomic_store_rel_64(&tsc_timecounter.tc_frequency, 779 freq >> (int)(intptr_t)tsc_timecounter.tc_priv); 780 } 781 return (error); 782 } 783 784 SYSCTL_PROC(_machdep, OID_AUTO, tsc_freq, 785 CTLTYPE_U64 | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 786 0, 0, sysctl_machdep_tsc_freq, "QU", 787 "Time Stamp Counter frequency"); 788 789 static u_int 790 tsc_get_timecount(struct timecounter *tc __unused) 791 { 792 793 return (rdtsc32()); 794 } 795 796 static inline u_int 797 tsc_get_timecount_low(struct timecounter *tc) 798 { 799 uint32_t rv; 800 801 __asm __volatile("rdtsc; shrd %%cl, %%edx, %0" 802 : "=a" (rv) : "c" ((int)(intptr_t)tc->tc_priv) : "edx"); 803 return (rv); 804 } 805 806 static u_int 807 tsc_get_timecount_lfence(struct timecounter *tc __unused) 808 { 809 810 lfence(); 811 return (rdtsc32()); 812 } 813 814 static u_int 815 tsc_get_timecount_low_lfence(struct timecounter *tc) 816 { 817 818 lfence(); 819 return (tsc_get_timecount_low(tc)); 820 } 821 822 static u_int 823 tsc_get_timecount_mfence(struct timecounter *tc __unused) 824 { 825 826 mfence(); 827 return (rdtsc32()); 828 } 829 830 static u_int 831 tsc_get_timecount_low_mfence(struct timecounter *tc) 832 { 833 834 mfence(); 835 return (tsc_get_timecount_low(tc)); 836 } 837 838 static uint32_t 839 x86_tsc_vdso_timehands(struct vdso_timehands *vdso_th, struct timecounter *tc) 840 { 841 842 vdso_th->th_algo = VDSO_TH_ALGO_X86_TSC; 843 vdso_th->th_x86_shift = (int)(intptr_t)tc->tc_priv; 844 vdso_th->th_x86_hpet_idx = 0xffffffff; 845 bzero(vdso_th->th_res, sizeof(vdso_th->th_res)); 846 return (1); 847 } 848 849 #ifdef COMPAT_FREEBSD32 850 static uint32_t 851 x86_tsc_vdso_timehands32(struct vdso_timehands32 *vdso_th32, 852 struct timecounter *tc) 853 { 854 855 vdso_th32->th_algo = VDSO_TH_ALGO_X86_TSC; 856 vdso_th32->th_x86_shift = (int)(intptr_t)tc->tc_priv; 857 vdso_th32->th_x86_hpet_idx = 0xffffffff; 858 bzero(vdso_th32->th_res, sizeof(vdso_th32->th_res)); 859 return (1); 860 } 861 #endif 862