1 /*- 2 * Copyright (c) 2003 Peter Wemm. 3 * Copyright (c) 1992 Terrence R. Lambert. 4 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * William Jolitz. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the University of 21 * California, Berkeley and its contributors. 22 * 4. Neither the name of the University nor the names of its contributors 23 * may be used to endorse or promote products derived from this software 24 * without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 * 38 * from: @(#)machdep.c 7.4 (Berkeley) 6/3/91 39 */ 40 41 #include <sys/cdefs.h> 42 __FBSDID("$FreeBSD$"); 43 44 #include "opt_atpic.h" 45 #include "opt_compat.h" 46 #include "opt_cpu.h" 47 #include "opt_ddb.h" 48 #include "opt_inet.h" 49 #include "opt_isa.h" 50 #include "opt_kdb.h" 51 #include "opt_kstack_pages.h" 52 #include "opt_maxmem.h" 53 #include "opt_mp_watchdog.h" 54 #include "opt_platform.h" 55 #ifdef __i386__ 56 #include "opt_apic.h" 57 #include "opt_xbox.h" 58 #endif 59 60 #include <sys/param.h> 61 #include <sys/proc.h> 62 #include <sys/systm.h> 63 #include <sys/bus.h> 64 #include <sys/cpu.h> 65 #include <sys/kdb.h> 66 #include <sys/kernel.h> 67 #include <sys/ktr.h> 68 #include <sys/lock.h> 69 #include <sys/malloc.h> 70 #include <sys/mutex.h> 71 #include <sys/pcpu.h> 72 #include <sys/rwlock.h> 73 #include <sys/sched.h> 74 #ifdef SMP 75 #include <sys/smp.h> 76 #endif 77 #include <sys/sysctl.h> 78 79 #include <machine/clock.h> 80 #include <machine/cpu.h> 81 #include <machine/cputypes.h> 82 #include <machine/specialreg.h> 83 #include <machine/md_var.h> 84 #include <machine/mp_watchdog.h> 85 #include <machine/tss.h> 86 #ifdef SMP 87 #include <machine/smp.h> 88 #endif 89 #include <x86/acpica_machdep.h> 90 91 #include <vm/vm.h> 92 #include <vm/vm_extern.h> 93 #include <vm/vm_kern.h> 94 #include <vm/vm_page.h> 95 #include <vm/vm_map.h> 96 #include <vm/vm_object.h> 97 #include <vm/vm_pager.h> 98 #include <vm/vm_param.h> 99 100 #define STATE_RUNNING 0x0 101 #define STATE_MWAIT 0x1 102 #define STATE_SLEEPING 0x2 103 104 /* 105 * Machine dependent boot() routine 106 * 107 * I haven't seen anything to put here yet 108 * Possibly some stuff might be grafted back here from boot() 109 */ 110 void 111 cpu_boot(int howto) 112 { 113 } 114 115 /* 116 * Flush the D-cache for non-DMA I/O so that the I-cache can 117 * be made coherent later. 118 */ 119 void 120 cpu_flush_dcache(void *ptr, size_t len) 121 { 122 /* Not applicable */ 123 } 124 125 void 126 acpi_cpu_c1(void) 127 { 128 129 __asm __volatile("sti; hlt"); 130 } 131 132 void 133 acpi_cpu_idle_mwait(uint32_t mwait_hint) 134 { 135 int *state; 136 137 /* 138 * XXXKIB. Software coordination mode should be supported, 139 * but all Intel CPUs provide hardware coordination. 140 */ 141 142 state = (int *)PCPU_PTR(monitorbuf); 143 KASSERT(*state == STATE_SLEEPING, 144 ("cpu_mwait_cx: wrong monitorbuf state")); 145 *state = STATE_MWAIT; 146 cpu_monitor(state, 0, 0); 147 if (*state == STATE_MWAIT) 148 cpu_mwait(MWAIT_INTRBREAK, mwait_hint); 149 150 /* 151 * We should exit on any event that interrupts mwait, because 152 * that event might be a wanted interrupt. 153 */ 154 *state = STATE_RUNNING; 155 } 156 157 /* Get current clock frequency for the given cpu id. */ 158 int 159 cpu_est_clockrate(int cpu_id, uint64_t *rate) 160 { 161 uint64_t tsc1, tsc2; 162 uint64_t acnt, mcnt, perf; 163 register_t reg; 164 165 if (pcpu_find(cpu_id) == NULL || rate == NULL) 166 return (EINVAL); 167 #ifdef __i386__ 168 if ((cpu_feature & CPUID_TSC) == 0) 169 return (EOPNOTSUPP); 170 #endif 171 172 /* 173 * If TSC is P-state invariant and APERF/MPERF MSRs do not exist, 174 * DELAY(9) based logic fails. 175 */ 176 if (tsc_is_invariant && !tsc_perf_stat) 177 return (EOPNOTSUPP); 178 179 #ifdef SMP 180 if (smp_cpus > 1) { 181 /* Schedule ourselves on the indicated cpu. */ 182 thread_lock(curthread); 183 sched_bind(curthread, cpu_id); 184 thread_unlock(curthread); 185 } 186 #endif 187 188 /* Calibrate by measuring a short delay. */ 189 reg = intr_disable(); 190 if (tsc_is_invariant) { 191 wrmsr(MSR_MPERF, 0); 192 wrmsr(MSR_APERF, 0); 193 tsc1 = rdtsc(); 194 DELAY(1000); 195 mcnt = rdmsr(MSR_MPERF); 196 acnt = rdmsr(MSR_APERF); 197 tsc2 = rdtsc(); 198 intr_restore(reg); 199 perf = 1000 * acnt / mcnt; 200 *rate = (tsc2 - tsc1) * perf; 201 } else { 202 tsc1 = rdtsc(); 203 DELAY(1000); 204 tsc2 = rdtsc(); 205 intr_restore(reg); 206 *rate = (tsc2 - tsc1) * 1000; 207 } 208 209 #ifdef SMP 210 if (smp_cpus > 1) { 211 thread_lock(curthread); 212 sched_unbind(curthread); 213 thread_unlock(curthread); 214 } 215 #endif 216 217 return (0); 218 } 219 220 /* 221 * Shutdown the CPU as much as possible 222 */ 223 void 224 cpu_halt(void) 225 { 226 for (;;) 227 halt(); 228 } 229 230 bool 231 cpu_mwait_usable(void) 232 { 233 234 return ((cpu_feature2 & CPUID2_MON) != 0 && ((cpu_mon_mwait_flags & 235 (CPUID5_MON_MWAIT_EXT | CPUID5_MWAIT_INTRBREAK)) == 236 (CPUID5_MON_MWAIT_EXT | CPUID5_MWAIT_INTRBREAK))); 237 } 238 239 void (*cpu_idle_hook)(sbintime_t) = NULL; /* ACPI idle hook. */ 240 static int cpu_ident_amdc1e = 0; /* AMD C1E supported. */ 241 static int idle_mwait = 1; /* Use MONITOR/MWAIT for short idle. */ 242 SYSCTL_INT(_machdep, OID_AUTO, idle_mwait, CTLFLAG_RWTUN, &idle_mwait, 243 0, "Use MONITOR/MWAIT for short idle"); 244 245 static void 246 cpu_idle_acpi(sbintime_t sbt) 247 { 248 int *state; 249 250 state = (int *)PCPU_PTR(monitorbuf); 251 *state = STATE_SLEEPING; 252 253 /* See comments in cpu_idle_hlt(). */ 254 disable_intr(); 255 if (sched_runnable()) 256 enable_intr(); 257 else if (cpu_idle_hook) 258 cpu_idle_hook(sbt); 259 else 260 acpi_cpu_c1(); 261 *state = STATE_RUNNING; 262 } 263 264 static void 265 cpu_idle_hlt(sbintime_t sbt) 266 { 267 int *state; 268 269 state = (int *)PCPU_PTR(monitorbuf); 270 *state = STATE_SLEEPING; 271 272 /* 273 * Since we may be in a critical section from cpu_idle(), if 274 * an interrupt fires during that critical section we may have 275 * a pending preemption. If the CPU halts, then that thread 276 * may not execute until a later interrupt awakens the CPU. 277 * To handle this race, check for a runnable thread after 278 * disabling interrupts and immediately return if one is 279 * found. Also, we must absolutely guarentee that hlt is 280 * the next instruction after sti. This ensures that any 281 * interrupt that fires after the call to disable_intr() will 282 * immediately awaken the CPU from hlt. Finally, please note 283 * that on x86 this works fine because of interrupts enabled only 284 * after the instruction following sti takes place, while IF is set 285 * to 1 immediately, allowing hlt instruction to acknowledge the 286 * interrupt. 287 */ 288 disable_intr(); 289 if (sched_runnable()) 290 enable_intr(); 291 else 292 acpi_cpu_c1(); 293 *state = STATE_RUNNING; 294 } 295 296 static void 297 cpu_idle_mwait(sbintime_t sbt) 298 { 299 int *state; 300 301 state = (int *)PCPU_PTR(monitorbuf); 302 *state = STATE_MWAIT; 303 304 /* See comments in cpu_idle_hlt(). */ 305 disable_intr(); 306 if (sched_runnable()) { 307 enable_intr(); 308 *state = STATE_RUNNING; 309 return; 310 } 311 cpu_monitor(state, 0, 0); 312 if (*state == STATE_MWAIT) 313 __asm __volatile("sti; mwait" : : "a" (MWAIT_C1), "c" (0)); 314 else 315 enable_intr(); 316 *state = STATE_RUNNING; 317 } 318 319 static void 320 cpu_idle_spin(sbintime_t sbt) 321 { 322 int *state; 323 int i; 324 325 state = (int *)PCPU_PTR(monitorbuf); 326 *state = STATE_RUNNING; 327 328 /* 329 * The sched_runnable() call is racy but as long as there is 330 * a loop missing it one time will have just a little impact if any 331 * (and it is much better than missing the check at all). 332 */ 333 for (i = 0; i < 1000; i++) { 334 if (sched_runnable()) 335 return; 336 cpu_spinwait(); 337 } 338 } 339 340 /* 341 * C1E renders the local APIC timer dead, so we disable it by 342 * reading the Interrupt Pending Message register and clearing 343 * both C1eOnCmpHalt (bit 28) and SmiOnCmpHalt (bit 27). 344 * 345 * Reference: 346 * "BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh Processors" 347 * #32559 revision 3.00+ 348 */ 349 #define MSR_AMDK8_IPM 0xc0010055 350 #define AMDK8_SMIONCMPHALT (1ULL << 27) 351 #define AMDK8_C1EONCMPHALT (1ULL << 28) 352 #define AMDK8_CMPHALT (AMDK8_SMIONCMPHALT | AMDK8_C1EONCMPHALT) 353 354 void 355 cpu_probe_amdc1e(void) 356 { 357 358 /* 359 * Detect the presence of C1E capability mostly on latest 360 * dual-cores (or future) k8 family. 361 */ 362 if (cpu_vendor_id == CPU_VENDOR_AMD && 363 (cpu_id & 0x00000f00) == 0x00000f00 && 364 (cpu_id & 0x0fff0000) >= 0x00040000) { 365 cpu_ident_amdc1e = 1; 366 } 367 } 368 369 void (*cpu_idle_fn)(sbintime_t) = cpu_idle_acpi; 370 371 void 372 cpu_idle(int busy) 373 { 374 uint64_t msr; 375 sbintime_t sbt = -1; 376 377 CTR2(KTR_SPARE2, "cpu_idle(%d) at %d", 378 busy, curcpu); 379 #ifdef MP_WATCHDOG 380 ap_watchdog(PCPU_GET(cpuid)); 381 #endif 382 383 /* If we are busy - try to use fast methods. */ 384 if (busy) { 385 if ((cpu_feature2 & CPUID2_MON) && idle_mwait) { 386 cpu_idle_mwait(busy); 387 goto out; 388 } 389 } 390 391 /* If we have time - switch timers into idle mode. */ 392 if (!busy) { 393 critical_enter(); 394 sbt = cpu_idleclock(); 395 } 396 397 /* Apply AMD APIC timer C1E workaround. */ 398 if (cpu_ident_amdc1e && cpu_disable_c3_sleep) { 399 msr = rdmsr(MSR_AMDK8_IPM); 400 if (msr & AMDK8_CMPHALT) 401 wrmsr(MSR_AMDK8_IPM, msr & ~AMDK8_CMPHALT); 402 } 403 404 /* Call main idle method. */ 405 cpu_idle_fn(sbt); 406 407 /* Switch timers back into active mode. */ 408 if (!busy) { 409 cpu_activeclock(); 410 critical_exit(); 411 } 412 out: 413 CTR2(KTR_SPARE2, "cpu_idle(%d) at %d done", 414 busy, curcpu); 415 } 416 417 int 418 cpu_idle_wakeup(int cpu) 419 { 420 struct pcpu *pcpu; 421 int *state; 422 423 pcpu = pcpu_find(cpu); 424 state = (int *)pcpu->pc_monitorbuf; 425 /* 426 * This doesn't need to be atomic since missing the race will 427 * simply result in unnecessary IPIs. 428 */ 429 if (*state == STATE_SLEEPING) 430 return (0); 431 if (*state == STATE_MWAIT) 432 *state = STATE_RUNNING; 433 return (1); 434 } 435 436 /* 437 * Ordered by speed/power consumption. 438 */ 439 struct { 440 void *id_fn; 441 char *id_name; 442 } idle_tbl[] = { 443 { cpu_idle_spin, "spin" }, 444 { cpu_idle_mwait, "mwait" }, 445 { cpu_idle_hlt, "hlt" }, 446 #if !defined(__i386__) 447 { cpu_idle_acpi, "acpi" }, 448 #endif 449 { NULL, NULL } 450 }; 451 452 static int 453 idle_sysctl_available(SYSCTL_HANDLER_ARGS) 454 { 455 char *avail, *p; 456 int error; 457 int i; 458 459 avail = malloc(256, M_TEMP, M_WAITOK); 460 p = avail; 461 for (i = 0; idle_tbl[i].id_name != NULL; i++) { 462 if (strstr(idle_tbl[i].id_name, "mwait") && 463 (cpu_feature2 & CPUID2_MON) == 0) 464 continue; 465 #if !defined(__i386__) 466 if (strcmp(idle_tbl[i].id_name, "acpi") == 0 && 467 cpu_idle_hook == NULL) 468 continue; 469 #endif 470 p += sprintf(p, "%s%s", p != avail ? ", " : "", 471 idle_tbl[i].id_name); 472 } 473 error = sysctl_handle_string(oidp, avail, 0, req); 474 free(avail, M_TEMP); 475 return (error); 476 } 477 478 SYSCTL_PROC(_machdep, OID_AUTO, idle_available, CTLTYPE_STRING | CTLFLAG_RD, 479 0, 0, idle_sysctl_available, "A", "list of available idle functions"); 480 481 static int 482 idle_sysctl(SYSCTL_HANDLER_ARGS) 483 { 484 char buf[16]; 485 int error; 486 char *p; 487 int i; 488 489 p = "unknown"; 490 for (i = 0; idle_tbl[i].id_name != NULL; i++) { 491 if (idle_tbl[i].id_fn == cpu_idle_fn) { 492 p = idle_tbl[i].id_name; 493 break; 494 } 495 } 496 strncpy(buf, p, sizeof(buf)); 497 error = sysctl_handle_string(oidp, buf, sizeof(buf), req); 498 if (error != 0 || req->newptr == NULL) 499 return (error); 500 for (i = 0; idle_tbl[i].id_name != NULL; i++) { 501 if (strstr(idle_tbl[i].id_name, "mwait") && 502 (cpu_feature2 & CPUID2_MON) == 0) 503 continue; 504 #if !defined(__i386__) 505 if (strcmp(idle_tbl[i].id_name, "acpi") == 0 && 506 cpu_idle_hook == NULL) 507 continue; 508 #endif 509 if (strcmp(idle_tbl[i].id_name, buf)) 510 continue; 511 cpu_idle_fn = idle_tbl[i].id_fn; 512 return (0); 513 } 514 return (EINVAL); 515 } 516 517 SYSCTL_PROC(_machdep, OID_AUTO, idle, CTLTYPE_STRING | CTLFLAG_RW, 0, 0, 518 idle_sysctl, "A", "currently selected idle function"); 519 520 static int panic_on_nmi = 1; 521 SYSCTL_INT(_machdep, OID_AUTO, panic_on_nmi, CTLFLAG_RWTUN, 522 &panic_on_nmi, 0, 523 "Panic on NMI"); 524 int nmi_is_broadcast = 1; 525 SYSCTL_INT(_machdep, OID_AUTO, nmi_is_broadcast, CTLFLAG_RWTUN, 526 &nmi_is_broadcast, 0, 527 "Chipset NMI is broadcast"); 528 #ifdef KDB 529 int kdb_on_nmi = 1; 530 SYSCTL_INT(_machdep, OID_AUTO, kdb_on_nmi, CTLFLAG_RWTUN, 531 &kdb_on_nmi, 0, 532 "Go to KDB on NMI"); 533 #endif 534 535 #ifdef DEV_ISA 536 void 537 nmi_call_kdb(u_int cpu, u_int type, struct trapframe *frame) 538 { 539 540 /* machine/parity/power fail/"kitchen sink" faults */ 541 if (isa_nmi(frame->tf_err) == 0) { 542 #ifdef KDB 543 /* 544 * NMI can be hooked up to a pushbutton for debugging. 545 */ 546 if (kdb_on_nmi) { 547 printf("NMI/cpu%d ... going to debugger\n", cpu); 548 kdb_trap(type, 0, frame); 549 } 550 #endif /* KDB */ 551 } else if (panic_on_nmi) { 552 panic("NMI indicates hardware failure"); 553 } 554 } 555 #endif 556 557 void 558 nmi_handle_intr(u_int type, struct trapframe *frame) 559 { 560 561 #ifdef DEV_ISA 562 #ifdef SMP 563 if (nmi_is_broadcast) { 564 nmi_call_kdb_smp(type, frame); 565 return; 566 } 567 #endif 568 nmi_call_kdb(PCPU_GET(cpuid), type, frame); 569 #endif 570 } 571