1 /*- 2 * Copyright (c) 2003 Peter Wemm. 3 * Copyright (c) 1992 Terrence R. Lambert. 4 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * William Jolitz. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the University of 21 * California, Berkeley and its contributors. 22 * 4. Neither the name of the University nor the names of its contributors 23 * may be used to endorse or promote products derived from this software 24 * without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 * 38 * from: @(#)machdep.c 7.4 (Berkeley) 6/3/91 39 */ 40 41 #include <sys/cdefs.h> 42 __FBSDID("$FreeBSD$"); 43 44 #include "opt_acpi.h" 45 #include "opt_atpic.h" 46 #include "opt_cpu.h" 47 #include "opt_ddb.h" 48 #include "opt_inet.h" 49 #include "opt_isa.h" 50 #include "opt_kdb.h" 51 #include "opt_kstack_pages.h" 52 #include "opt_maxmem.h" 53 #include "opt_mp_watchdog.h" 54 #include "opt_platform.h" 55 #ifdef __i386__ 56 #include "opt_apic.h" 57 #endif 58 59 #include <sys/param.h> 60 #include <sys/proc.h> 61 #include <sys/systm.h> 62 #include <sys/bus.h> 63 #include <sys/cpu.h> 64 #include <sys/domainset.h> 65 #include <sys/kdb.h> 66 #include <sys/kernel.h> 67 #include <sys/ktr.h> 68 #include <sys/lock.h> 69 #include <sys/malloc.h> 70 #include <sys/mutex.h> 71 #include <sys/pcpu.h> 72 #include <sys/rwlock.h> 73 #include <sys/sched.h> 74 #include <sys/smp.h> 75 #include <sys/sysctl.h> 76 77 #include <machine/clock.h> 78 #include <machine/cpu.h> 79 #include <machine/cputypes.h> 80 #include <machine/specialreg.h> 81 #include <machine/md_var.h> 82 #include <machine/mp_watchdog.h> 83 #include <machine/tss.h> 84 #ifdef SMP 85 #include <machine/smp.h> 86 #endif 87 #ifdef CPU_ELAN 88 #include <machine/elan_mmcr.h> 89 #endif 90 #include <x86/acpica_machdep.h> 91 92 #include <vm/vm.h> 93 #include <vm/vm_extern.h> 94 #include <vm/vm_kern.h> 95 #include <vm/vm_page.h> 96 #include <vm/vm_map.h> 97 #include <vm/vm_object.h> 98 #include <vm/vm_pager.h> 99 #include <vm/vm_param.h> 100 101 #include <isa/isareg.h> 102 103 #include <contrib/dev/acpica/include/acpi.h> 104 105 #define STATE_RUNNING 0x0 106 #define STATE_MWAIT 0x1 107 #define STATE_SLEEPING 0x2 108 109 #ifdef SMP 110 static u_int cpu_reset_proxyid; 111 static volatile u_int cpu_reset_proxy_active; 112 #endif 113 114 struct msr_op_arg { 115 u_int msr; 116 int op; 117 uint64_t arg1; 118 }; 119 120 static void 121 x86_msr_op_one(void *argp) 122 { 123 struct msr_op_arg *a; 124 uint64_t v; 125 126 a = argp; 127 switch (a->op) { 128 case MSR_OP_ANDNOT: 129 v = rdmsr(a->msr); 130 v &= ~a->arg1; 131 wrmsr(a->msr, v); 132 break; 133 case MSR_OP_OR: 134 v = rdmsr(a->msr); 135 v |= a->arg1; 136 wrmsr(a->msr, v); 137 break; 138 case MSR_OP_WRITE: 139 wrmsr(a->msr, a->arg1); 140 break; 141 } 142 } 143 144 #define MSR_OP_EXMODE_MASK 0xf0000000 145 #define MSR_OP_OP_MASK 0x000000ff 146 147 void 148 x86_msr_op(u_int msr, u_int op, uint64_t arg1) 149 { 150 struct thread *td; 151 struct msr_op_arg a; 152 u_int exmode; 153 int bound_cpu, i, is_bound; 154 155 a.op = op & MSR_OP_OP_MASK; 156 MPASS(a.op == MSR_OP_ANDNOT || a.op == MSR_OP_OR || 157 a.op == MSR_OP_WRITE); 158 exmode = op & MSR_OP_EXMODE_MASK; 159 MPASS(exmode == MSR_OP_LOCAL || exmode == MSR_OP_SCHED || 160 exmode == MSR_OP_RENDEZVOUS); 161 a.msr = msr; 162 a.arg1 = arg1; 163 switch (exmode) { 164 case MSR_OP_LOCAL: 165 x86_msr_op_one(&a); 166 break; 167 case MSR_OP_SCHED: 168 td = curthread; 169 thread_lock(td); 170 is_bound = sched_is_bound(td); 171 bound_cpu = td->td_oncpu; 172 CPU_FOREACH(i) { 173 sched_bind(td, i); 174 x86_msr_op_one(&a); 175 } 176 if (is_bound) 177 sched_bind(td, bound_cpu); 178 else 179 sched_unbind(td); 180 thread_unlock(td); 181 break; 182 case MSR_OP_RENDEZVOUS: 183 smp_rendezvous(NULL, x86_msr_op_one, NULL, &a); 184 break; 185 } 186 } 187 188 /* 189 * Automatically initialized per CPU errata in cpu_idle_tun below. 190 */ 191 bool mwait_cpustop_broken = false; 192 SYSCTL_BOOL(_machdep, OID_AUTO, mwait_cpustop_broken, CTLFLAG_RDTUN, 193 &mwait_cpustop_broken, 0, 194 "Can not reliably wake MONITOR/MWAIT cpus without interrupts"); 195 196 /* 197 * Machine dependent boot() routine 198 * 199 * I haven't seen anything to put here yet 200 * Possibly some stuff might be grafted back here from boot() 201 */ 202 void 203 cpu_boot(int howto) 204 { 205 } 206 207 /* 208 * Flush the D-cache for non-DMA I/O so that the I-cache can 209 * be made coherent later. 210 */ 211 void 212 cpu_flush_dcache(void *ptr, size_t len) 213 { 214 /* Not applicable */ 215 } 216 217 void 218 acpi_cpu_c1(void) 219 { 220 221 __asm __volatile("sti; hlt"); 222 } 223 224 /* 225 * Use mwait to pause execution while waiting for an interrupt or 226 * another thread to signal that there is more work. 227 * 228 * NOTE: Interrupts will cause a wakeup; however, this function does 229 * not enable interrupt handling. The caller is responsible to enable 230 * interrupts. 231 */ 232 void 233 acpi_cpu_idle_mwait(uint32_t mwait_hint) 234 { 235 int *state; 236 uint64_t v; 237 238 /* 239 * A comment in Linux patch claims that 'CPUs run faster with 240 * speculation protection disabled. All CPU threads in a core 241 * must disable speculation protection for it to be 242 * disabled. Disable it while we are idle so the other 243 * hyperthread can run fast.' 244 * 245 * XXXKIB. Software coordination mode should be supported, 246 * but all Intel CPUs provide hardware coordination. 247 */ 248 249 state = &PCPU_PTR(monitorbuf)->idle_state; 250 KASSERT(atomic_load_int(state) == STATE_SLEEPING, 251 ("cpu_mwait_cx: wrong monitorbuf state")); 252 atomic_store_int(state, STATE_MWAIT); 253 if (PCPU_GET(ibpb_set) || hw_ssb_active) { 254 v = rdmsr(MSR_IA32_SPEC_CTRL); 255 wrmsr(MSR_IA32_SPEC_CTRL, v & ~(IA32_SPEC_CTRL_IBRS | 256 IA32_SPEC_CTRL_STIBP | IA32_SPEC_CTRL_SSBD)); 257 } else { 258 v = 0; 259 } 260 cpu_monitor(state, 0, 0); 261 if (atomic_load_int(state) == STATE_MWAIT) 262 cpu_mwait(MWAIT_INTRBREAK, mwait_hint); 263 264 /* 265 * SSB cannot be disabled while we sleep, or rather, if it was 266 * disabled, the sysctl thread will bind to our cpu to tweak 267 * MSR. 268 */ 269 if (v != 0) 270 wrmsr(MSR_IA32_SPEC_CTRL, v); 271 272 /* 273 * We should exit on any event that interrupts mwait, because 274 * that event might be a wanted interrupt. 275 */ 276 atomic_store_int(state, STATE_RUNNING); 277 } 278 279 /* Get current clock frequency for the given cpu id. */ 280 int 281 cpu_est_clockrate(int cpu_id, uint64_t *rate) 282 { 283 uint64_t tsc1, tsc2; 284 uint64_t acnt, mcnt, perf; 285 register_t reg; 286 287 if (pcpu_find(cpu_id) == NULL || rate == NULL) 288 return (EINVAL); 289 #ifdef __i386__ 290 if ((cpu_feature & CPUID_TSC) == 0) 291 return (EOPNOTSUPP); 292 #endif 293 294 /* 295 * If TSC is P-state invariant and APERF/MPERF MSRs do not exist, 296 * DELAY(9) based logic fails. 297 */ 298 if (tsc_is_invariant && !tsc_perf_stat) 299 return (EOPNOTSUPP); 300 301 #ifdef SMP 302 if (smp_cpus > 1) { 303 /* Schedule ourselves on the indicated cpu. */ 304 thread_lock(curthread); 305 sched_bind(curthread, cpu_id); 306 thread_unlock(curthread); 307 } 308 #endif 309 310 /* Calibrate by measuring a short delay. */ 311 reg = intr_disable(); 312 if (tsc_is_invariant) { 313 wrmsr(MSR_MPERF, 0); 314 wrmsr(MSR_APERF, 0); 315 tsc1 = rdtsc(); 316 DELAY(1000); 317 mcnt = rdmsr(MSR_MPERF); 318 acnt = rdmsr(MSR_APERF); 319 tsc2 = rdtsc(); 320 intr_restore(reg); 321 perf = 1000 * acnt / mcnt; 322 *rate = (tsc2 - tsc1) * perf; 323 } else { 324 tsc1 = rdtsc(); 325 DELAY(1000); 326 tsc2 = rdtsc(); 327 intr_restore(reg); 328 *rate = (tsc2 - tsc1) * 1000; 329 } 330 331 #ifdef SMP 332 if (smp_cpus > 1) { 333 thread_lock(curthread); 334 sched_unbind(curthread); 335 thread_unlock(curthread); 336 } 337 #endif 338 339 return (0); 340 } 341 342 /* 343 * Shutdown the CPU as much as possible 344 */ 345 void 346 cpu_halt(void) 347 { 348 for (;;) 349 halt(); 350 } 351 352 static void 353 cpu_reset_real(void) 354 { 355 struct region_descriptor null_idt; 356 int b; 357 358 disable_intr(); 359 #ifdef CPU_ELAN 360 if (elan_mmcr != NULL) 361 elan_mmcr->RESCFG = 1; 362 #endif 363 #ifdef __i386__ 364 if (cpu == CPU_GEODE1100) { 365 /* Attempt Geode's own reset */ 366 outl(0xcf8, 0x80009044ul); 367 outl(0xcfc, 0xf); 368 } 369 #endif 370 #if !defined(BROKEN_KEYBOARD_RESET) 371 /* 372 * Attempt to do a CPU reset via the keyboard controller, 373 * do not turn off GateA20, as any machine that fails 374 * to do the reset here would then end up in no man's land. 375 */ 376 outb(IO_KBD + 4, 0xFE); 377 DELAY(500000); /* wait 0.5 sec to see if that did it */ 378 #endif 379 380 /* 381 * Attempt to force a reset via the Reset Control register at 382 * I/O port 0xcf9. Bit 2 forces a system reset when it 383 * transitions from 0 to 1. Bit 1 selects the type of reset 384 * to attempt: 0 selects a "soft" reset, and 1 selects a 385 * "hard" reset. We try a "hard" reset. The first write sets 386 * bit 1 to select a "hard" reset and clears bit 2. The 387 * second write forces a 0 -> 1 transition in bit 2 to trigger 388 * a reset. 389 */ 390 outb(0xcf9, 0x2); 391 outb(0xcf9, 0x6); 392 DELAY(500000); /* wait 0.5 sec to see if that did it */ 393 394 /* 395 * Attempt to force a reset via the Fast A20 and Init register 396 * at I/O port 0x92. Bit 1 serves as an alternate A20 gate. 397 * Bit 0 asserts INIT# when set to 1. We are careful to only 398 * preserve bit 1 while setting bit 0. We also must clear bit 399 * 0 before setting it if it isn't already clear. 400 */ 401 b = inb(0x92); 402 if (b != 0xff) { 403 if ((b & 0x1) != 0) 404 outb(0x92, b & 0xfe); 405 outb(0x92, b | 0x1); 406 DELAY(500000); /* wait 0.5 sec to see if that did it */ 407 } 408 409 printf("No known reset method worked, attempting CPU shutdown\n"); 410 DELAY(1000000); /* wait 1 sec for printf to complete */ 411 412 /* Wipe the IDT. */ 413 null_idt.rd_limit = 0; 414 null_idt.rd_base = 0; 415 lidt(&null_idt); 416 417 /* "good night, sweet prince .... <THUNK!>" */ 418 breakpoint(); 419 420 /* NOTREACHED */ 421 while(1); 422 } 423 424 #ifdef SMP 425 static void 426 cpu_reset_proxy(void) 427 { 428 429 cpu_reset_proxy_active = 1; 430 while (cpu_reset_proxy_active == 1) 431 ia32_pause(); /* Wait for other cpu to see that we've started */ 432 433 printf("cpu_reset_proxy: Stopped CPU %d\n", cpu_reset_proxyid); 434 DELAY(1000000); 435 cpu_reset_real(); 436 } 437 #endif 438 439 void 440 cpu_reset(void) 441 { 442 #ifdef SMP 443 struct monitorbuf *mb; 444 cpuset_t map; 445 u_int cnt; 446 447 if (smp_started) { 448 map = all_cpus; 449 CPU_CLR(PCPU_GET(cpuid), &map); 450 CPU_ANDNOT(&map, &stopped_cpus); 451 if (!CPU_EMPTY(&map)) { 452 printf("cpu_reset: Stopping other CPUs\n"); 453 stop_cpus(map); 454 } 455 456 if (PCPU_GET(cpuid) != 0) { 457 cpu_reset_proxyid = PCPU_GET(cpuid); 458 cpustop_restartfunc = cpu_reset_proxy; 459 cpu_reset_proxy_active = 0; 460 printf("cpu_reset: Restarting BSP\n"); 461 462 /* Restart CPU #0. */ 463 CPU_SETOF(0, &started_cpus); 464 mb = &pcpu_find(0)->pc_monitorbuf; 465 atomic_store_int(&mb->stop_state, 466 MONITOR_STOPSTATE_RUNNING); 467 468 cnt = 0; 469 while (cpu_reset_proxy_active == 0 && cnt < 10000000) { 470 ia32_pause(); 471 cnt++; /* Wait for BSP to announce restart */ 472 } 473 if (cpu_reset_proxy_active == 0) { 474 printf("cpu_reset: Failed to restart BSP\n"); 475 } else { 476 cpu_reset_proxy_active = 2; 477 while (1) 478 ia32_pause(); 479 /* NOTREACHED */ 480 } 481 } 482 483 DELAY(1000000); 484 } 485 #endif 486 cpu_reset_real(); 487 /* NOTREACHED */ 488 } 489 490 bool 491 cpu_mwait_usable(void) 492 { 493 494 return ((cpu_feature2 & CPUID2_MON) != 0 && ((cpu_mon_mwait_flags & 495 (CPUID5_MON_MWAIT_EXT | CPUID5_MWAIT_INTRBREAK)) == 496 (CPUID5_MON_MWAIT_EXT | CPUID5_MWAIT_INTRBREAK))); 497 } 498 499 void (*cpu_idle_hook)(sbintime_t) = NULL; /* ACPI idle hook. */ 500 static int cpu_ident_amdc1e = 0; /* AMD C1E supported. */ 501 static int idle_mwait = 1; /* Use MONITOR/MWAIT for short idle. */ 502 SYSCTL_INT(_machdep, OID_AUTO, idle_mwait, CTLFLAG_RWTUN, &idle_mwait, 503 0, "Use MONITOR/MWAIT for short idle"); 504 505 static void 506 cpu_idle_acpi(sbintime_t sbt) 507 { 508 int *state; 509 510 state = &PCPU_PTR(monitorbuf)->idle_state; 511 atomic_store_int(state, STATE_SLEEPING); 512 513 /* See comments in cpu_idle_hlt(). */ 514 disable_intr(); 515 if (sched_runnable()) 516 enable_intr(); 517 else if (cpu_idle_hook) 518 cpu_idle_hook(sbt); 519 else 520 acpi_cpu_c1(); 521 atomic_store_int(state, STATE_RUNNING); 522 } 523 524 static void 525 cpu_idle_hlt(sbintime_t sbt) 526 { 527 int *state; 528 529 state = &PCPU_PTR(monitorbuf)->idle_state; 530 atomic_store_int(state, STATE_SLEEPING); 531 532 /* 533 * Since we may be in a critical section from cpu_idle(), if 534 * an interrupt fires during that critical section we may have 535 * a pending preemption. If the CPU halts, then that thread 536 * may not execute until a later interrupt awakens the CPU. 537 * To handle this race, check for a runnable thread after 538 * disabling interrupts and immediately return if one is 539 * found. Also, we must absolutely guarentee that hlt is 540 * the next instruction after sti. This ensures that any 541 * interrupt that fires after the call to disable_intr() will 542 * immediately awaken the CPU from hlt. Finally, please note 543 * that on x86 this works fine because of interrupts enabled only 544 * after the instruction following sti takes place, while IF is set 545 * to 1 immediately, allowing hlt instruction to acknowledge the 546 * interrupt. 547 */ 548 disable_intr(); 549 if (sched_runnable()) 550 enable_intr(); 551 else 552 acpi_cpu_c1(); 553 atomic_store_int(state, STATE_RUNNING); 554 } 555 556 static void 557 cpu_idle_mwait(sbintime_t sbt) 558 { 559 int *state; 560 561 state = &PCPU_PTR(monitorbuf)->idle_state; 562 atomic_store_int(state, STATE_MWAIT); 563 564 /* See comments in cpu_idle_hlt(). */ 565 disable_intr(); 566 if (sched_runnable()) { 567 atomic_store_int(state, STATE_RUNNING); 568 enable_intr(); 569 return; 570 } 571 572 cpu_monitor(state, 0, 0); 573 if (atomic_load_int(state) == STATE_MWAIT) 574 __asm __volatile("sti; mwait" : : "a" (MWAIT_C1), "c" (0)); 575 else 576 enable_intr(); 577 atomic_store_int(state, STATE_RUNNING); 578 } 579 580 static void 581 cpu_idle_spin(sbintime_t sbt) 582 { 583 int *state; 584 int i; 585 586 state = &PCPU_PTR(monitorbuf)->idle_state; 587 atomic_store_int(state, STATE_RUNNING); 588 589 /* 590 * The sched_runnable() call is racy but as long as there is 591 * a loop missing it one time will have just a little impact if any 592 * (and it is much better than missing the check at all). 593 */ 594 for (i = 0; i < 1000; i++) { 595 if (sched_runnable()) 596 return; 597 cpu_spinwait(); 598 } 599 } 600 601 /* 602 * C1E renders the local APIC timer dead, so we disable it by 603 * reading the Interrupt Pending Message register and clearing 604 * both C1eOnCmpHalt (bit 28) and SmiOnCmpHalt (bit 27). 605 * 606 * Reference: 607 * "BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh Processors" 608 * #32559 revision 3.00+ 609 */ 610 #define MSR_AMDK8_IPM 0xc0010055 611 #define AMDK8_SMIONCMPHALT (1ULL << 27) 612 #define AMDK8_C1EONCMPHALT (1ULL << 28) 613 #define AMDK8_CMPHALT (AMDK8_SMIONCMPHALT | AMDK8_C1EONCMPHALT) 614 615 void 616 cpu_probe_amdc1e(void) 617 { 618 619 /* 620 * Detect the presence of C1E capability mostly on latest 621 * dual-cores (or future) k8 family. 622 */ 623 if (cpu_vendor_id == CPU_VENDOR_AMD && 624 (cpu_id & 0x00000f00) == 0x00000f00 && 625 (cpu_id & 0x0fff0000) >= 0x00040000) { 626 cpu_ident_amdc1e = 1; 627 } 628 } 629 630 void (*cpu_idle_fn)(sbintime_t) = cpu_idle_acpi; 631 632 void 633 cpu_idle(int busy) 634 { 635 uint64_t msr; 636 sbintime_t sbt = -1; 637 638 CTR2(KTR_SPARE2, "cpu_idle(%d) at %d", 639 busy, curcpu); 640 #ifdef MP_WATCHDOG 641 ap_watchdog(PCPU_GET(cpuid)); 642 #endif 643 644 /* If we are busy - try to use fast methods. */ 645 if (busy) { 646 if ((cpu_feature2 & CPUID2_MON) && idle_mwait) { 647 cpu_idle_mwait(busy); 648 goto out; 649 } 650 } 651 652 /* If we have time - switch timers into idle mode. */ 653 if (!busy) { 654 critical_enter(); 655 sbt = cpu_idleclock(); 656 } 657 658 /* Apply AMD APIC timer C1E workaround. */ 659 if (cpu_ident_amdc1e && cpu_disable_c3_sleep) { 660 msr = rdmsr(MSR_AMDK8_IPM); 661 if (msr & AMDK8_CMPHALT) 662 wrmsr(MSR_AMDK8_IPM, msr & ~AMDK8_CMPHALT); 663 } 664 665 /* Call main idle method. */ 666 cpu_idle_fn(sbt); 667 668 /* Switch timers back into active mode. */ 669 if (!busy) { 670 cpu_activeclock(); 671 critical_exit(); 672 } 673 out: 674 CTR2(KTR_SPARE2, "cpu_idle(%d) at %d done", 675 busy, curcpu); 676 } 677 678 static int cpu_idle_apl31_workaround; 679 SYSCTL_INT(_machdep, OID_AUTO, idle_apl31, CTLFLAG_RW, 680 &cpu_idle_apl31_workaround, 0, 681 "Apollo Lake APL31 MWAIT bug workaround"); 682 683 int 684 cpu_idle_wakeup(int cpu) 685 { 686 struct monitorbuf *mb; 687 int *state; 688 689 mb = &pcpu_find(cpu)->pc_monitorbuf; 690 state = &mb->idle_state; 691 switch (atomic_load_int(state)) { 692 case STATE_SLEEPING: 693 return (0); 694 case STATE_MWAIT: 695 atomic_store_int(state, STATE_RUNNING); 696 return (cpu_idle_apl31_workaround ? 0 : 1); 697 case STATE_RUNNING: 698 return (1); 699 default: 700 panic("bad monitor state"); 701 return (1); 702 } 703 } 704 705 /* 706 * Ordered by speed/power consumption. 707 */ 708 static struct { 709 void *id_fn; 710 char *id_name; 711 int id_cpuid2_flag; 712 } idle_tbl[] = { 713 { .id_fn = cpu_idle_spin, .id_name = "spin" }, 714 { .id_fn = cpu_idle_mwait, .id_name = "mwait", 715 .id_cpuid2_flag = CPUID2_MON }, 716 { .id_fn = cpu_idle_hlt, .id_name = "hlt" }, 717 { .id_fn = cpu_idle_acpi, .id_name = "acpi" }, 718 }; 719 720 static int 721 idle_sysctl_available(SYSCTL_HANDLER_ARGS) 722 { 723 char *avail, *p; 724 int error; 725 int i; 726 727 avail = malloc(256, M_TEMP, M_WAITOK); 728 p = avail; 729 for (i = 0; i < nitems(idle_tbl); i++) { 730 if (idle_tbl[i].id_cpuid2_flag != 0 && 731 (cpu_feature2 & idle_tbl[i].id_cpuid2_flag) == 0) 732 continue; 733 if (strcmp(idle_tbl[i].id_name, "acpi") == 0 && 734 cpu_idle_hook == NULL) 735 continue; 736 p += sprintf(p, "%s%s", p != avail ? ", " : "", 737 idle_tbl[i].id_name); 738 } 739 error = sysctl_handle_string(oidp, avail, 0, req); 740 free(avail, M_TEMP); 741 return (error); 742 } 743 744 SYSCTL_PROC(_machdep, OID_AUTO, idle_available, 745 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, 746 0, 0, idle_sysctl_available, "A", 747 "list of available idle functions"); 748 749 static bool 750 cpu_idle_selector(const char *new_idle_name) 751 { 752 int i; 753 754 for (i = 0; i < nitems(idle_tbl); i++) { 755 if (idle_tbl[i].id_cpuid2_flag != 0 && 756 (cpu_feature2 & idle_tbl[i].id_cpuid2_flag) == 0) 757 continue; 758 if (strcmp(idle_tbl[i].id_name, "acpi") == 0 && 759 cpu_idle_hook == NULL) 760 continue; 761 if (strcmp(idle_tbl[i].id_name, new_idle_name)) 762 continue; 763 cpu_idle_fn = idle_tbl[i].id_fn; 764 if (bootverbose) 765 printf("CPU idle set to %s\n", idle_tbl[i].id_name); 766 return (true); 767 } 768 return (false); 769 } 770 771 static int 772 cpu_idle_sysctl(SYSCTL_HANDLER_ARGS) 773 { 774 char buf[16], *p; 775 int error, i; 776 777 p = "unknown"; 778 for (i = 0; i < nitems(idle_tbl); i++) { 779 if (idle_tbl[i].id_fn == cpu_idle_fn) { 780 p = idle_tbl[i].id_name; 781 break; 782 } 783 } 784 strncpy(buf, p, sizeof(buf)); 785 error = sysctl_handle_string(oidp, buf, sizeof(buf), req); 786 if (error != 0 || req->newptr == NULL) 787 return (error); 788 return (cpu_idle_selector(buf) ? 0 : EINVAL); 789 } 790 791 SYSCTL_PROC(_machdep, OID_AUTO, idle, 792 CTLTYPE_STRING | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 793 0, 0, cpu_idle_sysctl, "A", 794 "currently selected idle function"); 795 796 static void 797 cpu_idle_tun(void *unused __unused) 798 { 799 char tunvar[16]; 800 801 if (TUNABLE_STR_FETCH("machdep.idle", tunvar, sizeof(tunvar))) 802 cpu_idle_selector(tunvar); 803 else if (cpu_vendor_id == CPU_VENDOR_AMD && 804 CPUID_TO_FAMILY(cpu_id) == 0x17 && CPUID_TO_MODEL(cpu_id) == 0x1) { 805 /* Ryzen erratas 1057, 1109. */ 806 cpu_idle_selector("hlt"); 807 idle_mwait = 0; 808 mwait_cpustop_broken = true; 809 } 810 811 if (cpu_vendor_id == CPU_VENDOR_INTEL && cpu_id == 0x506c9) { 812 /* 813 * Apollo Lake errata APL31 (public errata APL30). 814 * Stores to the armed address range may not trigger 815 * MWAIT to resume execution. OS needs to use 816 * interrupts to wake processors from MWAIT-induced 817 * sleep states. 818 */ 819 cpu_idle_apl31_workaround = 1; 820 mwait_cpustop_broken = true; 821 } 822 TUNABLE_INT_FETCH("machdep.idle_apl31", &cpu_idle_apl31_workaround); 823 } 824 SYSINIT(cpu_idle_tun, SI_SUB_CPU, SI_ORDER_MIDDLE, cpu_idle_tun, NULL); 825 826 static int panic_on_nmi = 0xff; 827 SYSCTL_INT(_machdep, OID_AUTO, panic_on_nmi, CTLFLAG_RWTUN, 828 &panic_on_nmi, 0, 829 "Panic on NMI: 1 = H/W failure; 2 = unknown; 0xff = all"); 830 int nmi_is_broadcast = 1; 831 SYSCTL_INT(_machdep, OID_AUTO, nmi_is_broadcast, CTLFLAG_RWTUN, 832 &nmi_is_broadcast, 0, 833 "Chipset NMI is broadcast"); 834 int (*apei_nmi)(void); 835 836 void 837 nmi_call_kdb(u_int cpu, u_int type, struct trapframe *frame) 838 { 839 bool claimed = false; 840 841 #ifdef DEV_ISA 842 /* machine/parity/power fail/"kitchen sink" faults */ 843 if (isa_nmi(frame->tf_err)) { 844 claimed = true; 845 if ((panic_on_nmi & 1) != 0) 846 panic("NMI indicates hardware failure"); 847 } 848 #endif /* DEV_ISA */ 849 850 /* ACPI Platform Error Interfaces callback. */ 851 if (apei_nmi != NULL && (*apei_nmi)()) 852 claimed = true; 853 854 /* 855 * NMIs can be useful for debugging. They can be hooked up to a 856 * pushbutton, usually on an ISA, PCI, or PCIe card. They can also be 857 * generated by an IPMI BMC, either manually or in response to a 858 * watchdog timeout. For example, see the "power diag" command in 859 * ports/sysutils/ipmitool. They can also be generated by a 860 * hypervisor; see "bhyvectl --inject-nmi". 861 */ 862 863 #ifdef KDB 864 if (!claimed && (panic_on_nmi & 2) != 0) { 865 if (debugger_on_panic) { 866 printf("NMI/cpu%d ... going to debugger\n", cpu); 867 claimed = kdb_trap(type, 0, frame); 868 } 869 } 870 #endif /* KDB */ 871 872 if (!claimed && panic_on_nmi != 0) 873 panic("NMI"); 874 } 875 876 void 877 nmi_handle_intr(u_int type, struct trapframe *frame) 878 { 879 880 #ifdef SMP 881 if (nmi_is_broadcast) { 882 nmi_call_kdb_smp(type, frame); 883 return; 884 } 885 #endif 886 nmi_call_kdb(PCPU_GET(cpuid), type, frame); 887 } 888 889 static int hw_ibrs_active; 890 int hw_ibrs_ibpb_active; 891 int hw_ibrs_disable = 1; 892 893 SYSCTL_INT(_hw, OID_AUTO, ibrs_active, CTLFLAG_RD, &hw_ibrs_active, 0, 894 "Indirect Branch Restricted Speculation active"); 895 896 SYSCTL_NODE(_machdep_mitigations, OID_AUTO, ibrs, 897 CTLFLAG_RW | CTLFLAG_MPSAFE, 0, 898 "Indirect Branch Restricted Speculation active"); 899 900 SYSCTL_INT(_machdep_mitigations_ibrs, OID_AUTO, active, CTLFLAG_RD, 901 &hw_ibrs_active, 0, "Indirect Branch Restricted Speculation active"); 902 903 void 904 hw_ibrs_recalculate(bool for_all_cpus) 905 { 906 if ((cpu_ia32_arch_caps & IA32_ARCH_CAP_IBRS_ALL) != 0) { 907 x86_msr_op(MSR_IA32_SPEC_CTRL, (for_all_cpus ? 908 MSR_OP_RENDEZVOUS : MSR_OP_LOCAL) | 909 (hw_ibrs_disable != 0 ? MSR_OP_ANDNOT : MSR_OP_OR), 910 IA32_SPEC_CTRL_IBRS); 911 hw_ibrs_active = hw_ibrs_disable == 0; 912 hw_ibrs_ibpb_active = 0; 913 } else { 914 hw_ibrs_active = hw_ibrs_ibpb_active = (cpu_stdext_feature3 & 915 CPUID_STDEXT3_IBPB) != 0 && !hw_ibrs_disable; 916 } 917 } 918 919 static int 920 hw_ibrs_disable_handler(SYSCTL_HANDLER_ARGS) 921 { 922 int error, val; 923 924 val = hw_ibrs_disable; 925 error = sysctl_handle_int(oidp, &val, 0, req); 926 if (error != 0 || req->newptr == NULL) 927 return (error); 928 hw_ibrs_disable = val != 0; 929 hw_ibrs_recalculate(true); 930 return (0); 931 } 932 SYSCTL_PROC(_hw, OID_AUTO, ibrs_disable, CTLTYPE_INT | CTLFLAG_RWTUN | 933 CTLFLAG_NOFETCH | CTLFLAG_MPSAFE, NULL, 0, hw_ibrs_disable_handler, "I", 934 "Disable Indirect Branch Restricted Speculation"); 935 936 SYSCTL_PROC(_machdep_mitigations_ibrs, OID_AUTO, disable, CTLTYPE_INT | 937 CTLFLAG_RWTUN | CTLFLAG_NOFETCH | CTLFLAG_MPSAFE, NULL, 0, 938 hw_ibrs_disable_handler, "I", 939 "Disable Indirect Branch Restricted Speculation"); 940 941 int hw_ssb_active; 942 int hw_ssb_disable; 943 944 SYSCTL_INT(_hw, OID_AUTO, spec_store_bypass_disable_active, CTLFLAG_RD, 945 &hw_ssb_active, 0, 946 "Speculative Store Bypass Disable active"); 947 948 SYSCTL_NODE(_machdep_mitigations, OID_AUTO, ssb, 949 CTLFLAG_RW | CTLFLAG_MPSAFE, 0, 950 "Speculative Store Bypass Disable active"); 951 952 SYSCTL_INT(_machdep_mitigations_ssb, OID_AUTO, active, CTLFLAG_RD, 953 &hw_ssb_active, 0, "Speculative Store Bypass Disable active"); 954 955 static void 956 hw_ssb_set(bool enable, bool for_all_cpus) 957 { 958 959 if ((cpu_stdext_feature3 & CPUID_STDEXT3_SSBD) == 0) { 960 hw_ssb_active = 0; 961 return; 962 } 963 hw_ssb_active = enable; 964 x86_msr_op(MSR_IA32_SPEC_CTRL, 965 (enable ? MSR_OP_OR : MSR_OP_ANDNOT) | 966 (for_all_cpus ? MSR_OP_SCHED : MSR_OP_LOCAL), IA32_SPEC_CTRL_SSBD); 967 } 968 969 void 970 hw_ssb_recalculate(bool all_cpus) 971 { 972 973 switch (hw_ssb_disable) { 974 default: 975 hw_ssb_disable = 0; 976 /* FALLTHROUGH */ 977 case 0: /* off */ 978 hw_ssb_set(false, all_cpus); 979 break; 980 case 1: /* on */ 981 hw_ssb_set(true, all_cpus); 982 break; 983 case 2: /* auto */ 984 hw_ssb_set((cpu_ia32_arch_caps & IA32_ARCH_CAP_SSB_NO) != 0 ? 985 false : true, all_cpus); 986 break; 987 } 988 } 989 990 static int 991 hw_ssb_disable_handler(SYSCTL_HANDLER_ARGS) 992 { 993 int error, val; 994 995 val = hw_ssb_disable; 996 error = sysctl_handle_int(oidp, &val, 0, req); 997 if (error != 0 || req->newptr == NULL) 998 return (error); 999 hw_ssb_disable = val; 1000 hw_ssb_recalculate(true); 1001 return (0); 1002 } 1003 SYSCTL_PROC(_hw, OID_AUTO, spec_store_bypass_disable, CTLTYPE_INT | 1004 CTLFLAG_RWTUN | CTLFLAG_NOFETCH | CTLFLAG_MPSAFE, NULL, 0, 1005 hw_ssb_disable_handler, "I", 1006 "Speculative Store Bypass Disable (0 - off, 1 - on, 2 - auto"); 1007 1008 SYSCTL_PROC(_machdep_mitigations_ssb, OID_AUTO, disable, CTLTYPE_INT | 1009 CTLFLAG_RWTUN | CTLFLAG_NOFETCH | CTLFLAG_MPSAFE, NULL, 0, 1010 hw_ssb_disable_handler, "I", 1011 "Speculative Store Bypass Disable (0 - off, 1 - on, 2 - auto"); 1012 1013 int hw_mds_disable; 1014 1015 /* 1016 * Handler for Microarchitectural Data Sampling issues. Really not a 1017 * pointer to C function: on amd64 the code must not change any CPU 1018 * architectural state except possibly %rflags. Also, it is always 1019 * called with interrupts disabled. 1020 */ 1021 void mds_handler_void(void); 1022 void mds_handler_verw(void); 1023 void mds_handler_ivb(void); 1024 void mds_handler_bdw(void); 1025 void mds_handler_skl_sse(void); 1026 void mds_handler_skl_avx(void); 1027 void mds_handler_skl_avx512(void); 1028 void mds_handler_silvermont(void); 1029 void (*mds_handler)(void) = mds_handler_void; 1030 1031 static int 1032 sysctl_hw_mds_disable_state_handler(SYSCTL_HANDLER_ARGS) 1033 { 1034 const char *state; 1035 1036 if (mds_handler == mds_handler_void) 1037 state = "inactive"; 1038 else if (mds_handler == mds_handler_verw) 1039 state = "VERW"; 1040 else if (mds_handler == mds_handler_ivb) 1041 state = "software IvyBridge"; 1042 else if (mds_handler == mds_handler_bdw) 1043 state = "software Broadwell"; 1044 else if (mds_handler == mds_handler_skl_sse) 1045 state = "software Skylake SSE"; 1046 else if (mds_handler == mds_handler_skl_avx) 1047 state = "software Skylake AVX"; 1048 else if (mds_handler == mds_handler_skl_avx512) 1049 state = "software Skylake AVX512"; 1050 else if (mds_handler == mds_handler_silvermont) 1051 state = "software Silvermont"; 1052 else 1053 state = "unknown"; 1054 return (SYSCTL_OUT(req, state, strlen(state))); 1055 } 1056 1057 SYSCTL_PROC(_hw, OID_AUTO, mds_disable_state, 1058 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, 0, 1059 sysctl_hw_mds_disable_state_handler, "A", 1060 "Microarchitectural Data Sampling Mitigation state"); 1061 1062 SYSCTL_NODE(_machdep_mitigations, OID_AUTO, mds, 1063 CTLFLAG_RW | CTLFLAG_MPSAFE, 0, 1064 "Microarchitectural Data Sampling Mitigation state"); 1065 1066 SYSCTL_PROC(_machdep_mitigations_mds, OID_AUTO, state, 1067 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, 0, 1068 sysctl_hw_mds_disable_state_handler, "A", 1069 "Microarchitectural Data Sampling Mitigation state"); 1070 1071 _Static_assert(__offsetof(struct pcpu, pc_mds_tmp) % 64 == 0, "MDS AVX512"); 1072 1073 void 1074 hw_mds_recalculate(void) 1075 { 1076 struct pcpu *pc; 1077 vm_offset_t b64; 1078 u_long xcr0; 1079 int i; 1080 1081 /* 1082 * Allow user to force VERW variant even if MD_CLEAR is not 1083 * reported. For instance, hypervisor might unknowingly 1084 * filter the cap out. 1085 * For the similar reasons, and for testing, allow to enable 1086 * mitigation even when MDS_NO cap is set. 1087 */ 1088 if (cpu_vendor_id != CPU_VENDOR_INTEL || hw_mds_disable == 0 || 1089 ((cpu_ia32_arch_caps & IA32_ARCH_CAP_MDS_NO) != 0 && 1090 hw_mds_disable == 3)) { 1091 mds_handler = mds_handler_void; 1092 } else if (((cpu_stdext_feature3 & CPUID_STDEXT3_MD_CLEAR) != 0 && 1093 hw_mds_disable == 3) || hw_mds_disable == 1) { 1094 mds_handler = mds_handler_verw; 1095 } else if (CPUID_TO_FAMILY(cpu_id) == 0x6 && 1096 (CPUID_TO_MODEL(cpu_id) == 0x2e || CPUID_TO_MODEL(cpu_id) == 0x1e || 1097 CPUID_TO_MODEL(cpu_id) == 0x1f || CPUID_TO_MODEL(cpu_id) == 0x1a || 1098 CPUID_TO_MODEL(cpu_id) == 0x2f || CPUID_TO_MODEL(cpu_id) == 0x25 || 1099 CPUID_TO_MODEL(cpu_id) == 0x2c || CPUID_TO_MODEL(cpu_id) == 0x2d || 1100 CPUID_TO_MODEL(cpu_id) == 0x2a || CPUID_TO_MODEL(cpu_id) == 0x3e || 1101 CPUID_TO_MODEL(cpu_id) == 0x3a) && 1102 (hw_mds_disable == 2 || hw_mds_disable == 3)) { 1103 /* 1104 * Nehalem, SandyBridge, IvyBridge 1105 */ 1106 CPU_FOREACH(i) { 1107 pc = pcpu_find(i); 1108 if (pc->pc_mds_buf == NULL) { 1109 pc->pc_mds_buf = malloc_domainset(672, M_TEMP, 1110 DOMAINSET_PREF(pc->pc_domain), M_WAITOK); 1111 bzero(pc->pc_mds_buf, 16); 1112 } 1113 } 1114 mds_handler = mds_handler_ivb; 1115 } else if (CPUID_TO_FAMILY(cpu_id) == 0x6 && 1116 (CPUID_TO_MODEL(cpu_id) == 0x3f || CPUID_TO_MODEL(cpu_id) == 0x3c || 1117 CPUID_TO_MODEL(cpu_id) == 0x45 || CPUID_TO_MODEL(cpu_id) == 0x46 || 1118 CPUID_TO_MODEL(cpu_id) == 0x56 || CPUID_TO_MODEL(cpu_id) == 0x4f || 1119 CPUID_TO_MODEL(cpu_id) == 0x47 || CPUID_TO_MODEL(cpu_id) == 0x3d) && 1120 (hw_mds_disable == 2 || hw_mds_disable == 3)) { 1121 /* 1122 * Haswell, Broadwell 1123 */ 1124 CPU_FOREACH(i) { 1125 pc = pcpu_find(i); 1126 if (pc->pc_mds_buf == NULL) { 1127 pc->pc_mds_buf = malloc_domainset(1536, M_TEMP, 1128 DOMAINSET_PREF(pc->pc_domain), M_WAITOK); 1129 bzero(pc->pc_mds_buf, 16); 1130 } 1131 } 1132 mds_handler = mds_handler_bdw; 1133 } else if (CPUID_TO_FAMILY(cpu_id) == 0x6 && 1134 ((CPUID_TO_MODEL(cpu_id) == 0x55 && (cpu_id & 1135 CPUID_STEPPING) <= 5) || 1136 CPUID_TO_MODEL(cpu_id) == 0x4e || CPUID_TO_MODEL(cpu_id) == 0x5e || 1137 (CPUID_TO_MODEL(cpu_id) == 0x8e && (cpu_id & 1138 CPUID_STEPPING) <= 0xb) || 1139 (CPUID_TO_MODEL(cpu_id) == 0x9e && (cpu_id & 1140 CPUID_STEPPING) <= 0xc)) && 1141 (hw_mds_disable == 2 || hw_mds_disable == 3)) { 1142 /* 1143 * Skylake, KabyLake, CoffeeLake, WhiskeyLake, 1144 * CascadeLake 1145 */ 1146 CPU_FOREACH(i) { 1147 pc = pcpu_find(i); 1148 if (pc->pc_mds_buf == NULL) { 1149 pc->pc_mds_buf = malloc_domainset(6 * 1024, 1150 M_TEMP, DOMAINSET_PREF(pc->pc_domain), 1151 M_WAITOK); 1152 b64 = (vm_offset_t)malloc_domainset(64 + 63, 1153 M_TEMP, DOMAINSET_PREF(pc->pc_domain), 1154 M_WAITOK); 1155 pc->pc_mds_buf64 = (void *)roundup2(b64, 64); 1156 bzero(pc->pc_mds_buf64, 64); 1157 } 1158 } 1159 xcr0 = rxcr(0); 1160 if ((xcr0 & XFEATURE_ENABLED_ZMM_HI256) != 0 && 1161 (cpu_stdext_feature & CPUID_STDEXT_AVX512DQ) != 0) 1162 mds_handler = mds_handler_skl_avx512; 1163 else if ((xcr0 & XFEATURE_ENABLED_AVX) != 0 && 1164 (cpu_feature2 & CPUID2_AVX) != 0) 1165 mds_handler = mds_handler_skl_avx; 1166 else 1167 mds_handler = mds_handler_skl_sse; 1168 } else if (CPUID_TO_FAMILY(cpu_id) == 0x6 && 1169 ((CPUID_TO_MODEL(cpu_id) == 0x37 || 1170 CPUID_TO_MODEL(cpu_id) == 0x4a || 1171 CPUID_TO_MODEL(cpu_id) == 0x4c || 1172 CPUID_TO_MODEL(cpu_id) == 0x4d || 1173 CPUID_TO_MODEL(cpu_id) == 0x5a || 1174 CPUID_TO_MODEL(cpu_id) == 0x5d || 1175 CPUID_TO_MODEL(cpu_id) == 0x6e || 1176 CPUID_TO_MODEL(cpu_id) == 0x65 || 1177 CPUID_TO_MODEL(cpu_id) == 0x75 || 1178 CPUID_TO_MODEL(cpu_id) == 0x1c || 1179 CPUID_TO_MODEL(cpu_id) == 0x26 || 1180 CPUID_TO_MODEL(cpu_id) == 0x27 || 1181 CPUID_TO_MODEL(cpu_id) == 0x35 || 1182 CPUID_TO_MODEL(cpu_id) == 0x36 || 1183 CPUID_TO_MODEL(cpu_id) == 0x7a))) { 1184 /* Silvermont, Airmont */ 1185 CPU_FOREACH(i) { 1186 pc = pcpu_find(i); 1187 if (pc->pc_mds_buf == NULL) 1188 pc->pc_mds_buf = malloc(256, M_TEMP, M_WAITOK); 1189 } 1190 mds_handler = mds_handler_silvermont; 1191 } else { 1192 hw_mds_disable = 0; 1193 mds_handler = mds_handler_void; 1194 } 1195 } 1196 1197 static void 1198 hw_mds_recalculate_boot(void *arg __unused) 1199 { 1200 1201 hw_mds_recalculate(); 1202 } 1203 SYSINIT(mds_recalc, SI_SUB_SMP, SI_ORDER_ANY, hw_mds_recalculate_boot, NULL); 1204 1205 static int 1206 sysctl_mds_disable_handler(SYSCTL_HANDLER_ARGS) 1207 { 1208 int error, val; 1209 1210 val = hw_mds_disable; 1211 error = sysctl_handle_int(oidp, &val, 0, req); 1212 if (error != 0 || req->newptr == NULL) 1213 return (error); 1214 if (val < 0 || val > 3) 1215 return (EINVAL); 1216 hw_mds_disable = val; 1217 hw_mds_recalculate(); 1218 return (0); 1219 } 1220 1221 SYSCTL_PROC(_hw, OID_AUTO, mds_disable, CTLTYPE_INT | 1222 CTLFLAG_RWTUN | CTLFLAG_NOFETCH | CTLFLAG_MPSAFE, NULL, 0, 1223 sysctl_mds_disable_handler, "I", 1224 "Microarchitectural Data Sampling Mitigation " 1225 "(0 - off, 1 - on VERW, 2 - on SW, 3 - on AUTO"); 1226 1227 SYSCTL_PROC(_machdep_mitigations_mds, OID_AUTO, disable, CTLTYPE_INT | 1228 CTLFLAG_RWTUN | CTLFLAG_NOFETCH | CTLFLAG_MPSAFE, NULL, 0, 1229 sysctl_mds_disable_handler, "I", 1230 "Microarchitectural Data Sampling Mitigation " 1231 "(0 - off, 1 - on VERW, 2 - on SW, 3 - on AUTO"); 1232 1233 /* 1234 * Intel Transactional Memory Asynchronous Abort Mitigation 1235 * CVE-2019-11135 1236 */ 1237 int x86_taa_enable; 1238 int x86_taa_state; 1239 enum { 1240 TAA_NONE = 0, /* No mitigation enabled */ 1241 TAA_TSX_DISABLE = 1, /* Disable TSX via MSR */ 1242 TAA_VERW = 2, /* Use VERW mitigation */ 1243 TAA_AUTO = 3, /* Automatically select the mitigation */ 1244 1245 /* The states below are not selectable by the operator */ 1246 1247 TAA_TAA_UC = 4, /* Mitigation present in microcode */ 1248 TAA_NOT_PRESENT = 5 /* TSX is not present */ 1249 }; 1250 1251 static void 1252 taa_set(bool enable, bool all) 1253 { 1254 1255 x86_msr_op(MSR_IA32_TSX_CTRL, 1256 (enable ? MSR_OP_OR : MSR_OP_ANDNOT) | 1257 (all ? MSR_OP_RENDEZVOUS : MSR_OP_LOCAL), 1258 IA32_TSX_CTRL_RTM_DISABLE | IA32_TSX_CTRL_TSX_CPUID_CLEAR); 1259 } 1260 1261 void 1262 x86_taa_recalculate(void) 1263 { 1264 static int taa_saved_mds_disable = 0; 1265 int taa_need = 0, taa_state = 0; 1266 int mds_disable = 0, need_mds_recalc = 0; 1267 1268 /* Check CPUID.07h.EBX.HLE and RTM for the presence of TSX */ 1269 if ((cpu_stdext_feature & CPUID_STDEXT_HLE) == 0 || 1270 (cpu_stdext_feature & CPUID_STDEXT_RTM) == 0) { 1271 /* TSX is not present */ 1272 x86_taa_state = TAA_NOT_PRESENT; 1273 return; 1274 } 1275 1276 /* Check to see what mitigation options the CPU gives us */ 1277 if (cpu_ia32_arch_caps & IA32_ARCH_CAP_TAA_NO) { 1278 /* CPU is not suseptible to TAA */ 1279 taa_need = TAA_TAA_UC; 1280 } else if (cpu_ia32_arch_caps & IA32_ARCH_CAP_TSX_CTRL) { 1281 /* 1282 * CPU can turn off TSX. This is the next best option 1283 * if TAA_NO hardware mitigation isn't present 1284 */ 1285 taa_need = TAA_TSX_DISABLE; 1286 } else { 1287 /* No TSX/TAA specific remedies are available. */ 1288 if (x86_taa_enable == TAA_TSX_DISABLE) { 1289 if (bootverbose) 1290 printf("TSX control not available\n"); 1291 return; 1292 } else 1293 taa_need = TAA_VERW; 1294 } 1295 1296 /* Can we automatically take action, or are we being forced? */ 1297 if (x86_taa_enable == TAA_AUTO) 1298 taa_state = taa_need; 1299 else 1300 taa_state = x86_taa_enable; 1301 1302 /* No state change, nothing to do */ 1303 if (taa_state == x86_taa_state) { 1304 if (bootverbose) 1305 printf("No TSX change made\n"); 1306 return; 1307 } 1308 1309 /* Does the MSR need to be turned on or off? */ 1310 if (taa_state == TAA_TSX_DISABLE) 1311 taa_set(true, true); 1312 else if (x86_taa_state == TAA_TSX_DISABLE) 1313 taa_set(false, true); 1314 1315 /* Does MDS need to be set to turn on VERW? */ 1316 if (taa_state == TAA_VERW) { 1317 taa_saved_mds_disable = hw_mds_disable; 1318 mds_disable = hw_mds_disable = 1; 1319 need_mds_recalc = 1; 1320 } else if (x86_taa_state == TAA_VERW) { 1321 mds_disable = hw_mds_disable = taa_saved_mds_disable; 1322 need_mds_recalc = 1; 1323 } 1324 if (need_mds_recalc) { 1325 hw_mds_recalculate(); 1326 if (mds_disable != hw_mds_disable) { 1327 if (bootverbose) 1328 printf("Cannot change MDS state for TAA\n"); 1329 /* Don't update our state */ 1330 return; 1331 } 1332 } 1333 1334 x86_taa_state = taa_state; 1335 return; 1336 } 1337 1338 static void 1339 taa_recalculate_boot(void * arg __unused) 1340 { 1341 1342 x86_taa_recalculate(); 1343 } 1344 SYSINIT(taa_recalc, SI_SUB_SMP, SI_ORDER_ANY, taa_recalculate_boot, NULL); 1345 1346 SYSCTL_NODE(_machdep_mitigations, OID_AUTO, taa, 1347 CTLFLAG_RW | CTLFLAG_MPSAFE, 0, 1348 "TSX Asynchronous Abort Mitigation"); 1349 1350 static int 1351 sysctl_taa_handler(SYSCTL_HANDLER_ARGS) 1352 { 1353 int error, val; 1354 1355 val = x86_taa_enable; 1356 error = sysctl_handle_int(oidp, &val, 0, req); 1357 if (error != 0 || req->newptr == NULL) 1358 return (error); 1359 if (val < TAA_NONE || val > TAA_AUTO) 1360 return (EINVAL); 1361 x86_taa_enable = val; 1362 x86_taa_recalculate(); 1363 return (0); 1364 } 1365 1366 SYSCTL_PROC(_machdep_mitigations_taa, OID_AUTO, enable, CTLTYPE_INT | 1367 CTLFLAG_RWTUN | CTLFLAG_NOFETCH | CTLFLAG_MPSAFE, NULL, 0, 1368 sysctl_taa_handler, "I", 1369 "TAA Mitigation enablement control " 1370 "(0 - off, 1 - disable TSX, 2 - VERW, 3 - on AUTO"); 1371 1372 static int 1373 sysctl_taa_state_handler(SYSCTL_HANDLER_ARGS) 1374 { 1375 const char *state; 1376 1377 switch (x86_taa_state) { 1378 case TAA_NONE: 1379 state = "inactive"; 1380 break; 1381 case TAA_TSX_DISABLE: 1382 state = "TSX disabled"; 1383 break; 1384 case TAA_VERW: 1385 state = "VERW"; 1386 break; 1387 case TAA_TAA_UC: 1388 state = "Mitigated in microcode"; 1389 break; 1390 case TAA_NOT_PRESENT: 1391 state = "TSX not present"; 1392 break; 1393 default: 1394 state = "unknown"; 1395 } 1396 1397 return (SYSCTL_OUT(req, state, strlen(state))); 1398 } 1399 1400 SYSCTL_PROC(_machdep_mitigations_taa, OID_AUTO, state, 1401 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, 0, 1402 sysctl_taa_state_handler, "A", 1403 "TAA Mitigation state"); 1404 1405 int __read_frequently cpu_flush_rsb_ctxsw; 1406 SYSCTL_INT(_machdep_mitigations, OID_AUTO, flush_rsb_ctxsw, 1407 CTLFLAG_RW | CTLFLAG_NOFETCH, &cpu_flush_rsb_ctxsw, 0, 1408 "Flush Return Stack Buffer on context switch"); 1409 1410 SYSCTL_NODE(_machdep_mitigations, OID_AUTO, rngds, 1411 CTLFLAG_RW | CTLFLAG_MPSAFE, 0, 1412 "MCU Optimization, disable RDSEED mitigation"); 1413 1414 int x86_rngds_mitg_enable = 1; 1415 void 1416 x86_rngds_mitg_recalculate(bool all_cpus) 1417 { 1418 if ((cpu_stdext_feature3 & CPUID_STDEXT3_MCUOPT) == 0) 1419 return; 1420 x86_msr_op(MSR_IA32_MCU_OPT_CTRL, 1421 (x86_rngds_mitg_enable ? MSR_OP_OR : MSR_OP_ANDNOT) | 1422 (all_cpus ? MSR_OP_RENDEZVOUS : MSR_OP_LOCAL), 1423 IA32_RNGDS_MITG_DIS); 1424 } 1425 1426 static int 1427 sysctl_rngds_mitg_enable_handler(SYSCTL_HANDLER_ARGS) 1428 { 1429 int error, val; 1430 1431 val = x86_rngds_mitg_enable; 1432 error = sysctl_handle_int(oidp, &val, 0, req); 1433 if (error != 0 || req->newptr == NULL) 1434 return (error); 1435 x86_rngds_mitg_enable = val; 1436 x86_rngds_mitg_recalculate(true); 1437 return (0); 1438 } 1439 SYSCTL_PROC(_machdep_mitigations_rngds, OID_AUTO, enable, CTLTYPE_INT | 1440 CTLFLAG_RWTUN | CTLFLAG_NOFETCH | CTLFLAG_MPSAFE, NULL, 0, 1441 sysctl_rngds_mitg_enable_handler, "I", 1442 "MCU Optimization, disabling RDSEED mitigation control " 1443 "(0 - mitigation disabled (RDSEED optimized), 1 - mitigation enabled"); 1444 1445 static int 1446 sysctl_rngds_state_handler(SYSCTL_HANDLER_ARGS) 1447 { 1448 const char *state; 1449 1450 if ((cpu_stdext_feature3 & CPUID_STDEXT3_MCUOPT) == 0) { 1451 state = "Not applicable"; 1452 } else if (x86_rngds_mitg_enable == 0) { 1453 state = "RDSEED not serialized"; 1454 } else { 1455 state = "Mitigated"; 1456 } 1457 return (SYSCTL_OUT(req, state, strlen(state))); 1458 } 1459 SYSCTL_PROC(_machdep_mitigations_rngds, OID_AUTO, state, 1460 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, 0, 1461 sysctl_rngds_state_handler, "A", 1462 "MCU Optimization state"); 1463 1464 /* 1465 * Enable and restore kernel text write permissions. 1466 * Callers must ensure that disable_wp()/restore_wp() are executed 1467 * without rescheduling on the same core. 1468 */ 1469 bool 1470 disable_wp(void) 1471 { 1472 u_int cr0; 1473 1474 cr0 = rcr0(); 1475 if ((cr0 & CR0_WP) == 0) 1476 return (false); 1477 load_cr0(cr0 & ~CR0_WP); 1478 return (true); 1479 } 1480 1481 void 1482 restore_wp(bool old_wp) 1483 { 1484 1485 if (old_wp) 1486 load_cr0(rcr0() | CR0_WP); 1487 } 1488 1489 bool 1490 acpi_get_fadt_bootflags(uint16_t *flagsp) 1491 { 1492 #ifdef DEV_ACPI 1493 ACPI_TABLE_FADT *fadt; 1494 vm_paddr_t physaddr; 1495 1496 physaddr = acpi_find_table(ACPI_SIG_FADT); 1497 if (physaddr == 0) 1498 return (false); 1499 fadt = acpi_map_table(physaddr, ACPI_SIG_FADT); 1500 if (fadt == NULL) 1501 return (false); 1502 *flagsp = fadt->BootFlags; 1503 acpi_unmap_table(fadt); 1504 return (true); 1505 #else 1506 return (false); 1507 #endif 1508 } 1509