1 /*- 2 * Copyright (c) 2003 Peter Wemm. 3 * Copyright (c) 1992 Terrence R. Lambert. 4 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * William Jolitz. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the University of 21 * California, Berkeley and its contributors. 22 * 4. Neither the name of the University nor the names of its contributors 23 * may be used to endorse or promote products derived from this software 24 * without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 * 38 * from: @(#)machdep.c 7.4 (Berkeley) 6/3/91 39 */ 40 41 #include <sys/cdefs.h> 42 __FBSDID("$FreeBSD$"); 43 44 #include "opt_acpi.h" 45 #include "opt_atpic.h" 46 #include "opt_cpu.h" 47 #include "opt_ddb.h" 48 #include "opt_inet.h" 49 #include "opt_isa.h" 50 #include "opt_kdb.h" 51 #include "opt_kstack_pages.h" 52 #include "opt_maxmem.h" 53 #include "opt_platform.h" 54 #include "opt_sched.h" 55 #ifdef __i386__ 56 #include "opt_apic.h" 57 #endif 58 59 #include <sys/param.h> 60 #include <sys/proc.h> 61 #include <sys/systm.h> 62 #include <sys/bus.h> 63 #include <sys/cpu.h> 64 #include <sys/domainset.h> 65 #include <sys/kdb.h> 66 #include <sys/kernel.h> 67 #include <sys/ktr.h> 68 #include <sys/lock.h> 69 #include <sys/malloc.h> 70 #include <sys/mutex.h> 71 #include <sys/pcpu.h> 72 #include <sys/rwlock.h> 73 #include <sys/sched.h> 74 #include <sys/smp.h> 75 #include <sys/sysctl.h> 76 77 #include <machine/clock.h> 78 #include <machine/cpu.h> 79 #include <machine/cpufunc.h> 80 #include <machine/cputypes.h> 81 #include <machine/specialreg.h> 82 #include <machine/md_var.h> 83 #include <machine/tss.h> 84 #ifdef SMP 85 #include <machine/smp.h> 86 #endif 87 #ifdef CPU_ELAN 88 #include <machine/elan_mmcr.h> 89 #endif 90 #include <x86/acpica_machdep.h> 91 #include <x86/ifunc.h> 92 93 #include <vm/vm.h> 94 #include <vm/vm_extern.h> 95 #include <vm/vm_kern.h> 96 #include <vm/vm_page.h> 97 #include <vm/vm_map.h> 98 #include <vm/vm_object.h> 99 #include <vm/vm_pager.h> 100 #include <vm/vm_param.h> 101 102 #include <isa/isareg.h> 103 104 #include <contrib/dev/acpica/include/acpi.h> 105 106 #define STATE_RUNNING 0x0 107 #define STATE_MWAIT 0x1 108 #define STATE_SLEEPING 0x2 109 110 #ifdef SMP 111 static u_int cpu_reset_proxyid; 112 static volatile u_int cpu_reset_proxy_active; 113 #endif 114 115 char bootmethod[16]; 116 SYSCTL_STRING(_machdep, OID_AUTO, bootmethod, CTLFLAG_RD, bootmethod, 0, 117 "System firmware boot method"); 118 119 struct msr_op_arg { 120 u_int msr; 121 int op; 122 uint64_t arg1; 123 uint64_t *res; 124 }; 125 126 static void 127 x86_msr_op_one(void *argp) 128 { 129 struct msr_op_arg *a; 130 uint64_t v; 131 132 a = argp; 133 switch (a->op) { 134 case MSR_OP_ANDNOT: 135 v = rdmsr(a->msr); 136 v &= ~a->arg1; 137 wrmsr(a->msr, v); 138 break; 139 case MSR_OP_OR: 140 v = rdmsr(a->msr); 141 v |= a->arg1; 142 wrmsr(a->msr, v); 143 break; 144 case MSR_OP_WRITE: 145 wrmsr(a->msr, a->arg1); 146 break; 147 case MSR_OP_READ: 148 v = rdmsr(a->msr); 149 *a->res = v; 150 break; 151 } 152 } 153 154 #define MSR_OP_EXMODE_MASK 0xf0000000 155 #define MSR_OP_OP_MASK 0x000000ff 156 #define MSR_OP_GET_CPUID(x) (((x) & ~MSR_OP_EXMODE_MASK) >> 8) 157 158 void 159 x86_msr_op(u_int msr, u_int op, uint64_t arg1, uint64_t *res) 160 { 161 struct thread *td; 162 struct msr_op_arg a; 163 cpuset_t set; 164 u_int exmode; 165 int bound_cpu, cpu, i, is_bound; 166 167 a.op = op & MSR_OP_OP_MASK; 168 MPASS(a.op == MSR_OP_ANDNOT || a.op == MSR_OP_OR || 169 a.op == MSR_OP_WRITE || a.op == MSR_OP_READ); 170 exmode = op & MSR_OP_EXMODE_MASK; 171 MPASS(exmode == MSR_OP_LOCAL || exmode == MSR_OP_SCHED_ALL || 172 exmode == MSR_OP_SCHED_ONE || exmode == MSR_OP_RENDEZVOUS_ALL || 173 exmode == MSR_OP_RENDEZVOUS_ONE); 174 a.msr = msr; 175 a.arg1 = arg1; 176 a.res = res; 177 switch (exmode) { 178 case MSR_OP_LOCAL: 179 x86_msr_op_one(&a); 180 break; 181 case MSR_OP_SCHED_ALL: 182 td = curthread; 183 thread_lock(td); 184 is_bound = sched_is_bound(td); 185 bound_cpu = td->td_oncpu; 186 CPU_FOREACH(i) { 187 sched_bind(td, i); 188 x86_msr_op_one(&a); 189 } 190 if (is_bound) 191 sched_bind(td, bound_cpu); 192 else 193 sched_unbind(td); 194 thread_unlock(td); 195 break; 196 case MSR_OP_SCHED_ONE: 197 td = curthread; 198 cpu = MSR_OP_GET_CPUID(op); 199 thread_lock(td); 200 is_bound = sched_is_bound(td); 201 bound_cpu = td->td_oncpu; 202 if (!is_bound || bound_cpu != cpu) 203 sched_bind(td, cpu); 204 x86_msr_op_one(&a); 205 if (is_bound) { 206 if (bound_cpu != cpu) 207 sched_bind(td, bound_cpu); 208 } else { 209 sched_unbind(td); 210 } 211 thread_unlock(td); 212 break; 213 case MSR_OP_RENDEZVOUS_ALL: 214 smp_rendezvous(smp_no_rendezvous_barrier, x86_msr_op_one, 215 smp_no_rendezvous_barrier, &a); 216 break; 217 case MSR_OP_RENDEZVOUS_ONE: 218 cpu = MSR_OP_GET_CPUID(op); 219 CPU_SETOF(cpu, &set); 220 smp_rendezvous_cpus(set, smp_no_rendezvous_barrier, 221 x86_msr_op_one, smp_no_rendezvous_barrier, &a); 222 break; 223 } 224 } 225 226 /* 227 * Automatically initialized per CPU errata in cpu_idle_tun below. 228 */ 229 bool mwait_cpustop_broken = false; 230 SYSCTL_BOOL(_machdep, OID_AUTO, mwait_cpustop_broken, CTLFLAG_RDTUN, 231 &mwait_cpustop_broken, 0, 232 "Can not reliably wake MONITOR/MWAIT cpus without interrupts"); 233 234 /* 235 * Flush the D-cache for non-DMA I/O so that the I-cache can 236 * be made coherent later. 237 */ 238 void 239 cpu_flush_dcache(void *ptr, size_t len) 240 { 241 /* Not applicable */ 242 } 243 244 void 245 acpi_cpu_c1(void) 246 { 247 248 __asm __volatile("sti; hlt"); 249 } 250 251 /* 252 * Use mwait to pause execution while waiting for an interrupt or 253 * another thread to signal that there is more work. 254 * 255 * NOTE: Interrupts will cause a wakeup; however, this function does 256 * not enable interrupt handling. The caller is responsible to enable 257 * interrupts. 258 */ 259 void 260 acpi_cpu_idle_mwait(uint32_t mwait_hint) 261 { 262 int *state; 263 uint64_t v; 264 265 /* 266 * A comment in Linux patch claims that 'CPUs run faster with 267 * speculation protection disabled. All CPU threads in a core 268 * must disable speculation protection for it to be 269 * disabled. Disable it while we are idle so the other 270 * hyperthread can run fast.' 271 * 272 * XXXKIB. Software coordination mode should be supported, 273 * but all Intel CPUs provide hardware coordination. 274 */ 275 276 state = &PCPU_PTR(monitorbuf)->idle_state; 277 KASSERT(atomic_load_int(state) == STATE_SLEEPING, 278 ("cpu_mwait_cx: wrong monitorbuf state")); 279 atomic_store_int(state, STATE_MWAIT); 280 if (PCPU_GET(ibpb_set) || hw_ssb_active) { 281 v = rdmsr(MSR_IA32_SPEC_CTRL); 282 wrmsr(MSR_IA32_SPEC_CTRL, v & ~(IA32_SPEC_CTRL_IBRS | 283 IA32_SPEC_CTRL_STIBP | IA32_SPEC_CTRL_SSBD)); 284 } else { 285 v = 0; 286 } 287 cpu_monitor(state, 0, 0); 288 if (atomic_load_int(state) == STATE_MWAIT) 289 cpu_mwait(MWAIT_INTRBREAK, mwait_hint); 290 291 /* 292 * SSB cannot be disabled while we sleep, or rather, if it was 293 * disabled, the sysctl thread will bind to our cpu to tweak 294 * MSR. 295 */ 296 if (v != 0) 297 wrmsr(MSR_IA32_SPEC_CTRL, v); 298 299 /* 300 * We should exit on any event that interrupts mwait, because 301 * that event might be a wanted interrupt. 302 */ 303 atomic_store_int(state, STATE_RUNNING); 304 } 305 306 /* Get current clock frequency for the given cpu id. */ 307 int 308 cpu_est_clockrate(int cpu_id, uint64_t *rate) 309 { 310 uint64_t tsc1, tsc2; 311 uint64_t acnt, mcnt, perf; 312 register_t reg; 313 314 if (pcpu_find(cpu_id) == NULL || rate == NULL) 315 return (EINVAL); 316 #ifdef __i386__ 317 if ((cpu_feature & CPUID_TSC) == 0) 318 return (EOPNOTSUPP); 319 #endif 320 321 /* 322 * If TSC is P-state invariant and APERF/MPERF MSRs do not exist, 323 * DELAY(9) based logic fails. 324 */ 325 if (tsc_is_invariant && !tsc_perf_stat) 326 return (EOPNOTSUPP); 327 328 #ifdef SMP 329 if (smp_cpus > 1) { 330 /* Schedule ourselves on the indicated cpu. */ 331 thread_lock(curthread); 332 sched_bind(curthread, cpu_id); 333 thread_unlock(curthread); 334 } 335 #endif 336 337 /* Calibrate by measuring a short delay. */ 338 reg = intr_disable(); 339 if (tsc_is_invariant) { 340 wrmsr(MSR_MPERF, 0); 341 wrmsr(MSR_APERF, 0); 342 tsc1 = rdtsc(); 343 DELAY(1000); 344 mcnt = rdmsr(MSR_MPERF); 345 acnt = rdmsr(MSR_APERF); 346 tsc2 = rdtsc(); 347 intr_restore(reg); 348 perf = 1000 * acnt / mcnt; 349 *rate = (tsc2 - tsc1) * perf; 350 } else { 351 tsc1 = rdtsc(); 352 DELAY(1000); 353 tsc2 = rdtsc(); 354 intr_restore(reg); 355 *rate = (tsc2 - tsc1) * 1000; 356 } 357 358 #ifdef SMP 359 if (smp_cpus > 1) { 360 thread_lock(curthread); 361 sched_unbind(curthread); 362 thread_unlock(curthread); 363 } 364 #endif 365 366 return (0); 367 } 368 369 /* 370 * Shutdown the CPU as much as possible 371 */ 372 void 373 cpu_halt(void) 374 { 375 for (;;) 376 halt(); 377 } 378 379 static void 380 cpu_reset_real(void) 381 { 382 struct region_descriptor null_idt; 383 int b; 384 385 disable_intr(); 386 #ifdef CPU_ELAN 387 if (elan_mmcr != NULL) 388 elan_mmcr->RESCFG = 1; 389 #endif 390 #ifdef __i386__ 391 if (cpu == CPU_GEODE1100) { 392 /* Attempt Geode's own reset */ 393 outl(0xcf8, 0x80009044ul); 394 outl(0xcfc, 0xf); 395 } 396 #endif 397 #if !defined(BROKEN_KEYBOARD_RESET) 398 /* 399 * Attempt to do a CPU reset via the keyboard controller, 400 * do not turn off GateA20, as any machine that fails 401 * to do the reset here would then end up in no man's land. 402 */ 403 outb(IO_KBD + 4, 0xFE); 404 DELAY(500000); /* wait 0.5 sec to see if that did it */ 405 #endif 406 407 /* 408 * Attempt to force a reset via the Reset Control register at 409 * I/O port 0xcf9. Bit 2 forces a system reset when it 410 * transitions from 0 to 1. Bit 1 selects the type of reset 411 * to attempt: 0 selects a "soft" reset, and 1 selects a 412 * "hard" reset. We try a "hard" reset. The first write sets 413 * bit 1 to select a "hard" reset and clears bit 2. The 414 * second write forces a 0 -> 1 transition in bit 2 to trigger 415 * a reset. 416 */ 417 outb(0xcf9, 0x2); 418 outb(0xcf9, 0x6); 419 DELAY(500000); /* wait 0.5 sec to see if that did it */ 420 421 /* 422 * Attempt to force a reset via the Fast A20 and Init register 423 * at I/O port 0x92. Bit 1 serves as an alternate A20 gate. 424 * Bit 0 asserts INIT# when set to 1. We are careful to only 425 * preserve bit 1 while setting bit 0. We also must clear bit 426 * 0 before setting it if it isn't already clear. 427 */ 428 b = inb(0x92); 429 if (b != 0xff) { 430 if ((b & 0x1) != 0) 431 outb(0x92, b & 0xfe); 432 outb(0x92, b | 0x1); 433 DELAY(500000); /* wait 0.5 sec to see if that did it */ 434 } 435 436 printf("No known reset method worked, attempting CPU shutdown\n"); 437 DELAY(1000000); /* wait 1 sec for printf to complete */ 438 439 /* Wipe the IDT. */ 440 null_idt.rd_limit = 0; 441 null_idt.rd_base = 0; 442 lidt(&null_idt); 443 444 /* "good night, sweet prince .... <THUNK!>" */ 445 breakpoint(); 446 447 /* NOTREACHED */ 448 while(1); 449 } 450 451 #ifdef SMP 452 static void 453 cpu_reset_proxy(void) 454 { 455 456 cpu_reset_proxy_active = 1; 457 while (cpu_reset_proxy_active == 1) 458 ia32_pause(); /* Wait for other cpu to see that we've started */ 459 460 printf("cpu_reset_proxy: Stopped CPU %d\n", cpu_reset_proxyid); 461 DELAY(1000000); 462 cpu_reset_real(); 463 } 464 #endif 465 466 void 467 cpu_reset(void) 468 { 469 #ifdef SMP 470 struct monitorbuf *mb; 471 cpuset_t map; 472 u_int cnt; 473 474 if (smp_started) { 475 map = all_cpus; 476 CPU_CLR(PCPU_GET(cpuid), &map); 477 CPU_ANDNOT(&map, &map, &stopped_cpus); 478 if (!CPU_EMPTY(&map)) { 479 printf("cpu_reset: Stopping other CPUs\n"); 480 stop_cpus(map); 481 } 482 483 if (PCPU_GET(cpuid) != 0) { 484 cpu_reset_proxyid = PCPU_GET(cpuid); 485 cpustop_restartfunc = cpu_reset_proxy; 486 cpu_reset_proxy_active = 0; 487 printf("cpu_reset: Restarting BSP\n"); 488 489 /* Restart CPU #0. */ 490 CPU_SETOF(0, &started_cpus); 491 mb = &pcpu_find(0)->pc_monitorbuf; 492 atomic_store_int(&mb->stop_state, 493 MONITOR_STOPSTATE_RUNNING); 494 495 cnt = 0; 496 while (cpu_reset_proxy_active == 0 && cnt < 10000000) { 497 ia32_pause(); 498 cnt++; /* Wait for BSP to announce restart */ 499 } 500 if (cpu_reset_proxy_active == 0) { 501 printf("cpu_reset: Failed to restart BSP\n"); 502 } else { 503 cpu_reset_proxy_active = 2; 504 while (1) 505 ia32_pause(); 506 /* NOTREACHED */ 507 } 508 } 509 } 510 #endif 511 cpu_reset_real(); 512 /* NOTREACHED */ 513 } 514 515 bool 516 cpu_mwait_usable(void) 517 { 518 519 return ((cpu_feature2 & CPUID2_MON) != 0 && ((cpu_mon_mwait_flags & 520 (CPUID5_MON_MWAIT_EXT | CPUID5_MWAIT_INTRBREAK)) == 521 (CPUID5_MON_MWAIT_EXT | CPUID5_MWAIT_INTRBREAK))); 522 } 523 524 void (*cpu_idle_hook)(sbintime_t) = NULL; /* ACPI idle hook. */ 525 526 int cpu_amdc1e_bug = 0; /* AMD C1E APIC workaround required. */ 527 528 static int idle_mwait = 1; /* Use MONITOR/MWAIT for short idle. */ 529 SYSCTL_INT(_machdep, OID_AUTO, idle_mwait, CTLFLAG_RWTUN, &idle_mwait, 530 0, "Use MONITOR/MWAIT for short idle"); 531 532 static bool 533 cpu_idle_enter(int *statep, int newstate) 534 { 535 KASSERT(atomic_load_int(statep) == STATE_RUNNING, 536 ("%s: state %d", __func__, atomic_load_int(statep))); 537 538 /* 539 * A fence is needed to prevent reordering of the load in 540 * sched_runnable() with this store to the idle state word. Without it, 541 * cpu_idle_wakeup() can observe the state as STATE_RUNNING after having 542 * added load to the queue, and elide an IPI. Then, sched_runnable() 543 * can observe tdq_load == 0, so the CPU ends up idling with pending 544 * work. tdq_notify() similarly ensures that a prior update to tdq_load 545 * is visible before calling cpu_idle_wakeup(). 546 */ 547 atomic_store_int(statep, newstate); 548 #if defined(SCHED_ULE) && defined(SMP) 549 atomic_thread_fence_seq_cst(); 550 #endif 551 552 /* 553 * Since we may be in a critical section from cpu_idle(), if 554 * an interrupt fires during that critical section we may have 555 * a pending preemption. If the CPU halts, then that thread 556 * may not execute until a later interrupt awakens the CPU. 557 * To handle this race, check for a runnable thread after 558 * disabling interrupts and immediately return if one is 559 * found. Also, we must absolutely guarentee that hlt is 560 * the next instruction after sti. This ensures that any 561 * interrupt that fires after the call to disable_intr() will 562 * immediately awaken the CPU from hlt. Finally, please note 563 * that on x86 this works fine because of interrupts enabled only 564 * after the instruction following sti takes place, while IF is set 565 * to 1 immediately, allowing hlt instruction to acknowledge the 566 * interrupt. 567 */ 568 disable_intr(); 569 if (sched_runnable()) { 570 enable_intr(); 571 atomic_store_int(statep, STATE_RUNNING); 572 return (false); 573 } else { 574 return (true); 575 } 576 } 577 578 static void 579 cpu_idle_exit(int *statep) 580 { 581 atomic_store_int(statep, STATE_RUNNING); 582 } 583 584 static void 585 cpu_idle_acpi(sbintime_t sbt) 586 { 587 int *state; 588 589 state = &PCPU_PTR(monitorbuf)->idle_state; 590 if (cpu_idle_enter(state, STATE_SLEEPING)) { 591 if (cpu_idle_hook) 592 cpu_idle_hook(sbt); 593 else 594 acpi_cpu_c1(); 595 cpu_idle_exit(state); 596 } 597 } 598 599 static void 600 cpu_idle_hlt(sbintime_t sbt) 601 { 602 int *state; 603 604 state = &PCPU_PTR(monitorbuf)->idle_state; 605 if (cpu_idle_enter(state, STATE_SLEEPING)) { 606 acpi_cpu_c1(); 607 atomic_store_int(state, STATE_RUNNING); 608 } 609 } 610 611 static void 612 cpu_idle_mwait(sbintime_t sbt) 613 { 614 int *state; 615 616 state = &PCPU_PTR(monitorbuf)->idle_state; 617 if (cpu_idle_enter(state, STATE_MWAIT)) { 618 cpu_monitor(state, 0, 0); 619 if (atomic_load_int(state) == STATE_MWAIT) 620 __asm __volatile("sti; mwait" : : "a" (MWAIT_C1), "c" (0)); 621 else 622 enable_intr(); 623 cpu_idle_exit(state); 624 } 625 } 626 627 static void 628 cpu_idle_spin(sbintime_t sbt) 629 { 630 int *state; 631 int i; 632 633 state = &PCPU_PTR(monitorbuf)->idle_state; 634 atomic_store_int(state, STATE_RUNNING); 635 636 /* 637 * The sched_runnable() call is racy but as long as there is 638 * a loop missing it one time will have just a little impact if any 639 * (and it is much better than missing the check at all). 640 */ 641 for (i = 0; i < 1000; i++) { 642 if (sched_runnable()) 643 return; 644 cpu_spinwait(); 645 } 646 } 647 648 void (*cpu_idle_fn)(sbintime_t) = cpu_idle_acpi; 649 650 void 651 cpu_idle(int busy) 652 { 653 uint64_t msr; 654 sbintime_t sbt = -1; 655 656 CTR1(KTR_SPARE2, "cpu_idle(%d)", busy); 657 658 /* If we are busy - try to use fast methods. */ 659 if (busy) { 660 if ((cpu_feature2 & CPUID2_MON) && idle_mwait) { 661 cpu_idle_mwait(busy); 662 goto out; 663 } 664 } 665 666 /* If we have time - switch timers into idle mode. */ 667 if (!busy) { 668 critical_enter(); 669 sbt = cpu_idleclock(); 670 } 671 672 /* Apply AMD APIC timer C1E workaround. */ 673 if (cpu_amdc1e_bug && cpu_disable_c3_sleep) { 674 msr = rdmsr(MSR_AMDK8_IPM); 675 if ((msr & (AMDK8_SMIONCMPHALT | AMDK8_C1EONCMPHALT)) != 0) 676 wrmsr(MSR_AMDK8_IPM, msr & ~(AMDK8_SMIONCMPHALT | 677 AMDK8_C1EONCMPHALT)); 678 } 679 680 /* Call main idle method. */ 681 cpu_idle_fn(sbt); 682 683 /* Switch timers back into active mode. */ 684 if (!busy) { 685 cpu_activeclock(); 686 critical_exit(); 687 } 688 out: 689 CTR1(KTR_SPARE2, "cpu_idle(%d) done", busy); 690 } 691 692 static int cpu_idle_apl31_workaround; 693 SYSCTL_INT(_machdep, OID_AUTO, idle_apl31, CTLFLAG_RW, 694 &cpu_idle_apl31_workaround, 0, 695 "Apollo Lake APL31 MWAIT bug workaround"); 696 697 int 698 cpu_idle_wakeup(int cpu) 699 { 700 struct monitorbuf *mb; 701 int *state; 702 703 mb = &pcpu_find(cpu)->pc_monitorbuf; 704 state = &mb->idle_state; 705 switch (atomic_load_int(state)) { 706 case STATE_SLEEPING: 707 return (0); 708 case STATE_MWAIT: 709 atomic_store_int(state, STATE_RUNNING); 710 return (cpu_idle_apl31_workaround ? 0 : 1); 711 case STATE_RUNNING: 712 return (1); 713 default: 714 panic("bad monitor state"); 715 return (1); 716 } 717 } 718 719 /* 720 * Ordered by speed/power consumption. 721 */ 722 static const struct { 723 void *id_fn; 724 const char *id_name; 725 int id_cpuid2_flag; 726 } idle_tbl[] = { 727 { .id_fn = cpu_idle_spin, .id_name = "spin" }, 728 { .id_fn = cpu_idle_mwait, .id_name = "mwait", 729 .id_cpuid2_flag = CPUID2_MON }, 730 { .id_fn = cpu_idle_hlt, .id_name = "hlt" }, 731 { .id_fn = cpu_idle_acpi, .id_name = "acpi" }, 732 }; 733 734 static int 735 idle_sysctl_available(SYSCTL_HANDLER_ARGS) 736 { 737 char *avail, *p; 738 int error; 739 int i; 740 741 avail = malloc(256, M_TEMP, M_WAITOK); 742 p = avail; 743 for (i = 0; i < nitems(idle_tbl); i++) { 744 if (idle_tbl[i].id_cpuid2_flag != 0 && 745 (cpu_feature2 & idle_tbl[i].id_cpuid2_flag) == 0) 746 continue; 747 if (strcmp(idle_tbl[i].id_name, "acpi") == 0 && 748 cpu_idle_hook == NULL) 749 continue; 750 p += sprintf(p, "%s%s", p != avail ? ", " : "", 751 idle_tbl[i].id_name); 752 } 753 error = sysctl_handle_string(oidp, avail, 0, req); 754 free(avail, M_TEMP); 755 return (error); 756 } 757 758 SYSCTL_PROC(_machdep, OID_AUTO, idle_available, 759 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, 760 0, 0, idle_sysctl_available, "A", 761 "list of available idle functions"); 762 763 static bool 764 cpu_idle_selector(const char *new_idle_name) 765 { 766 int i; 767 768 for (i = 0; i < nitems(idle_tbl); i++) { 769 if (idle_tbl[i].id_cpuid2_flag != 0 && 770 (cpu_feature2 & idle_tbl[i].id_cpuid2_flag) == 0) 771 continue; 772 if (strcmp(idle_tbl[i].id_name, "acpi") == 0 && 773 cpu_idle_hook == NULL) 774 continue; 775 if (strcmp(idle_tbl[i].id_name, new_idle_name)) 776 continue; 777 cpu_idle_fn = idle_tbl[i].id_fn; 778 if (bootverbose) 779 printf("CPU idle set to %s\n", idle_tbl[i].id_name); 780 return (true); 781 } 782 return (false); 783 } 784 785 static int 786 cpu_idle_sysctl(SYSCTL_HANDLER_ARGS) 787 { 788 char buf[16]; 789 const char *p; 790 int error, i; 791 792 p = "unknown"; 793 for (i = 0; i < nitems(idle_tbl); i++) { 794 if (idle_tbl[i].id_fn == cpu_idle_fn) { 795 p = idle_tbl[i].id_name; 796 break; 797 } 798 } 799 strncpy(buf, p, sizeof(buf)); 800 error = sysctl_handle_string(oidp, buf, sizeof(buf), req); 801 if (error != 0 || req->newptr == NULL) 802 return (error); 803 return (cpu_idle_selector(buf) ? 0 : EINVAL); 804 } 805 806 SYSCTL_PROC(_machdep, OID_AUTO, idle, 807 CTLTYPE_STRING | CTLFLAG_RW | CTLFLAG_MPSAFE, 808 0, 0, cpu_idle_sysctl, "A", 809 "currently selected idle function"); 810 811 static void 812 cpu_idle_tun(void *unused __unused) 813 { 814 char tunvar[16]; 815 816 if (TUNABLE_STR_FETCH("machdep.idle", tunvar, sizeof(tunvar))) 817 cpu_idle_selector(tunvar); 818 else if (cpu_vendor_id == CPU_VENDOR_AMD && 819 CPUID_TO_FAMILY(cpu_id) == 0x17 && CPUID_TO_MODEL(cpu_id) == 0x1) { 820 /* Ryzen erratas 1057, 1109. */ 821 cpu_idle_selector("hlt"); 822 idle_mwait = 0; 823 mwait_cpustop_broken = true; 824 } 825 826 if (cpu_vendor_id == CPU_VENDOR_INTEL && 827 CPUID_TO_FAMILY(cpu_id) == 0x6 && CPUID_TO_MODEL(cpu_id) == 0x5c) { 828 /* 829 * Apollo Lake errata APL31 (public errata APL30). 830 * Stores to the armed address range may not trigger 831 * MWAIT to resume execution. OS needs to use 832 * interrupts to wake processors from MWAIT-induced 833 * sleep states. 834 */ 835 cpu_idle_apl31_workaround = 1; 836 mwait_cpustop_broken = true; 837 } 838 TUNABLE_INT_FETCH("machdep.idle_apl31", &cpu_idle_apl31_workaround); 839 } 840 SYSINIT(cpu_idle_tun, SI_SUB_CPU, SI_ORDER_MIDDLE, cpu_idle_tun, NULL); 841 842 static int panic_on_nmi = 0xff; 843 SYSCTL_INT(_machdep, OID_AUTO, panic_on_nmi, CTLFLAG_RWTUN, 844 &panic_on_nmi, 0, 845 "Panic on NMI: 1 = H/W failure; 2 = unknown; 0xff = all"); 846 int nmi_is_broadcast = 1; 847 SYSCTL_INT(_machdep, OID_AUTO, nmi_is_broadcast, CTLFLAG_RWTUN, 848 &nmi_is_broadcast, 0, 849 "Chipset NMI is broadcast"); 850 int (*apei_nmi)(void); 851 852 void 853 nmi_call_kdb(u_int cpu, u_int type, struct trapframe *frame) 854 { 855 bool claimed = false; 856 857 #ifdef DEV_ISA 858 /* machine/parity/power fail/"kitchen sink" faults */ 859 if (isa_nmi(frame->tf_err)) { 860 claimed = true; 861 if ((panic_on_nmi & 1) != 0) 862 panic("NMI indicates hardware failure"); 863 } 864 #endif /* DEV_ISA */ 865 866 /* ACPI Platform Error Interfaces callback. */ 867 if (apei_nmi != NULL && (*apei_nmi)()) 868 claimed = true; 869 870 /* 871 * NMIs can be useful for debugging. They can be hooked up to a 872 * pushbutton, usually on an ISA, PCI, or PCIe card. They can also be 873 * generated by an IPMI BMC, either manually or in response to a 874 * watchdog timeout. For example, see the "power diag" command in 875 * ports/sysutils/ipmitool. They can also be generated by a 876 * hypervisor; see "bhyvectl --inject-nmi". 877 */ 878 879 #ifdef KDB 880 if (!claimed && (panic_on_nmi & 2) != 0) { 881 if (debugger_on_panic) { 882 printf("NMI/cpu%d ... going to debugger\n", cpu); 883 claimed = kdb_trap(type, 0, frame); 884 } 885 } 886 #endif /* KDB */ 887 888 if (!claimed && panic_on_nmi != 0) 889 panic("NMI"); 890 } 891 892 void 893 nmi_handle_intr(u_int type, struct trapframe *frame) 894 { 895 896 #ifdef SMP 897 if (nmi_is_broadcast) { 898 nmi_call_kdb_smp(type, frame); 899 return; 900 } 901 #endif 902 nmi_call_kdb(PCPU_GET(cpuid), type, frame); 903 } 904 905 static int hw_ibrs_active; 906 int hw_ibrs_ibpb_active; 907 int hw_ibrs_disable = 1; 908 909 SYSCTL_INT(_hw, OID_AUTO, ibrs_active, CTLFLAG_RD, &hw_ibrs_active, 0, 910 "Indirect Branch Restricted Speculation active"); 911 912 SYSCTL_NODE(_machdep_mitigations, OID_AUTO, ibrs, 913 CTLFLAG_RW | CTLFLAG_MPSAFE, 0, 914 "Indirect Branch Restricted Speculation active"); 915 916 SYSCTL_INT(_machdep_mitigations_ibrs, OID_AUTO, active, CTLFLAG_RD, 917 &hw_ibrs_active, 0, "Indirect Branch Restricted Speculation active"); 918 919 void 920 hw_ibrs_recalculate(bool for_all_cpus) 921 { 922 if ((cpu_ia32_arch_caps & IA32_ARCH_CAP_IBRS_ALL) != 0) { 923 x86_msr_op(MSR_IA32_SPEC_CTRL, (for_all_cpus ? 924 MSR_OP_RENDEZVOUS_ALL : MSR_OP_LOCAL) | 925 (hw_ibrs_disable != 0 ? MSR_OP_ANDNOT : MSR_OP_OR), 926 IA32_SPEC_CTRL_IBRS, NULL); 927 hw_ibrs_active = hw_ibrs_disable == 0; 928 hw_ibrs_ibpb_active = 0; 929 } else { 930 hw_ibrs_active = hw_ibrs_ibpb_active = (cpu_stdext_feature3 & 931 CPUID_STDEXT3_IBPB) != 0 && !hw_ibrs_disable; 932 } 933 } 934 935 static int 936 hw_ibrs_disable_handler(SYSCTL_HANDLER_ARGS) 937 { 938 int error, val; 939 940 val = hw_ibrs_disable; 941 error = sysctl_handle_int(oidp, &val, 0, req); 942 if (error != 0 || req->newptr == NULL) 943 return (error); 944 hw_ibrs_disable = val != 0; 945 hw_ibrs_recalculate(true); 946 return (0); 947 } 948 SYSCTL_PROC(_hw, OID_AUTO, ibrs_disable, CTLTYPE_INT | CTLFLAG_RWTUN | 949 CTLFLAG_NOFETCH | CTLFLAG_MPSAFE, NULL, 0, hw_ibrs_disable_handler, "I", 950 "Disable Indirect Branch Restricted Speculation"); 951 952 SYSCTL_PROC(_machdep_mitigations_ibrs, OID_AUTO, disable, CTLTYPE_INT | 953 CTLFLAG_RWTUN | CTLFLAG_NOFETCH | CTLFLAG_MPSAFE, NULL, 0, 954 hw_ibrs_disable_handler, "I", 955 "Disable Indirect Branch Restricted Speculation"); 956 957 int hw_ssb_active; 958 int hw_ssb_disable; 959 960 SYSCTL_INT(_hw, OID_AUTO, spec_store_bypass_disable_active, CTLFLAG_RD, 961 &hw_ssb_active, 0, 962 "Speculative Store Bypass Disable active"); 963 964 SYSCTL_NODE(_machdep_mitigations, OID_AUTO, ssb, 965 CTLFLAG_RW | CTLFLAG_MPSAFE, 0, 966 "Speculative Store Bypass Disable active"); 967 968 SYSCTL_INT(_machdep_mitigations_ssb, OID_AUTO, active, CTLFLAG_RD, 969 &hw_ssb_active, 0, "Speculative Store Bypass Disable active"); 970 971 static void 972 hw_ssb_set(bool enable, bool for_all_cpus) 973 { 974 975 if ((cpu_stdext_feature3 & CPUID_STDEXT3_SSBD) == 0) { 976 hw_ssb_active = 0; 977 return; 978 } 979 hw_ssb_active = enable; 980 x86_msr_op(MSR_IA32_SPEC_CTRL, 981 (enable ? MSR_OP_OR : MSR_OP_ANDNOT) | 982 (for_all_cpus ? MSR_OP_SCHED_ALL : MSR_OP_LOCAL), 983 IA32_SPEC_CTRL_SSBD, NULL); 984 } 985 986 void 987 hw_ssb_recalculate(bool all_cpus) 988 { 989 990 switch (hw_ssb_disable) { 991 default: 992 hw_ssb_disable = 0; 993 /* FALLTHROUGH */ 994 case 0: /* off */ 995 hw_ssb_set(false, all_cpus); 996 break; 997 case 1: /* on */ 998 hw_ssb_set(true, all_cpus); 999 break; 1000 case 2: /* auto */ 1001 hw_ssb_set((cpu_ia32_arch_caps & IA32_ARCH_CAP_SSB_NO) != 0 ? 1002 false : true, all_cpus); 1003 break; 1004 } 1005 } 1006 1007 static int 1008 hw_ssb_disable_handler(SYSCTL_HANDLER_ARGS) 1009 { 1010 int error, val; 1011 1012 val = hw_ssb_disable; 1013 error = sysctl_handle_int(oidp, &val, 0, req); 1014 if (error != 0 || req->newptr == NULL) 1015 return (error); 1016 hw_ssb_disable = val; 1017 hw_ssb_recalculate(true); 1018 return (0); 1019 } 1020 SYSCTL_PROC(_hw, OID_AUTO, spec_store_bypass_disable, CTLTYPE_INT | 1021 CTLFLAG_RWTUN | CTLFLAG_NOFETCH | CTLFLAG_MPSAFE, NULL, 0, 1022 hw_ssb_disable_handler, "I", 1023 "Speculative Store Bypass Disable (0 - off, 1 - on, 2 - auto)"); 1024 1025 SYSCTL_PROC(_machdep_mitigations_ssb, OID_AUTO, disable, CTLTYPE_INT | 1026 CTLFLAG_RWTUN | CTLFLAG_NOFETCH | CTLFLAG_MPSAFE, NULL, 0, 1027 hw_ssb_disable_handler, "I", 1028 "Speculative Store Bypass Disable (0 - off, 1 - on, 2 - auto)"); 1029 1030 int hw_mds_disable; 1031 1032 /* 1033 * Handler for Microarchitectural Data Sampling issues. Really not a 1034 * pointer to C function: on amd64 the code must not change any CPU 1035 * architectural state except possibly %rflags. Also, it is always 1036 * called with interrupts disabled. 1037 */ 1038 void mds_handler_void(void); 1039 void mds_handler_verw(void); 1040 void mds_handler_ivb(void); 1041 void mds_handler_bdw(void); 1042 void mds_handler_skl_sse(void); 1043 void mds_handler_skl_avx(void); 1044 void mds_handler_skl_avx512(void); 1045 void mds_handler_silvermont(void); 1046 void (*mds_handler)(void) = mds_handler_void; 1047 1048 static int 1049 sysctl_hw_mds_disable_state_handler(SYSCTL_HANDLER_ARGS) 1050 { 1051 const char *state; 1052 1053 if (mds_handler == mds_handler_void) 1054 state = "inactive"; 1055 else if (mds_handler == mds_handler_verw) 1056 state = "VERW"; 1057 else if (mds_handler == mds_handler_ivb) 1058 state = "software IvyBridge"; 1059 else if (mds_handler == mds_handler_bdw) 1060 state = "software Broadwell"; 1061 else if (mds_handler == mds_handler_skl_sse) 1062 state = "software Skylake SSE"; 1063 else if (mds_handler == mds_handler_skl_avx) 1064 state = "software Skylake AVX"; 1065 else if (mds_handler == mds_handler_skl_avx512) 1066 state = "software Skylake AVX512"; 1067 else if (mds_handler == mds_handler_silvermont) 1068 state = "software Silvermont"; 1069 else 1070 state = "unknown"; 1071 return (SYSCTL_OUT(req, state, strlen(state))); 1072 } 1073 1074 SYSCTL_PROC(_hw, OID_AUTO, mds_disable_state, 1075 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, 0, 1076 sysctl_hw_mds_disable_state_handler, "A", 1077 "Microarchitectural Data Sampling Mitigation state"); 1078 1079 SYSCTL_NODE(_machdep_mitigations, OID_AUTO, mds, 1080 CTLFLAG_RW | CTLFLAG_MPSAFE, 0, 1081 "Microarchitectural Data Sampling Mitigation state"); 1082 1083 SYSCTL_PROC(_machdep_mitigations_mds, OID_AUTO, state, 1084 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, 0, 1085 sysctl_hw_mds_disable_state_handler, "A", 1086 "Microarchitectural Data Sampling Mitigation state"); 1087 1088 _Static_assert(__offsetof(struct pcpu, pc_mds_tmp) % 64 == 0, "MDS AVX512"); 1089 1090 void 1091 hw_mds_recalculate(void) 1092 { 1093 struct pcpu *pc; 1094 vm_offset_t b64; 1095 u_long xcr0; 1096 int i; 1097 1098 /* 1099 * Allow user to force VERW variant even if MD_CLEAR is not 1100 * reported. For instance, hypervisor might unknowingly 1101 * filter the cap out. 1102 * For the similar reasons, and for testing, allow to enable 1103 * mitigation even when MDS_NO cap is set. 1104 */ 1105 if (cpu_vendor_id != CPU_VENDOR_INTEL || hw_mds_disable == 0 || 1106 ((cpu_ia32_arch_caps & IA32_ARCH_CAP_MDS_NO) != 0 && 1107 hw_mds_disable == 3)) { 1108 mds_handler = mds_handler_void; 1109 } else if (((cpu_stdext_feature3 & CPUID_STDEXT3_MD_CLEAR) != 0 && 1110 hw_mds_disable == 3) || hw_mds_disable == 1) { 1111 mds_handler = mds_handler_verw; 1112 } else if (CPUID_TO_FAMILY(cpu_id) == 0x6 && 1113 (CPUID_TO_MODEL(cpu_id) == 0x2e || CPUID_TO_MODEL(cpu_id) == 0x1e || 1114 CPUID_TO_MODEL(cpu_id) == 0x1f || CPUID_TO_MODEL(cpu_id) == 0x1a || 1115 CPUID_TO_MODEL(cpu_id) == 0x2f || CPUID_TO_MODEL(cpu_id) == 0x25 || 1116 CPUID_TO_MODEL(cpu_id) == 0x2c || CPUID_TO_MODEL(cpu_id) == 0x2d || 1117 CPUID_TO_MODEL(cpu_id) == 0x2a || CPUID_TO_MODEL(cpu_id) == 0x3e || 1118 CPUID_TO_MODEL(cpu_id) == 0x3a) && 1119 (hw_mds_disable == 2 || hw_mds_disable == 3)) { 1120 /* 1121 * Nehalem, SandyBridge, IvyBridge 1122 */ 1123 CPU_FOREACH(i) { 1124 pc = pcpu_find(i); 1125 if (pc->pc_mds_buf == NULL) { 1126 pc->pc_mds_buf = malloc_domainset(672, M_TEMP, 1127 DOMAINSET_PREF(pc->pc_domain), M_WAITOK); 1128 bzero(pc->pc_mds_buf, 16); 1129 } 1130 } 1131 mds_handler = mds_handler_ivb; 1132 } else if (CPUID_TO_FAMILY(cpu_id) == 0x6 && 1133 (CPUID_TO_MODEL(cpu_id) == 0x3f || CPUID_TO_MODEL(cpu_id) == 0x3c || 1134 CPUID_TO_MODEL(cpu_id) == 0x45 || CPUID_TO_MODEL(cpu_id) == 0x46 || 1135 CPUID_TO_MODEL(cpu_id) == 0x56 || CPUID_TO_MODEL(cpu_id) == 0x4f || 1136 CPUID_TO_MODEL(cpu_id) == 0x47 || CPUID_TO_MODEL(cpu_id) == 0x3d) && 1137 (hw_mds_disable == 2 || hw_mds_disable == 3)) { 1138 /* 1139 * Haswell, Broadwell 1140 */ 1141 CPU_FOREACH(i) { 1142 pc = pcpu_find(i); 1143 if (pc->pc_mds_buf == NULL) { 1144 pc->pc_mds_buf = malloc_domainset(1536, M_TEMP, 1145 DOMAINSET_PREF(pc->pc_domain), M_WAITOK); 1146 bzero(pc->pc_mds_buf, 16); 1147 } 1148 } 1149 mds_handler = mds_handler_bdw; 1150 } else if (CPUID_TO_FAMILY(cpu_id) == 0x6 && 1151 ((CPUID_TO_MODEL(cpu_id) == 0x55 && (cpu_id & 1152 CPUID_STEPPING) <= 5) || 1153 CPUID_TO_MODEL(cpu_id) == 0x4e || CPUID_TO_MODEL(cpu_id) == 0x5e || 1154 (CPUID_TO_MODEL(cpu_id) == 0x8e && (cpu_id & 1155 CPUID_STEPPING) <= 0xb) || 1156 (CPUID_TO_MODEL(cpu_id) == 0x9e && (cpu_id & 1157 CPUID_STEPPING) <= 0xc)) && 1158 (hw_mds_disable == 2 || hw_mds_disable == 3)) { 1159 /* 1160 * Skylake, KabyLake, CoffeeLake, WhiskeyLake, 1161 * CascadeLake 1162 */ 1163 CPU_FOREACH(i) { 1164 pc = pcpu_find(i); 1165 if (pc->pc_mds_buf == NULL) { 1166 pc->pc_mds_buf = malloc_domainset(6 * 1024, 1167 M_TEMP, DOMAINSET_PREF(pc->pc_domain), 1168 M_WAITOK); 1169 b64 = (vm_offset_t)malloc_domainset(64 + 63, 1170 M_TEMP, DOMAINSET_PREF(pc->pc_domain), 1171 M_WAITOK); 1172 pc->pc_mds_buf64 = (void *)roundup2(b64, 64); 1173 bzero(pc->pc_mds_buf64, 64); 1174 } 1175 } 1176 xcr0 = rxcr(0); 1177 if ((xcr0 & XFEATURE_ENABLED_ZMM_HI256) != 0 && 1178 (cpu_stdext_feature & CPUID_STDEXT_AVX512DQ) != 0) 1179 mds_handler = mds_handler_skl_avx512; 1180 else if ((xcr0 & XFEATURE_ENABLED_AVX) != 0 && 1181 (cpu_feature2 & CPUID2_AVX) != 0) 1182 mds_handler = mds_handler_skl_avx; 1183 else 1184 mds_handler = mds_handler_skl_sse; 1185 } else if (CPUID_TO_FAMILY(cpu_id) == 0x6 && 1186 ((CPUID_TO_MODEL(cpu_id) == 0x37 || 1187 CPUID_TO_MODEL(cpu_id) == 0x4a || 1188 CPUID_TO_MODEL(cpu_id) == 0x4c || 1189 CPUID_TO_MODEL(cpu_id) == 0x4d || 1190 CPUID_TO_MODEL(cpu_id) == 0x5a || 1191 CPUID_TO_MODEL(cpu_id) == 0x5d || 1192 CPUID_TO_MODEL(cpu_id) == 0x6e || 1193 CPUID_TO_MODEL(cpu_id) == 0x65 || 1194 CPUID_TO_MODEL(cpu_id) == 0x75 || 1195 CPUID_TO_MODEL(cpu_id) == 0x1c || 1196 CPUID_TO_MODEL(cpu_id) == 0x26 || 1197 CPUID_TO_MODEL(cpu_id) == 0x27 || 1198 CPUID_TO_MODEL(cpu_id) == 0x35 || 1199 CPUID_TO_MODEL(cpu_id) == 0x36 || 1200 CPUID_TO_MODEL(cpu_id) == 0x7a))) { 1201 /* Silvermont, Airmont */ 1202 CPU_FOREACH(i) { 1203 pc = pcpu_find(i); 1204 if (pc->pc_mds_buf == NULL) 1205 pc->pc_mds_buf = malloc(256, M_TEMP, M_WAITOK); 1206 } 1207 mds_handler = mds_handler_silvermont; 1208 } else { 1209 hw_mds_disable = 0; 1210 mds_handler = mds_handler_void; 1211 } 1212 } 1213 1214 static void 1215 hw_mds_recalculate_boot(void *arg __unused) 1216 { 1217 1218 hw_mds_recalculate(); 1219 } 1220 SYSINIT(mds_recalc, SI_SUB_SMP, SI_ORDER_ANY, hw_mds_recalculate_boot, NULL); 1221 1222 static int 1223 sysctl_mds_disable_handler(SYSCTL_HANDLER_ARGS) 1224 { 1225 int error, val; 1226 1227 val = hw_mds_disable; 1228 error = sysctl_handle_int(oidp, &val, 0, req); 1229 if (error != 0 || req->newptr == NULL) 1230 return (error); 1231 if (val < 0 || val > 3) 1232 return (EINVAL); 1233 hw_mds_disable = val; 1234 hw_mds_recalculate(); 1235 return (0); 1236 } 1237 1238 SYSCTL_PROC(_hw, OID_AUTO, mds_disable, CTLTYPE_INT | 1239 CTLFLAG_RWTUN | CTLFLAG_NOFETCH | CTLFLAG_MPSAFE, NULL, 0, 1240 sysctl_mds_disable_handler, "I", 1241 "Microarchitectural Data Sampling Mitigation " 1242 "(0 - off, 1 - on VERW, 2 - on SW, 3 - on AUTO)"); 1243 1244 SYSCTL_PROC(_machdep_mitigations_mds, OID_AUTO, disable, CTLTYPE_INT | 1245 CTLFLAG_RWTUN | CTLFLAG_NOFETCH | CTLFLAG_MPSAFE, NULL, 0, 1246 sysctl_mds_disable_handler, "I", 1247 "Microarchitectural Data Sampling Mitigation " 1248 "(0 - off, 1 - on VERW, 2 - on SW, 3 - on AUTO)"); 1249 1250 /* 1251 * Intel Transactional Memory Asynchronous Abort Mitigation 1252 * CVE-2019-11135 1253 */ 1254 int x86_taa_enable; 1255 int x86_taa_state; 1256 enum { 1257 TAA_NONE = 0, /* No mitigation enabled */ 1258 TAA_TSX_DISABLE = 1, /* Disable TSX via MSR */ 1259 TAA_VERW = 2, /* Use VERW mitigation */ 1260 TAA_AUTO = 3, /* Automatically select the mitigation */ 1261 1262 /* The states below are not selectable by the operator */ 1263 1264 TAA_TAA_UC = 4, /* Mitigation present in microcode */ 1265 TAA_NOT_PRESENT = 5 /* TSX is not present */ 1266 }; 1267 1268 static void 1269 taa_set(bool enable, bool all) 1270 { 1271 1272 x86_msr_op(MSR_IA32_TSX_CTRL, 1273 (enable ? MSR_OP_OR : MSR_OP_ANDNOT) | 1274 (all ? MSR_OP_RENDEZVOUS_ALL : MSR_OP_LOCAL), 1275 IA32_TSX_CTRL_RTM_DISABLE | IA32_TSX_CTRL_TSX_CPUID_CLEAR, 1276 NULL); 1277 } 1278 1279 void 1280 x86_taa_recalculate(void) 1281 { 1282 static int taa_saved_mds_disable = 0; 1283 int taa_need = 0, taa_state = 0; 1284 int mds_disable = 0, need_mds_recalc = 0; 1285 1286 /* Check CPUID.07h.EBX.HLE and RTM for the presence of TSX */ 1287 if ((cpu_stdext_feature & CPUID_STDEXT_HLE) == 0 || 1288 (cpu_stdext_feature & CPUID_STDEXT_RTM) == 0) { 1289 /* TSX is not present */ 1290 x86_taa_state = TAA_NOT_PRESENT; 1291 return; 1292 } 1293 1294 /* Check to see what mitigation options the CPU gives us */ 1295 if (cpu_ia32_arch_caps & IA32_ARCH_CAP_TAA_NO) { 1296 /* CPU is not suseptible to TAA */ 1297 taa_need = TAA_TAA_UC; 1298 } else if (cpu_ia32_arch_caps & IA32_ARCH_CAP_TSX_CTRL) { 1299 /* 1300 * CPU can turn off TSX. This is the next best option 1301 * if TAA_NO hardware mitigation isn't present 1302 */ 1303 taa_need = TAA_TSX_DISABLE; 1304 } else { 1305 /* No TSX/TAA specific remedies are available. */ 1306 if (x86_taa_enable == TAA_TSX_DISABLE) { 1307 if (bootverbose) 1308 printf("TSX control not available\n"); 1309 return; 1310 } else 1311 taa_need = TAA_VERW; 1312 } 1313 1314 /* Can we automatically take action, or are we being forced? */ 1315 if (x86_taa_enable == TAA_AUTO) 1316 taa_state = taa_need; 1317 else 1318 taa_state = x86_taa_enable; 1319 1320 /* No state change, nothing to do */ 1321 if (taa_state == x86_taa_state) { 1322 if (bootverbose) 1323 printf("No TSX change made\n"); 1324 return; 1325 } 1326 1327 /* Does the MSR need to be turned on or off? */ 1328 if (taa_state == TAA_TSX_DISABLE) 1329 taa_set(true, true); 1330 else if (x86_taa_state == TAA_TSX_DISABLE) 1331 taa_set(false, true); 1332 1333 /* Does MDS need to be set to turn on VERW? */ 1334 if (taa_state == TAA_VERW) { 1335 taa_saved_mds_disable = hw_mds_disable; 1336 mds_disable = hw_mds_disable = 1; 1337 need_mds_recalc = 1; 1338 } else if (x86_taa_state == TAA_VERW) { 1339 mds_disable = hw_mds_disable = taa_saved_mds_disable; 1340 need_mds_recalc = 1; 1341 } 1342 if (need_mds_recalc) { 1343 hw_mds_recalculate(); 1344 if (mds_disable != hw_mds_disable) { 1345 if (bootverbose) 1346 printf("Cannot change MDS state for TAA\n"); 1347 /* Don't update our state */ 1348 return; 1349 } 1350 } 1351 1352 x86_taa_state = taa_state; 1353 return; 1354 } 1355 1356 static void 1357 taa_recalculate_boot(void * arg __unused) 1358 { 1359 1360 x86_taa_recalculate(); 1361 } 1362 SYSINIT(taa_recalc, SI_SUB_SMP, SI_ORDER_ANY, taa_recalculate_boot, NULL); 1363 1364 SYSCTL_NODE(_machdep_mitigations, OID_AUTO, taa, 1365 CTLFLAG_RW | CTLFLAG_MPSAFE, 0, 1366 "TSX Asynchronous Abort Mitigation"); 1367 1368 static int 1369 sysctl_taa_handler(SYSCTL_HANDLER_ARGS) 1370 { 1371 int error, val; 1372 1373 val = x86_taa_enable; 1374 error = sysctl_handle_int(oidp, &val, 0, req); 1375 if (error != 0 || req->newptr == NULL) 1376 return (error); 1377 if (val < TAA_NONE || val > TAA_AUTO) 1378 return (EINVAL); 1379 x86_taa_enable = val; 1380 x86_taa_recalculate(); 1381 return (0); 1382 } 1383 1384 SYSCTL_PROC(_machdep_mitigations_taa, OID_AUTO, enable, CTLTYPE_INT | 1385 CTLFLAG_RWTUN | CTLFLAG_NOFETCH | CTLFLAG_MPSAFE, NULL, 0, 1386 sysctl_taa_handler, "I", 1387 "TAA Mitigation enablement control " 1388 "(0 - off, 1 - disable TSX, 2 - VERW, 3 - on AUTO)"); 1389 1390 static int 1391 sysctl_taa_state_handler(SYSCTL_HANDLER_ARGS) 1392 { 1393 const char *state; 1394 1395 switch (x86_taa_state) { 1396 case TAA_NONE: 1397 state = "inactive"; 1398 break; 1399 case TAA_TSX_DISABLE: 1400 state = "TSX disabled"; 1401 break; 1402 case TAA_VERW: 1403 state = "VERW"; 1404 break; 1405 case TAA_TAA_UC: 1406 state = "Mitigated in microcode"; 1407 break; 1408 case TAA_NOT_PRESENT: 1409 state = "TSX not present"; 1410 break; 1411 default: 1412 state = "unknown"; 1413 } 1414 1415 return (SYSCTL_OUT(req, state, strlen(state))); 1416 } 1417 1418 SYSCTL_PROC(_machdep_mitigations_taa, OID_AUTO, state, 1419 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, 0, 1420 sysctl_taa_state_handler, "A", 1421 "TAA Mitigation state"); 1422 1423 int __read_frequently cpu_flush_rsb_ctxsw; 1424 SYSCTL_INT(_machdep_mitigations, OID_AUTO, flush_rsb_ctxsw, 1425 CTLFLAG_RW | CTLFLAG_NOFETCH, &cpu_flush_rsb_ctxsw, 0, 1426 "Flush Return Stack Buffer on context switch"); 1427 1428 SYSCTL_NODE(_machdep_mitigations, OID_AUTO, rngds, 1429 CTLFLAG_RW | CTLFLAG_MPSAFE, 0, 1430 "MCU Optimization, disable RDSEED mitigation"); 1431 1432 int x86_rngds_mitg_enable = 1; 1433 void 1434 x86_rngds_mitg_recalculate(bool all_cpus) 1435 { 1436 if ((cpu_stdext_feature3 & CPUID_STDEXT3_MCUOPT) == 0) 1437 return; 1438 x86_msr_op(MSR_IA32_MCU_OPT_CTRL, 1439 (x86_rngds_mitg_enable ? MSR_OP_OR : MSR_OP_ANDNOT) | 1440 (all_cpus ? MSR_OP_RENDEZVOUS_ALL : MSR_OP_LOCAL), 1441 IA32_RNGDS_MITG_DIS, NULL); 1442 } 1443 1444 static int 1445 sysctl_rngds_mitg_enable_handler(SYSCTL_HANDLER_ARGS) 1446 { 1447 int error, val; 1448 1449 val = x86_rngds_mitg_enable; 1450 error = sysctl_handle_int(oidp, &val, 0, req); 1451 if (error != 0 || req->newptr == NULL) 1452 return (error); 1453 x86_rngds_mitg_enable = val; 1454 x86_rngds_mitg_recalculate(true); 1455 return (0); 1456 } 1457 SYSCTL_PROC(_machdep_mitigations_rngds, OID_AUTO, enable, CTLTYPE_INT | 1458 CTLFLAG_RWTUN | CTLFLAG_NOFETCH | CTLFLAG_MPSAFE, NULL, 0, 1459 sysctl_rngds_mitg_enable_handler, "I", 1460 "MCU Optimization, disabling RDSEED mitigation control " 1461 "(0 - mitigation disabled (RDSEED optimized), 1 - mitigation enabled)"); 1462 1463 static int 1464 sysctl_rngds_state_handler(SYSCTL_HANDLER_ARGS) 1465 { 1466 const char *state; 1467 1468 if ((cpu_stdext_feature3 & CPUID_STDEXT3_MCUOPT) == 0) { 1469 state = "Not applicable"; 1470 } else if (x86_rngds_mitg_enable == 0) { 1471 state = "RDSEED not serialized"; 1472 } else { 1473 state = "Mitigated"; 1474 } 1475 return (SYSCTL_OUT(req, state, strlen(state))); 1476 } 1477 SYSCTL_PROC(_machdep_mitigations_rngds, OID_AUTO, state, 1478 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, 0, 1479 sysctl_rngds_state_handler, "A", 1480 "MCU Optimization state"); 1481 1482 /* 1483 * Enable and restore kernel text write permissions. 1484 * Callers must ensure that disable_wp()/restore_wp() are executed 1485 * without rescheduling on the same core. 1486 */ 1487 bool 1488 disable_wp(void) 1489 { 1490 u_int cr0; 1491 1492 cr0 = rcr0(); 1493 if ((cr0 & CR0_WP) == 0) 1494 return (false); 1495 load_cr0(cr0 & ~CR0_WP); 1496 return (true); 1497 } 1498 1499 void 1500 restore_wp(bool old_wp) 1501 { 1502 1503 if (old_wp) 1504 load_cr0(rcr0() | CR0_WP); 1505 } 1506 1507 bool 1508 acpi_get_fadt_bootflags(uint16_t *flagsp) 1509 { 1510 #ifdef DEV_ACPI 1511 ACPI_TABLE_FADT *fadt; 1512 vm_paddr_t physaddr; 1513 1514 physaddr = acpi_find_table(ACPI_SIG_FADT); 1515 if (physaddr == 0) 1516 return (false); 1517 fadt = acpi_map_table(physaddr, ACPI_SIG_FADT); 1518 if (fadt == NULL) 1519 return (false); 1520 *flagsp = fadt->BootFlags; 1521 acpi_unmap_table(fadt); 1522 return (true); 1523 #else 1524 return (false); 1525 #endif 1526 } 1527 1528 DEFINE_IFUNC(, uint64_t, rdtsc_ordered, (void)) 1529 { 1530 bool cpu_is_amd = cpu_vendor_id == CPU_VENDOR_AMD || 1531 cpu_vendor_id == CPU_VENDOR_HYGON; 1532 1533 if ((amd_feature & AMDID_RDTSCP) != 0) 1534 return (rdtscp); 1535 else if ((cpu_feature & CPUID_SSE2) != 0) 1536 return (cpu_is_amd ? rdtsc_ordered_mfence : 1537 rdtsc_ordered_lfence); 1538 else 1539 return (rdtsc); 1540 } 1541