1 /*- 2 * Copyright (c) 2003 Peter Wemm. 3 * Copyright (c) 1992 Terrence R. Lambert. 4 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * William Jolitz. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the University of 21 * California, Berkeley and its contributors. 22 * 4. Neither the name of the University nor the names of its contributors 23 * may be used to endorse or promote products derived from this software 24 * without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 * 38 * from: @(#)machdep.c 7.4 (Berkeley) 6/3/91 39 */ 40 41 #include <sys/cdefs.h> 42 __FBSDID("$FreeBSD$"); 43 44 #include "opt_atpic.h" 45 #include "opt_cpu.h" 46 #include "opt_ddb.h" 47 #include "opt_inet.h" 48 #include "opt_isa.h" 49 #include "opt_kdb.h" 50 #include "opt_kstack_pages.h" 51 #include "opt_maxmem.h" 52 #include "opt_mp_watchdog.h" 53 #include "opt_platform.h" 54 #ifdef __i386__ 55 #include "opt_apic.h" 56 #endif 57 58 #include <sys/param.h> 59 #include <sys/proc.h> 60 #include <sys/systm.h> 61 #include <sys/bus.h> 62 #include <sys/cpu.h> 63 #include <sys/kdb.h> 64 #include <sys/kernel.h> 65 #include <sys/ktr.h> 66 #include <sys/lock.h> 67 #include <sys/malloc.h> 68 #include <sys/mutex.h> 69 #include <sys/pcpu.h> 70 #include <sys/rwlock.h> 71 #include <sys/sched.h> 72 #ifdef SMP 73 #include <sys/smp.h> 74 #endif 75 #include <sys/sysctl.h> 76 77 #include <machine/clock.h> 78 #include <machine/cpu.h> 79 #include <machine/cputypes.h> 80 #include <machine/specialreg.h> 81 #include <machine/md_var.h> 82 #include <machine/mp_watchdog.h> 83 #include <machine/tss.h> 84 #ifdef SMP 85 #include <machine/smp.h> 86 #endif 87 #ifdef CPU_ELAN 88 #include <machine/elan_mmcr.h> 89 #endif 90 #include <x86/acpica_machdep.h> 91 92 #include <vm/vm.h> 93 #include <vm/vm_extern.h> 94 #include <vm/vm_kern.h> 95 #include <vm/vm_page.h> 96 #include <vm/vm_map.h> 97 #include <vm/vm_object.h> 98 #include <vm/vm_pager.h> 99 #include <vm/vm_param.h> 100 101 #include <isa/isareg.h> 102 103 #define STATE_RUNNING 0x0 104 #define STATE_MWAIT 0x1 105 #define STATE_SLEEPING 0x2 106 107 #ifdef SMP 108 static u_int cpu_reset_proxyid; 109 static volatile u_int cpu_reset_proxy_active; 110 #endif 111 112 113 /* 114 * Machine dependent boot() routine 115 * 116 * I haven't seen anything to put here yet 117 * Possibly some stuff might be grafted back here from boot() 118 */ 119 void 120 cpu_boot(int howto) 121 { 122 } 123 124 /* 125 * Flush the D-cache for non-DMA I/O so that the I-cache can 126 * be made coherent later. 127 */ 128 void 129 cpu_flush_dcache(void *ptr, size_t len) 130 { 131 /* Not applicable */ 132 } 133 134 void 135 acpi_cpu_c1(void) 136 { 137 138 __asm __volatile("sti; hlt"); 139 } 140 141 /* 142 * Use mwait to pause execution while waiting for an interrupt or 143 * another thread to signal that there is more work. 144 * 145 * NOTE: Interrupts will cause a wakeup; however, this function does 146 * not enable interrupt handling. The caller is responsible to enable 147 * interrupts. 148 */ 149 void 150 acpi_cpu_idle_mwait(uint32_t mwait_hint) 151 { 152 int *state; 153 154 /* 155 * A comment in Linux patch claims that 'CPUs run faster with 156 * speculation protection disabled. All CPU threads in a core 157 * must disable speculation protection for it to be 158 * disabled. Disable it while we are idle so the other 159 * hyperthread can run fast.' 160 * 161 * XXXKIB. Software coordination mode should be supported, 162 * but all Intel CPUs provide hardware coordination. 163 */ 164 165 state = (int *)PCPU_PTR(monitorbuf); 166 KASSERT(atomic_load_int(state) == STATE_SLEEPING, 167 ("cpu_mwait_cx: wrong monitorbuf state")); 168 atomic_store_int(state, STATE_MWAIT); 169 handle_ibrs_entry(); 170 cpu_monitor(state, 0, 0); 171 if (atomic_load_int(state) == STATE_MWAIT) 172 cpu_mwait(MWAIT_INTRBREAK, mwait_hint); 173 handle_ibrs_exit(); 174 175 /* 176 * We should exit on any event that interrupts mwait, because 177 * that event might be a wanted interrupt. 178 */ 179 atomic_store_int(state, STATE_RUNNING); 180 } 181 182 /* Get current clock frequency for the given cpu id. */ 183 int 184 cpu_est_clockrate(int cpu_id, uint64_t *rate) 185 { 186 uint64_t tsc1, tsc2; 187 uint64_t acnt, mcnt, perf; 188 register_t reg; 189 190 if (pcpu_find(cpu_id) == NULL || rate == NULL) 191 return (EINVAL); 192 #ifdef __i386__ 193 if ((cpu_feature & CPUID_TSC) == 0) 194 return (EOPNOTSUPP); 195 #endif 196 197 /* 198 * If TSC is P-state invariant and APERF/MPERF MSRs do not exist, 199 * DELAY(9) based logic fails. 200 */ 201 if (tsc_is_invariant && !tsc_perf_stat) 202 return (EOPNOTSUPP); 203 204 #ifdef SMP 205 if (smp_cpus > 1) { 206 /* Schedule ourselves on the indicated cpu. */ 207 thread_lock(curthread); 208 sched_bind(curthread, cpu_id); 209 thread_unlock(curthread); 210 } 211 #endif 212 213 /* Calibrate by measuring a short delay. */ 214 reg = intr_disable(); 215 if (tsc_is_invariant) { 216 wrmsr(MSR_MPERF, 0); 217 wrmsr(MSR_APERF, 0); 218 tsc1 = rdtsc(); 219 DELAY(1000); 220 mcnt = rdmsr(MSR_MPERF); 221 acnt = rdmsr(MSR_APERF); 222 tsc2 = rdtsc(); 223 intr_restore(reg); 224 perf = 1000 * acnt / mcnt; 225 *rate = (tsc2 - tsc1) * perf; 226 } else { 227 tsc1 = rdtsc(); 228 DELAY(1000); 229 tsc2 = rdtsc(); 230 intr_restore(reg); 231 *rate = (tsc2 - tsc1) * 1000; 232 } 233 234 #ifdef SMP 235 if (smp_cpus > 1) { 236 thread_lock(curthread); 237 sched_unbind(curthread); 238 thread_unlock(curthread); 239 } 240 #endif 241 242 return (0); 243 } 244 245 /* 246 * Shutdown the CPU as much as possible 247 */ 248 void 249 cpu_halt(void) 250 { 251 for (;;) 252 halt(); 253 } 254 255 static void 256 cpu_reset_real(void) 257 { 258 struct region_descriptor null_idt; 259 int b; 260 261 disable_intr(); 262 #ifdef CPU_ELAN 263 if (elan_mmcr != NULL) 264 elan_mmcr->RESCFG = 1; 265 #endif 266 #ifdef __i386__ 267 if (cpu == CPU_GEODE1100) { 268 /* Attempt Geode's own reset */ 269 outl(0xcf8, 0x80009044ul); 270 outl(0xcfc, 0xf); 271 } 272 #endif 273 #if !defined(BROKEN_KEYBOARD_RESET) 274 /* 275 * Attempt to do a CPU reset via the keyboard controller, 276 * do not turn off GateA20, as any machine that fails 277 * to do the reset here would then end up in no man's land. 278 */ 279 outb(IO_KBD + 4, 0xFE); 280 DELAY(500000); /* wait 0.5 sec to see if that did it */ 281 #endif 282 283 /* 284 * Attempt to force a reset via the Reset Control register at 285 * I/O port 0xcf9. Bit 2 forces a system reset when it 286 * transitions from 0 to 1. Bit 1 selects the type of reset 287 * to attempt: 0 selects a "soft" reset, and 1 selects a 288 * "hard" reset. We try a "hard" reset. The first write sets 289 * bit 1 to select a "hard" reset and clears bit 2. The 290 * second write forces a 0 -> 1 transition in bit 2 to trigger 291 * a reset. 292 */ 293 outb(0xcf9, 0x2); 294 outb(0xcf9, 0x6); 295 DELAY(500000); /* wait 0.5 sec to see if that did it */ 296 297 /* 298 * Attempt to force a reset via the Fast A20 and Init register 299 * at I/O port 0x92. Bit 1 serves as an alternate A20 gate. 300 * Bit 0 asserts INIT# when set to 1. We are careful to only 301 * preserve bit 1 while setting bit 0. We also must clear bit 302 * 0 before setting it if it isn't already clear. 303 */ 304 b = inb(0x92); 305 if (b != 0xff) { 306 if ((b & 0x1) != 0) 307 outb(0x92, b & 0xfe); 308 outb(0x92, b | 0x1); 309 DELAY(500000); /* wait 0.5 sec to see if that did it */ 310 } 311 312 printf("No known reset method worked, attempting CPU shutdown\n"); 313 DELAY(1000000); /* wait 1 sec for printf to complete */ 314 315 /* Wipe the IDT. */ 316 null_idt.rd_limit = 0; 317 null_idt.rd_base = 0; 318 lidt(&null_idt); 319 320 /* "good night, sweet prince .... <THUNK!>" */ 321 breakpoint(); 322 323 /* NOTREACHED */ 324 while(1); 325 } 326 327 #ifdef SMP 328 static void 329 cpu_reset_proxy(void) 330 { 331 332 cpu_reset_proxy_active = 1; 333 while (cpu_reset_proxy_active == 1) 334 ia32_pause(); /* Wait for other cpu to see that we've started */ 335 336 printf("cpu_reset_proxy: Stopped CPU %d\n", cpu_reset_proxyid); 337 DELAY(1000000); 338 cpu_reset_real(); 339 } 340 #endif 341 342 void 343 cpu_reset(void) 344 { 345 #ifdef SMP 346 cpuset_t map; 347 u_int cnt; 348 349 if (smp_started) { 350 map = all_cpus; 351 CPU_CLR(PCPU_GET(cpuid), &map); 352 CPU_NAND(&map, &stopped_cpus); 353 if (!CPU_EMPTY(&map)) { 354 printf("cpu_reset: Stopping other CPUs\n"); 355 stop_cpus(map); 356 } 357 358 if (PCPU_GET(cpuid) != 0) { 359 cpu_reset_proxyid = PCPU_GET(cpuid); 360 cpustop_restartfunc = cpu_reset_proxy; 361 cpu_reset_proxy_active = 0; 362 printf("cpu_reset: Restarting BSP\n"); 363 364 /* Restart CPU #0. */ 365 CPU_SETOF(0, &started_cpus); 366 wmb(); 367 368 cnt = 0; 369 while (cpu_reset_proxy_active == 0 && cnt < 10000000) { 370 ia32_pause(); 371 cnt++; /* Wait for BSP to announce restart */ 372 } 373 if (cpu_reset_proxy_active == 0) { 374 printf("cpu_reset: Failed to restart BSP\n"); 375 } else { 376 cpu_reset_proxy_active = 2; 377 while (1) 378 ia32_pause(); 379 /* NOTREACHED */ 380 } 381 } 382 383 DELAY(1000000); 384 } 385 #endif 386 cpu_reset_real(); 387 /* NOTREACHED */ 388 } 389 390 bool 391 cpu_mwait_usable(void) 392 { 393 394 return ((cpu_feature2 & CPUID2_MON) != 0 && ((cpu_mon_mwait_flags & 395 (CPUID5_MON_MWAIT_EXT | CPUID5_MWAIT_INTRBREAK)) == 396 (CPUID5_MON_MWAIT_EXT | CPUID5_MWAIT_INTRBREAK))); 397 } 398 399 void (*cpu_idle_hook)(sbintime_t) = NULL; /* ACPI idle hook. */ 400 static int cpu_ident_amdc1e = 0; /* AMD C1E supported. */ 401 static int idle_mwait = 1; /* Use MONITOR/MWAIT for short idle. */ 402 SYSCTL_INT(_machdep, OID_AUTO, idle_mwait, CTLFLAG_RWTUN, &idle_mwait, 403 0, "Use MONITOR/MWAIT for short idle"); 404 405 static void 406 cpu_idle_acpi(sbintime_t sbt) 407 { 408 int *state; 409 410 state = (int *)PCPU_PTR(monitorbuf); 411 atomic_store_int(state, STATE_SLEEPING); 412 413 /* See comments in cpu_idle_hlt(). */ 414 disable_intr(); 415 if (sched_runnable()) 416 enable_intr(); 417 else if (cpu_idle_hook) 418 cpu_idle_hook(sbt); 419 else 420 acpi_cpu_c1(); 421 atomic_store_int(state, STATE_RUNNING); 422 } 423 424 static void 425 cpu_idle_hlt(sbintime_t sbt) 426 { 427 int *state; 428 429 state = (int *)PCPU_PTR(monitorbuf); 430 atomic_store_int(state, STATE_SLEEPING); 431 432 /* 433 * Since we may be in a critical section from cpu_idle(), if 434 * an interrupt fires during that critical section we may have 435 * a pending preemption. If the CPU halts, then that thread 436 * may not execute until a later interrupt awakens the CPU. 437 * To handle this race, check for a runnable thread after 438 * disabling interrupts and immediately return if one is 439 * found. Also, we must absolutely guarentee that hlt is 440 * the next instruction after sti. This ensures that any 441 * interrupt that fires after the call to disable_intr() will 442 * immediately awaken the CPU from hlt. Finally, please note 443 * that on x86 this works fine because of interrupts enabled only 444 * after the instruction following sti takes place, while IF is set 445 * to 1 immediately, allowing hlt instruction to acknowledge the 446 * interrupt. 447 */ 448 disable_intr(); 449 if (sched_runnable()) 450 enable_intr(); 451 else 452 acpi_cpu_c1(); 453 atomic_store_int(state, STATE_RUNNING); 454 } 455 456 static void 457 cpu_idle_mwait(sbintime_t sbt) 458 { 459 int *state; 460 461 state = (int *)PCPU_PTR(monitorbuf); 462 atomic_store_int(state, STATE_MWAIT); 463 464 /* See comments in cpu_idle_hlt(). */ 465 disable_intr(); 466 if (sched_runnable()) { 467 atomic_store_int(state, STATE_RUNNING); 468 enable_intr(); 469 return; 470 } 471 472 cpu_monitor(state, 0, 0); 473 if (atomic_load_int(state) == STATE_MWAIT) 474 __asm __volatile("sti; mwait" : : "a" (MWAIT_C1), "c" (0)); 475 else 476 enable_intr(); 477 atomic_store_int(state, STATE_RUNNING); 478 } 479 480 static void 481 cpu_idle_spin(sbintime_t sbt) 482 { 483 int *state; 484 int i; 485 486 state = (int *)PCPU_PTR(monitorbuf); 487 atomic_store_int(state, STATE_RUNNING); 488 489 /* 490 * The sched_runnable() call is racy but as long as there is 491 * a loop missing it one time will have just a little impact if any 492 * (and it is much better than missing the check at all). 493 */ 494 for (i = 0; i < 1000; i++) { 495 if (sched_runnable()) 496 return; 497 cpu_spinwait(); 498 } 499 } 500 501 /* 502 * C1E renders the local APIC timer dead, so we disable it by 503 * reading the Interrupt Pending Message register and clearing 504 * both C1eOnCmpHalt (bit 28) and SmiOnCmpHalt (bit 27). 505 * 506 * Reference: 507 * "BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh Processors" 508 * #32559 revision 3.00+ 509 */ 510 #define MSR_AMDK8_IPM 0xc0010055 511 #define AMDK8_SMIONCMPHALT (1ULL << 27) 512 #define AMDK8_C1EONCMPHALT (1ULL << 28) 513 #define AMDK8_CMPHALT (AMDK8_SMIONCMPHALT | AMDK8_C1EONCMPHALT) 514 515 void 516 cpu_probe_amdc1e(void) 517 { 518 519 /* 520 * Detect the presence of C1E capability mostly on latest 521 * dual-cores (or future) k8 family. 522 */ 523 if (cpu_vendor_id == CPU_VENDOR_AMD && 524 (cpu_id & 0x00000f00) == 0x00000f00 && 525 (cpu_id & 0x0fff0000) >= 0x00040000) { 526 cpu_ident_amdc1e = 1; 527 } 528 } 529 530 void (*cpu_idle_fn)(sbintime_t) = cpu_idle_acpi; 531 532 void 533 cpu_idle(int busy) 534 { 535 uint64_t msr; 536 sbintime_t sbt = -1; 537 538 CTR2(KTR_SPARE2, "cpu_idle(%d) at %d", 539 busy, curcpu); 540 #ifdef MP_WATCHDOG 541 ap_watchdog(PCPU_GET(cpuid)); 542 #endif 543 544 /* If we are busy - try to use fast methods. */ 545 if (busy) { 546 if ((cpu_feature2 & CPUID2_MON) && idle_mwait) { 547 cpu_idle_mwait(busy); 548 goto out; 549 } 550 } 551 552 /* If we have time - switch timers into idle mode. */ 553 if (!busy) { 554 critical_enter(); 555 sbt = cpu_idleclock(); 556 } 557 558 /* Apply AMD APIC timer C1E workaround. */ 559 if (cpu_ident_amdc1e && cpu_disable_c3_sleep) { 560 msr = rdmsr(MSR_AMDK8_IPM); 561 if (msr & AMDK8_CMPHALT) 562 wrmsr(MSR_AMDK8_IPM, msr & ~AMDK8_CMPHALT); 563 } 564 565 /* Call main idle method. */ 566 cpu_idle_fn(sbt); 567 568 /* Switch timers back into active mode. */ 569 if (!busy) { 570 cpu_activeclock(); 571 critical_exit(); 572 } 573 out: 574 CTR2(KTR_SPARE2, "cpu_idle(%d) at %d done", 575 busy, curcpu); 576 } 577 578 static int cpu_idle_apl31_workaround; 579 SYSCTL_INT(_machdep, OID_AUTO, idle_apl31, CTLFLAG_RW, 580 &cpu_idle_apl31_workaround, 0, 581 "Apollo Lake APL31 MWAIT bug workaround"); 582 583 int 584 cpu_idle_wakeup(int cpu) 585 { 586 int *state; 587 588 state = (int *)pcpu_find(cpu)->pc_monitorbuf; 589 switch (atomic_load_int(state)) { 590 case STATE_SLEEPING: 591 return (0); 592 case STATE_MWAIT: 593 atomic_store_int(state, STATE_RUNNING); 594 return (cpu_idle_apl31_workaround ? 0 : 1); 595 case STATE_RUNNING: 596 return (1); 597 default: 598 panic("bad monitor state"); 599 return (1); 600 } 601 } 602 603 /* 604 * Ordered by speed/power consumption. 605 */ 606 static struct { 607 void *id_fn; 608 char *id_name; 609 int id_cpuid2_flag; 610 } idle_tbl[] = { 611 { .id_fn = cpu_idle_spin, .id_name = "spin" }, 612 { .id_fn = cpu_idle_mwait, .id_name = "mwait", 613 .id_cpuid2_flag = CPUID2_MON }, 614 { .id_fn = cpu_idle_hlt, .id_name = "hlt" }, 615 { .id_fn = cpu_idle_acpi, .id_name = "acpi" }, 616 }; 617 618 static int 619 idle_sysctl_available(SYSCTL_HANDLER_ARGS) 620 { 621 char *avail, *p; 622 int error; 623 int i; 624 625 avail = malloc(256, M_TEMP, M_WAITOK); 626 p = avail; 627 for (i = 0; i < nitems(idle_tbl); i++) { 628 if (idle_tbl[i].id_cpuid2_flag != 0 && 629 (cpu_feature2 & idle_tbl[i].id_cpuid2_flag) == 0) 630 continue; 631 if (strcmp(idle_tbl[i].id_name, "acpi") == 0 && 632 cpu_idle_hook == NULL) 633 continue; 634 p += sprintf(p, "%s%s", p != avail ? ", " : "", 635 idle_tbl[i].id_name); 636 } 637 error = sysctl_handle_string(oidp, avail, 0, req); 638 free(avail, M_TEMP); 639 return (error); 640 } 641 642 SYSCTL_PROC(_machdep, OID_AUTO, idle_available, CTLTYPE_STRING | CTLFLAG_RD, 643 0, 0, idle_sysctl_available, "A", "list of available idle functions"); 644 645 static bool 646 cpu_idle_selector(const char *new_idle_name) 647 { 648 int i; 649 650 for (i = 0; i < nitems(idle_tbl); i++) { 651 if (idle_tbl[i].id_cpuid2_flag != 0 && 652 (cpu_feature2 & idle_tbl[i].id_cpuid2_flag) == 0) 653 continue; 654 if (strcmp(idle_tbl[i].id_name, "acpi") == 0 && 655 cpu_idle_hook == NULL) 656 continue; 657 if (strcmp(idle_tbl[i].id_name, new_idle_name)) 658 continue; 659 cpu_idle_fn = idle_tbl[i].id_fn; 660 if (bootverbose) 661 printf("CPU idle set to %s\n", idle_tbl[i].id_name); 662 return (true); 663 } 664 return (false); 665 } 666 667 static int 668 cpu_idle_sysctl(SYSCTL_HANDLER_ARGS) 669 { 670 char buf[16], *p; 671 int error, i; 672 673 p = "unknown"; 674 for (i = 0; i < nitems(idle_tbl); i++) { 675 if (idle_tbl[i].id_fn == cpu_idle_fn) { 676 p = idle_tbl[i].id_name; 677 break; 678 } 679 } 680 strncpy(buf, p, sizeof(buf)); 681 error = sysctl_handle_string(oidp, buf, sizeof(buf), req); 682 if (error != 0 || req->newptr == NULL) 683 return (error); 684 return (cpu_idle_selector(buf) ? 0 : EINVAL); 685 } 686 687 SYSCTL_PROC(_machdep, OID_AUTO, idle, CTLTYPE_STRING | CTLFLAG_RW, 0, 0, 688 cpu_idle_sysctl, "A", "currently selected idle function"); 689 690 static void 691 cpu_idle_tun(void *unused __unused) 692 { 693 char tunvar[16]; 694 695 if (TUNABLE_STR_FETCH("machdep.idle", tunvar, sizeof(tunvar))) 696 cpu_idle_selector(tunvar); 697 if (cpu_vendor_id == CPU_VENDOR_INTEL && cpu_id == 0x506c9) { 698 /* 699 * Apollo Lake errata APL31 (public errata APL30). 700 * Stores to the armed address range may not trigger 701 * MWAIT to resume execution. OS needs to use 702 * interrupts to wake processors from MWAIT-induced 703 * sleep states. 704 */ 705 cpu_idle_apl31_workaround = 1; 706 } 707 TUNABLE_INT_FETCH("machdep.idle_apl31", &cpu_idle_apl31_workaround); 708 } 709 SYSINIT(cpu_idle_tun, SI_SUB_CPU, SI_ORDER_MIDDLE, cpu_idle_tun, NULL); 710 711 static int panic_on_nmi = 1; 712 SYSCTL_INT(_machdep, OID_AUTO, panic_on_nmi, CTLFLAG_RWTUN, 713 &panic_on_nmi, 0, 714 "Panic on NMI"); 715 int nmi_is_broadcast = 1; 716 SYSCTL_INT(_machdep, OID_AUTO, nmi_is_broadcast, CTLFLAG_RWTUN, 717 &nmi_is_broadcast, 0, 718 "Chipset NMI is broadcast"); 719 #ifdef KDB 720 int kdb_on_nmi = 1; 721 SYSCTL_INT(_machdep, OID_AUTO, kdb_on_nmi, CTLFLAG_RWTUN, 722 &kdb_on_nmi, 0, 723 "Go to KDB on NMI"); 724 #endif 725 726 #ifdef DEV_ISA 727 void 728 nmi_call_kdb(u_int cpu, u_int type, struct trapframe *frame) 729 { 730 731 /* machine/parity/power fail/"kitchen sink" faults */ 732 if (isa_nmi(frame->tf_err) == 0) { 733 #ifdef KDB 734 /* 735 * NMI can be hooked up to a pushbutton for debugging. 736 */ 737 if (kdb_on_nmi) { 738 printf("NMI/cpu%d ... going to debugger\n", cpu); 739 kdb_trap(type, 0, frame); 740 } 741 #endif /* KDB */ 742 } else if (panic_on_nmi) { 743 panic("NMI indicates hardware failure"); 744 } 745 } 746 #endif 747 748 void 749 nmi_handle_intr(u_int type, struct trapframe *frame) 750 { 751 752 #ifdef DEV_ISA 753 #ifdef SMP 754 if (nmi_is_broadcast) { 755 nmi_call_kdb_smp(type, frame); 756 return; 757 } 758 #endif 759 nmi_call_kdb(PCPU_GET(cpuid), type, frame); 760 #endif 761 } 762 763 int hw_ibrs_active; 764 int hw_ibrs_disable = 1; 765 766 SYSCTL_INT(_hw, OID_AUTO, ibrs_active, CTLFLAG_RD, &hw_ibrs_active, 0, 767 "Indirect Branch Restricted Speculation active"); 768 769 void 770 hw_ibrs_recalculate(void) 771 { 772 uint64_t v; 773 774 if ((cpu_ia32_arch_caps & IA32_ARCH_CAP_IBRS_ALL) != 0) { 775 if (hw_ibrs_disable) { 776 v= rdmsr(MSR_IA32_SPEC_CTRL); 777 v &= ~(uint64_t)IA32_SPEC_CTRL_IBRS; 778 wrmsr(MSR_IA32_SPEC_CTRL, v); 779 } else { 780 v= rdmsr(MSR_IA32_SPEC_CTRL); 781 v |= IA32_SPEC_CTRL_IBRS; 782 wrmsr(MSR_IA32_SPEC_CTRL, v); 783 } 784 return; 785 } 786 hw_ibrs_active = (cpu_stdext_feature3 & CPUID_STDEXT3_IBPB) != 0 && 787 !hw_ibrs_disable; 788 } 789 790 static int 791 hw_ibrs_disable_handler(SYSCTL_HANDLER_ARGS) 792 { 793 int error, val; 794 795 val = hw_ibrs_disable; 796 error = sysctl_handle_int(oidp, &val, 0, req); 797 if (error != 0 || req->newptr == NULL) 798 return (error); 799 hw_ibrs_disable = val != 0; 800 hw_ibrs_recalculate(); 801 return (0); 802 } 803 SYSCTL_PROC(_hw, OID_AUTO, ibrs_disable, CTLTYPE_INT | CTLFLAG_RWTUN | 804 CTLFLAG_NOFETCH | CTLFLAG_MPSAFE, NULL, 0, hw_ibrs_disable_handler, "I", 805 "Disable Indirect Branch Restricted Speculation"); 806 807 /* 808 * Enable and restore kernel text write permissions. 809 * Callers must ensure that disable_wp()/restore_wp() are executed 810 * without rescheduling on the same core. 811 */ 812 bool 813 disable_wp(void) 814 { 815 u_int cr0; 816 817 cr0 = rcr0(); 818 if ((cr0 & CR0_WP) == 0) 819 return (false); 820 load_cr0(cr0 & ~CR0_WP); 821 return (true); 822 } 823 824 void 825 restore_wp(bool old_wp) 826 { 827 828 if (old_wp) 829 load_cr0(rcr0() | CR0_WP); 830 } 831 832