1 /*- 2 * Copyright (c) 2003 Peter Wemm. 3 * Copyright (c) 1992 Terrence R. Lambert. 4 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * William Jolitz. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the University of 21 * California, Berkeley and its contributors. 22 * 4. Neither the name of the University nor the names of its contributors 23 * may be used to endorse or promote products derived from this software 24 * without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 * 38 * from: @(#)machdep.c 7.4 (Berkeley) 6/3/91 39 */ 40 41 #include <sys/cdefs.h> 42 __FBSDID("$FreeBSD$"); 43 44 #include "opt_acpi.h" 45 #include "opt_atpic.h" 46 #include "opt_cpu.h" 47 #include "opt_ddb.h" 48 #include "opt_inet.h" 49 #include "opt_isa.h" 50 #include "opt_kdb.h" 51 #include "opt_kstack_pages.h" 52 #include "opt_maxmem.h" 53 #include "opt_mp_watchdog.h" 54 #include "opt_platform.h" 55 #ifdef __i386__ 56 #include "opt_apic.h" 57 #endif 58 59 #include <sys/param.h> 60 #include <sys/proc.h> 61 #include <sys/systm.h> 62 #include <sys/bus.h> 63 #include <sys/cpu.h> 64 #include <sys/kdb.h> 65 #include <sys/kernel.h> 66 #include <sys/ktr.h> 67 #include <sys/lock.h> 68 #include <sys/malloc.h> 69 #include <sys/mutex.h> 70 #include <sys/pcpu.h> 71 #include <sys/rwlock.h> 72 #include <sys/sched.h> 73 #include <sys/smp.h> 74 #include <sys/sysctl.h> 75 76 #include <machine/clock.h> 77 #include <machine/cpu.h> 78 #include <machine/cputypes.h> 79 #include <machine/specialreg.h> 80 #include <machine/md_var.h> 81 #include <machine/mp_watchdog.h> 82 #include <machine/tss.h> 83 #ifdef SMP 84 #include <machine/smp.h> 85 #endif 86 #ifdef CPU_ELAN 87 #include <machine/elan_mmcr.h> 88 #endif 89 #include <x86/acpica_machdep.h> 90 91 #include <vm/vm.h> 92 #include <vm/vm_extern.h> 93 #include <vm/vm_kern.h> 94 #include <vm/vm_page.h> 95 #include <vm/vm_map.h> 96 #include <vm/vm_object.h> 97 #include <vm/vm_pager.h> 98 #include <vm/vm_param.h> 99 100 #include <isa/isareg.h> 101 102 #include <contrib/dev/acpica/include/acpi.h> 103 104 #define STATE_RUNNING 0x0 105 #define STATE_MWAIT 0x1 106 #define STATE_SLEEPING 0x2 107 108 #ifdef SMP 109 static u_int cpu_reset_proxyid; 110 static volatile u_int cpu_reset_proxy_active; 111 #endif 112 113 /* 114 * Automatically initialized per CPU errata in cpu_idle_tun below. 115 */ 116 bool mwait_cpustop_broken = false; 117 SYSCTL_BOOL(_machdep, OID_AUTO, mwait_cpustop_broken, CTLFLAG_RDTUN, 118 &mwait_cpustop_broken, 0, 119 "Can not reliably wake MONITOR/MWAIT cpus without interrupts"); 120 121 /* 122 * Machine dependent boot() routine 123 * 124 * I haven't seen anything to put here yet 125 * Possibly some stuff might be grafted back here from boot() 126 */ 127 void 128 cpu_boot(int howto) 129 { 130 } 131 132 /* 133 * Flush the D-cache for non-DMA I/O so that the I-cache can 134 * be made coherent later. 135 */ 136 void 137 cpu_flush_dcache(void *ptr, size_t len) 138 { 139 /* Not applicable */ 140 } 141 142 void 143 acpi_cpu_c1(void) 144 { 145 146 __asm __volatile("sti; hlt"); 147 } 148 149 /* 150 * Use mwait to pause execution while waiting for an interrupt or 151 * another thread to signal that there is more work. 152 * 153 * NOTE: Interrupts will cause a wakeup; however, this function does 154 * not enable interrupt handling. The caller is responsible to enable 155 * interrupts. 156 */ 157 void 158 acpi_cpu_idle_mwait(uint32_t mwait_hint) 159 { 160 int *state; 161 uint64_t v; 162 163 /* 164 * A comment in Linux patch claims that 'CPUs run faster with 165 * speculation protection disabled. All CPU threads in a core 166 * must disable speculation protection for it to be 167 * disabled. Disable it while we are idle so the other 168 * hyperthread can run fast.' 169 * 170 * XXXKIB. Software coordination mode should be supported, 171 * but all Intel CPUs provide hardware coordination. 172 */ 173 174 state = &PCPU_PTR(monitorbuf)->idle_state; 175 KASSERT(atomic_load_int(state) == STATE_SLEEPING, 176 ("cpu_mwait_cx: wrong monitorbuf state")); 177 atomic_store_int(state, STATE_MWAIT); 178 if (PCPU_GET(ibpb_set) || hw_ssb_active) { 179 v = rdmsr(MSR_IA32_SPEC_CTRL); 180 wrmsr(MSR_IA32_SPEC_CTRL, v & ~(IA32_SPEC_CTRL_IBRS | 181 IA32_SPEC_CTRL_STIBP | IA32_SPEC_CTRL_SSBD)); 182 } else { 183 v = 0; 184 } 185 cpu_monitor(state, 0, 0); 186 if (atomic_load_int(state) == STATE_MWAIT) 187 cpu_mwait(MWAIT_INTRBREAK, mwait_hint); 188 189 /* 190 * SSB cannot be disabled while we sleep, or rather, if it was 191 * disabled, the sysctl thread will bind to our cpu to tweak 192 * MSR. 193 */ 194 if (v != 0) 195 wrmsr(MSR_IA32_SPEC_CTRL, v); 196 197 /* 198 * We should exit on any event that interrupts mwait, because 199 * that event might be a wanted interrupt. 200 */ 201 atomic_store_int(state, STATE_RUNNING); 202 } 203 204 /* Get current clock frequency for the given cpu id. */ 205 int 206 cpu_est_clockrate(int cpu_id, uint64_t *rate) 207 { 208 uint64_t tsc1, tsc2; 209 uint64_t acnt, mcnt, perf; 210 register_t reg; 211 212 if (pcpu_find(cpu_id) == NULL || rate == NULL) 213 return (EINVAL); 214 #ifdef __i386__ 215 if ((cpu_feature & CPUID_TSC) == 0) 216 return (EOPNOTSUPP); 217 #endif 218 219 /* 220 * If TSC is P-state invariant and APERF/MPERF MSRs do not exist, 221 * DELAY(9) based logic fails. 222 */ 223 if (tsc_is_invariant && !tsc_perf_stat) 224 return (EOPNOTSUPP); 225 226 #ifdef SMP 227 if (smp_cpus > 1) { 228 /* Schedule ourselves on the indicated cpu. */ 229 thread_lock(curthread); 230 sched_bind(curthread, cpu_id); 231 thread_unlock(curthread); 232 } 233 #endif 234 235 /* Calibrate by measuring a short delay. */ 236 reg = intr_disable(); 237 if (tsc_is_invariant) { 238 wrmsr(MSR_MPERF, 0); 239 wrmsr(MSR_APERF, 0); 240 tsc1 = rdtsc(); 241 DELAY(1000); 242 mcnt = rdmsr(MSR_MPERF); 243 acnt = rdmsr(MSR_APERF); 244 tsc2 = rdtsc(); 245 intr_restore(reg); 246 perf = 1000 * acnt / mcnt; 247 *rate = (tsc2 - tsc1) * perf; 248 } else { 249 tsc1 = rdtsc(); 250 DELAY(1000); 251 tsc2 = rdtsc(); 252 intr_restore(reg); 253 *rate = (tsc2 - tsc1) * 1000; 254 } 255 256 #ifdef SMP 257 if (smp_cpus > 1) { 258 thread_lock(curthread); 259 sched_unbind(curthread); 260 thread_unlock(curthread); 261 } 262 #endif 263 264 return (0); 265 } 266 267 /* 268 * Shutdown the CPU as much as possible 269 */ 270 void 271 cpu_halt(void) 272 { 273 for (;;) 274 halt(); 275 } 276 277 static void 278 cpu_reset_real(void) 279 { 280 struct region_descriptor null_idt; 281 int b; 282 283 disable_intr(); 284 #ifdef CPU_ELAN 285 if (elan_mmcr != NULL) 286 elan_mmcr->RESCFG = 1; 287 #endif 288 #ifdef __i386__ 289 if (cpu == CPU_GEODE1100) { 290 /* Attempt Geode's own reset */ 291 outl(0xcf8, 0x80009044ul); 292 outl(0xcfc, 0xf); 293 } 294 #endif 295 #if !defined(BROKEN_KEYBOARD_RESET) 296 /* 297 * Attempt to do a CPU reset via the keyboard controller, 298 * do not turn off GateA20, as any machine that fails 299 * to do the reset here would then end up in no man's land. 300 */ 301 outb(IO_KBD + 4, 0xFE); 302 DELAY(500000); /* wait 0.5 sec to see if that did it */ 303 #endif 304 305 /* 306 * Attempt to force a reset via the Reset Control register at 307 * I/O port 0xcf9. Bit 2 forces a system reset when it 308 * transitions from 0 to 1. Bit 1 selects the type of reset 309 * to attempt: 0 selects a "soft" reset, and 1 selects a 310 * "hard" reset. We try a "hard" reset. The first write sets 311 * bit 1 to select a "hard" reset and clears bit 2. The 312 * second write forces a 0 -> 1 transition in bit 2 to trigger 313 * a reset. 314 */ 315 outb(0xcf9, 0x2); 316 outb(0xcf9, 0x6); 317 DELAY(500000); /* wait 0.5 sec to see if that did it */ 318 319 /* 320 * Attempt to force a reset via the Fast A20 and Init register 321 * at I/O port 0x92. Bit 1 serves as an alternate A20 gate. 322 * Bit 0 asserts INIT# when set to 1. We are careful to only 323 * preserve bit 1 while setting bit 0. We also must clear bit 324 * 0 before setting it if it isn't already clear. 325 */ 326 b = inb(0x92); 327 if (b != 0xff) { 328 if ((b & 0x1) != 0) 329 outb(0x92, b & 0xfe); 330 outb(0x92, b | 0x1); 331 DELAY(500000); /* wait 0.5 sec to see if that did it */ 332 } 333 334 printf("No known reset method worked, attempting CPU shutdown\n"); 335 DELAY(1000000); /* wait 1 sec for printf to complete */ 336 337 /* Wipe the IDT. */ 338 null_idt.rd_limit = 0; 339 null_idt.rd_base = 0; 340 lidt(&null_idt); 341 342 /* "good night, sweet prince .... <THUNK!>" */ 343 breakpoint(); 344 345 /* NOTREACHED */ 346 while(1); 347 } 348 349 #ifdef SMP 350 static void 351 cpu_reset_proxy(void) 352 { 353 354 cpu_reset_proxy_active = 1; 355 while (cpu_reset_proxy_active == 1) 356 ia32_pause(); /* Wait for other cpu to see that we've started */ 357 358 printf("cpu_reset_proxy: Stopped CPU %d\n", cpu_reset_proxyid); 359 DELAY(1000000); 360 cpu_reset_real(); 361 } 362 #endif 363 364 void 365 cpu_reset(void) 366 { 367 #ifdef SMP 368 struct monitorbuf *mb; 369 cpuset_t map; 370 u_int cnt; 371 372 if (smp_started) { 373 map = all_cpus; 374 CPU_CLR(PCPU_GET(cpuid), &map); 375 CPU_NAND(&map, &stopped_cpus); 376 if (!CPU_EMPTY(&map)) { 377 printf("cpu_reset: Stopping other CPUs\n"); 378 stop_cpus(map); 379 } 380 381 if (PCPU_GET(cpuid) != 0) { 382 cpu_reset_proxyid = PCPU_GET(cpuid); 383 cpustop_restartfunc = cpu_reset_proxy; 384 cpu_reset_proxy_active = 0; 385 printf("cpu_reset: Restarting BSP\n"); 386 387 /* Restart CPU #0. */ 388 CPU_SETOF(0, &started_cpus); 389 mb = &pcpu_find(0)->pc_monitorbuf; 390 atomic_store_int(&mb->stop_state, 391 MONITOR_STOPSTATE_RUNNING); 392 wmb(); 393 394 cnt = 0; 395 while (cpu_reset_proxy_active == 0 && cnt < 10000000) { 396 ia32_pause(); 397 cnt++; /* Wait for BSP to announce restart */ 398 } 399 if (cpu_reset_proxy_active == 0) { 400 printf("cpu_reset: Failed to restart BSP\n"); 401 } else { 402 cpu_reset_proxy_active = 2; 403 while (1) 404 ia32_pause(); 405 /* NOTREACHED */ 406 } 407 } 408 409 DELAY(1000000); 410 } 411 #endif 412 cpu_reset_real(); 413 /* NOTREACHED */ 414 } 415 416 bool 417 cpu_mwait_usable(void) 418 { 419 420 return ((cpu_feature2 & CPUID2_MON) != 0 && ((cpu_mon_mwait_flags & 421 (CPUID5_MON_MWAIT_EXT | CPUID5_MWAIT_INTRBREAK)) == 422 (CPUID5_MON_MWAIT_EXT | CPUID5_MWAIT_INTRBREAK))); 423 } 424 425 void (*cpu_idle_hook)(sbintime_t) = NULL; /* ACPI idle hook. */ 426 static int cpu_ident_amdc1e = 0; /* AMD C1E supported. */ 427 static int idle_mwait = 1; /* Use MONITOR/MWAIT for short idle. */ 428 SYSCTL_INT(_machdep, OID_AUTO, idle_mwait, CTLFLAG_RWTUN, &idle_mwait, 429 0, "Use MONITOR/MWAIT for short idle"); 430 431 static void 432 cpu_idle_acpi(sbintime_t sbt) 433 { 434 int *state; 435 436 state = &PCPU_PTR(monitorbuf)->idle_state; 437 atomic_store_int(state, STATE_SLEEPING); 438 439 /* See comments in cpu_idle_hlt(). */ 440 disable_intr(); 441 if (sched_runnable()) 442 enable_intr(); 443 else if (cpu_idle_hook) 444 cpu_idle_hook(sbt); 445 else 446 acpi_cpu_c1(); 447 atomic_store_int(state, STATE_RUNNING); 448 } 449 450 static void 451 cpu_idle_hlt(sbintime_t sbt) 452 { 453 int *state; 454 455 state = &PCPU_PTR(monitorbuf)->idle_state; 456 atomic_store_int(state, STATE_SLEEPING); 457 458 /* 459 * Since we may be in a critical section from cpu_idle(), if 460 * an interrupt fires during that critical section we may have 461 * a pending preemption. If the CPU halts, then that thread 462 * may not execute until a later interrupt awakens the CPU. 463 * To handle this race, check for a runnable thread after 464 * disabling interrupts and immediately return if one is 465 * found. Also, we must absolutely guarentee that hlt is 466 * the next instruction after sti. This ensures that any 467 * interrupt that fires after the call to disable_intr() will 468 * immediately awaken the CPU from hlt. Finally, please note 469 * that on x86 this works fine because of interrupts enabled only 470 * after the instruction following sti takes place, while IF is set 471 * to 1 immediately, allowing hlt instruction to acknowledge the 472 * interrupt. 473 */ 474 disable_intr(); 475 if (sched_runnable()) 476 enable_intr(); 477 else 478 acpi_cpu_c1(); 479 atomic_store_int(state, STATE_RUNNING); 480 } 481 482 static void 483 cpu_idle_mwait(sbintime_t sbt) 484 { 485 int *state; 486 487 state = &PCPU_PTR(monitorbuf)->idle_state; 488 atomic_store_int(state, STATE_MWAIT); 489 490 /* See comments in cpu_idle_hlt(). */ 491 disable_intr(); 492 if (sched_runnable()) { 493 atomic_store_int(state, STATE_RUNNING); 494 enable_intr(); 495 return; 496 } 497 498 cpu_monitor(state, 0, 0); 499 if (atomic_load_int(state) == STATE_MWAIT) 500 __asm __volatile("sti; mwait" : : "a" (MWAIT_C1), "c" (0)); 501 else 502 enable_intr(); 503 atomic_store_int(state, STATE_RUNNING); 504 } 505 506 static void 507 cpu_idle_spin(sbintime_t sbt) 508 { 509 int *state; 510 int i; 511 512 state = &PCPU_PTR(monitorbuf)->idle_state; 513 atomic_store_int(state, STATE_RUNNING); 514 515 /* 516 * The sched_runnable() call is racy but as long as there is 517 * a loop missing it one time will have just a little impact if any 518 * (and it is much better than missing the check at all). 519 */ 520 for (i = 0; i < 1000; i++) { 521 if (sched_runnable()) 522 return; 523 cpu_spinwait(); 524 } 525 } 526 527 /* 528 * C1E renders the local APIC timer dead, so we disable it by 529 * reading the Interrupt Pending Message register and clearing 530 * both C1eOnCmpHalt (bit 28) and SmiOnCmpHalt (bit 27). 531 * 532 * Reference: 533 * "BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh Processors" 534 * #32559 revision 3.00+ 535 */ 536 #define MSR_AMDK8_IPM 0xc0010055 537 #define AMDK8_SMIONCMPHALT (1ULL << 27) 538 #define AMDK8_C1EONCMPHALT (1ULL << 28) 539 #define AMDK8_CMPHALT (AMDK8_SMIONCMPHALT | AMDK8_C1EONCMPHALT) 540 541 void 542 cpu_probe_amdc1e(void) 543 { 544 545 /* 546 * Detect the presence of C1E capability mostly on latest 547 * dual-cores (or future) k8 family. 548 */ 549 if (cpu_vendor_id == CPU_VENDOR_AMD && 550 (cpu_id & 0x00000f00) == 0x00000f00 && 551 (cpu_id & 0x0fff0000) >= 0x00040000) { 552 cpu_ident_amdc1e = 1; 553 } 554 } 555 556 void (*cpu_idle_fn)(sbintime_t) = cpu_idle_acpi; 557 558 void 559 cpu_idle(int busy) 560 { 561 uint64_t msr; 562 sbintime_t sbt = -1; 563 564 CTR2(KTR_SPARE2, "cpu_idle(%d) at %d", 565 busy, curcpu); 566 #ifdef MP_WATCHDOG 567 ap_watchdog(PCPU_GET(cpuid)); 568 #endif 569 570 /* If we are busy - try to use fast methods. */ 571 if (busy) { 572 if ((cpu_feature2 & CPUID2_MON) && idle_mwait) { 573 cpu_idle_mwait(busy); 574 goto out; 575 } 576 } 577 578 /* If we have time - switch timers into idle mode. */ 579 if (!busy) { 580 critical_enter(); 581 sbt = cpu_idleclock(); 582 } 583 584 /* Apply AMD APIC timer C1E workaround. */ 585 if (cpu_ident_amdc1e && cpu_disable_c3_sleep) { 586 msr = rdmsr(MSR_AMDK8_IPM); 587 if (msr & AMDK8_CMPHALT) 588 wrmsr(MSR_AMDK8_IPM, msr & ~AMDK8_CMPHALT); 589 } 590 591 /* Call main idle method. */ 592 cpu_idle_fn(sbt); 593 594 /* Switch timers back into active mode. */ 595 if (!busy) { 596 cpu_activeclock(); 597 critical_exit(); 598 } 599 out: 600 CTR2(KTR_SPARE2, "cpu_idle(%d) at %d done", 601 busy, curcpu); 602 } 603 604 static int cpu_idle_apl31_workaround; 605 SYSCTL_INT(_machdep, OID_AUTO, idle_apl31, CTLFLAG_RW, 606 &cpu_idle_apl31_workaround, 0, 607 "Apollo Lake APL31 MWAIT bug workaround"); 608 609 int 610 cpu_idle_wakeup(int cpu) 611 { 612 struct monitorbuf *mb; 613 int *state; 614 615 mb = &pcpu_find(cpu)->pc_monitorbuf; 616 state = &mb->idle_state; 617 switch (atomic_load_int(state)) { 618 case STATE_SLEEPING: 619 return (0); 620 case STATE_MWAIT: 621 atomic_store_int(state, STATE_RUNNING); 622 return (cpu_idle_apl31_workaround ? 0 : 1); 623 case STATE_RUNNING: 624 return (1); 625 default: 626 panic("bad monitor state"); 627 return (1); 628 } 629 } 630 631 /* 632 * Ordered by speed/power consumption. 633 */ 634 static struct { 635 void *id_fn; 636 char *id_name; 637 int id_cpuid2_flag; 638 } idle_tbl[] = { 639 { .id_fn = cpu_idle_spin, .id_name = "spin" }, 640 { .id_fn = cpu_idle_mwait, .id_name = "mwait", 641 .id_cpuid2_flag = CPUID2_MON }, 642 { .id_fn = cpu_idle_hlt, .id_name = "hlt" }, 643 { .id_fn = cpu_idle_acpi, .id_name = "acpi" }, 644 }; 645 646 static int 647 idle_sysctl_available(SYSCTL_HANDLER_ARGS) 648 { 649 char *avail, *p; 650 int error; 651 int i; 652 653 avail = malloc(256, M_TEMP, M_WAITOK); 654 p = avail; 655 for (i = 0; i < nitems(idle_tbl); i++) { 656 if (idle_tbl[i].id_cpuid2_flag != 0 && 657 (cpu_feature2 & idle_tbl[i].id_cpuid2_flag) == 0) 658 continue; 659 if (strcmp(idle_tbl[i].id_name, "acpi") == 0 && 660 cpu_idle_hook == NULL) 661 continue; 662 p += sprintf(p, "%s%s", p != avail ? ", " : "", 663 idle_tbl[i].id_name); 664 } 665 error = sysctl_handle_string(oidp, avail, 0, req); 666 free(avail, M_TEMP); 667 return (error); 668 } 669 670 SYSCTL_PROC(_machdep, OID_AUTO, idle_available, CTLTYPE_STRING | CTLFLAG_RD, 671 0, 0, idle_sysctl_available, "A", "list of available idle functions"); 672 673 static bool 674 cpu_idle_selector(const char *new_idle_name) 675 { 676 int i; 677 678 for (i = 0; i < nitems(idle_tbl); i++) { 679 if (idle_tbl[i].id_cpuid2_flag != 0 && 680 (cpu_feature2 & idle_tbl[i].id_cpuid2_flag) == 0) 681 continue; 682 if (strcmp(idle_tbl[i].id_name, "acpi") == 0 && 683 cpu_idle_hook == NULL) 684 continue; 685 if (strcmp(idle_tbl[i].id_name, new_idle_name)) 686 continue; 687 cpu_idle_fn = idle_tbl[i].id_fn; 688 if (bootverbose) 689 printf("CPU idle set to %s\n", idle_tbl[i].id_name); 690 return (true); 691 } 692 return (false); 693 } 694 695 static int 696 cpu_idle_sysctl(SYSCTL_HANDLER_ARGS) 697 { 698 char buf[16], *p; 699 int error, i; 700 701 p = "unknown"; 702 for (i = 0; i < nitems(idle_tbl); i++) { 703 if (idle_tbl[i].id_fn == cpu_idle_fn) { 704 p = idle_tbl[i].id_name; 705 break; 706 } 707 } 708 strncpy(buf, p, sizeof(buf)); 709 error = sysctl_handle_string(oidp, buf, sizeof(buf), req); 710 if (error != 0 || req->newptr == NULL) 711 return (error); 712 return (cpu_idle_selector(buf) ? 0 : EINVAL); 713 } 714 715 SYSCTL_PROC(_machdep, OID_AUTO, idle, CTLTYPE_STRING | CTLFLAG_RW, 0, 0, 716 cpu_idle_sysctl, "A", "currently selected idle function"); 717 718 static void 719 cpu_idle_tun(void *unused __unused) 720 { 721 char tunvar[16]; 722 723 if (TUNABLE_STR_FETCH("machdep.idle", tunvar, sizeof(tunvar))) 724 cpu_idle_selector(tunvar); 725 else if (cpu_vendor_id == CPU_VENDOR_AMD && 726 CPUID_TO_FAMILY(cpu_id) == 0x17 && CPUID_TO_MODEL(cpu_id) == 0x1) { 727 /* Ryzen erratas 1057, 1109. */ 728 cpu_idle_selector("hlt"); 729 idle_mwait = 0; 730 mwait_cpustop_broken = true; 731 } 732 733 if (cpu_vendor_id == CPU_VENDOR_INTEL && cpu_id == 0x506c9) { 734 /* 735 * Apollo Lake errata APL31 (public errata APL30). 736 * Stores to the armed address range may not trigger 737 * MWAIT to resume execution. OS needs to use 738 * interrupts to wake processors from MWAIT-induced 739 * sleep states. 740 */ 741 cpu_idle_apl31_workaround = 1; 742 mwait_cpustop_broken = true; 743 } 744 TUNABLE_INT_FETCH("machdep.idle_apl31", &cpu_idle_apl31_workaround); 745 } 746 SYSINIT(cpu_idle_tun, SI_SUB_CPU, SI_ORDER_MIDDLE, cpu_idle_tun, NULL); 747 748 static int panic_on_nmi = 1; 749 SYSCTL_INT(_machdep, OID_AUTO, panic_on_nmi, CTLFLAG_RWTUN, 750 &panic_on_nmi, 0, 751 "Panic on NMI raised by hardware failure"); 752 int nmi_is_broadcast = 1; 753 SYSCTL_INT(_machdep, OID_AUTO, nmi_is_broadcast, CTLFLAG_RWTUN, 754 &nmi_is_broadcast, 0, 755 "Chipset NMI is broadcast"); 756 #ifdef KDB 757 int kdb_on_nmi = 1; 758 SYSCTL_INT(_machdep, OID_AUTO, kdb_on_nmi, CTLFLAG_RWTUN, 759 &kdb_on_nmi, 0, 760 "Go to KDB on NMI with unknown source"); 761 #endif 762 763 void 764 nmi_call_kdb(u_int cpu, u_int type, struct trapframe *frame) 765 { 766 bool claimed = false; 767 768 #ifdef DEV_ISA 769 /* machine/parity/power fail/"kitchen sink" faults */ 770 if (isa_nmi(frame->tf_err)) { 771 claimed = true; 772 if (panic_on_nmi) 773 panic("NMI indicates hardware failure"); 774 } 775 #endif /* DEV_ISA */ 776 #ifdef KDB 777 if (!claimed && kdb_on_nmi) { 778 /* 779 * NMI can be hooked up to a pushbutton for debugging. 780 */ 781 printf("NMI/cpu%d ... going to debugger\n", cpu); 782 kdb_trap(type, 0, frame); 783 } 784 #endif /* KDB */ 785 } 786 787 void 788 nmi_handle_intr(u_int type, struct trapframe *frame) 789 { 790 791 #ifdef SMP 792 if (nmi_is_broadcast) { 793 nmi_call_kdb_smp(type, frame); 794 return; 795 } 796 #endif 797 nmi_call_kdb(PCPU_GET(cpuid), type, frame); 798 } 799 800 int hw_ibrs_active; 801 int hw_ibrs_disable = 1; 802 803 SYSCTL_INT(_hw, OID_AUTO, ibrs_active, CTLFLAG_RD, &hw_ibrs_active, 0, 804 "Indirect Branch Restricted Speculation active"); 805 806 void 807 hw_ibrs_recalculate(void) 808 { 809 uint64_t v; 810 811 if ((cpu_ia32_arch_caps & IA32_ARCH_CAP_IBRS_ALL) != 0) { 812 if (hw_ibrs_disable) { 813 v = rdmsr(MSR_IA32_SPEC_CTRL); 814 v &= ~(uint64_t)IA32_SPEC_CTRL_IBRS; 815 wrmsr(MSR_IA32_SPEC_CTRL, v); 816 } else { 817 v = rdmsr(MSR_IA32_SPEC_CTRL); 818 v |= IA32_SPEC_CTRL_IBRS; 819 wrmsr(MSR_IA32_SPEC_CTRL, v); 820 } 821 return; 822 } 823 hw_ibrs_active = (cpu_stdext_feature3 & CPUID_STDEXT3_IBPB) != 0 && 824 !hw_ibrs_disable; 825 } 826 827 static int 828 hw_ibrs_disable_handler(SYSCTL_HANDLER_ARGS) 829 { 830 int error, val; 831 832 val = hw_ibrs_disable; 833 error = sysctl_handle_int(oidp, &val, 0, req); 834 if (error != 0 || req->newptr == NULL) 835 return (error); 836 hw_ibrs_disable = val != 0; 837 hw_ibrs_recalculate(); 838 return (0); 839 } 840 SYSCTL_PROC(_hw, OID_AUTO, ibrs_disable, CTLTYPE_INT | CTLFLAG_RWTUN | 841 CTLFLAG_NOFETCH | CTLFLAG_MPSAFE, NULL, 0, hw_ibrs_disable_handler, "I", 842 "Disable Indirect Branch Restricted Speculation"); 843 844 int hw_ssb_active; 845 int hw_ssb_disable; 846 847 SYSCTL_INT(_hw, OID_AUTO, spec_store_bypass_disable_active, CTLFLAG_RD, 848 &hw_ssb_active, 0, 849 "Speculative Store Bypass Disable active"); 850 851 static void 852 hw_ssb_set_one(bool enable) 853 { 854 uint64_t v; 855 856 v = rdmsr(MSR_IA32_SPEC_CTRL); 857 if (enable) 858 v |= (uint64_t)IA32_SPEC_CTRL_SSBD; 859 else 860 v &= ~(uint64_t)IA32_SPEC_CTRL_SSBD; 861 wrmsr(MSR_IA32_SPEC_CTRL, v); 862 } 863 864 static void 865 hw_ssb_set(bool enable, bool for_all_cpus) 866 { 867 struct thread *td; 868 int bound_cpu, i, is_bound; 869 870 if ((cpu_stdext_feature3 & CPUID_STDEXT3_SSBD) == 0) { 871 hw_ssb_active = 0; 872 return; 873 } 874 hw_ssb_active = enable; 875 if (for_all_cpus) { 876 td = curthread; 877 thread_lock(td); 878 is_bound = sched_is_bound(td); 879 bound_cpu = td->td_oncpu; 880 CPU_FOREACH(i) { 881 sched_bind(td, i); 882 hw_ssb_set_one(enable); 883 } 884 if (is_bound) 885 sched_bind(td, bound_cpu); 886 else 887 sched_unbind(td); 888 thread_unlock(td); 889 } else { 890 hw_ssb_set_one(enable); 891 } 892 } 893 894 void 895 hw_ssb_recalculate(bool all_cpus) 896 { 897 898 switch (hw_ssb_disable) { 899 default: 900 hw_ssb_disable = 0; 901 /* FALLTHROUGH */ 902 case 0: /* off */ 903 hw_ssb_set(false, all_cpus); 904 break; 905 case 1: /* on */ 906 hw_ssb_set(true, all_cpus); 907 break; 908 case 2: /* auto */ 909 hw_ssb_set((cpu_ia32_arch_caps & IA32_ARCH_CAP_SSB_NO) != 0 ? 910 false : true, all_cpus); 911 break; 912 } 913 } 914 915 static int 916 hw_ssb_disable_handler(SYSCTL_HANDLER_ARGS) 917 { 918 int error, val; 919 920 val = hw_ssb_disable; 921 error = sysctl_handle_int(oidp, &val, 0, req); 922 if (error != 0 || req->newptr == NULL) 923 return (error); 924 hw_ssb_disable = val; 925 hw_ssb_recalculate(true); 926 return (0); 927 } 928 SYSCTL_PROC(_hw, OID_AUTO, spec_store_bypass_disable, CTLTYPE_INT | 929 CTLFLAG_RWTUN | CTLFLAG_NOFETCH | CTLFLAG_MPSAFE, NULL, 0, 930 hw_ssb_disable_handler, "I", 931 "Speculative Store Bypass Disable (0 - off, 1 - on, 2 - auto"); 932 933 /* 934 * Enable and restore kernel text write permissions. 935 * Callers must ensure that disable_wp()/restore_wp() are executed 936 * without rescheduling on the same core. 937 */ 938 bool 939 disable_wp(void) 940 { 941 u_int cr0; 942 943 cr0 = rcr0(); 944 if ((cr0 & CR0_WP) == 0) 945 return (false); 946 load_cr0(cr0 & ~CR0_WP); 947 return (true); 948 } 949 950 void 951 restore_wp(bool old_wp) 952 { 953 954 if (old_wp) 955 load_cr0(rcr0() | CR0_WP); 956 } 957 958 bool 959 acpi_get_fadt_bootflags(uint16_t *flagsp) 960 { 961 #ifdef DEV_ACPI 962 ACPI_TABLE_FADT *fadt; 963 vm_paddr_t physaddr; 964 965 physaddr = acpi_find_table(ACPI_SIG_FADT); 966 if (physaddr == 0) 967 return (false); 968 fadt = acpi_map_table(physaddr, ACPI_SIG_FADT); 969 if (fadt == NULL) 970 return (false); 971 *flagsp = fadt->BootFlags; 972 acpi_unmap_table(fadt); 973 return (true); 974 #else 975 return (false); 976 #endif 977 } 978