1 /*- 2 * Copyright (c) 2003 Peter Wemm. 3 * Copyright (c) 1992 Terrence R. Lambert. 4 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * William Jolitz. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the University of 21 * California, Berkeley and its contributors. 22 * 4. Neither the name of the University nor the names of its contributors 23 * may be used to endorse or promote products derived from this software 24 * without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 * 38 * from: @(#)machdep.c 7.4 (Berkeley) 6/3/91 39 */ 40 41 #include <sys/cdefs.h> 42 __FBSDID("$FreeBSD$"); 43 44 #include "opt_atpic.h" 45 #include "opt_compat.h" 46 #include "opt_cpu.h" 47 #include "opt_ddb.h" 48 #include "opt_inet.h" 49 #include "opt_isa.h" 50 #include "opt_kdb.h" 51 #include "opt_kstack_pages.h" 52 #include "opt_maxmem.h" 53 #include "opt_mp_watchdog.h" 54 #include "opt_platform.h" 55 #ifdef __i386__ 56 #include "opt_npx.h" 57 #include "opt_apic.h" 58 #include "opt_xbox.h" 59 #endif 60 61 #include <sys/param.h> 62 #include <sys/proc.h> 63 #include <sys/systm.h> 64 #include <sys/bus.h> 65 #include <sys/cpu.h> 66 #include <sys/kdb.h> 67 #include <sys/kernel.h> 68 #include <sys/ktr.h> 69 #include <sys/lock.h> 70 #include <sys/malloc.h> 71 #include <sys/mutex.h> 72 #include <sys/pcpu.h> 73 #include <sys/rwlock.h> 74 #include <sys/sched.h> 75 #ifdef SMP 76 #include <sys/smp.h> 77 #endif 78 #include <sys/sysctl.h> 79 80 #include <machine/clock.h> 81 #include <machine/cpu.h> 82 #include <machine/cputypes.h> 83 #include <machine/specialreg.h> 84 #include <machine/md_var.h> 85 #include <machine/mp_watchdog.h> 86 #include <machine/tss.h> 87 #ifdef SMP 88 #include <machine/smp.h> 89 #endif 90 #include <x86/acpica_machdep.h> 91 92 #include <vm/vm.h> 93 #include <vm/vm_extern.h> 94 #include <vm/vm_kern.h> 95 #include <vm/vm_page.h> 96 #include <vm/vm_map.h> 97 #include <vm/vm_object.h> 98 #include <vm/vm_pager.h> 99 #include <vm/vm_param.h> 100 101 #define STATE_RUNNING 0x0 102 #define STATE_MWAIT 0x1 103 #define STATE_SLEEPING 0x2 104 105 /* 106 * Machine dependent boot() routine 107 * 108 * I haven't seen anything to put here yet 109 * Possibly some stuff might be grafted back here from boot() 110 */ 111 void 112 cpu_boot(int howto) 113 { 114 } 115 116 /* 117 * Flush the D-cache for non-DMA I/O so that the I-cache can 118 * be made coherent later. 119 */ 120 void 121 cpu_flush_dcache(void *ptr, size_t len) 122 { 123 /* Not applicable */ 124 } 125 126 void 127 acpi_cpu_c1(void) 128 { 129 130 __asm __volatile("sti; hlt"); 131 } 132 133 void 134 acpi_cpu_idle_mwait(uint32_t mwait_hint) 135 { 136 int *state; 137 138 /* 139 * XXXKIB. Software coordination mode should be supported, 140 * but all Intel CPUs provide hardware coordination. 141 */ 142 143 state = (int *)PCPU_PTR(monitorbuf); 144 KASSERT(*state == STATE_SLEEPING, 145 ("cpu_mwait_cx: wrong monitorbuf state")); 146 *state = STATE_MWAIT; 147 cpu_monitor(state, 0, 0); 148 if (*state == STATE_MWAIT) 149 cpu_mwait(MWAIT_INTRBREAK, mwait_hint); 150 151 /* 152 * We should exit on any event that interrupts mwait, because 153 * that event might be a wanted interrupt. 154 */ 155 *state = STATE_RUNNING; 156 } 157 158 /* Get current clock frequency for the given cpu id. */ 159 int 160 cpu_est_clockrate(int cpu_id, uint64_t *rate) 161 { 162 uint64_t tsc1, tsc2; 163 uint64_t acnt, mcnt, perf; 164 register_t reg; 165 166 if (pcpu_find(cpu_id) == NULL || rate == NULL) 167 return (EINVAL); 168 #ifdef __i386__ 169 if ((cpu_feature & CPUID_TSC) == 0) 170 return (EOPNOTSUPP); 171 #endif 172 173 /* 174 * If TSC is P-state invariant and APERF/MPERF MSRs do not exist, 175 * DELAY(9) based logic fails. 176 */ 177 if (tsc_is_invariant && !tsc_perf_stat) 178 return (EOPNOTSUPP); 179 180 #ifdef SMP 181 if (smp_cpus > 1) { 182 /* Schedule ourselves on the indicated cpu. */ 183 thread_lock(curthread); 184 sched_bind(curthread, cpu_id); 185 thread_unlock(curthread); 186 } 187 #endif 188 189 /* Calibrate by measuring a short delay. */ 190 reg = intr_disable(); 191 if (tsc_is_invariant) { 192 wrmsr(MSR_MPERF, 0); 193 wrmsr(MSR_APERF, 0); 194 tsc1 = rdtsc(); 195 DELAY(1000); 196 mcnt = rdmsr(MSR_MPERF); 197 acnt = rdmsr(MSR_APERF); 198 tsc2 = rdtsc(); 199 intr_restore(reg); 200 perf = 1000 * acnt / mcnt; 201 *rate = (tsc2 - tsc1) * perf; 202 } else { 203 tsc1 = rdtsc(); 204 DELAY(1000); 205 tsc2 = rdtsc(); 206 intr_restore(reg); 207 *rate = (tsc2 - tsc1) * 1000; 208 } 209 210 #ifdef SMP 211 if (smp_cpus > 1) { 212 thread_lock(curthread); 213 sched_unbind(curthread); 214 thread_unlock(curthread); 215 } 216 #endif 217 218 return (0); 219 } 220 221 /* 222 * Shutdown the CPU as much as possible 223 */ 224 void 225 cpu_halt(void) 226 { 227 for (;;) 228 halt(); 229 } 230 231 bool 232 cpu_mwait_usable(void) 233 { 234 235 return ((cpu_feature2 & CPUID2_MON) != 0 && ((cpu_mon_mwait_flags & 236 (CPUID5_MON_MWAIT_EXT | CPUID5_MWAIT_INTRBREAK)) == 237 (CPUID5_MON_MWAIT_EXT | CPUID5_MWAIT_INTRBREAK))); 238 } 239 240 void (*cpu_idle_hook)(sbintime_t) = NULL; /* ACPI idle hook. */ 241 static int cpu_ident_amdc1e = 0; /* AMD C1E supported. */ 242 static int idle_mwait = 1; /* Use MONITOR/MWAIT for short idle. */ 243 SYSCTL_INT(_machdep, OID_AUTO, idle_mwait, CTLFLAG_RWTUN, &idle_mwait, 244 0, "Use MONITOR/MWAIT for short idle"); 245 246 #ifndef PC98 247 static void 248 cpu_idle_acpi(sbintime_t sbt) 249 { 250 int *state; 251 252 state = (int *)PCPU_PTR(monitorbuf); 253 *state = STATE_SLEEPING; 254 255 /* See comments in cpu_idle_hlt(). */ 256 disable_intr(); 257 if (sched_runnable()) 258 enable_intr(); 259 else if (cpu_idle_hook) 260 cpu_idle_hook(sbt); 261 else 262 acpi_cpu_c1(); 263 *state = STATE_RUNNING; 264 } 265 #endif /* !PC98 */ 266 267 static void 268 cpu_idle_hlt(sbintime_t sbt) 269 { 270 int *state; 271 272 state = (int *)PCPU_PTR(monitorbuf); 273 *state = STATE_SLEEPING; 274 275 /* 276 * Since we may be in a critical section from cpu_idle(), if 277 * an interrupt fires during that critical section we may have 278 * a pending preemption. If the CPU halts, then that thread 279 * may not execute until a later interrupt awakens the CPU. 280 * To handle this race, check for a runnable thread after 281 * disabling interrupts and immediately return if one is 282 * found. Also, we must absolutely guarentee that hlt is 283 * the next instruction after sti. This ensures that any 284 * interrupt that fires after the call to disable_intr() will 285 * immediately awaken the CPU from hlt. Finally, please note 286 * that on x86 this works fine because of interrupts enabled only 287 * after the instruction following sti takes place, while IF is set 288 * to 1 immediately, allowing hlt instruction to acknowledge the 289 * interrupt. 290 */ 291 disable_intr(); 292 if (sched_runnable()) 293 enable_intr(); 294 else 295 acpi_cpu_c1(); 296 *state = STATE_RUNNING; 297 } 298 299 static void 300 cpu_idle_mwait(sbintime_t sbt) 301 { 302 int *state; 303 304 state = (int *)PCPU_PTR(monitorbuf); 305 *state = STATE_MWAIT; 306 307 /* See comments in cpu_idle_hlt(). */ 308 disable_intr(); 309 if (sched_runnable()) { 310 enable_intr(); 311 *state = STATE_RUNNING; 312 return; 313 } 314 cpu_monitor(state, 0, 0); 315 if (*state == STATE_MWAIT) 316 __asm __volatile("sti; mwait" : : "a" (MWAIT_C1), "c" (0)); 317 else 318 enable_intr(); 319 *state = STATE_RUNNING; 320 } 321 322 static void 323 cpu_idle_spin(sbintime_t sbt) 324 { 325 int *state; 326 int i; 327 328 state = (int *)PCPU_PTR(monitorbuf); 329 *state = STATE_RUNNING; 330 331 /* 332 * The sched_runnable() call is racy but as long as there is 333 * a loop missing it one time will have just a little impact if any 334 * (and it is much better than missing the check at all). 335 */ 336 for (i = 0; i < 1000; i++) { 337 if (sched_runnable()) 338 return; 339 cpu_spinwait(); 340 } 341 } 342 343 /* 344 * C1E renders the local APIC timer dead, so we disable it by 345 * reading the Interrupt Pending Message register and clearing 346 * both C1eOnCmpHalt (bit 28) and SmiOnCmpHalt (bit 27). 347 * 348 * Reference: 349 * "BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh Processors" 350 * #32559 revision 3.00+ 351 */ 352 #define MSR_AMDK8_IPM 0xc0010055 353 #define AMDK8_SMIONCMPHALT (1ULL << 27) 354 #define AMDK8_C1EONCMPHALT (1ULL << 28) 355 #define AMDK8_CMPHALT (AMDK8_SMIONCMPHALT | AMDK8_C1EONCMPHALT) 356 357 void 358 cpu_probe_amdc1e(void) 359 { 360 361 /* 362 * Detect the presence of C1E capability mostly on latest 363 * dual-cores (or future) k8 family. 364 */ 365 if (cpu_vendor_id == CPU_VENDOR_AMD && 366 (cpu_id & 0x00000f00) == 0x00000f00 && 367 (cpu_id & 0x0fff0000) >= 0x00040000) { 368 cpu_ident_amdc1e = 1; 369 } 370 } 371 372 #if defined(__i386__) && defined(PC98) 373 void (*cpu_idle_fn)(sbintime_t) = cpu_idle_hlt; 374 #else 375 void (*cpu_idle_fn)(sbintime_t) = cpu_idle_acpi; 376 #endif 377 378 void 379 cpu_idle(int busy) 380 { 381 uint64_t msr; 382 sbintime_t sbt = -1; 383 384 CTR2(KTR_SPARE2, "cpu_idle(%d) at %d", 385 busy, curcpu); 386 #ifdef MP_WATCHDOG 387 ap_watchdog(PCPU_GET(cpuid)); 388 #endif 389 390 /* If we are busy - try to use fast methods. */ 391 if (busy) { 392 if ((cpu_feature2 & CPUID2_MON) && idle_mwait) { 393 cpu_idle_mwait(busy); 394 goto out; 395 } 396 } 397 398 /* If we have time - switch timers into idle mode. */ 399 if (!busy) { 400 critical_enter(); 401 sbt = cpu_idleclock(); 402 } 403 404 /* Apply AMD APIC timer C1E workaround. */ 405 if (cpu_ident_amdc1e && cpu_disable_c3_sleep) { 406 msr = rdmsr(MSR_AMDK8_IPM); 407 if (msr & AMDK8_CMPHALT) 408 wrmsr(MSR_AMDK8_IPM, msr & ~AMDK8_CMPHALT); 409 } 410 411 /* Call main idle method. */ 412 cpu_idle_fn(sbt); 413 414 /* Switch timers back into active mode. */ 415 if (!busy) { 416 cpu_activeclock(); 417 critical_exit(); 418 } 419 out: 420 CTR2(KTR_SPARE2, "cpu_idle(%d) at %d done", 421 busy, curcpu); 422 } 423 424 int 425 cpu_idle_wakeup(int cpu) 426 { 427 struct pcpu *pcpu; 428 int *state; 429 430 pcpu = pcpu_find(cpu); 431 state = (int *)pcpu->pc_monitorbuf; 432 /* 433 * This doesn't need to be atomic since missing the race will 434 * simply result in unnecessary IPIs. 435 */ 436 if (*state == STATE_SLEEPING) 437 return (0); 438 if (*state == STATE_MWAIT) 439 *state = STATE_RUNNING; 440 return (1); 441 } 442 443 /* 444 * Ordered by speed/power consumption. 445 */ 446 struct { 447 void *id_fn; 448 char *id_name; 449 } idle_tbl[] = { 450 { cpu_idle_spin, "spin" }, 451 { cpu_idle_mwait, "mwait" }, 452 { cpu_idle_hlt, "hlt" }, 453 #if !defined(__i386__) || !defined(PC98) 454 { cpu_idle_acpi, "acpi" }, 455 #endif 456 { NULL, NULL } 457 }; 458 459 static int 460 idle_sysctl_available(SYSCTL_HANDLER_ARGS) 461 { 462 char *avail, *p; 463 int error; 464 int i; 465 466 avail = malloc(256, M_TEMP, M_WAITOK); 467 p = avail; 468 for (i = 0; idle_tbl[i].id_name != NULL; i++) { 469 if (strstr(idle_tbl[i].id_name, "mwait") && 470 (cpu_feature2 & CPUID2_MON) == 0) 471 continue; 472 #if !defined(__i386__) || !defined(PC98) 473 if (strcmp(idle_tbl[i].id_name, "acpi") == 0 && 474 cpu_idle_hook == NULL) 475 continue; 476 #endif 477 p += sprintf(p, "%s%s", p != avail ? ", " : "", 478 idle_tbl[i].id_name); 479 } 480 error = sysctl_handle_string(oidp, avail, 0, req); 481 free(avail, M_TEMP); 482 return (error); 483 } 484 485 SYSCTL_PROC(_machdep, OID_AUTO, idle_available, CTLTYPE_STRING | CTLFLAG_RD, 486 0, 0, idle_sysctl_available, "A", "list of available idle functions"); 487 488 static int 489 idle_sysctl(SYSCTL_HANDLER_ARGS) 490 { 491 char buf[16]; 492 int error; 493 char *p; 494 int i; 495 496 p = "unknown"; 497 for (i = 0; idle_tbl[i].id_name != NULL; i++) { 498 if (idle_tbl[i].id_fn == cpu_idle_fn) { 499 p = idle_tbl[i].id_name; 500 break; 501 } 502 } 503 strncpy(buf, p, sizeof(buf)); 504 error = sysctl_handle_string(oidp, buf, sizeof(buf), req); 505 if (error != 0 || req->newptr == NULL) 506 return (error); 507 for (i = 0; idle_tbl[i].id_name != NULL; i++) { 508 if (strstr(idle_tbl[i].id_name, "mwait") && 509 (cpu_feature2 & CPUID2_MON) == 0) 510 continue; 511 #if !defined(__i386__) || !defined(PC98) 512 if (strcmp(idle_tbl[i].id_name, "acpi") == 0 && 513 cpu_idle_hook == NULL) 514 continue; 515 #endif 516 if (strcmp(idle_tbl[i].id_name, buf)) 517 continue; 518 cpu_idle_fn = idle_tbl[i].id_fn; 519 return (0); 520 } 521 return (EINVAL); 522 } 523 524 SYSCTL_PROC(_machdep, OID_AUTO, idle, CTLTYPE_STRING | CTLFLAG_RW, 0, 0, 525 idle_sysctl, "A", "currently selected idle function"); 526 527 static int panic_on_nmi = 1; 528 SYSCTL_INT(_machdep, OID_AUTO, panic_on_nmi, CTLFLAG_RWTUN, 529 &panic_on_nmi, 0, 530 "Panic on NMI"); 531 int nmi_is_broadcast = 1; 532 SYSCTL_INT(_machdep, OID_AUTO, nmi_is_broadcast, CTLFLAG_RWTUN, 533 &nmi_is_broadcast, 0, 534 "Chipset NMI is broadcast"); 535 #ifdef KDB 536 int kdb_on_nmi = 1; 537 SYSCTL_INT(_machdep, OID_AUTO, kdb_on_nmi, CTLFLAG_RWTUN, 538 &kdb_on_nmi, 0, 539 "Go to KDB on NMI"); 540 #endif 541 542 #ifdef DEV_ISA 543 void 544 nmi_call_kdb(u_int cpu, u_int type, struct trapframe *frame) 545 { 546 547 /* machine/parity/power fail/"kitchen sink" faults */ 548 if (isa_nmi(frame->tf_err) == 0) { 549 #ifdef KDB 550 /* 551 * NMI can be hooked up to a pushbutton for debugging. 552 */ 553 if (kdb_on_nmi) { 554 printf("NMI/cpu%d ... going to debugger\n", cpu); 555 kdb_trap(type, 0, frame); 556 } 557 #endif /* KDB */ 558 } else if (panic_on_nmi) { 559 panic("NMI indicates hardware failure"); 560 } 561 } 562 #endif 563 564 void 565 nmi_handle_intr(u_int type, struct trapframe *frame) 566 { 567 568 #ifdef DEV_ISA 569 #ifdef SMP 570 if (nmi_is_broadcast) { 571 nmi_call_kdb_smp(type, frame); 572 return; 573 } 574 #endif 575 nmi_call_kdb(PCPU_GET(cpuid), type, frame); 576 #endif 577 } 578