1 /*- 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include "opt_cpu.h" 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/bus.h> 35 #include <sys/kernel.h> 36 #include <sys/malloc.h> 37 #include <sys/module.h> 38 #include <sys/rman.h> 39 #include <sys/sysctl.h> 40 41 #include <dev/pci/pcivar.h> 42 #include <dev/pci/pcireg.h> 43 #include <dev/pci/pcib_private.h> 44 #include <isa/isavar.h> 45 #ifdef CPU_ELAN 46 #include <machine/md_var.h> 47 #endif 48 #include <machine/legacyvar.h> 49 #include <machine/pci_cfgreg.h> 50 #include <machine/resource.h> 51 52 #include "pcib_if.h" 53 54 int 55 legacy_pcib_maxslots(device_t dev) 56 { 57 return 31; 58 } 59 60 /* read configuration space register */ 61 62 uint32_t 63 legacy_pcib_read_config(device_t dev, u_int bus, u_int slot, u_int func, 64 u_int reg, int bytes) 65 { 66 return(pci_cfgregread(bus, slot, func, reg, bytes)); 67 } 68 69 /* write configuration space register */ 70 71 void 72 legacy_pcib_write_config(device_t dev, u_int bus, u_int slot, u_int func, 73 u_int reg, uint32_t data, int bytes) 74 { 75 pci_cfgregwrite(bus, slot, func, reg, data, bytes); 76 } 77 78 /* route interrupt */ 79 80 static int 81 legacy_pcib_route_interrupt(device_t pcib, device_t dev, int pin) 82 { 83 84 #ifdef __HAVE_PIR 85 return (pci_pir_route_interrupt(pci_get_bus(dev), pci_get_slot(dev), 86 pci_get_function(dev), pin)); 87 #else 88 /* No routing possible */ 89 return (PCI_INVALID_IRQ); 90 #endif 91 } 92 93 /* Pass MSI requests up to the nexus. */ 94 95 static int 96 legacy_pcib_alloc_msi(device_t pcib, device_t dev, int count, int maxcount, 97 int *irqs) 98 { 99 device_t bus; 100 101 bus = device_get_parent(pcib); 102 return (PCIB_ALLOC_MSI(device_get_parent(bus), dev, count, maxcount, 103 irqs)); 104 } 105 106 static int 107 legacy_pcib_alloc_msix(device_t pcib, device_t dev, int *irq) 108 { 109 device_t bus; 110 111 bus = device_get_parent(pcib); 112 return (PCIB_ALLOC_MSIX(device_get_parent(bus), dev, irq)); 113 } 114 115 static int 116 legacy_pcib_map_msi(device_t pcib, device_t dev, int irq, uint64_t *addr, 117 uint32_t *data) 118 { 119 device_t bus; 120 121 bus = device_get_parent(pcib); 122 return (PCIB_MAP_MSI(device_get_parent(bus), dev, irq, addr, data)); 123 } 124 125 static const char * 126 legacy_pcib_is_host_bridge(int bus, int slot, int func, 127 uint32_t id, uint8_t class, uint8_t subclass, 128 uint8_t *busnum) 129 { 130 #ifdef __i386__ 131 const char *s = NULL; 132 static uint8_t pxb[4]; /* hack for 450nx */ 133 134 *busnum = 0; 135 136 switch (id) { 137 case 0x12258086: 138 s = "Intel 824?? host to PCI bridge"; 139 /* XXX This is a guess */ 140 /* *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x41, 1); */ 141 *busnum = bus; 142 break; 143 case 0x71208086: 144 s = "Intel 82810 (i810 GMCH) Host To Hub bridge"; 145 break; 146 case 0x71228086: 147 s = "Intel 82810-DC100 (i810-DC100 GMCH) Host To Hub bridge"; 148 break; 149 case 0x71248086: 150 s = "Intel 82810E (i810E GMCH) Host To Hub bridge"; 151 break; 152 case 0x11308086: 153 s = "Intel 82815 (i815 GMCH) Host To Hub bridge"; 154 break; 155 case 0x71808086: 156 s = "Intel 82443LX (440 LX) host to PCI bridge"; 157 break; 158 case 0x71908086: 159 s = "Intel 82443BX (440 BX) host to PCI bridge"; 160 break; 161 case 0x71928086: 162 s = "Intel 82443BX host to PCI bridge (AGP disabled)"; 163 break; 164 case 0x71948086: 165 s = "Intel 82443MX host to PCI bridge"; 166 break; 167 case 0x71a08086: 168 s = "Intel 82443GX host to PCI bridge"; 169 break; 170 case 0x71a18086: 171 s = "Intel 82443GX host to AGP bridge"; 172 break; 173 case 0x71a28086: 174 s = "Intel 82443GX host to PCI bridge (AGP disabled)"; 175 break; 176 case 0x84c48086: 177 s = "Intel 82454KX/GX (Orion) host to PCI bridge"; 178 *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x4a, 1); 179 break; 180 case 0x84ca8086: 181 /* 182 * For the 450nx chipset, there is a whole bundle of 183 * things pretending to be host bridges. The MIOC will 184 * be seen first and isn't really a pci bridge (the 185 * actual busses are attached to the PXB's). We need to 186 * read the registers of the MIOC to figure out the 187 * bus numbers for the PXB channels. 188 * 189 * Since the MIOC doesn't have a pci bus attached, we 190 * pretend it wasn't there. 191 */ 192 pxb[0] = legacy_pcib_read_config(0, bus, slot, func, 193 0xd0, 1); /* BUSNO[0] */ 194 pxb[1] = legacy_pcib_read_config(0, bus, slot, func, 195 0xd1, 1) + 1; /* SUBA[0]+1 */ 196 pxb[2] = legacy_pcib_read_config(0, bus, slot, func, 197 0xd3, 1); /* BUSNO[1] */ 198 pxb[3] = legacy_pcib_read_config(0, bus, slot, func, 199 0xd4, 1) + 1; /* SUBA[1]+1 */ 200 return NULL; 201 case 0x84cb8086: 202 switch (slot) { 203 case 0x12: 204 s = "Intel 82454NX PXB#0, Bus#A"; 205 *busnum = pxb[0]; 206 break; 207 case 0x13: 208 s = "Intel 82454NX PXB#0, Bus#B"; 209 *busnum = pxb[1]; 210 break; 211 case 0x14: 212 s = "Intel 82454NX PXB#1, Bus#A"; 213 *busnum = pxb[2]; 214 break; 215 case 0x15: 216 s = "Intel 82454NX PXB#1, Bus#B"; 217 *busnum = pxb[3]; 218 break; 219 } 220 break; 221 case 0x1A308086: 222 s = "Intel 82845 Host to PCI bridge"; 223 break; 224 225 /* AMD -- vendor 0x1022 */ 226 case 0x30001022: 227 s = "AMD Elan SC520 host to PCI bridge"; 228 #ifdef CPU_ELAN 229 init_AMD_Elan_sc520(); 230 #else 231 printf( 232 "*** WARNING: missing CPU_ELAN -- timekeeping may be wrong\n"); 233 #endif 234 break; 235 case 0x70061022: 236 s = "AMD-751 host to PCI bridge"; 237 break; 238 case 0x700e1022: 239 s = "AMD-761 host to PCI bridge"; 240 break; 241 242 /* SiS -- vendor 0x1039 */ 243 case 0x04961039: 244 s = "SiS 85c496"; 245 break; 246 case 0x04061039: 247 s = "SiS 85c501"; 248 break; 249 case 0x06011039: 250 s = "SiS 85c601"; 251 break; 252 case 0x55911039: 253 s = "SiS 5591 host to PCI bridge"; 254 break; 255 case 0x00011039: 256 s = "SiS 5591 host to AGP bridge"; 257 break; 258 259 /* VLSI -- vendor 0x1004 */ 260 case 0x00051004: 261 s = "VLSI 82C592 Host to PCI bridge"; 262 break; 263 264 /* XXX Here is MVP3, I got the datasheet but NO M/B to test it */ 265 /* totally. Please let me know if anything wrong. -F */ 266 /* XXX need info on the MVP3 -- any takers? */ 267 case 0x05981106: 268 s = "VIA 82C598MVP (Apollo MVP3) host bridge"; 269 break; 270 271 /* AcerLabs -- vendor 0x10b9 */ 272 /* Funny : The datasheet told me vendor id is "10b8",sub-vendor */ 273 /* id is '10b9" but the register always shows "10b9". -Foxfair */ 274 case 0x154110b9: 275 s = "AcerLabs M1541 (Aladdin-V) PCI host bridge"; 276 break; 277 278 /* OPTi -- vendor 0x1045 */ 279 case 0xc7011045: 280 s = "OPTi 82C700 host to PCI bridge"; 281 break; 282 case 0xc8221045: 283 s = "OPTi 82C822 host to PCI Bridge"; 284 break; 285 286 /* ServerWorks -- vendor 0x1166 */ 287 case 0x00051166: 288 s = "ServerWorks NB6536 2.0HE host to PCI bridge"; 289 *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1); 290 break; 291 292 case 0x00061166: 293 /* FALLTHROUGH */ 294 case 0x00081166: 295 /* FALLTHROUGH */ 296 case 0x02011166: 297 /* FALLTHROUGH */ 298 case 0x010f1014: /* IBM re-badged ServerWorks chipset */ 299 s = "ServerWorks host to PCI bridge"; 300 *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1); 301 break; 302 303 case 0x00091166: 304 s = "ServerWorks NB6635 3.0LE host to PCI bridge"; 305 *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1); 306 break; 307 308 case 0x00101166: 309 s = "ServerWorks CIOB30 host to PCI bridge"; 310 *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1); 311 break; 312 313 case 0x00111166: 314 /* FALLTHROUGH */ 315 case 0x03021014: /* IBM re-badged ServerWorks chipset */ 316 s = "ServerWorks CMIC-HE host to PCI-X bridge"; 317 *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1); 318 break; 319 320 /* XXX unknown chipset, but working */ 321 case 0x00171166: 322 /* FALLTHROUGH */ 323 case 0x01011166: 324 case 0x01101166: 325 case 0x02251166: 326 s = "ServerWorks host to PCI bridge(unknown chipset)"; 327 *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1); 328 break; 329 330 /* Compaq/HP -- vendor 0x0e11 */ 331 case 0x60100e11: 332 s = "Compaq/HP Model 6010 HotPlug PCI Bridge"; 333 *busnum = legacy_pcib_read_config(0, bus, slot, func, 0xc8, 1); 334 break; 335 336 /* Integrated Micro Solutions -- vendor 0x10e0 */ 337 case 0x884910e0: 338 s = "Integrated Micro Solutions VL Bridge"; 339 break; 340 341 default: 342 if (class == PCIC_BRIDGE && subclass == PCIS_BRIDGE_HOST) 343 s = "Host to PCI bridge"; 344 break; 345 } 346 347 return s; 348 #else 349 const char *s = NULL; 350 351 *busnum = 0; 352 if (class == PCIC_BRIDGE && subclass == PCIS_BRIDGE_HOST) 353 s = "Host to PCI bridge"; 354 return s; 355 #endif 356 } 357 358 /* 359 * Scan the first pci bus for host-pci bridges and add pcib instances 360 * to the nexus for each bridge. 361 */ 362 static void 363 legacy_pcib_identify(driver_t *driver, device_t parent) 364 { 365 int bus, slot, func; 366 uint8_t hdrtype; 367 int found = 0; 368 int pcifunchigh; 369 int found824xx = 0; 370 int found_orion = 0; 371 device_t child; 372 devclass_t pci_devclass; 373 374 if (pci_cfgregopen() == 0) 375 return; 376 /* 377 * Check to see if we haven't already had a PCI bus added 378 * via some other means. If we have, bail since otherwise 379 * we're going to end up duplicating it. 380 */ 381 if ((pci_devclass = devclass_find("pci")) && 382 devclass_get_device(pci_devclass, 0)) 383 return; 384 385 386 bus = 0; 387 retry: 388 for (slot = 0; slot <= PCI_SLOTMAX; slot++) { 389 func = 0; 390 hdrtype = legacy_pcib_read_config(0, bus, slot, func, 391 PCIR_HDRTYPE, 1); 392 /* 393 * When enumerating bus devices, the standard says that 394 * one should check the header type and ignore the slots whose 395 * header types that the software doesn't know about. We use 396 * this to filter out devices. 397 */ 398 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE) 399 continue; 400 if ((hdrtype & PCIM_MFDEV) && 401 (!found_orion || hdrtype != 0xff)) 402 pcifunchigh = PCI_FUNCMAX; 403 else 404 pcifunchigh = 0; 405 for (func = 0; func <= pcifunchigh; func++) { 406 /* 407 * Read the IDs and class from the device. 408 */ 409 uint32_t id; 410 uint8_t class, subclass, busnum; 411 const char *s; 412 device_t *devs; 413 int ndevs, i; 414 415 id = legacy_pcib_read_config(0, bus, slot, func, 416 PCIR_DEVVENDOR, 4); 417 if (id == -1) 418 continue; 419 class = legacy_pcib_read_config(0, bus, slot, func, 420 PCIR_CLASS, 1); 421 subclass = legacy_pcib_read_config(0, bus, slot, func, 422 PCIR_SUBCLASS, 1); 423 424 s = legacy_pcib_is_host_bridge(bus, slot, func, 425 id, class, subclass, 426 &busnum); 427 if (s == NULL) 428 continue; 429 430 /* 431 * Check to see if the physical bus has already 432 * been seen. Eg: hybrid 32 and 64 bit host 433 * bridges to the same logical bus. 434 */ 435 if (device_get_children(parent, &devs, &ndevs) == 0) { 436 for (i = 0; s != NULL && i < ndevs; i++) { 437 if (strcmp(device_get_name(devs[i]), 438 "pcib") != 0) 439 continue; 440 if (legacy_get_pcibus(devs[i]) == busnum) 441 s = NULL; 442 } 443 free(devs, M_TEMP); 444 } 445 446 if (s == NULL) 447 continue; 448 /* 449 * Add at priority 100 to make sure we 450 * go after any motherboard resources 451 */ 452 child = BUS_ADD_CHILD(parent, 100, 453 "pcib", busnum); 454 device_set_desc(child, s); 455 legacy_set_pcibus(child, busnum); 456 457 found = 1; 458 if (id == 0x12258086) 459 found824xx = 1; 460 if (id == 0x84c48086) 461 found_orion = 1; 462 } 463 } 464 if (found824xx && bus == 0) { 465 bus++; 466 goto retry; 467 } 468 469 /* 470 * Make sure we add at least one bridge since some old 471 * hardware doesn't actually have a host-pci bridge device. 472 * Note that pci_cfgregopen() thinks we have PCI devices.. 473 */ 474 if (!found) { 475 if (bootverbose) 476 printf( 477 "legacy_pcib_identify: no bridge found, adding pcib0 anyway\n"); 478 child = BUS_ADD_CHILD(parent, 100, "pcib", 0); 479 legacy_set_pcibus(child, 0); 480 } 481 } 482 483 static int 484 legacy_pcib_probe(device_t dev) 485 { 486 487 if (pci_cfgregopen() == 0) 488 return ENXIO; 489 return -100; 490 } 491 492 static int 493 legacy_pcib_attach(device_t dev) 494 { 495 #ifdef __HAVE_PIR 496 device_t pir; 497 #endif 498 int bus; 499 500 bus = pcib_get_bus(dev); 501 #ifdef __HAVE_PIR 502 /* 503 * Look for a PCI BIOS interrupt routing table as that will be 504 * our method of routing interrupts if we have one. 505 */ 506 if (pci_pir_probe(bus, 0)) { 507 pir = BUS_ADD_CHILD(device_get_parent(dev), 0, "pir", 0); 508 if (pir != NULL) 509 device_probe_and_attach(pir); 510 } 511 #endif 512 device_add_child(dev, "pci", bus); 513 return bus_generic_attach(dev); 514 } 515 516 int 517 legacy_pcib_read_ivar(device_t dev, device_t child, int which, 518 uintptr_t *result) 519 { 520 521 switch (which) { 522 case PCIB_IVAR_DOMAIN: 523 *result = 0; 524 return 0; 525 case PCIB_IVAR_BUS: 526 *result = legacy_get_pcibus(dev); 527 return 0; 528 } 529 return ENOENT; 530 } 531 532 int 533 legacy_pcib_write_ivar(device_t dev, device_t child, int which, 534 uintptr_t value) 535 { 536 537 switch (which) { 538 case PCIB_IVAR_DOMAIN: 539 return EINVAL; 540 case PCIB_IVAR_BUS: 541 legacy_set_pcibus(dev, value); 542 return 0; 543 } 544 return ENOENT; 545 } 546 547 /* 548 * Helper routine for x86 Host-PCI bridge driver resource allocation. 549 * This is used to adjust the start address of wildcard allocation 550 * requests to avoid low addresses that are known to be problematic. 551 * 552 * If no memory preference is given, use upper 32MB slot most BIOSes 553 * use for their memory window. This is typically only used on older 554 * laptops that don't have PCI busses behind a PCI bridge, so assuming 555 * > 32MB is likely OK. 556 * 557 * However, this can cause problems for other chipsets, so we make 558 * this tunable by hw.pci.host_mem_start. 559 */ 560 SYSCTL_DECL(_hw_pci); 561 562 static unsigned long host_mem_start = 0x80000000; 563 TUNABLE_ULONG("hw.pci.host_mem_start", &host_mem_start); 564 SYSCTL_ULONG(_hw_pci, OID_AUTO, host_mem_start, CTLFLAG_RDTUN, &host_mem_start, 565 0, "Limit the host bridge memory to being above this address."); 566 567 u_long 568 hostb_alloc_start(int type, u_long start, u_long end, u_long count) 569 { 570 571 if (start + count - 1 != end) { 572 if (type == SYS_RES_MEMORY && start < host_mem_start) 573 start = host_mem_start; 574 if (type == SYS_RES_IOPORT && start < 0x1000) 575 start = 0x1000; 576 } 577 return (start); 578 } 579 580 struct resource * 581 legacy_pcib_alloc_resource(device_t dev, device_t child, int type, int *rid, 582 u_long start, u_long end, u_long count, u_int flags) 583 { 584 585 start = hostb_alloc_start(type, start, end, count); 586 return (bus_generic_alloc_resource(dev, child, type, rid, start, end, 587 count, flags)); 588 } 589 590 static device_method_t legacy_pcib_methods[] = { 591 /* Device interface */ 592 DEVMETHOD(device_identify, legacy_pcib_identify), 593 DEVMETHOD(device_probe, legacy_pcib_probe), 594 DEVMETHOD(device_attach, legacy_pcib_attach), 595 DEVMETHOD(device_shutdown, bus_generic_shutdown), 596 DEVMETHOD(device_suspend, bus_generic_suspend), 597 DEVMETHOD(device_resume, bus_generic_resume), 598 599 /* Bus interface */ 600 DEVMETHOD(bus_read_ivar, legacy_pcib_read_ivar), 601 DEVMETHOD(bus_write_ivar, legacy_pcib_write_ivar), 602 DEVMETHOD(bus_alloc_resource, legacy_pcib_alloc_resource), 603 DEVMETHOD(bus_adjust_resource, bus_generic_adjust_resource), 604 DEVMETHOD(bus_release_resource, bus_generic_release_resource), 605 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 606 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 607 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 608 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 609 610 /* pcib interface */ 611 DEVMETHOD(pcib_maxslots, legacy_pcib_maxslots), 612 DEVMETHOD(pcib_read_config, legacy_pcib_read_config), 613 DEVMETHOD(pcib_write_config, legacy_pcib_write_config), 614 DEVMETHOD(pcib_route_interrupt, legacy_pcib_route_interrupt), 615 DEVMETHOD(pcib_alloc_msi, legacy_pcib_alloc_msi), 616 DEVMETHOD(pcib_release_msi, pcib_release_msi), 617 DEVMETHOD(pcib_alloc_msix, legacy_pcib_alloc_msix), 618 DEVMETHOD(pcib_release_msix, pcib_release_msix), 619 DEVMETHOD(pcib_map_msi, legacy_pcib_map_msi), 620 621 DEVMETHOD_END 622 }; 623 624 static devclass_t hostb_devclass; 625 626 DEFINE_CLASS_0(pcib, legacy_pcib_driver, legacy_pcib_methods, 1); 627 DRIVER_MODULE(pcib, legacy, legacy_pcib_driver, hostb_devclass, 0, 0); 628 629 630 /* 631 * Install placeholder to claim the resources owned by the 632 * PCI bus interface. This could be used to extract the 633 * config space registers in the extreme case where the PnP 634 * ID is available and the PCI BIOS isn't, but for now we just 635 * eat the PnP ID and do nothing else. 636 * 637 * XXX we should silence this probe, as it will generally confuse 638 * people. 639 */ 640 static struct isa_pnp_id pcibus_pnp_ids[] = { 641 { 0x030ad041 /* PNP0A03 */, "PCI Bus" }, 642 { 0x080ad041 /* PNP0A08 */, "PCIe Bus" }, 643 { 0 } 644 }; 645 646 static int 647 pcibus_pnp_probe(device_t dev) 648 { 649 int result; 650 651 if ((result = ISA_PNP_PROBE(device_get_parent(dev), dev, pcibus_pnp_ids)) <= 0) 652 device_quiet(dev); 653 return(result); 654 } 655 656 static int 657 pcibus_pnp_attach(device_t dev) 658 { 659 return(0); 660 } 661 662 static device_method_t pcibus_pnp_methods[] = { 663 /* Device interface */ 664 DEVMETHOD(device_probe, pcibus_pnp_probe), 665 DEVMETHOD(device_attach, pcibus_pnp_attach), 666 DEVMETHOD(device_detach, bus_generic_detach), 667 DEVMETHOD(device_shutdown, bus_generic_shutdown), 668 DEVMETHOD(device_suspend, bus_generic_suspend), 669 DEVMETHOD(device_resume, bus_generic_resume), 670 { 0, 0 } 671 }; 672 673 static devclass_t pcibus_pnp_devclass; 674 675 DEFINE_CLASS_0(pcibus_pnp, pcibus_pnp_driver, pcibus_pnp_methods, 1); 676 DRIVER_MODULE(pcibus_pnp, isa, pcibus_pnp_driver, pcibus_pnp_devclass, 0, 0); 677 678 #ifdef __HAVE_PIR 679 /* 680 * Provide a PCI-PCI bridge driver for PCI busses behind PCI-PCI bridges 681 * that appear in the PCIBIOS Interrupt Routing Table to use the routing 682 * table for interrupt routing when possible. 683 */ 684 static int pcibios_pcib_probe(device_t bus); 685 686 static device_method_t pcibios_pcib_pci_methods[] = { 687 /* Device interface */ 688 DEVMETHOD(device_probe, pcibios_pcib_probe), 689 690 /* pcib interface */ 691 DEVMETHOD(pcib_route_interrupt, legacy_pcib_route_interrupt), 692 693 {0, 0} 694 }; 695 696 static devclass_t pcib_devclass; 697 698 DEFINE_CLASS_1(pcib, pcibios_pcib_driver, pcibios_pcib_pci_methods, 699 sizeof(struct pcib_softc), pcib_driver); 700 DRIVER_MODULE(pcibios_pcib, pci, pcibios_pcib_driver, pcib_devclass, 0, 0); 701 702 static int 703 pcibios_pcib_probe(device_t dev) 704 { 705 int bus; 706 707 if ((pci_get_class(dev) != PCIC_BRIDGE) || 708 (pci_get_subclass(dev) != PCIS_BRIDGE_PCI)) 709 return (ENXIO); 710 bus = pci_read_config(dev, PCIR_SECBUS_1, 1); 711 if (bus == 0) 712 return (ENXIO); 713 if (!pci_pir_probe(bus, 1)) 714 return (ENXIO); 715 device_set_desc(dev, "PCIBIOS PCI-PCI bridge"); 716 return (-2000); 717 } 718 #endif 719